siliconcompiler 0.26.5__py3-none-any.whl

siliconcompiler/flows/asicflow.py

@@ -0,0 +1,180 @@
+import siliconcompiler
+
+from siliconcompiler.flows._common import setup_multiple_frontends
+from siliconcompiler.flows._common import _make_docs
+
+from siliconcompiler.tools.yosys import syn_asic
+from siliconcompiler.tools.openroad import floorplan
+from siliconcompiler.tools.openroad import physyn
+from siliconcompiler.tools.openroad import place
+from siliconcompiler.tools.openroad import cts
+from siliconcompiler.tools.openroad import route
+from siliconcompiler.tools.openroad import dfm
+from siliconcompiler.tools.openroad import export as openroad_export
+from siliconcompiler.tools.klayout import export as klayout_export
+
+from siliconcompiler.tools.builtin import minimum
+
+
+############################################################################
+# DOCS
+############################################################################
+def make_docs(chip):
+    n = 3
+    _make_docs(chip)
+    return setup(chip, syn_np=n, floorplan_np=n, physyn_np=n, place_np=n, cts_np=n, route_np=n)
+
+
+###########################################################################
+# Flowgraph Setup
+############################################################################
+def setup(chip,
+          flowname='asicflow',
+          syn_np=1,
+          floorplan_np=1,
+          physyn_np=1,
+          place_np=1,
+          cts_np=1,
+          route_np=1):
+    '''
+    A configurable ASIC compilation flow.
+
+    The 'asicflow' includes the stages below. The steps syn, floorplan,
+    physyn, place, cts, route, and dfm have minimization associated
+    with them. To view the flowgraph, see the .png file.
+
+    * **import**: Sources are collected and packaged for compilation
+    * **syn**: Translates RTL to netlist using Yosys
+    * **floorplan**: Floorplanning
+    * **physyn**: Physical Synthesis
+    * **place**: Global and detailed placement
+    * **cts**: Clock tree synthesis
+    * **route**: Global and detailed routing
+    * **dfm**: Metal fill, atenna fixes and any other post routing steps
+    * **export**: Export design from APR tool and merge with library GDS
+    * **sta**: Static timing analysis (signoff)
+    * **lvs**: Layout versus schematic check (signoff)
+    * **drc**: Design rule check (signoff)
+
+    The syn, physyn, place, cts, route steps supports per process
+    options that can be set up by setting '<step>_np'
+    arg to a value > 1, as detailed below:
+
+    * syn_np : Number of parallel synthesis jobs to launch
+    * floorplan_np : Number of parallel floorplan jobs to launch
+    * physyn_np : Number of parallel physical synthesis jobs to launch
+    * place_np : Number of parallel place jobs to launch
+    * cts_np : Number of parallel clock tree synthesis jobs to launch
+    * route_np : Number of parallel routing jobs to launch
+    '''
+
+    flow = siliconcompiler.Flow(chip, flowname)
+
+    # Linear flow, up until branch to run parallel verification steps.
+    longpipe = ['syn',
+                'synmin',
+                'floorplan',
+                'floorplanmin',
+                'place',
+                'placemin',
+                'cts',
+                'ctsmin',
+                'route',
+                'routemin',
+                'dfm']
+
+    # step --> task
+    tasks = {
+        'syn': syn_asic,
+        'synmin': minimum,
+        'floorplan': floorplan,
+        'floorplanmin': minimum,
+        'physyn': physyn,
+        'physynmin': minimum,
+        'place': place,
+        'placemin': minimum,
+        'cts': cts,
+        'ctsmin': minimum,
+        'route': route,
+        'routemin': minimum,
+        'dfm': dfm
+    }
+
+    np = {
+        "syn": syn_np,
+        "floorplan": floorplan_np,
+        "physyn": physyn_np,
+        "place": place_np,
+        "cts": cts_np,
+        "route": route_np
+    }
+
+    prevstep = None
+    # Remove built in steps where appropriate
+    flowpipe = []
+    for step in longpipe:
+        task = tasks[step]
+        if task == minimum:
+            if prevstep in np and np[prevstep] > 1:
+                flowpipe.append(step)
+        else:
+            flowpipe.append(step)
+        prevstep = step
+
+    flowtasks = []
+    for step in flowpipe:
+        flowtasks.append((step, tasks[step]))
+
+    # Programmatically build linear portion of flowgraph and fanin/fanout args
+    prevstep = setup_multiple_frontends(chip, flow)
+    for step, task in flowtasks:
+        fanout = 1
+        if step in np:
+            fanout = np[step]
+        # create nodes
+        for index in range(fanout):
+            # nodes
+            flow.node(flowname, step, task, index=index)
+
+            # edges
+            if task == minimum:
+                fanin = 1
+                if prevstep in np:
+                    fanin = np[prevstep]
+                for i in range(fanin):
+                    flow.edge(flowname, prevstep, step, tail_index=i)
+            elif prevstep:
+                flow.edge(flowname, prevstep, step, head_index=index)
+
+            # metrics
+            goal_metrics = ()
+            weight_metrics = ()
+            if task in (syn_asic, ):
+                goal_metrics = ('errors',)
+                weight_metrics = ()
+            elif task in (floorplan, physyn, place, cts, route, dfm):
+                goal_metrics = ('errors', 'setupwns', 'setuptns')
+                weight_metrics = ('cellarea', 'peakpower', 'leakagepower')
+
+            for metric in goal_metrics:
+                flow.set('flowgraph', flowname, step, str(index), 'goal', metric, 0)
+            for metric in weight_metrics:
+                flow.set('flowgraph', flowname, step, str(index), 'weight', metric, 1.0)
+        prevstep = step
+
+    # add write information steps
+    flow.node(flowname, 'write_gds', klayout_export)
+    flow.edge(flowname, prevstep, 'write_gds')
+    flow.node(flowname, 'write_data', openroad_export)
+    flow.edge(flowname, prevstep, 'write_data')
+
+    return flow
+
+
+##################################################
+if __name__ == "__main__":
+    chip = siliconcompiler.Chip('design')
+    chip.set('input', 'constraint', 'sdc', 'test')
+    flow = make_docs(chip)
+    chip.use(flow)
+    chip.write_flowgraph(f"{flow.top()}.png", flow=flow.top())

siliconcompiler/flows/asictopflow.py

@@ -0,0 +1,38 @@
+import siliconcompiler
+
+from siliconcompiler.tools.surelog import parse as surelog_parse
+from siliconcompiler.tools.yosys import syn_asic
+from siliconcompiler.tools.klayout import export
+from siliconcompiler.flows._common import _make_docs
+
+
+def setup(chip):
+    '''A flow for stitching together hardened blocks without doing any automated
+    place-and-route.
+
+    This flow generates a GDS and a netlist for passing to a
+    verification/signoff flow.
+    '''
+    flow = siliconcompiler.Flow(chip, 'asictopflow')
+
+    flow.node(flow.design, 'import', surelog_parse)
+    flow.node(flow.design, 'syn', syn_asic)
+    flow.node(flow.design, 'export', export)
+
+    flow.edge(flow.design, 'import', 'export')
+    flow.edge(flow.design, 'import', 'syn')
+
+    # Set default goal
+    for step in flow.getkeys('flowgraph', flow.design):
+        flow.set('flowgraph', flow.design, step, '0', 'goal', 'errors', 0)
+
+    return flow
+
+
+##################################################
+if __name__ == "__main__":
+    chip = siliconcompiler.Chip('design')
+    _make_docs(chip)
+    flow = setup(chip)
+    chip.use(flow)
+    chip.write_flowgraph(f"{flow.top()}.png", flow=flow.top())

siliconcompiler/flows/dvflow.py

@@ -0,0 +1,86 @@
+import siliconcompiler
+
+from siliconcompiler.tools.icarus import compile as icarus_compile
+from siliconcompiler.tools.verilator import compile as verilator_compile
+from siliconcompiler.tools.execute import exec_input
+
+
+############################################################################
+# DOCS
+############################################################################
+def make_docs(chip):
+    chip.set('input', 'rtl', 'netlist', 'test')
+    return setup(chip, np=5)
+
+
+#############################################################################
+# Flowgraph Setup
+#############################################################################
+def setup(chip,
+          flowname='dvflow',
+          tool='icarus',
+          np=1):
+    '''
+    A configurable constrained random stimulus DV flow.
+
+    The verification pipeline includes the following steps:
+
+    * **compile**: RTL sources are compiled into object form (once)
+    * **sim**: Compiled RTL is exercised using generated test
+
+    The dvflow can be parametrized using a single 'np' parameter.
+    Setting 'np' > 1 results in multiple independent verification
+    pipelines to be launched.
+
+    This flow is a WIP
+    '''
+
+    flow = siliconcompiler.Flow(chip, flowname)
+
+    tasks = {
+        'compile': None,
+        'sim': None
+    }
+
+    if tool == 'icarus':
+        tasks['compile'] = icarus_compile
+        tasks['sim'] = exec_input
+    elif tool == 'verilator':
+        tasks['compile'] = verilator_compile
+        tasks['sim'] = exec_input
+    else:
+        raise ValueError(f'{tool} is not a supported tool for {flowname}: icarus')
+
+    flowpipe = [
+        'compile',
+        'sim'
+    ]
+    flow_np = {
+        'compile': 1,
+        'sim': np
+    }
+
+    prevstep = None
+    # Flow setup
+    for step in flowpipe:
+        task = tasks[step]
+
+        parallel = flow_np[step]
+
+        for n in range(parallel):
+            flow.node(flowname, step, task, index=n)
+
+            if prevstep:
+                flow.edge(flowname, prevstep, step, tail_index=0, head_index=n)
+
+        prevstep = step
+
+    return flow
+
+
+##################################################
+if __name__ == "__main__":
+    chip = siliconcompiler.Chip('design')
+    flow = make_docs(chip)
+    chip.use(flow)
+    chip.write_flowgraph(f"{flow.top()}.png", flow=flow.top())

siliconcompiler/flows/fpgaflow.py

@@ -0,0 +1,202 @@
+import siliconcompiler
+import re
+
+from siliconcompiler import SiliconCompilerError
+from siliconcompiler.flows._common import setup_multiple_frontends
+from siliconcompiler.flows._common import _make_docs
+
+from siliconcompiler.tools.yosys import syn_fpga as yosys_syn
+from siliconcompiler.tools.vpr import place as vpr_place
+from siliconcompiler.tools.vpr import route as vpr_route
+from siliconcompiler.tools.genfasm import bitstream as genfasm_bitstream
+
+from siliconcompiler.tools.vivado import syn_fpga as vivado_syn
+from siliconcompiler.tools.vivado import place as vivado_place
+from siliconcompiler.tools.vivado import route as vivado_route
+from siliconcompiler.tools.vivado import bitstream as vivado_bitstream
+
+from siliconcompiler.tools.nextpnr import apr as nextpnr_apr
+
+
+############################################################################
+# DOCS
+############################################################################
+def make_docs(chip):
+    _make_docs(chip)
+    chip.set('fpga', 'partname', 'example_arch')
+    return setup(chip)
+
+
+############################################################################
+# Flowgraph Setup
+############################################################################
+def setup(chip, flowname='fpgaflow', fpgaflow_type=None, partname=None):
+    '''
+    A configurable FPGA compilation flow.
+
+    The 'fpgaflow' module is a configurable FPGA flow with support for
+    open source and commercial tool flows.
+
+    The following step convention is recommended for VPR.
+
+    * **import**: Sources are collected and packaged for compilation
+    * **syn**: Synthesize RTL into an device specific netlist
+    * **place**: FPGA specific placement step
+    * **route**: FPGA specific routing step
+    * **bitstream**: Bitstream generation
+
+    Note that nextpnr does not appear to support breaking placement, routing,
+    and bitstream generation into individual steps, leading to the following
+    recommended step convention
+
+    * **import**: Sources are collected and packaged for compilation
+    * **syn**: Synthesize RTL into an device specific netlist
+    * **apr**: One-step execution of place, route, bitstream with nextpnr
+
+    Args:
+        - fpgaflow_type (str): this parameter can be used to select a specific
+          fpga flow instead of one selected from the partname.
+        - partname (str): this parameter can be used to select a specific fpga
+          flow instead of one selected from the partname set in the schema.
+    '''
+
+    flow = siliconcompiler.Flow(chip, flowname)
+
+    if not partname:
+        partname = chip.get('fpga', 'partname')
+
+    if fpgaflow_type:
+        flow_pipe = flow_lookup_by_type(fpgaflow_type)
+    else:
+        flow_pipe = flow_lookup(partname)
+
+    # Minimal setup
+    prevstep = setup_multiple_frontends(chip, flow)
+    for step, tool_module in flow_pipe:
+        # Flow
+        flow.node(flowname, step, tool_module)
+        if prevstep:
+            flow.edge(flowname, prevstep, step)
+        # Hard goals
+        for metric in ('errors', 'warnings', 'drvs', 'unconstrained',
+                       'holdwns', 'holdtns', 'holdpaths',
+                       'setupwns', 'setuptns', 'setuppaths'):
+            flow.set('flowgraph', flowname, step, '0', 'goal', metric, 0)
+        # Metrics
+        for metric in ('luts', 'dsps', 'brams', 'registers', 'pins'):
+            flow.set('flowgraph', flowname, step, '0', 'weight', metric, 1.0)
+        prevstep = step
+
+    return flow
+
+
+##################################################
+def flow_lookup_by_type(name):
+    '''
+    Returns a list for the the flow selected based on name of the flow type.
+    '''
+
+    vivado_flow = [
+        ('syn_fpga', vivado_syn),
+        ('place', vivado_place),
+        ('route', vivado_route),
+        ('bitstream', vivado_bitstream)]
+    nextpnr_flow = [('syn', yosys_syn),
+                    ('apr', nextpnr_apr)]
+    vpr_flow = [('syn', yosys_syn),
+                ('place', vpr_place),
+                ('route', vpr_route),
+                ('bitstream', genfasm_bitstream)]
+
+    flow_map = {
+        "vivado": vivado_flow,
+        "nextpnr": nextpnr_flow,
+        "vpr": vpr_flow
+    }
+
+    if name not in flow_map:
+        raise SiliconCompilerError(f'{name} is not a supported FPGA flow type')
+
+    return flow_map[name]
+
+
+##################################################
+def flow_lookup(partname):
+    '''
+    Returns a list for the the flow selected based on the part number
+    regular expression.
+    '''
+
+    if not partname:
+        raise SiliconCompilerError('A part number must be specified to setup the fpga flow.')
+
+    partname = partname.lower()
+
+    ###########
+    # xilinx
+    ###########
+
+    spartan6 = bool(re.match('^xc6', partname))
+    spartan7 = bool(re.match('^xc7s', partname))
+    artix = bool(re.match('^xc7a', partname))
+    artixultra = bool(re.match('^au', partname))
+    kintex7 = bool(re.match('^xc7k', partname))
+    kintexultra = bool(re.match('^xcku', partname))
+    zynq = bool(re.match(r'^z\-7', partname))
+    zynqultra = bool(re.match('^zu', partname))
+    virtex7 = bool(re.match('^xc7v', partname))
+    virtexultra = bool(re.match('^xcvu', partname))
+
+    xilinx = spartan6 or spartan7 or \
+        artix or artixultra or \
+        kintex7 or kintexultra or \
+        zynq or zynqultra or \
+        virtex7 or virtexultra
+
+    #############
+    # intel
+    #############
+
+    cyclone4 = bool(re.match('^ep4', partname))
+    cyclone5 = bool(re.match('^5cs', partname))
+    cyclone10 = bool(re.match('^10cl', partname))
+    stratix5 = bool(re.match('^5sg', partname))
+
+    intel = cyclone10 or cyclone4 or cyclone5 or stratix5
+
+    ###########
+    # lattice
+    ###########
+
+    ice40 = re.match('^ice40', partname)
+
+    ###########
+    # example
+    ###########
+
+    example = re.match('^example_arch', partname)
+
+    flow = None
+    if xilinx:
+        flow = flow_lookup_by_type('vivado')
+    elif intel:
+        flow = flow_lookup_by_type('intel')
+    elif ice40:
+        flow = flow_lookup_by_type('nextpnr')
+    elif example:
+        flow = flow_lookup_by_type('vpr')
+
+    if not flow:
+        raise SiliconCompilerError(
+            f'fpgaflow: unsupported partname {partname}'
+        )
+
+    return flow
+
+
+##################################################
+if __name__ == "__main__":
+    chip = siliconcompiler.Chip('design')
+    flow = make_docs(chip)
+    chip.use(flow)
+    chip.write_flowgraph(f"{flow.top()}.png", flow=flow.top())

siliconcompiler/flows/generate_openroad_rcx.py

@@ -0,0 +1,66 @@
+import siliconcompiler
+
+from siliconcompiler.tools.openroad import rcx_bench
+from siliconcompiler.tools.openroad import rcx_extract
+from siliconcompiler.tools.builtin import nop
+from siliconcompiler.flows._common import _make_docs
+
+
+############################################################################
+# DOCS
+############################################################################
+def make_docs(chip):
+    _make_docs(chip)
+    return setup(chip, corners=5)
+
+
+###########################################################################
+# Flowgraph Setup
+############################################################################
+def setup(chip, extraction_task=None, corners=1, serial_extraction=False):
+    '''
+    Flow to generate the OpenRCX decks needed by OpenROAD to do parasitic
+    extraction.
+    '''
+
+    flowname = 'generate_rcx'
+    flow = siliconcompiler.Flow(chip, flowname)
+
+    if not extraction_task:
+        chip.logger.warning('Valid extraction not specified, defaulting to builtin/nop')
+        extraction_task = nop
+
+    flow.node(flowname, 'bench', rcx_bench)
+    prev = 'bench'
+    for corner in range(corners):
+        # For each corner generate a pex step to build the reference SPEF file
+        # and the extract step to use the SPEF file to build the new OpenRCX deck
+        flow.node(flowname, 'pex', extraction_task, index=corner)
+        flow.node(flowname, 'extract', rcx_extract, index=corner)
+
+        if corner == 0:
+            prev = 'bench'
+            prev_index = 0
+        else:
+            prev = 'pex'
+            prev_index = corner - 1
+
+        flow.edge(flowname, 'bench', 'pex', head_index=corner, tail_index=0)
+        flow.edge(flowname, 'pex', 'extract', head_index=corner, tail_index=corner)
+        flow.edge(flowname, 'bench', 'extract', head_index=corner, tail_index=0)
+
+        if serial_extraction and corner > 0:
+            # For license restrictions make each pex step dependent on the previous pex step
+            flow.edge(flowname, prev, 'pex', head_index=corner, tail_index=prev_index)
+
+    flow.node(flowname, 'bench', rcx_bench)
+
+    return flow
+
+
+##################################################
+if __name__ == "__main__":
+    chip = siliconcompiler.Chip('design')
+    flow = make_docs(chip)
+    chip.use(flow)
+    chip.write_flowgraph(f"{flow.top()}.png", flow=flow.top())

siliconcompiler/flows/lintflow.py

@@ -0,0 +1,35 @@
+import siliconcompiler
+
+from siliconcompiler.flows._common import _make_docs
+from siliconcompiler.tools.verilator import lint as verilator_lint
+from siliconcompiler.tools.slang import lint as slang_lint
+
+
+###########################################################################
+# Flowgraph Setup
+############################################################################
+def setup(chip, tool='verilator'):
+    '''
+    An RTL linting flow.
+    '''
+
+    flowname = 'lintflow'
+    flow = siliconcompiler.Flow(chip, flowname)
+
+    if tool == 'verilator':
+        flow.node(flowname, 'lint', verilator_lint)
+    elif tool == 'slang':
+        flow.node(flowname, 'lint', slang_lint)
+    else:
+        raise ValueError(f'Unsupported lint tool: {tool}')
+
+    return flow
+
+
+##################################################
+if __name__ == "__main__":
+    chip = siliconcompiler.Chip('design')
+    _make_docs(chip)
+    flow = setup(chip)
+    chip.use(flow)
+    chip.write_flowgraph(f"{flow.top()}.png", flow=flow.top())

siliconcompiler/flows/screenshotflow.py

@@ -0,0 +1,51 @@
+from siliconcompiler import Chip, Flow
+
+from siliconcompiler.tools.klayout import operations
+from siliconcompiler.tools.klayout import screenshot
+from siliconcompiler.tools.montage import tile
+
+
+def make_docs(chip):
+    chip.set('input', 'layout', 'gds', 'test')
+    chip.set('tool', 'klayout', 'task', 'screenshot', 'var', 'xbins', 2)
+    chip.set('tool', 'klayout', 'task', 'screenshot', 'var', 'ybins', 2)
+    chip.set('tool', 'montage', 'task', 'tile', 'var', 'xbins', 2)
+    chip.set('tool', 'montage', 'task', 'tile', 'var', 'ybins', 2)
+    return setup(chip)
+
+
+def setup(chip, flowname='screenshotflow'):
+    '''
+    Flow to generate a high resolution design image from a GDS or OAS file.
+
+    The 'screenshotflow' includes the stages below.
+
+    * **prepare**: Prepare the stream file, such as flattening design, removing layers, and merging shapes
+    * **screenshot**: Generate a set of screenshots tiled across the design
+    * **merge**: Merge tiled images into a single image
+    '''  # noqa E501
+
+    pipe = [
+        ('prepare', operations),
+        ('screenshot', screenshot),
+        ('merge', tile)
+    ]
+
+    flow = Flow(chip, flowname)
+
+    prevstep = None
+    for step, task in pipe:
+        flow.node(flowname, step, task)
+        if prevstep:
+            flow.edge(flowname, prevstep, step)
+        prevstep = step
+
+    return flow
+
+
+##################################################
+if __name__ == "__main__":
+    chip = Chip('design')
+    flow = make_docs(chip)
+    chip.use(flow)
+    chip.write_flowgraph(f"{flow.top()}.png", flow=flow.top())