siliconcompiler 0.26.5__py3-none-any.whl

siliconcompiler/tools/yosys/syn_fpga.tcl

@@ -0,0 +1,233 @@
+
+source "$sc_refdir/syn_asic_fpga_shared.tcl"
+
+proc legalize_flops { feature_set } {
+
+    set legalize_flop_types []
+
+    if { [lsearch -exact $feature_set enable] >= 0 && \
+         [lsearch -exact $feature_set async_set] >= 0 && \
+         [lsearch -exact $feature_set async_reset] >= 0 } {
+        lappend legalize_flop_types \$_DFF_P_
+        lappend legalize_flop_types \$_DFF_PN?_
+        lappend legalize_flop_types \$_DFFE_PP_
+        lappend legalize_flop_types \$_DFFE_PN?P_
+        lappend legalize_flop_types \$_DFFSR_PNN_
+        lappend legalize_flop_types \$_DFFSRE_PNNP_
+    } elseif { [lsearch -exact $feature_set enable] >= 0 && \
+               [lsearch -exact $feature_set async_set] >= 0 } {
+        lappend legalize_flop_types \$_DFF_P_
+        lappend legalize_flop_types \$_DFF_PN1_
+        lappend legalize_flop_types \$_DFFE_PP_
+        lappend legalize_flop_types \$_DFFE_PN1P_
+    } elseif { [lsearch -exact $feature_set enable] >= 0 && \
+               [lsearch -exact $feature_set async_reset] >= 0 } {
+        lappend legalize_flop_types \$_DFF_P_
+        lappend legalize_flop_types \$_DFF_PN0_
+        lappend legalize_flop_types \$_DFFE_PP_
+        lappend legalize_flop_types \$_DFFE_PN0P_
+    } elseif { [lsearch -exact $feature_set enable] >= 0 } {
+        lappend legalize_flop_types \$_DFF_P_
+        lappend legalize_flop_types \$_DFF_P??_
+        lappend legalize_flop_types \$_DFFE_PP_
+        lappend legalize_flop_types \$_DFFE_P??P_
+    } elseif { [lsearch -exact $feature_set async_set] >= 0 && \
+               [lsearch -exact $feature_set async_reset] >= 0 } {
+        lappend legalize_flop_types \$_DFF_P_
+        lappend legalize_flop_types \$_DFF_PN?_
+        lappend legalize_flop_types \$_DFFSR_PNN_
+    } elseif { [lsearch -exact $feature_set async_set] >= 0 } {
+        lappend legalize_flop_types \$_DFF_P_
+        lappend legalize_flop_types \$_DFF_PN1_
+    } elseif { [lsearch -exact $feature_set async_reset] >= 0 } {
+        lappend legalize_flop_types \$_DFF_P_
+        lappend legalize_flop_types \$_DFF_PN0_
+    } else {
+        # Choose to legalize to async resets even though they
+        # won't tech map.  Goal is to get the user to fix
+        # their code and put in synchronous resets
+        lappend legalize_flop_types \$_DFF_P_
+        lappend legalize_flop_types \$_DFF_P??_
+    }
+
+    set legalize_list []
+    foreach flop_type $legalize_flop_types {
+        lappend legalize_list -cell $flop_type 01
+    }
+    yosys log "Legalize list: $legalize_list"
+    yosys dfflegalize {*}$legalize_list
+}
+
+proc get_dsp_options { sc_syn_dsp_options } {
+
+    set option_text [ list ]
+    foreach dsp_option $sc_syn_dsp_options {
+        lappend option_text -D $dsp_option
+    }
+    return $option_text
+}
+
+set sc_partname [sc_cfg_get fpga partname]
+set build_dir [sc_cfg_get option builddir]
+set job_name [sc_cfg_get option jobname]
+set step [sc_cfg_get arg step]
+set index [sc_cfg_get arg index]
+
+set sc_syn_lut_size \
+    [sc_cfg_get fpga $sc_partname lutsize]
+
+if { [sc_cfg_exists fpga $sc_partname var feature_set] } {
+    set sc_syn_feature_set \
+        [sc_cfg_get fpga $sc_partname var feature_set]
+} else {
+    set sc_syn_feature_set [ list ]
+}
+
+if { [sc_cfg_exists fpga $sc_partname var yosys_dsp_options] } {
+    yosys log "Process Yosys DSP techmap options."
+    set sc_syn_dsp_options \
+        [sc_cfg_get fpga $sc_partname var yosys_dsp_options]
+    yosys log "Yosys DSP techmap options = $sc_syn_dsp_options"
+} else {
+    set sc_syn_dsp_options [ list ]
+}
+
+# TODO: add logic that remaps yosys built in name based on part number
+
+# Run this first to handle module instantiations in generate blocks -- see
+# comment in syn_asic.tcl for longer explanation.
+yosys hierarchy -top $sc_design
+
+if { [string match {ice*} $sc_partname] } {
+    yosys synth_ice40 -top $sc_design -json "${sc_design}.netlist.json"
+} else {
+
+    # Pre-processing step:  if DSPs instance are hard-coded into
+    # the user's design, we can use a blackbox flow for DSP mapping
+    # as follows:
+
+    if { [sc_cfg_exists fpga $sc_partname file yosys_macrolib] } {
+
+        set sc_syn_macrolibs \
+            [sc_cfg_get fpga $sc_partname file yosys_macrolib]
+
+        foreach macrolib $sc_syn_macrolibs {
+            yosys read_verilog -lib $macrolib
+        }
+    }
+
+    # Match VPR reference flow's hierarchy check, including their comments
+
+    yosys proc
+    yosys flatten
+
+    #Generic optimization passes; this is a fusion of the VTR reference
+    #flow and the Yosys synth_ice40 flow
+    yosys opt_expr
+    yosys opt_clean
+    yosys check
+    yosys opt -nodffe -nosdff
+    yosys fsm
+    yosys opt
+    yosys wreduce
+    yosys peepopt
+    yosys opt_clean
+    yosys share
+    yosys techmap -map +/cmp2lut.v -D LUT_WIDTH=$sc_syn_lut_size
+    yosys opt_expr
+    yosys opt_clean
+
+    #Map DSP blocks before doing anything else,
+    #so that we don't convert any math blocks
+    #into other primitives
+
+    # Note there are two possibilities for how mapping might be done:
+    # using the extract command (to pattern match user RTL against
+    # the techmap) or using the techmap command.  The latter is better
+    # for mapping simple multipliers; the former is better (for now)
+    # for mapping more complex DSP blocks (MAC, pipelined blocks, etc).
+    # and also more extensible to arbitrary hard macros.  Run separate
+    # passes of both to get best of both worlds
+
+    if { [sc_cfg_exists fpga $sc_partname file yosys_extractlib] } {
+        set sc_syn_extractlibs \
+            [sc_cfg_get fpga $sc_partname file yosys_extractlib]
+
+        foreach extractlib $sc_syn_extractlibs {
+            yosys log "Run extract with $extractlib"
+            yosys extract -map $extractlib
+        }
+    }
+
+    if { [sc_cfg_exists fpga $sc_partname file yosys_dsp_techmap] } {
+        set sc_syn_dsp_library \
+            [sc_cfg_get fpga $sc_partname file yosys_dsp_techmap]
+
+        yosys log "Run techmap flow for DSP Blocks"
+        set formatted_dsp_options [get_dsp_options $sc_syn_dsp_options]
+        yosys techmap -map +/mul2dsp.v -map $sc_syn_dsp_library \
+            {*}$formatted_dsp_options
+
+        post_techmap
+    }
+
+    #Mimic ICE40 flow by running an alumacc and memory -nomap passes
+    #after DSP mapping
+    yosys alumacc
+    yosys opt
+    yosys memory -nomap
+    yosys opt -full
+
+    yosys techmap -map +/techmap.v
+
+    set sc_syn_memory_libmap ""
+    if { [sc_cfg_exists fpga $sc_partname file yosys_memory_libmap] } {
+        set sc_syn_memory_libmap \
+            [sc_cfg_get fpga $sc_partname file yosys_memory_libmap]
+    }
+    set sc_do_rom_map [expr { [lsearch -exact $sc_syn_feature_set mem_init] < 0 }]
+    set sc_syn_memory_library ""
+    if { [sc_cfg_exists fpga $sc_partname file yosys_memory_techmap] } {
+        set sc_syn_memory_library \
+            [sc_cfg_get fpga $sc_partname file yosys_memory_techmap]
+    }
+
+    if { [sc_map_memory $sc_syn_memory_libmap $sc_syn_memory_library $sc_do_rom_map] } {
+        post_techmap
+    }
+
+    #After doing memory mapping, turn any remaining
+    #$mem_v2 instances into flop arrays
+    yosys memory_map
+    yosys demuxmap
+    yosys simplemap
+
+    legalize_flops $sc_syn_feature_set
+
+    if { [sc_cfg_exists fpga $sc_partname file yosys_flop_techmap] } {
+        set sc_syn_flop_library \
+            [sc_cfg_get fpga $sc_partname file yosys_flop_techmap]
+        yosys techmap -map $sc_syn_flop_library
+
+        post_techmap
+    }
+
+    #Perform preliminary buffer insertion before passing to ABC to help reduce
+    #the overhead of final buffer insertion downstream
+    yosys insbuf
+
+    yosys abc -lut $sc_syn_lut_size
+
+    yosys setundef -zero
+    yosys clean -purge
+}
+
+yosys echo off
+yosys tee -o ./reports/stat.json stat -json -top $sc_design
+yosys echo on
+
+########################################################
+# Write Netlist
+########################################################
+yosys write_blif "outputs/${sc_design}.blif"
+yosys write_json "outputs/${sc_design}.netlist.json"

siliconcompiler/tools/yosys/syn_strategies.tcl

@@ -0,0 +1,81 @@
+# ABC scripts
+# Adapted from:
+# https://github.com/The-OpenROAD-Project/OpenLane/blob/23b9177502c19ef749836aef8f4ee06416961a18/scripts/synth.tcl
+
+# OpenLANE defaults
+# TODO: we can introduce a flag to allow the user to choose between these "fine
+# tuning" variations
+set buffering 1
+set sizing 0
+
+set abc_rs_K    "resub,-K,"
+set abc_rs      "resub"
+set abc_rsz     "resub,-z"
+set abc_rw_K    "rewrite,-K,"
+set abc_rw      "rewrite"
+set abc_rwz     "rewrite,-z"
+set abc_rf      "refactor"
+set abc_rfz     "refactor,-z"
+set abc_b       "balance"
+
+set abc_resyn2        "${abc_b}; ${abc_rw}; ${abc_rf}; ${abc_b}; ${abc_rw}; ${abc_rwz}; ${abc_b}; ${abc_rfz}; ${abc_rwz}; ${abc_b}"
+set abc_share         "strash; multi,-m; ${abc_resyn2}"
+set abc_resyn2a       "${abc_b};${abc_rw};${abc_b};${abc_rw};${abc_rwz};${abc_b};${abc_rwz};${abc_b}"
+set abc_resyn3        "balance;resub;resub,-K,6;balance;resub,-z;resub,-z,-K,6;balance;resub,-z,-K,5;balance"
+set abc_resyn2rs      "${abc_b};${abc_rs_K},6;${abc_rw};${abc_rs_K},6,-N,2;${abc_rf};${abc_rs_K},8;${abc_rw};${abc_rs_K},10;${abc_rwz};${abc_rs_K},10,-N,2;${abc_b},${abc_rs_K},12;${abc_rfz};${abc_rs_K},12,-N,2;${abc_rwz};${abc_b}"
+
+set abc_choice        "fraig_store; ${abc_resyn2}; fraig_store; ${abc_resyn2}; fraig_store; fraig_restore"
+set abc_choice2      "fraig_store; balance; fraig_store; ${abc_resyn2}; fraig_store; ${abc_resyn2}; fraig_store; ${abc_resyn2}; fraig_store; fraig_restore"
+
+set abc_map_old_cnt			"map,-p,-a,-B,0.2,-A,0.9,-M,0"
+set abc_map_old_dly         "map,-p,-B,0.2,-A,0.9,-M,0"
+set abc_retime_area         "retime,-D,{D},-M,5"
+set abc_retime_dly          "retime,-D,{D},-M,6"
+set abc_map_new_area        "amap,-m,-Q,0.1,-F,20,-A,20,-C,5000"
+
+set abc_area_recovery_1       "${abc_choice}; map;"
+set abc_area_recovery_2       "${abc_choice2}; map;"
+
+set map_old_cnt			    "map,-p,-a,-B,0.2,-A,0.9,-M,0"
+set map_old_dly			    "map,-p,-B,0.2,-A,0.9,-M,0"
+set abc_retime_area   	"retime,-D,{D},-M,5"
+set abc_retime_dly    	"retime,-D,{D},-M,6"
+set abc_map_new_area  	"amap,-m,-Q,0.1,-F,20,-A,20,-C,5000"
+
+if {$buffering==1} {
+	# TODO: reintroduce the arguments to buffer: max_FO is a
+	# synthesis-specific max fanout argument, while max_Tran defaults to
+	# 0.1x the clock period. However, since the Yosys default script uses the default
+	# arguments to buffer, this should be safe to skip for now.
+
+	# set abc_fine_tune		"buffer,-N,${max_FO},-S,${max_Tran};upsize,{D};dnsize,{D}"
+	set abc_fine_tune		"buffer;upsize,{D};dnsize,{D}"
+} elseif {$sizing} {
+	set abc_fine_tune       "upsize,{D};dnsize,{D}"
+} else {
+	set abc_fine_tune       ""
+}
+
+# TODO: all of these scripts used to begin with a call to `read_constr` which
+# took in a pass to an SDC file. In OpenLANE, this file was autogenerated and
+# only includes a set_driving_cell and set_load call that are set up based on
+# user-provided params (i.e. not a user-provided SDC file). We can consider
+# adding something like this back if we want.
+
+# Also had to adjust each script to rewrite 'retime,-D,{D}' as 'retime,{D}' to
+# avoid errors when a -D flag isn't passed in. I think this should be equivalent
+# -- the default Yosys scripts use a similar syntax.
+
+dict set syn_strategies "DELAY0" "+fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_dly}; scleanup;${abc_map_old_dly};retime,{D};${abc_fine_tune};stime,-p;print_stats -m"
+dict set syn_strategies "DELAY1" "+fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_dly}; scleanup;${abc_choice2};${abc_map_old_dly};${abc_area_recovery_2}; retime,{D};${abc_fine_tune};stime,-p;print_stats -m"
+dict set syn_strategies "DELAY2" "+fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_dly}; scleanup;${abc_choice};${abc_map_old_dly};${abc_area_recovery_1}; retime,{D};${abc_fine_tune};stime,-p;print_stats -m"
+dict set syn_strategies "DELAY3" "+fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};${abc_choice2};${abc_map_old_dly};retime,{D};${abc_fine_tune};stime,-p;print_stats -m"
+dict set syn_strategies "AREA0" "+fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};retime,{D};${abc_fine_tune};stime,-p;print_stats -m"
+dict set syn_strategies "AREA1" "+fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};${abc_choice2};${abc_map_new_area};retime,{D};${abc_fine_tune};stime,-p;print_stats -m"
+dict set syn_strategies "AREA2" "+fx;mfs;strash;refactor;${abc_choice2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};${abc_choice2};${abc_map_new_area};retime,{D};${abc_fine_tune};stime,-p;print_stats -m"
+
+# Adopted from: https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/3c605819af855200bf567bfd04b7309218cc8013/flow/scripts/abc_area.script
+dict set syn_strategies "AREA3" "+strash;dch;map,-B,0.9;topo;stime,-c;buffer,-c;upsize,-c;dnsize,-c;stime,-p;print_stats,-m"
+# Adopted from: https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/3c605819af855200bf567bfd04b7309218cc8013/flow/scripts/abc_speed.script
+set or_abc_loop "&get,-n;&st;&syn2;&if,-g,-K,6;&synch2;&nf;&put"
+dict set syn_strategies "DELAY4" "+&get,-n;&st;&dch;&nf;&put;${or_abc_loop};${or_abc_loop};${or_abc_loop};${or_abc_loop};${or_abc_loop};buffer,-c;topo;stime,-c;upsize,-c;dnsize,-c;stime,-p;print_stats,-m"

siliconcompiler/tools/yosys/techmaps/lcu_kogge_stone.v

@@ -0,0 +1,39 @@
+(* techmap_celltype = "$lcu" *)
+module _80_lcu_kogge_stone (
+    P,
+    G,
+    CI,
+    CO
+);
+    parameter WIDTH = 2;
+
+    (* force_downto *)
+    input [WIDTH-1:0] P, G;
+    input CI;
+
+    (* force_downto *)
+    output [WIDTH-1:0] CO;
+
+    integer i, j;
+    (* force_downto *)
+    reg [WIDTH-1:0] p, g;
+
+    wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
+
+    always @* begin
+        p = P;
+        g = G;
+
+        // in almost all cases CI will be constant zero
+        g[0] = g[0] | (p[0] & CI);
+
+        for (i = 0; i < $clog2(WIDTH); i = i + 1) begin
+            for (j = WIDTH - 1; j >= 2 ** i; j = j - 1) begin
+                g[j] = g[j] | p[j] & g[j-2**i];
+                p[j] = p[j] & p[j-2**i];
+            end
+        end
+    end
+
+    assign CO = g;
+endmodule

siliconcompiler/tools/yosys/templates/abc.const

@@ -0,0 +1,2 @@
+{% if abc_driver %}set_driving_cell {{ abc_driver }}{% endif %}
+{% if abc_load %}set_load {{ abc_load }}{% endif %}

siliconcompiler/tools/yosys/yosys.py

@@ -0,0 +1,147 @@
+'''
+Yosys is a framework for RTL synthesis that takes synthesizable
+Verilog-2005 design and converts it to BLIF, EDIF, BTOR, SMT,
+Verilog netlist etc. The tool supports logical synthesis and
+tech mapping to ASIC standard cell libraries, FPGA architectures.
+In addition it has built in formal methods for property and
+equivalence checking.
+
+Documentation: https://yosyshq.readthedocs.io/projects/yosys/en/latest/
+
+Sources: https://github.com/YosysHQ/yosys
+
+Installation: https://github.com/YosysHQ/yosys
+'''
+
+import re
+import json
+from siliconcompiler import sc_open
+from siliconcompiler.tools._common import get_tool_task, record_metric
+
+
+######################################################################
+# Make Docs
+######################################################################
+def make_docs(chip):
+    chip.load_target("asap7_demo")
+
+
+################################
+# Setup Tool (pre executable)
+################################
+def setup(chip):
+    ''' Tool specific function to run before step execution
+    '''
+
+    # If the 'lock' bit is set, don't reconfigure.
+    tool = 'yosys'
+    refdir = 'tools/' + tool
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    _, task = get_tool_task(chip, step, index)
+
+    # Standard Setup
+    chip.set('tool', tool, 'exe', 'yosys')
+    chip.set('tool', tool, 'vswitch', '--version')
+    chip.set('tool', tool, 'version', '>=0.41', clobber=False)
+    chip.set('tool', tool, 'format', 'tcl', clobber=False)
+
+    # Task Setup
+    # common to all
+    option = []
+    if chip.get('option', 'breakpoint', step=step, index=index):
+        option.append('-C')
+    option.append('-c')
+    chip.set('tool', tool, 'task', task, 'option', option, step=step, index=index, clobber=False)
+    chip.set('tool', tool, 'task', task, 'refdir', refdir, step=step, index=index,
+             package='siliconcompiler', clobber=False)
+    chip.set('tool', tool, 'task', task, 'regex', 'warnings', "Warning:",
+             step=step, index=index, clobber=False)
+    chip.set('tool', tool, 'task', task, 'regex', 'errors', "^ERROR",
+             step=step, index=index, clobber=False)
+
+
+################################
+# Version Check
+################################
+def parse_version(stdout):
+    # Yosys 0.9+3672 (git sha1 014c7e26, gcc 7.5.0-3ubuntu1~18.04 -fPIC -Os)
+    return stdout.split()[1]
+
+
+def normalize_version(version):
+    # Replace '+', which represents a "local version label", with '-', which is
+    # an "implicit post release number".
+    return version.replace('+', '-')
+
+
+def syn_setup(chip):
+    ''' Helper method for configs specific to synthesis tasks.
+    '''
+
+    # Generic tool setup.
+    setup(chip)
+
+    tool = 'yosys'
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    _, task = get_tool_task(chip, step, index)
+    design = chip.top()
+
+    # Set yosys script path.
+    chip.set('tool', tool, 'task', task, 'script', 'sc_syn.tcl',
+             step=step, index=index, clobber=False)
+
+    # Input/output requirements.
+    chip.set('tool', tool, 'task', task, 'input', design + '.v', step=step, index=index)
+    chip.set('tool', tool, 'task', task, 'output', design + '.vg', step=step, index=index)
+
+
+##################################################
+def syn_post_process(chip):
+    ''' Tool specific function to run after step execution
+    '''
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+
+    with sc_open("reports/stat.json") as f:
+        metrics = json.load(f)
+        if "design" in metrics:
+            metrics = metrics["design"]
+
+        if "area" in metrics:
+            record_metric(chip, step, index, 'cellarea',
+                          float(metrics["area"]),
+                          "reports/stat.json",
+                          source_unit='um^2')
+        if "num_cells" in metrics:
+            record_metric(chip, step, index, 'cells',
+                          metrics["num_cells"],
+                          "reports/stat.json")
+        if "num_wire_bits" in metrics:
+            record_metric(chip, step, index, 'nets',
+                          metrics["num_wire_bits"],
+                          "reports/stat.json")
+        if "num_port_bits" in metrics:
+            record_metric(chip, step, index, 'pins',
+                          metrics["num_port_bits"],
+                          "reports/stat.json")
+
+    registers = None
+    with sc_open(f"{step}.log") as f:
+        for line in f:
+            line_registers = re.findall(r"^\s*mapped ([0-9]+) \$_DFF.*", line)
+            if line_registers:
+                if registers is None:
+                    registers = 0
+                registers += int(line_registers[0])
+    if registers is not None:
+        record_metric(chip, step, index, 'registers', registers, f"{step}.log")
+
+
+##################################################
+if __name__ == "__main__":
+
+    chip = make_docs()
+    chip.write_manifest("yosys.json")