siliconcompiler 0.26.5__py3-none-any.whl

siliconcompiler/tools/_common/sdc/sc_constraints.sdc

@@ -0,0 +1,76 @@
+# Default constraints file that sets up clocks based on definitions in schema.
+
+source sc_manifest.tcl > /dev/null
+
+### Create clocks
+if { [sc_cfg_exists datasheet pin] } {
+    set clock_idx 0
+    foreach pin [dict keys [sc_cfg_get datasheet pin]] {
+        if { [sc_cfg_get datasheet pin $pin type global] == "clock" } {
+            # If clock...
+
+            set periodtuple [sc_cfg_get datasheet pin $pin tperiod global]
+            set period [sta::time_sta_ui [lindex $periodtuple 1]]
+            set jittertuple [sc_cfg_get datasheet pin $pin tjitter global]
+            set jitter [sta::time_sta_ui [lindex $jittertuple 1]]
+
+            set clk_name "clk${clock_idx}"
+            incr clock_idx
+
+            set period_fmt \
+                [sta::format_time [sta::time_ui_sta $period] 3][sta::unit_scale_abbreviation time]
+            set jitter_fmt \
+                [sta::format_time [sta::time_ui_sta $jitter] 3][sta::unit_scale_abbreviation time]
+            puts \
+                "Creating clock $clk_name with ${period_fmt}s period and ${jitter_fmt}s jitter."
+            create_clock -name $clk_name -period $period $pin
+            set_clock_uncertainty $jitter [get_clock $clk_name]
+        }
+    }
+}
+
+### Create IO constraints
+set sc_sdc_buffer []
+if { [sc_cfg_tool_task_exists {var} sdc_buffer] } {
+    set sc_sdc_buffer [sc_cfg_tool_task_get {var} sdc_buffer]
+}
+set buffer_cell "NULL"
+if { [llength $sc_sdc_buffer] == 0 } {
+    foreach cell [get_lib_cells *] {
+        if { [get_property $cell is_buffer] } {
+            # Find first buffer and use that as IO constraints
+            set buffer_cell $cell
+            break
+        }
+    }
+} else {
+    set buffer_cell [get_lib_cells [lindex $sc_sdc_buffer 0]]
+}
+
+if { $buffer_cell != "NULL" && $buffer_cell != "" } {
+    puts "Using [get_name $buffer_cell] as the SDC IO constraint cell"
+
+    set driving_port "NULL"
+    set load_cap 0.0
+    set port_itr [$buffer_cell liberty_port_iterator]
+    while { [$port_itr has_next] } {
+        set port [$port_itr next]
+        set pcap [$port capacitance NULL max]
+        if { [get_property $port direction] == "input" } {
+            set load_cap [expr { 10 * $pcap }]
+        } elseif { [get_property $port direction] == "output" } {
+            set driving_port [get_name $port]
+        }
+    }
+    $port_itr finish
+
+    if { $load_cap > 0.0 } {
+        set cap_fmt [sta::format_capacitance $load_cap 3][sta::unit_scale_abbreviation capacitance]
+        puts "Setting output load constraint to ${cap_fmt}F."
+        set_load [sta::capacitance_sta_ui $load_cap] [all_outputs]
+    }
+    if { $driving_port != "NULL" } {
+        puts "Setting input driving pin constraint to [get_name $buffer_cell]/$driving_port."
+        set_driving_cell -lib_cell [$buffer_cell name] -pin $driving_port [all_inputs]
+    }
+}

siliconcompiler/tools/_common/tcl/sc_pin_constraints.tcl

@@ -0,0 +1,63 @@
+proc sc_collect_pin_constraints { \
+    placement_pins_arg \
+    ordered_pins_arg \
+    sc_side_layer_func \
+    { print_func puts } } {
+
+    upvar 1 $placement_pins_arg placement_pins
+    upvar 1 $ordered_pins_arg ordered_pins
+
+    set pin_order [dict create]
+    set placement_pins [list ]
+
+    dict for {name params} [sc_cfg_get constraint pin] {
+        set order [dict get $params order]
+        set side [dict get $params side]
+        set place [dict get $params placement]
+
+        if { [llength $place] != 0 } {
+            # Pin has placement information
+            if { [llength $order] != 0 } {
+                # Pin also has order information
+                $print_func "Pin $name has placement specified in constraints, but also order."
+            }
+            lappend placement_pins $name
+        } else {
+            # Pin doesn't have placement
+            if { [llength $side] == 0 || [llength $order] == 0 } {
+                # Pin information is incomplete
+                $print_func \
+                    "Warning: Pin $name doesn't have enough information to perform placement."
+            } else {
+                set side [lindex $side 0]
+                set order [lindex $order 0]
+                if { ![dict exists $pin_order $side $order] } {
+                    dict set pin_order $side $order []
+                }
+
+                set pin_list [dict get $pin_order $side $order]
+                lappend pin_list $name
+                dict set pin_order $side $order $pin_list
+            }
+        }
+    }
+
+    set ordered_pins [dict create]
+    dict for {side pins} $pin_order {
+        if { [dict size $pins] == 0 } {
+            continue
+        }
+
+        set side_pin_order []
+        dict for {index pin} $pins {
+            lappend side_pin_order {*}$pin
+        }
+
+        set pin_layer_ordering [dict create]
+        foreach pin $side_pin_order {
+            set layer [$sc_side_layer_func $pin]
+            dict lappend pin_layer_ordering $layer $pin
+        }
+        dict set ordered_pins $side $pin_layer_ordering
+    }
+}

siliconcompiler/tools/bambu/bambu.py

@@ -0,0 +1,32 @@
+'''
+The primary objective of the PandA project is to develop a usable framework that will
+enable the research of new ideas in the HW-SW Co-Design field.
+
+The PandA framework includes methodologies supporting the research on high-level synthesis
+of hardware accelerators, on parallelism extraction for embedded systems, on hardware/software
+partitioning and mapping, on metrics for performance estimation of embedded software
+applications and on dynamic reconfigurable devices.
+
+Documentation: https://github.com/ferrandi/PandA-bambu
+
+Sources: https://github.com/ferrandi/PandA-bambu
+
+Installation: https://panda.dei.polimi.it/?page_id=88
+'''
+
+from siliconcompiler.tools.bambu import convert
+
+
+####################################################################
+# Make Docs
+####################################################################
+def make_docs(chip):
+    convert.setup(chip)
+    return chip
+
+
+def parse_version(stdout):
+    # Long multiline output, but second-to-last line looks like:
+    # Version: PandA 0.9.6 - Revision 5e5e306b86383a7d85274d64977a3d71fdcff4fe-main
+    version_line = stdout.split('\n')[-3]
+    return version_line.split()[2]

siliconcompiler/tools/bambu/convert.py

@@ -0,0 +1,77 @@
+import os
+import shutil
+from siliconcompiler.tools._common import \
+    add_frontend_requires, add_require_input, get_frontend_options, get_input_files, \
+    get_tool_task, has_input_files
+
+
+def setup(chip):
+    '''
+    Performs high level synthesis to generate a verilog output
+    '''
+
+    if not has_input_files(chip, 'input', 'hll', 'c'):
+        return "no files in [input,hll,c]"
+
+    tool = 'bambu'
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    _, task = get_tool_task(chip, step, index)
+
+    # Standard Setup
+    refdir = 'tools/' + tool
+    chip.set('tool', tool, 'exe', 'bambu')
+    chip.set('tool', tool, 'vswitch', '--version')
+    chip.set('tool', tool, 'version', '>=2024.03', clobber=False)
+
+    chip.set('tool', tool, 'task', task, 'refdir', refdir,
+             step=step, index=index,
+             package='siliconcompiler', clobber=False)
+    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+             step=step, index=index, clobber=False)
+
+    # Input/Output requirements
+    chip.add('tool', tool, 'task', task, 'output', chip.top() + '.v', step=step, index=index)
+
+    # Schema requirements
+    add_require_input(chip, 'input', 'hll', 'c')
+    add_frontend_requires(chip, ['idir', 'define'])
+
+
+################################
+#  Custom runtime options
+################################
+def runtime_options(chip):
+    cmdlist = []
+
+    cmdlist.append('--memory-allocation-policy=NO_BRAM')
+
+    opts = get_frontend_options(chip, ['idir', 'define'])
+
+    for value in opts['idir']:
+        cmdlist.append('-I' + value)
+    for value in opts['define']:
+        cmdlist.append('-D' + value)
+    for value in get_input_files(chip, 'input', 'hll', 'c'):
+        cmdlist.append(value)
+
+    cmdlist.append('--memory-allocation-policy=NO_BRAM')
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+
+    cmdlist.append(f'--top-fname={chip.top(step, index)}')
+
+    return cmdlist
+
+
+################################
+# Post_process (post executable)
+################################
+def post_process(chip):
+    ''' Tool specific function to run after step execution
+    '''
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+
+    shutil.copy2(f'{chip.top(step, index)}.v', os.path.join('outputs', f'{chip.top()}.v'))

siliconcompiler/tools/bluespec/bluespec.py

@@ -0,0 +1,40 @@
+
+'''
+Bluespec is a high-level hardware description language. It has a variety of
+advanced features including a powerful type system that can prevent errors
+prior to synthesis time, and its most distinguishing feature, Guarded Atomic
+Actions, allow you to define hardware components in a modular manner based
+on their invariants, and let the compiler pick a scheduler.
+
+Documentation: https://github.com/B-Lang-org/bsc#documentation
+
+Sources: https://github.com/B-Lang-org/bsc
+
+Installation: https://github.com/B-Lang-org/bsc#download
+'''
+
+from siliconcompiler.tools.bluespec import convert
+
+
+####################################################################
+# Make Docs
+####################################################################
+def make_docs(chip):
+    convert.setup(chip)
+    return chip
+
+
+# Directory inside step/index dir to store bsc intermediate results.
+VLOG_DIR = 'verilog'
+
+
+################################
+# Setup Tool (pre executable)
+################################
+def parse_version(stdout):
+    # Examples:
+    # Bluespec Compiler, version 2021.12.1-27-g9a7d5e05 (build 9a7d5e05)
+    # Bluespec Compiler, version 2021.07 (build 4cac6eba)
+
+    long_version = stdout.split()[3]
+    return long_version.split('-')[0]

siliconcompiler/tools/bluespec/convert.py

@@ -0,0 +1,103 @@
+import os
+import shutil
+from siliconcompiler.tools._common import \
+    add_require_input, add_frontend_requires, get_frontend_options, get_input_files, \
+    get_tool_task, has_input_files
+from siliconcompiler import sc_open
+
+# Directory inside step/index dir to store bsc intermediate results.
+VLOG_DIR = 'verilog'
+
+
+def setup(chip):
+    '''
+    Performs high level synthesis to generate a verilog output
+    '''
+
+    if not has_input_files(chip, 'input', 'hll', 'bsv'):
+        return "no files in [input,hll,bsv]"
+
+    tool = 'bluespec'
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    _, task = get_tool_task(chip, step, index)
+
+    # Standard Setup
+    refdir = 'tools/' + tool
+    chip.set('tool', tool, 'exe', 'bsc')
+    # This is technically the 'verbose' flag, but used alone it happens to give
+    # us the version and exit cleanly, so we'll use it here.
+    chip.set('tool', tool, 'vswitch', '-v')
+    chip.set('tool', tool, 'version', '>=2021.07', clobber=False)
+
+    chip.set('tool', tool, 'task', task, 'refdir', refdir,
+             step=step, index=index,
+             package='siliconcompiler', clobber=False)
+    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+             step=step, index=index, clobber=False)
+
+    # Input/Output requirements
+    chip.add('tool', tool, 'task', task, 'output', chip.top() + '.v', step=step, index=index)
+
+    # Schema requirements
+    add_require_input(chip, 'input', 'hll', 'bsv')
+    add_frontend_requires(chip, ['idir', 'ydir', 'define'])
+
+
+################################
+# Pre-process
+################################
+def pre_process(chip):
+    # bsc requires its output directory exists before being called.
+    if os.path.isdir(VLOG_DIR):
+        shutil.rmtree(VLOG_DIR)
+    os.makedirs(VLOG_DIR)
+
+
+################################
+#  Custom runtime options
+################################
+def runtime_options(chip):
+    cmdlist = []
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+
+    opts = get_frontend_options(chip, ['idir', 'ydir', 'define'])
+
+    cmdlist.append('-verilog')
+    cmdlist.append(f'-vdir {VLOG_DIR}')
+    cmdlist.append('-u')
+
+    cmdlist.append(f'-g {chip.top(step, index)}')
+
+    bsc_path = ':'.join(opts['ydir'] + ['%/Libraries'])
+    cmdlist.append('-p ' + bsc_path)
+
+    for value in opts['idir']:
+        cmdlist.append('-I ' + value)
+    for value in opts['define']:
+        cmdlist.append('-D ' + value)
+
+    sources = get_input_files(chip, 'input', 'hll', 'bsv', add_library_files=False)
+    if len(sources) != 1:
+        raise ValueError('Bluespec frontend only supports one source file!')
+    cmdlist.extend(sources)
+
+    return cmdlist
+
+
+################################
+# Post-process (post executable)
+################################
+def post_process(chip):
+    ''' Tool specific function to run after step execution
+    '''
+
+    # bsc outputs each compiled module to its own Verilog file, so we
+    # concatenate them all to create a pickled output we can pass along.
+    design = chip.top()
+    with open(os.path.join('outputs', f'{design}.v'), 'w') as pickled_vlog:
+        for src in os.listdir(VLOG_DIR):
+            with sc_open(os.path.join(VLOG_DIR, src)) as vlog_mod:
+                pickled_vlog.write(vlog_mod.read())

siliconcompiler/tools/builtin/_common.py

@@ -0,0 +1,155 @@
+
+from siliconcompiler import NodeStatus, SiliconCompilerError
+from siliconcompiler import utils
+import shutil
+from siliconcompiler.tools._common import get_tool_task
+from siliconcompiler.flowgraph import _get_pruned_node_inputs
+
+
+###########################################################################
+def _mux(chip, *nodes, operations=None):
+    '''
+    Shared function used for min and max calculation.
+    '''
+
+    nodelist = list(nodes)
+
+    # Keeping track of the steps/indexes that have goals met
+    failed = {}
+    for step, index in nodelist:
+        if step not in failed:
+            failed[step] = {}
+        failed[step][index] = False
+
+        if chip.get('record', 'status', step=step, index=index) == NodeStatus.ERROR:
+            failed[step][index] = True
+        else:
+            failed[step][index] = False
+
+    candidates = [(step, index) for step, index in nodelist if not failed[step][index]]
+    best_score = 0
+    for metric, op in operations:
+        if op not in ('minimum', 'maximum'):
+            raise ValueError('Invalid op')
+
+        values = [chip.get('metric', metric, step=step, index=index) for step, index in candidates]
+
+        if op == 'minimum':
+            target = min(values)
+        else:
+            target = max(values)
+
+        winners = []
+        for value, node in zip(values, candidates):
+            if value == target:
+                winners.append(node)
+        candidates = winners
+
+        if len(candidates) == 1:
+            break
+
+    if len(candidates) == 0:
+        # Restore step list and pick first step
+        candidates = nodelist
+
+    return (best_score, candidates[0])
+
+
+###########################################################################
+def _minmax(chip, *nodes, op=None):
+    '''
+    Shared function used for min and max calculation.
+    '''
+
+    if op not in ('minimum', 'maximum'):
+        raise ValueError('Invalid op')
+
+    flow = chip.get('option', 'flow')
+    nodelist = list(nodes)
+
+    # Keeping track of the steps/indexes that have goals met
+    failed = {}
+    for step, index in nodelist:
+        if step not in failed:
+            failed[step] = {}
+        failed[step][index] = False
+
+        if chip.get('record', 'status', step=step, index=index) == NodeStatus.ERROR:
+            failed[step][index] = True
+        else:
+            for metric in chip.getkeys('metric'):
+                if chip.valid('flowgraph', flow, step, index, 'goal', metric):
+                    goal = chip.get('flowgraph', flow, step, index, 'goal', metric)
+                    real = chip.get('metric', metric, step=step, index=index)
+                    if real is None:
+                        raise SiliconCompilerError(
+                            f'Metric {metric} has goal for {step}{index} '
+                            'but it has not been set.', chip=chip)
+                    if abs(real) > goal:
+                        chip.logger.warning(f"Step {step}{index} failed "
+                                            f"because it didn't meet goals for '{metric}' "
+                                            "metric.")
+                        failed[step][index] = True
+
+    # Calculate max/min values for each metric
+    max_val = {}
+    min_val = {}
+    for metric in chip.getkeys('metric'):
+        max_val[metric] = 0
+        min_val[metric] = float("inf")
+        for step, index in nodelist:
+            if not failed[step][index]:
+                real = chip.get('metric', metric, step=step, index=index)
+                if real is None:
+                    continue
+                max_val[metric] = max(max_val[metric], real)
+                min_val[metric] = min(min_val[metric], real)
+
+    # Select the minimum index
+    best_score = float('inf') if op == 'minimum' else float('-inf')
+    winner = None
+    for step, index in nodelist:
+        if failed[step][index]:
+            continue
+
+        score = 0.0
+        for metric in chip.getkeys('flowgraph', flow, step, index, 'weight'):
+            weight = chip.get('flowgraph', flow, step, index, 'weight', metric)
+            if not weight:
+                # skip if weight is 0 or None
+                continue
+
+            real = chip.get('metric', metric, step=step, index=index)
+            if real is None:
+                raise SiliconCompilerError(
+                    f'Metric {metric} has weight for {step}{index} '
+                    'but it has not been set.', chip=chip)
+
+            if not (max_val[metric] - min_val[metric]) == 0:
+                scaled = (real - min_val[metric]) / (max_val[metric] - min_val[metric])
+            else:
+                scaled = max_val[metric]
+            score = score + scaled * weight
+
+        if ((op == 'minimum' and score < best_score) or (op == 'maximum' and score > best_score)):
+            best_score = score
+            winner = (step, index)
+
+    return (best_score, winner)
+
+
+def run(chip):
+    return 0
+
+
+def post_process(chip):
+    shutil.copytree('inputs', 'outputs', dirs_exist_ok=True, copy_function=utils.link_symlink_copy)
+
+
+def _select_inputs(chip, step, index):
+    _, task = get_tool_task(chip, step, index)
+
+    chip.logger.info(f"Running builtin task '{task}'")
+
+    flow = chip.get('option', 'flow')
+    return _get_pruned_node_inputs(chip, flow, (step, index))

siliconcompiler/tools/builtin/builtin.py

@@ -0,0 +1,26 @@
+'''
+Builtin tools for SiliconCompiler
+'''
+from siliconcompiler.tools._common import input_provides, get_tool_task
+
+
+####################################################################
+# Make Docs
+####################################################################
+def make_docs(chip):
+    return chip
+
+
+def set_io_files(chip, inputs=True, outputs=True):
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    if inputs:
+        chip.set('tool', tool, 'task', task, 'input',
+                 list(input_provides(chip, step, index).keys()),
+                 step=step, index=index)
+    if outputs:
+        chip.set('tool', tool, 'task', task, 'output',
+                 list(input_provides(chip, step, index).keys()),
+                 step=step, index=index)

siliconcompiler/tools/builtin/concatenate.py

@@ -0,0 +1,85 @@
+from siliconcompiler.tools.builtin import _common
+import os
+from siliconcompiler import sc_open, SiliconCompilerError
+from siliconcompiler import utils
+from siliconcompiler.tools._common import input_provides, input_file_node_name, get_tool_task
+from siliconcompiler import flowgraph
+
+
+def setup(chip):
+    '''
+    A file concatenation pass that merges input files into a single set of outputs.
+    '''
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    input_nodes = set()
+    for nodes in input_provides(chip, step, index).values():
+        input_nodes.update(nodes)
+
+    if not input_nodes:
+        raise SiliconCompilerError("Concatenate will not receive anything")
+    if len(input_nodes) == 1:
+        # nothing to concate to so remove
+        return "no need to concatenate file"
+
+    chip.set('tool', tool, 'task', task, 'input', [], step=step, index=index)
+    chip.set('tool', tool, 'task', task, 'output', [], step=step, index=index)
+    for file, nodes in input_provides(chip, step, index).items():
+        chip.add('tool', tool, 'task', task, 'output', file,
+                 step=step, index=index)
+        for in_step, in_index in nodes:
+            chip.add('tool', tool, 'task', task, 'input',
+                     input_file_node_name(file, in_step, in_index),
+                     step=step, index=index)
+
+
+def _select_inputs(chip, step, index):
+    return _common._select_inputs(chip, step, index)
+
+
+def _gather_outputs(chip, step, index):
+    '''Return set of filenames that are guaranteed to be in outputs
+    directory after a successful run of step/index.'''
+
+    flow = chip.get('option', 'flow')
+
+    in_nodes = chip.get('flowgraph', flow, step, index, 'input')
+    in_task_outputs = [flowgraph._gather_outputs(chip, *node) for node in in_nodes]
+
+    if len(in_task_outputs) > 0:
+        return in_task_outputs[0].union(*in_task_outputs[1:])
+
+    return []
+
+
+def run(chip):
+    return _common.run(chip)
+
+
+def post_process(chip):
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+
+    def comment_flag(ext):
+        if ext.startswith('tcl'):
+            return '#'
+        if ext.startswith('v'):
+            return '//'
+        return None
+
+    for file, nodes in input_provides(chip, step, index).items():
+        comment = comment_flag(utils.get_file_ext(file))
+        with open(f'outputs/{file}', 'w') as out:
+            for in_step, in_index in nodes:
+                ifile = f'inputs/{input_file_node_name(file, in_step, in_index)}'
+                if not os.path.isfile(ifile):
+                    continue
+                with sc_open(ifile) as in_file:
+                    if comment:
+                        out.write(f'{comment} Start of SiliconCompiler input: {ifile}\n')
+                    out.write(in_file.read())
+                    if comment:
+                        out.write(f'{comment} End of SiliconCompiler input: {ifile}\n\n')

siliconcompiler/tools/builtin/join.py

@@ -0,0 +1,27 @@
+from siliconcompiler.tools.builtin import _common
+from siliconcompiler.tools.builtin import nop
+from siliconcompiler.tools.builtin.builtin import set_io_files
+
+
+def setup(chip):
+    '''
+    Merges outputs from a list of input tasks.
+    '''
+
+    set_io_files(chip)
+
+
+def _select_inputs(chip, step, index):
+    return _common._select_inputs(chip, step, index)
+
+
+def _gather_outputs(chip, step, index):
+    return nop._gather_outputs(chip, step, index)
+
+
+def run(chip):
+    return _common.run(chip)
+
+
+def post_process(chip):
+    _common.post_process(chip)