siliconcompiler 0.26.5__py3-none-any.whl

siliconcompiler/tools/slang/lint.py

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+'''
+Lint system verilog
+'''
+from siliconcompiler.tools import slang
+from siliconcompiler.tools._common import \
+    add_require_input, add_frontend_requires, get_frontend_options, get_input_files, get_tool_task
+import os
+
+
+def setup(chip):
+    slang.setup(chip)
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+             clobber=False, step=step, index=index)
+
+    add_require_input(chip, 'input', 'rtl', 'verilog')
+    add_require_input(chip, 'input', 'rtl', 'systemverilog')
+    add_frontend_requires(chip, ['ydir', 'idir', 'vlib', 'libext', 'define', 'param'])
+
+
+def runtime_options(chip):
+    options = ["-lint-only"]
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    options.extend(['-j', str(chip.get('tool', tool, 'task', task, 'threads',
+                              step=step, index=index))])
+
+    opts = get_frontend_options(chip,
+                                ['ydir',
+                                 'idir',
+                                 'vlib',
+                                 'libext',
+                                 'define',
+                                 'param'])
+
+    if opts['libext']:
+        options.append(f'--libext {",".join(opts["libext"])}')
+
+    #####################
+    # Library directories
+    #####################
+    if opts['ydir']:
+        options.append(f'-y {",".join(opts["ydir"])}')
+
+    #####################
+    # Library files
+    #####################
+    if opts['vlib']:
+        options.append(f'-libfile {",".join(opts["vlib"])}')
+
+    #####################
+    # Include paths
+    #####################
+    if opts['idir']:
+        options.append(f'--include-directory {",".join(opts["idir"])}')
+
+    #######################
+    # Variable Definitions
+    #######################
+    for value in opts['define']:
+        options.append('-D ' + value)
+
+    #######################
+    # Command files
+    #######################
+    cmdfiles = get_input_files(chip, 'input', 'cmdfile', 'f')
+    if cmdfiles:
+        options.append(f'-F {",".join(cmdfiles)}')
+
+    #######################
+    # Sources
+    #######################
+    for value in get_input_files(chip, 'input', 'rtl', 'systemverilog'):
+        options.append(value)
+    for value in get_input_files(chip, 'input', 'rtl', 'verilog'):
+        options.append(value)
+
+    #######################
+    # Top Module
+    #######################
+    options.append('--top ' + chip.top())
+
+    ###############################
+    # Parameters (top module only)
+    ###############################
+    # Set up user-provided parameters to ensure we elaborate the correct modules
+    for param, value in opts['param']:
+        options.append(f'-G {param}={value}')
+
+    return options
+
+
+def post_process(chip):
+    slang.post_process(chip)

siliconcompiler/tools/surelog/__init__.py

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+'''
+Surelog is a SystemVerilog pre-processor, parser, elaborator,
+and UHDM compiler that provides IEEE design and testbench
+C/C++ VPI and a Python AST API.
+
+Documentation: https://github.com/chipsalliance/Surelog
+
+Sources: https://github.com/chipsalliance/Surelog
+
+Installation: https://github.com/chipsalliance/Surelog
+'''
+
+import surelog
+from siliconcompiler.tools._common import get_tool_task
+
+
+################################
+# Setup Tool (pre executable)
+################################
+def setup(chip):
+    ''' Sets up default settings common to running Surelog.
+    '''
+
+    tool = 'surelog'
+    # Nothing in this method should rely on the value of 'step' or 'index', but they are used
+    # as schema keys in some important places, so we still need to fetch them.
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    exe = tool
+    _, task = get_tool_task(chip, step, index)
+
+    is_docker = chip.get('option', 'scheduler', 'name', step=step, index=index) == 'docker'
+    if not is_docker:
+        exe = surelog.get_bin()
+    else:
+        exe = surelog.get_bin('linux')
+
+    # Standard Setup
+    chip.set('tool', tool, 'exe', exe)
+    chip.set('tool', tool, 'vswitch', '--version')
+    chip.set('tool', tool, 'version', '>=1.51', clobber=False)
+
+    # We package SC wheels with a precompiled copy of Surelog installed to
+    # tools/surelog/bin. If the user doesn't have Surelog installed on their
+    # system path, set the path to the bundled copy in the schema.
+    if not surelog.has_system_surelog() and not is_docker:
+        chip.set('tool', tool, 'path', surelog.get_path(), clobber=False)
+
+    # Log file parsing
+    chip.set('tool', tool, 'task', task, 'regex', 'warnings', r'^\[WRN:',
+             step=step, index=index, clobber=False)
+    chip.set('tool', tool, 'task', task, 'regex', 'errors', r'^\[(ERR|FTL|SNT):',
+             step=step, index=index, clobber=False)
+
+    for warning in chip.get('tool', tool, 'task', task, 'warningoff', step=step, index=index):
+        chip.add('tool', tool, 'regex', step, index, 'warnings', f'-v {warning}',
+                 step=step, index=index)
+
+    chip.set('tool', tool, 'task', task, 'var', 'enable_lowmem',
+             'true/false, when true instructs Surelog to minimize its maximum memory usage.',
+             field='help')
+    chip.set('tool', tool, 'task', task, 'var', 'enable_lowmem', 'false',
+             step=step, index=index, clobber=False)
+
+    chip.set('tool', tool, 'task', task, 'var', 'disable_write_cache',
+             'true/false, when true instructs Surelog to not write to its cache.',
+             field='help')
+    chip.set('tool', tool, 'task', task, 'var', 'disable_write_cache', 'false',
+             step=step, index=index, clobber=False)
+
+    chip.set('tool', tool, 'task', task, 'var', 'disable_info',
+             'true/false, when true instructs Surelog to not log infos.',
+             field='help')
+    chip.set('tool', tool, 'task', task, 'var', 'disable_info', 'false',
+             step=step, index=index, clobber=False)
+
+    chip.set('tool', tool, 'task', task, 'var', 'disable_note',
+             'true/false, when true instructs Surelog to not log notes.',
+             field='help')
+    chip.set('tool', tool, 'task', task, 'var', 'disable_note', 'false',
+             step=step, index=index, clobber=False)
+
+
+def parse_version(stdout):
+    # Surelog --version output looks like:
+    # VERSION: 1.13
+    # BUILT  : Nov 10 2021
+
+    # grab version # by splitting on whitespace
+    return stdout.split()[1]
+
+
+def runtime_options(chip):
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    # Command-line options.
+    options = []
+
+    # With newer versions of Surelog (at least 1.35 and up), this option is
+    # necessary to make bundled versions work.
+    # TODO: why?
+    options.append('-nocache')
+
+    lowmem = chip.get('tool', tool, 'task', task, 'var', 'enable_lowmem', step=step, index=index)
+    if lowmem == ['true']:
+        options.append('-lowmem')
+
+    no_write_cache = chip.get('tool', tool, 'task', task, 'var', 'disable_write_cache', step=step,
+                              index=index)
+    if no_write_cache == ['true']:
+        options.append('-nowritecache')
+
+    no_info = chip.get('tool', tool, 'task', task, 'var', 'disable_info', step=step, index=index)
+    if no_info == ['true']:
+        options.append('-noinfo')
+
+    no_note = chip.get('tool', tool, 'task', task, 'var', 'disable_note', step=step, index=index)
+    if no_note == ['true']:
+        options.append('-nonote')
+
+    return options

siliconcompiler/tools/surelog/parse.py

@@ -0,0 +1,183 @@
+import os
+import re
+from siliconcompiler.tools._common import \
+    add_require_input, get_input_files, add_frontend_requires, get_frontend_options, \
+    get_tool_task, has_input_files
+from siliconcompiler.tools.surelog import setup as setup_tool
+from siliconcompiler.tools.surelog import runtime_options as runtime_options_tool
+from siliconcompiler import sc_open
+from siliconcompiler import utils
+
+
+##################################################
+def setup(chip):
+    '''
+    Import verilog files
+    '''
+
+    if not has_input_files(chip, 'input', 'rtl', 'verilog') and \
+       not has_input_files(chip, 'input', 'rtl', 'systemverilog'):
+        return "no files in [input,rtl,systemverilog] or [input,rtl,verilog]"
+
+    # Generic tool setup.
+    setup_tool(chip)
+
+    tool = 'surelog'
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    _, task = get_tool_task(chip, step, index)
+
+    # Runtime parameters.
+    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+             step=step, index=index, clobber=False)
+
+    # Input/Output requirements
+    chip.set('tool', tool, 'task', task, 'output', __outputfile(chip), step=step, index=index)
+
+    # Schema requirements
+    add_require_input(chip, 'input', 'rtl', 'verilog')
+    add_require_input(chip, 'input', 'rtl', 'systemverilog')
+    add_require_input(chip, 'input', 'cmdfile', 'f')
+    add_frontend_requires(chip, ['ydir', 'idir', 'vlib', 'libext', 'define', 'param'])
+
+
+################################
+#  Custom runtime options
+################################
+def runtime_options(chip):
+
+    ''' Custom runtime options, returnst list of command line options.
+    '''
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+
+    opts = get_frontend_options(chip,
+                                ['ydir',
+                                 'idir',
+                                 'vlib',
+                                 'libext',
+                                 'define',
+                                 'param'])
+
+    # Command-line options.
+    cmdlist = runtime_options_tool(chip)
+
+    # -parse is slow but ensures the SV code is valid
+    # we might want an option to control when to enable this
+    # or replace surelog with a SV linter for the validate step
+    cmdlist.append('-parse')
+    # We don't use UHDM currently, so disable. For large designs, this file is
+    # very big and takes a while to write out.
+    cmdlist.append('-nouhdm')
+
+    libext = opts['libext']
+    if libext:
+        libext_option = f"+libext+.{'+.'.join(libext)}"
+    else:
+        # default value for backwards compatibility
+        libext_option = '+libext+.sv+.v'
+    cmdlist.append(libext_option)
+
+    #####################
+    # Library directories
+    #####################
+    for value in opts['ydir']:
+        cmdlist.append('-y ' + value)
+
+    #####################
+    # Library files
+    #####################
+    for value in opts['vlib']:
+        cmdlist.append('-v ' + value)
+
+    #####################
+    # Include paths
+    #####################
+    for value in opts['idir']:
+        cmdlist.append('-I' + value)
+
+    #######################
+    # Variable Definitions
+    #######################
+    for value in opts['define']:
+        cmdlist.append('-D' + value)
+
+    #######################
+    # Command files
+    #######################
+    for value in get_input_files(chip, 'input', 'cmdfile', 'f'):
+        cmdlist.append('-f ' + value)
+
+    #######################
+    # Sources
+    #######################
+    for value in get_input_files(chip, 'input', 'rtl', 'systemverilog'):
+        cmdlist.append(value)
+    for value in get_input_files(chip, 'input', 'rtl', 'verilog'):
+        cmdlist.append(value)
+
+    #######################
+    # Top Module
+    #######################
+    cmdlist.append(f'-top {chip.top(step, index)}')
+
+    ###############################
+    # Parameters (top module only)
+    ###############################
+    # Set up user-provided parameters to ensure we elaborate the correct modules
+    for param, value in opts['param']:
+        cmdlist.append(f'-P{param}={value}')
+
+    return cmdlist
+
+
+##################################################
+def post_process(chip):
+    ''' Tool specific function to run after step execution
+    '''
+
+    filemap = []
+    with sc_open('slpp_all/file_map.lst') as filelist:
+        for mapping in filelist:
+            filemap.append(mapping)
+
+    def lookup_sources(file):
+        for fmap in filemap:
+            if fmap.startswith(file):
+                return fmap[len(file):].strip()
+        return "unknown"
+
+    # https://github.com/chipsalliance/Surelog/issues/3776#issuecomment-1652465581
+    surelog_escape = re.compile(r"#~@([a-zA-Z_0-9.\$/\:\[\] ]*)#~@")
+
+    # Look in slpp_all/file_elab.lst for list of Verilog files included in
+    # design, read these and concatenate them into one pickled output file.
+    output_template = utils.get_file_template('output.v',
+                                              root=os.path.join(os.path.dirname(__file__),
+                                                                'templates'))
+
+    with sc_open('slpp_all/file_elab.lst') as filelist, \
+            open(f'outputs/{__outputfile(chip)}', 'w') as outfile:
+        for path in filelist.read().split('\n'):
+            path = path.strip('"')
+            if not path:
+                # skip empty lines
+                continue
+            with sc_open(path) as infile:
+                source_files = lookup_sources(path)
+                unescaped_data = surelog_escape.sub(r"\\\1 ", infile.read())
+
+                outfile.write(output_template.render(
+                    source_file=source_files,
+                    content=unescaped_data
+                ))
+
+                outfile.write('\n')
+
+
+def __outputfile(chip):
+    is_systemverilog = has_input_files(chip, 'input', 'rtl', 'systemverilog')
+    if is_systemverilog:
+        return f'{chip.top()}.sv'
+    return f'{chip.top()}.v'

siliconcompiler/tools/surelog/templates/output.v

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+////////////////////////////////////////////////////////////////
+// Start of: {{ source_file }}
+
+{{ content }}
+
+// End of: {{ source_file }}
+////////////////////////////////////////////////////////////////

siliconcompiler/tools/sv2v/convert.py

@@ -0,0 +1,46 @@
+import os
+from siliconcompiler.tools._common import input_provides
+
+
+def setup(chip):
+    '''
+    Convert SystemVerilog to verilog
+    '''
+
+    chip.logger.debug("Setting up sv2v")
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+
+    topmodule = chip.top()
+    if topmodule + ".sv" not in input_provides(chip, step, index):
+        return "will not receive systemverilog to convert"
+
+    tool = 'sv2v'
+    task = 'convert'
+
+    chip.set('tool', tool, 'exe', tool)
+    chip.set('tool', tool, 'vswitch', '--numeric-version')
+    chip.set('tool', tool, 'version', '>=0.0.9', clobber=False)
+
+    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+             step=step, index=index, clobber=False)
+
+    # Since we run sv2v after the import/preprocess step, there should be no
+    # need for specifying include dirs/defines. However we don't want to pass
+    # --skip-preprocessor because there may still be unused preprocessor
+    # directives not removed by the importer and passing the --skip-preprocessor
+    # flag would cause sv2v to error.
+
+    # since this step should run after import, the top design module should be
+    # set and we can read the pickled Verilog without accessing the original
+    # sources
+    topmodule = chip.top()
+    chip.set('tool', tool, 'task', task, 'option', [], step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'option', "inputs/" + topmodule + ".sv",
+             step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'option', "--write=outputs/" + topmodule + ".v",
+             step=step, index=index)
+
+    chip.set('tool', tool, 'task', task, 'input', f'{topmodule}.sv', step=step, index=index)
+    chip.set('tool', tool, 'task', task, 'output', f'{topmodule}.v', step=step, index=index)

siliconcompiler/tools/sv2v/sv2v.py

@@ -0,0 +1,37 @@
+'''
+sv2v converts SystemVerilog (IEEE 1800-2017) to Verilog
+(IEEE 1364-2005), with an emphasis on supporting synthesizable
+language constructs. The primary goal of this project is to
+create a completely free and open-source tool for converting
+SystemVerilog to Verilog. While methods for performing this
+conversion already exist, they generally either rely on
+commercial tools, or are limited in scope.
+
+Documentation: https://github.com/zachjs/sv2v
+
+Sources: https://github.com/zachjs/sv2v
+
+Installation: https://github.com/zachjs/sv2v
+'''
+
+from siliconcompiler.tools.sv2v import convert
+
+
+####################################################################
+# Make Docs
+####################################################################
+def make_docs(chip):
+    convert.setup(chip)
+    return chip
+
+
+def parse_version(stdout):
+    # 0.0.7-130-g1aa30ea
+    return '-'.join(stdout.split('-')[:-1])
+
+
+##################################################
+if __name__ == "__main__":
+
+    chip = make_docs()
+    chip.write_manifest("sv2v.json")

siliconcompiler/tools/template/template.py

@@ -0,0 +1,125 @@
+'''
+Tool description
+
+Documentation: https://
+
+Sources: https://
+
+Installation: https://
+'''
+
+import os
+import siliconcompiler
+from siliconcompiler.tools._common import get_tool_task
+
+
+def make_docs():
+
+    chip = siliconcompiler.Chip('<design>')
+    chip.set('arg', 'step', '<step>')
+    chip.set('arg', 'index', '<index>')
+    setup(chip)
+    return chip
+
+
+def setup(chip):
+    '''
+    Setup Tool (pre executable)
+    '''
+
+    ##################################
+    # Simple settings
+    ##################################
+
+    tool = 'template'                    # tool name, must match file name
+    exe = ''                             # name of executable
+    refdir = ''                          # path to reference scripts
+    script = ''                          # path to entry script
+    options = ''                         # executable command line options
+    outputs = []                         # output files (inside ./outputs)
+    inputs = []                          # input files (inside ./inputs)
+    requires = []                        # required parameters
+    variables = {}                       # key/value tool variables
+
+    ##################################
+    # Advanced settings below
+    ##################################
+
+    # Fetching current step and index
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    _, task = get_tool_task(chip, step, index)
+
+    # Required for all
+    chip.set('tool', tool, 'exe', exe)
+    chip.set('tool', tool, 'vswitch', '-version')
+    chip.set('tool', tool, 'version', 'v2.0', clobber=False)
+
+    # Required for script tools
+    chip.set('tool', tool, 'format', 'tcl', clobber=False)
+
+    chip.set('tool', tool, 'task', task, 'option', options,
+             step=step, index=index, clobber=False)
+    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+             step=step, index=index, clobber=False)
+
+    # Required for script based tools
+    chip.set('tool', tool, 'task', task, 'refdir', refdir,
+             step=step, index=index,
+             package='siliconcompiler', clobber=False)
+    chip.set('tool', tool, 'task', task, 'script', refdir + script,
+             step=step, index=index, clobber=False)
+    for key in variables:
+        chip.set('tool', tool, 'task', task, 'var', key, variables[key],
+                 step=step, index=index, clobber=False)
+
+    # Required for checker
+    chip.add('tool', tool, 'task', task, 'output', outputs,
+             step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'input', inputs,
+             step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'require', requires,
+             step=step, index=index)
+
+
+def runtime_options(chip):
+    '''
+    Custom runtime options, returns list of command line options.
+    '''
+
+    cmdlist = []
+
+    # resolve paths using chip.find_files
+
+    return cmdlist
+
+
+def parse_version(stdout):
+    '''
+    Version check based on stdout
+    Depends on tool reported string
+    '''
+    # version = stdout.split()[1]
+    # return version.split('+')[0]
+    return 0
+
+
+def pre_process(chip):
+    '''
+    Logic to run prior to executable
+    '''
+    pass
+
+
+def post_process(chip):
+    '''
+    Logic to run after executable
+    '''
+    pass
+
+
+##################################################
+if __name__ == "__main__":
+
+    chip = make_docs()
+    chip.write_manifest("template.json")