wasmtime 24.0.0 → 25.0.0
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- checksums.yaml +4 -4
- data/Cargo.lock +112 -111
- data/ext/Cargo.toml +5 -5
- data/ext/cargo-vendor/cranelift-bforest-0.112.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-bforest-0.112.0/Cargo.toml +59 -0
- data/ext/cargo-vendor/cranelift-bforest-0.112.0/src/node.rs +806 -0
- data/ext/cargo-vendor/cranelift-bforest-0.112.0/src/path.rs +830 -0
- data/ext/cargo-vendor/cranelift-bforest-0.112.0/src/pool.rs +219 -0
- data/ext/cargo-vendor/cranelift-bitset-0.112.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-bitset-0.112.0/Cargo.toml +74 -0
- data/ext/cargo-vendor/cranelift-bitset-0.112.0/src/scalar.rs +626 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/Cargo.toml +222 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/build.rs +267 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/binemit/mod.rs +168 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/cfg_printer.rs +83 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/data_value.rs +402 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/dbg.rs +28 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/egraph.rs +835 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/incremental_cache.rs +256 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/inst_predicates.rs +207 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/ir/constant.rs +485 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/ir/dfg.rs +1802 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/ir/entities.rs +564 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/ir/extfunc.rs +408 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/ir/extname.rs +333 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/ir/function.rs +500 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/ir/globalvalue.rs +147 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/ir/immediates.rs +1941 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/ir/instructions.rs +1021 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/ir/memtype.rs +190 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/ir/progpoint.rs +75 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/ir/trapcode.rs +148 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/ir/types.rs +624 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/ir/user_stack_maps.rs +199 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/aarch64/abi.rs +1520 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/aarch64/inst/args.rs +711 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/aarch64/inst/emit.rs +3567 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/aarch64/inst/emit_tests.rs +7972 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/aarch64/inst/imms.rs +1244 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/aarch64/inst/mod.rs +3051 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/aarch64/inst/regs.rs +269 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/aarch64/inst/unwind/systemv.rs +174 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/aarch64/inst.isle +4267 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/aarch64/lower/isle.rs +811 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/aarch64/lower.isle +2968 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/aarch64/pcc.rs +570 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/aarch64/settings.rs +9 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/mod.rs +471 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/pulley32.rs +13 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/pulley64.rs +13 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/pulley_shared/abi.rs +798 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/pulley_shared/inst/args.rs +192 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/pulley_shared/inst/emit.rs +482 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/pulley_shared/inst/mod.rs +905 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/pulley_shared/inst/regs.rs +164 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/pulley_shared/inst.isle +543 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/pulley_shared/lower/isle/generated_code.rs +17 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/pulley_shared/lower/isle.rs +195 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/pulley_shared/lower.isle +178 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/pulley_shared/lower.rs +36 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/pulley_shared/mod.rs +281 -0
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- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/riscv64/abi.rs +993 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/riscv64/inst/args.rs +1957 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/riscv64/inst/emit.rs +2685 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/riscv64/inst/emit_tests.rs +2277 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/riscv64/inst/encode.rs +721 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/riscv64/inst/mod.rs +1865 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/riscv64/inst/unwind/systemv.rs +170 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/riscv64/inst/vector.rs +1150 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/riscv64/inst.isle +3128 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/riscv64/inst_vector.isle +1907 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/riscv64/lower/isle.rs +721 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/riscv64/lower.isle +2940 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/s390x/abi.rs +1348 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/s390x/inst/emit.rs +3470 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/s390x/inst/emit_tests.rs +13370 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/s390x/inst/mod.rs +3461 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/s390x/inst/regs.rs +169 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/s390x/inst/unwind/systemv.rs +212 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/s390x/inst.isle +5071 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/s390x/lower/isle.rs +1109 -0
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- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/unwind/systemv.rs +276 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/x64/abi.rs +1390 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/x64/encoding/evex.rs +747 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/x64/inst/args.rs +2318 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/x64/inst/emit.rs +4400 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/x64/inst/emit_state.rs +55 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/x64/inst/emit_tests.rs +5146 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/x64/inst/mod.rs +2811 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/x64/inst/regs.rs +275 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/x64/inst/stack_switch.rs +52 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/x64/inst/unwind/systemv.rs +198 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/x64/inst.isle +5382 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/x64/lower/isle.rs +1047 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/x64/lower.isle +4919 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/x64/lower.rs +338 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/x64/mod.rs +239 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/x64/pcc.rs +1022 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isle_prelude.rs +1144 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/lib.rs +106 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/machinst/abi.rs +2417 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/machinst/buffer.rs +2492 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/machinst/isle.rs +890 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/machinst/lower.rs +1590 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/machinst/mod.rs +560 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/machinst/reg.rs +484 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/machinst/vcode.rs +1762 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/opts/extends.isle +95 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/opts/icmp.isle +258 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/opts/selects.isle +88 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/prelude.isle +751 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/prelude_lower.isle +1081 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/print_errors.rs +223 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/remove_constant_phis.rs +419 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/result.rs +111 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/settings.rs +591 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/timing.rs +296 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/verifier/mod.rs +1941 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/write.rs +694 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.112.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.112.0/Cargo.toml +54 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.112.0/src/cdsl/settings.rs +429 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.112.0/src/cdsl/types.rs +420 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.112.0/src/cdsl/typevar.rs +946 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.112.0/src/error.rs +48 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.112.0/src/gen_inst.rs +1274 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.112.0/src/gen_isle.rs +519 -0
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- data/ext/cargo-vendor/cranelift-codegen-meta-0.112.0/src/gen_types.rs +70 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.112.0/src/isa/arm64.rs +59 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.112.0/src/isa/mod.rs +81 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.112.0/src/isa/pulley.rs +14 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.112.0/src/isa/riscv64.rs +181 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.112.0/src/isa/x86.rs +414 -0
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- data/ext/cargo-vendor/cranelift-codegen-meta-0.112.0/src/srcgen.rs +464 -0
- data/ext/cargo-vendor/cranelift-codegen-shared-0.112.0/.cargo-checksum.json +1 -0
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- data/ext/cargo-vendor/cranelift-control-0.112.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-control-0.112.0/Cargo.toml +43 -0
- data/ext/cargo-vendor/cranelift-entity-0.112.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-entity-0.112.0/Cargo.toml +75 -0
- data/ext/cargo-vendor/cranelift-entity-0.112.0/src/lib.rs +381 -0
- data/ext/cargo-vendor/cranelift-entity-0.112.0/src/packed_option.rs +173 -0
- data/ext/cargo-vendor/cranelift-entity-0.112.0/src/sparse.rs +367 -0
- data/ext/cargo-vendor/cranelift-frontend-0.112.0/.cargo-checksum.json +1 -0
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- data/ext/cargo-vendor/cranelift-frontend-0.112.0/src/frontend.rs +1963 -0
- data/ext/cargo-vendor/cranelift-frontend-0.112.0/src/ssa.rs +1325 -0
- data/ext/cargo-vendor/cranelift-frontend-0.112.0/src/switch.rs +676 -0
- data/ext/cargo-vendor/cranelift-isle-0.112.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-isle-0.112.0/Cargo.toml +69 -0
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- data/ext/cargo-vendor/cranelift-isle-0.112.0/src/compile.rs +65 -0
- data/ext/cargo-vendor/cranelift-isle-0.112.0/src/error.rs +318 -0
- data/ext/cargo-vendor/cranelift-isle-0.112.0/src/files.rs +133 -0
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- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/resources-empty.wit.json +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/resources-multiple-returns-own.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/resources-multiple-returns-own.wit.json +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/resources-multiple.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/resources-multiple.wit.json +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/resources-return-own.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/resources-return-own.wit.json +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/resources.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/resources.wit.json +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/resources1.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/resources1.wit.json +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/same-name-import-export.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/same-name-import-export.wit.json +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/shared-types.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/shared-types.wit.json +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/simple-wasm-text.wat +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/simple-wasm-text.wit.json +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/stress-export-elaborate.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/stress-export-elaborate.wit.json +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/type-then-eof.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/type-then-eof.wit.json +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/types.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/types.wit.json +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/union-fuzz-1.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/union-fuzz-1.wit.json +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/union-fuzz-2.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/union-fuzz-2.wit.json +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/use-chain.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/use-chain.wit.json +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/use.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/use.wit.json +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/version-syntax.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/version-syntax.wit.json +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/versions/deps/a1/foo.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/versions/deps/a2/foo.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/versions/foo.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/versions.wit.json +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/wasi.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/wasi.wit.json +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/world-diamond.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/world-diamond.wit.json +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/world-iface-no-collide.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/world-iface-no-collide.wit.json +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/world-implicit-import1.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/world-implicit-import1.wit.json +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/world-implicit-import2.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/world-implicit-import2.wit.json +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/world-implicit-import3.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/world-implicit-import3.wit.json +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/world-same-fields4.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/world-same-fields4.wit.json +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/world-top-level-funcs.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/world-top-level-funcs.wit.json +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/world-top-level-resources.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/world-top-level-resources.wit.json +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/worlds-union-dedup.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/worlds-union-dedup.wit.json +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/worlds-with-types.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/worlds-with-types.wit.json +0 -0
@@ -1,1410 +0,0 @@
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//! Implementation of the standard x64 ABI.
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use crate::ir::{self, types, LibCall, MemFlags, Signature, TrapCode};
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use crate::ir::{types::*, ExternalName};
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use crate::isa;
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use crate::isa::{unwind::UnwindInst, x64::inst::*, x64::settings as x64_settings, CallConv};
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use crate::machinst::abi::*;
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use crate::machinst::*;
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use crate::settings;
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use crate::{CodegenError, CodegenResult};
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use alloc::boxed::Box;
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use alloc::vec::Vec;
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use args::*;
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use regalloc2::{MachineEnv, PReg, PRegSet};
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use smallvec::{smallvec, SmallVec};
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use std::sync::OnceLock;
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/// This is the limit for the size of argument and return-value areas on the
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/// stack. We place a reasonable limit here to avoid integer overflow issues
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/// with 32-bit arithmetic: for now, 128 MB.
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static STACK_ARG_RET_SIZE_LIMIT: u32 = 128 * 1024 * 1024;
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/// Support for the x64 ABI from the callee side (within a function body).
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pub(crate) type X64Callee = Callee<X64ABIMachineSpec>;
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/// Support for the x64 ABI from the caller side (at a callsite).
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pub(crate) type X64CallSite = CallSite<X64ABIMachineSpec>;
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/// Implementation of ABI primitives for x64.
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pub struct X64ABIMachineSpec;
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impl X64ABIMachineSpec {
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fn gen_probestack_unroll(insts: &mut SmallInstVec<Inst>, guard_size: u32, probe_count: u32) {
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insts.reserve(probe_count as usize);
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for _ in 0..probe_count {
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// "Allocate" stack space for the probe by decrementing the stack pointer before
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// the write. This is required to make valgrind happy.
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// See: https://github.com/bytecodealliance/wasmtime/issues/7454
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insts.extend(Self::gen_sp_reg_adjust(-(guard_size as i32)));
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// TODO: It would be nice if we could store the imm 0, but we don't have insts for those
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// so store the stack pointer. Any register will do, since the stack is undefined at this point
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insts.push(Inst::store(
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I32,
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regs::rsp(),
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Amode::imm_reg(0, regs::rsp()),
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));
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}
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// Restore the stack pointer to its original value
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insts.extend(Self::gen_sp_reg_adjust((guard_size * probe_count) as i32));
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}
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fn gen_probestack_loop(
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insts: &mut SmallInstVec<Inst>,
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_call_conv: isa::CallConv,
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frame_size: u32,
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guard_size: u32,
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) {
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// We have to use a caller-saved register since clobbering only
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// happens after stack probing.
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// `r11` is caller saved on both Fastcall and SystemV, and not used
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// for argument passing, so it's pretty much free. It is also not
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// used by the stacklimit mechanism.
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let tmp = regs::r11();
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debug_assert!({
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let real_reg = tmp.to_real_reg().unwrap();
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!is_callee_save_systemv(real_reg, false) && !is_callee_save_fastcall(real_reg, false)
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});
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insts.push(Inst::StackProbeLoop {
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tmp: Writable::from_reg(tmp),
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frame_size,
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guard_size,
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});
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}
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}
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impl IsaFlags for x64_settings::Flags {}
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impl ABIMachineSpec for X64ABIMachineSpec {
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type I = Inst;
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type F = x64_settings::Flags;
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fn word_bits() -> u32 {
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64
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}
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/// Return required stack alignment in bytes.
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fn stack_align(_call_conv: isa::CallConv) -> u32 {
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16
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}
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fn compute_arg_locs(
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call_conv: isa::CallConv,
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flags: &settings::Flags,
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params: &[ir::AbiParam],
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args_or_rets: ArgsOrRets,
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add_ret_area_ptr: bool,
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mut args: ArgsAccumulator,
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) -> CodegenResult<(u32, Option<usize>)> {
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let is_fastcall = call_conv.extends_windows_fastcall();
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let mut next_gpr = 0;
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let mut next_vreg = 0;
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let mut next_stack: u32 = 0;
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let mut next_param_idx = 0; // Fastcall cares about overall param index
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if args_or_rets == ArgsOrRets::Args && is_fastcall {
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// Fastcall always reserves 32 bytes of shadow space corresponding to
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// the four initial in-arg parameters.
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//
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// (See:
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// https://docs.microsoft.com/en-us/cpp/build/x64-calling-convention?view=msvc-160)
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next_stack = 32;
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}
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// If any param uses extension, the winch calling convention will not pack its results
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// on the stack and will instead align them to 8-byte boundaries the same way that all the
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// other calling conventions do. This isn't consistent with Winch itself, but is fine as
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// Winch only uses this calling convention via trampolines, and those trampolines don't add
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// extension annotations. Additionally, handling extension attributes this way allows clif
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// functions that use them with the Winch calling convention to interact successfully with
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// testing infrastructure.
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// The results are also not packed if any of the types are `f16`. This is to simplify the
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// implementation of `Inst::load`/`Inst::store` (which would otherwise require multiple
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// instructions), and doesn't affect Winch itself as Winch doesn't support `f16` at all.
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let uses_extension = params
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.iter()
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.any(|p| p.extension != ir::ArgumentExtension::None || p.value_type == types::F16);
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for (ix, param) in params.iter().enumerate() {
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let last_param = ix == params.len() - 1;
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if let ir::ArgumentPurpose::StructArgument(size) = param.purpose {
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let offset = next_stack as i64;
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let size = size;
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assert!(size % 8 == 0, "StructArgument size is not properly aligned");
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next_stack += size;
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args.push(ABIArg::StructArg {
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pointer: None,
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offset,
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size: size as u64,
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purpose: param.purpose,
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});
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continue;
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}
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// Find regclass(es) of the register(s) used to store a value of this type.
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let (rcs, reg_tys) = Inst::rc_for_type(param.value_type)?;
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// Now assign ABIArgSlots for each register-sized part.
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//
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// Note that the handling of `i128` values is unique here:
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//
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// - If `enable_llvm_abi_extensions` is set in the flags, each
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// `i128` is split into two `i64`s and assigned exactly as if it
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// were two consecutive 64-bit args, except that if one of the
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// two halves is forced onto the stack, the other half is too.
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// This is consistent with LLVM's behavior, and is needed for
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// some uses of Cranelift (e.g., the rustc backend).
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//
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// - Otherwise, both SysV and Fastcall specify behavior (use of
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// vector register, a register pair, or passing by reference
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// depending on the case), but for simplicity, we will just panic if
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// an i128 type appears in a signature and the LLVM extensions flag
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// is not set.
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//
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// For examples of how rustc compiles i128 args and return values on
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// both SysV and Fastcall platforms, see:
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// https://godbolt.org/z/PhG3ob
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if param.value_type.bits() > 64
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&& !(param.value_type.is_vector() || param.value_type.is_float())
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&& !flags.enable_llvm_abi_extensions()
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{
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panic!(
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"i128 args/return values not supported unless LLVM ABI extensions are enabled"
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);
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}
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// As MSVC doesn't support f16/f128 there is no standard way to pass/return them with
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183
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// the Windows ABI. LLVM passes/returns them in XMM registers.
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if matches!(param.value_type, types::F16 | types::F128)
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&& is_fastcall
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&& !flags.enable_llvm_abi_extensions()
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{
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panic!(
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"f16/f128 args/return values not supported for windows_fastcall unless LLVM ABI extensions are enabled"
|
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);
|
191
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}
|
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|
193
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// Windows fastcall dictates that `__m128i` parameters to a function
|
194
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// are passed indirectly as pointers, so handle that as a special
|
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// case before the loop below.
|
196
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if param.value_type.is_vector()
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&& param.value_type.bits() >= 128
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198
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&& args_or_rets == ArgsOrRets::Args
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&& is_fastcall
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{
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201
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let pointer = match get_intreg_for_arg(&call_conv, next_gpr, next_param_idx) {
|
202
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Some(reg) => {
|
203
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next_gpr += 1;
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204
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ABIArgSlot::Reg {
|
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reg: reg.to_real_reg().unwrap(),
|
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ty: ir::types::I64,
|
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|
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extension: ir::ArgumentExtension::None,
|
208
|
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}
|
209
|
-
}
|
210
|
-
|
211
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None => {
|
212
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next_stack = align_to(next_stack, 8) + 8;
|
213
|
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ABIArgSlot::Stack {
|
214
|
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offset: (next_stack - 8) as i64,
|
215
|
-
ty: ir::types::I64,
|
216
|
-
extension: param.extension,
|
217
|
-
}
|
218
|
-
}
|
219
|
-
};
|
220
|
-
next_param_idx += 1;
|
221
|
-
args.push(ABIArg::ImplicitPtrArg {
|
222
|
-
// NB: this is filled in after this loop
|
223
|
-
offset: 0,
|
224
|
-
pointer,
|
225
|
-
ty: param.value_type,
|
226
|
-
purpose: param.purpose,
|
227
|
-
});
|
228
|
-
continue;
|
229
|
-
}
|
230
|
-
|
231
|
-
// SystemV dictates that 128bit int parameters are always either
|
232
|
-
// passed in two registers or on the stack, so handle that as a
|
233
|
-
// special case before the loop below.
|
234
|
-
if param.value_type == types::I128
|
235
|
-
&& args_or_rets == ArgsOrRets::Args
|
236
|
-
&& call_conv == CallConv::SystemV
|
237
|
-
{
|
238
|
-
let mut slots = ABIArgSlotVec::new();
|
239
|
-
match (
|
240
|
-
get_intreg_for_arg(&CallConv::SystemV, next_gpr, next_param_idx),
|
241
|
-
get_intreg_for_arg(&CallConv::SystemV, next_gpr + 1, next_param_idx + 1),
|
242
|
-
) {
|
243
|
-
(Some(reg1), Some(reg2)) => {
|
244
|
-
slots.push(ABIArgSlot::Reg {
|
245
|
-
reg: reg1.to_real_reg().unwrap(),
|
246
|
-
ty: ir::types::I64,
|
247
|
-
extension: ir::ArgumentExtension::None,
|
248
|
-
});
|
249
|
-
slots.push(ABIArgSlot::Reg {
|
250
|
-
reg: reg2.to_real_reg().unwrap(),
|
251
|
-
ty: ir::types::I64,
|
252
|
-
extension: ir::ArgumentExtension::None,
|
253
|
-
});
|
254
|
-
}
|
255
|
-
_ => {
|
256
|
-
let size = 16;
|
257
|
-
|
258
|
-
// Align.
|
259
|
-
next_stack = align_to(next_stack, size);
|
260
|
-
|
261
|
-
slots.push(ABIArgSlot::Stack {
|
262
|
-
offset: next_stack as i64,
|
263
|
-
ty: ir::types::I64,
|
264
|
-
extension: param.extension,
|
265
|
-
});
|
266
|
-
slots.push(ABIArgSlot::Stack {
|
267
|
-
offset: next_stack as i64 + 8,
|
268
|
-
ty: ir::types::I64,
|
269
|
-
extension: param.extension,
|
270
|
-
});
|
271
|
-
next_stack += size;
|
272
|
-
}
|
273
|
-
};
|
274
|
-
// Unconditionally increment next_gpr even when storing the
|
275
|
-
// argument on the stack to prevent reusing a possibly
|
276
|
-
// remaining register for the next argument.
|
277
|
-
next_gpr += 2;
|
278
|
-
next_param_idx += 2;
|
279
|
-
|
280
|
-
args.push(ABIArg::Slots {
|
281
|
-
slots,
|
282
|
-
purpose: param.purpose,
|
283
|
-
});
|
284
|
-
continue;
|
285
|
-
}
|
286
|
-
|
287
|
-
let mut slots = ABIArgSlotVec::new();
|
288
|
-
for (ix, (rc, reg_ty)) in rcs.iter().zip(reg_tys.iter()).enumerate() {
|
289
|
-
let last_slot = last_param && ix == rcs.len() - 1;
|
290
|
-
|
291
|
-
let intreg = *rc == RegClass::Int;
|
292
|
-
let nextreg = if intreg {
|
293
|
-
match args_or_rets {
|
294
|
-
ArgsOrRets::Args => {
|
295
|
-
get_intreg_for_arg(&call_conv, next_gpr, next_param_idx)
|
296
|
-
}
|
297
|
-
ArgsOrRets::Rets => {
|
298
|
-
get_intreg_for_retval(&call_conv, flags, next_gpr, last_slot)
|
299
|
-
}
|
300
|
-
}
|
301
|
-
} else {
|
302
|
-
match args_or_rets {
|
303
|
-
ArgsOrRets::Args => {
|
304
|
-
get_fltreg_for_arg(&call_conv, next_vreg, next_param_idx)
|
305
|
-
}
|
306
|
-
ArgsOrRets::Rets => get_fltreg_for_retval(&call_conv, next_vreg, last_slot),
|
307
|
-
}
|
308
|
-
};
|
309
|
-
next_param_idx += 1;
|
310
|
-
if let Some(reg) = nextreg {
|
311
|
-
if intreg {
|
312
|
-
next_gpr += 1;
|
313
|
-
} else {
|
314
|
-
next_vreg += 1;
|
315
|
-
}
|
316
|
-
slots.push(ABIArgSlot::Reg {
|
317
|
-
reg: reg.to_real_reg().unwrap(),
|
318
|
-
ty: *reg_ty,
|
319
|
-
extension: param.extension,
|
320
|
-
});
|
321
|
-
} else {
|
322
|
-
let size = reg_ty.bytes();
|
323
|
-
let size = if call_conv == CallConv::Winch
|
324
|
-
&& args_or_rets == ArgsOrRets::Rets
|
325
|
-
&& !uses_extension
|
326
|
-
{
|
327
|
-
size
|
328
|
-
} else {
|
329
|
-
let size = std::cmp::max(size, 8);
|
330
|
-
|
331
|
-
// Align.
|
332
|
-
debug_assert!(size.is_power_of_two());
|
333
|
-
next_stack = align_to(next_stack, size);
|
334
|
-
size
|
335
|
-
};
|
336
|
-
|
337
|
-
slots.push(ABIArgSlot::Stack {
|
338
|
-
offset: next_stack as i64,
|
339
|
-
ty: *reg_ty,
|
340
|
-
extension: param.extension,
|
341
|
-
});
|
342
|
-
next_stack += size;
|
343
|
-
}
|
344
|
-
}
|
345
|
-
|
346
|
-
args.push(ABIArg::Slots {
|
347
|
-
slots,
|
348
|
-
purpose: param.purpose,
|
349
|
-
});
|
350
|
-
}
|
351
|
-
|
352
|
-
// Fastcall's indirect 128+ bit vector arguments are all located on the
|
353
|
-
// stack, and stack space is reserved after all parameters are passed,
|
354
|
-
// so allocate from the space now.
|
355
|
-
if args_or_rets == ArgsOrRets::Args && is_fastcall {
|
356
|
-
for arg in args.args_mut() {
|
357
|
-
if let ABIArg::ImplicitPtrArg { offset, .. } = arg {
|
358
|
-
assert_eq!(*offset, 0);
|
359
|
-
next_stack = align_to(next_stack, 16);
|
360
|
-
*offset = next_stack as i64;
|
361
|
-
next_stack += 16;
|
362
|
-
}
|
363
|
-
}
|
364
|
-
}
|
365
|
-
|
366
|
-
let extra_arg = if add_ret_area_ptr {
|
367
|
-
debug_assert!(args_or_rets == ArgsOrRets::Args);
|
368
|
-
if let Some(reg) = get_intreg_for_arg(&call_conv, next_gpr, next_param_idx) {
|
369
|
-
args.push_non_formal(ABIArg::reg(
|
370
|
-
reg.to_real_reg().unwrap(),
|
371
|
-
types::I64,
|
372
|
-
ir::ArgumentExtension::None,
|
373
|
-
ir::ArgumentPurpose::Normal,
|
374
|
-
));
|
375
|
-
} else {
|
376
|
-
args.push_non_formal(ABIArg::stack(
|
377
|
-
next_stack as i64,
|
378
|
-
types::I64,
|
379
|
-
ir::ArgumentExtension::None,
|
380
|
-
ir::ArgumentPurpose::Normal,
|
381
|
-
));
|
382
|
-
next_stack += 8;
|
383
|
-
}
|
384
|
-
Some(args.args().len() - 1)
|
385
|
-
} else {
|
386
|
-
None
|
387
|
-
};
|
388
|
-
|
389
|
-
// Winch writes the first result to the highest offset, so we need to iterate through the
|
390
|
-
// args and adjust the offsets down.
|
391
|
-
if call_conv == CallConv::Winch && args_or_rets == ArgsOrRets::Rets {
|
392
|
-
for arg in args.args_mut() {
|
393
|
-
if let ABIArg::Slots { slots, .. } = arg {
|
394
|
-
for slot in slots.iter_mut() {
|
395
|
-
if let ABIArgSlot::Stack { offset, ty, .. } = slot {
|
396
|
-
let size = if uses_extension {
|
397
|
-
i64::from(std::cmp::max(ty.bytes(), 8))
|
398
|
-
} else {
|
399
|
-
i64::from(ty.bytes())
|
400
|
-
};
|
401
|
-
|
402
|
-
*offset = i64::from(next_stack) - *offset - size;
|
403
|
-
}
|
404
|
-
}
|
405
|
-
} else {
|
406
|
-
unreachable!("Winch cannot handle {arg:?}");
|
407
|
-
}
|
408
|
-
}
|
409
|
-
}
|
410
|
-
|
411
|
-
next_stack = align_to(next_stack, 16);
|
412
|
-
|
413
|
-
// To avoid overflow issues, limit the arg/return size to something reasonable.
|
414
|
-
if next_stack > STACK_ARG_RET_SIZE_LIMIT {
|
415
|
-
return Err(CodegenError::ImplLimitExceeded);
|
416
|
-
}
|
417
|
-
|
418
|
-
Ok((next_stack, extra_arg))
|
419
|
-
}
|
420
|
-
|
421
|
-
fn gen_load_stack(mem: StackAMode, into_reg: Writable<Reg>, ty: Type) -> Self::I {
|
422
|
-
// For integer-typed values, we always load a full 64 bits (and we always spill a full 64
|
423
|
-
// bits as well -- see `Inst::store()`).
|
424
|
-
let ty = match ty {
|
425
|
-
types::I8 | types::I16 | types::I32 => types::I64,
|
426
|
-
// Stack slots are always at least 8 bytes, so it's fine to load 4 bytes instead of only
|
427
|
-
// two.
|
428
|
-
types::F16 => types::F32,
|
429
|
-
_ => ty,
|
430
|
-
};
|
431
|
-
Inst::load(ty, mem, into_reg, ExtKind::None)
|
432
|
-
}
|
433
|
-
|
434
|
-
fn gen_store_stack(mem: StackAMode, from_reg: Reg, ty: Type) -> Self::I {
|
435
|
-
let ty = match ty {
|
436
|
-
// See `gen_load_stack`.
|
437
|
-
types::F16 => types::F32,
|
438
|
-
_ => ty,
|
439
|
-
};
|
440
|
-
Inst::store(ty, from_reg, mem)
|
441
|
-
}
|
442
|
-
|
443
|
-
fn gen_move(to_reg: Writable<Reg>, from_reg: Reg, ty: Type) -> Self::I {
|
444
|
-
Inst::gen_move(to_reg, from_reg, ty)
|
445
|
-
}
|
446
|
-
|
447
|
-
/// Generate an integer-extend operation.
|
448
|
-
fn gen_extend(
|
449
|
-
to_reg: Writable<Reg>,
|
450
|
-
from_reg: Reg,
|
451
|
-
is_signed: bool,
|
452
|
-
from_bits: u8,
|
453
|
-
to_bits: u8,
|
454
|
-
) -> Self::I {
|
455
|
-
let ext_mode = ExtMode::new(from_bits as u16, to_bits as u16)
|
456
|
-
.unwrap_or_else(|| panic!("invalid extension: {} -> {}", from_bits, to_bits));
|
457
|
-
if is_signed {
|
458
|
-
Inst::movsx_rm_r(ext_mode, RegMem::reg(from_reg), to_reg)
|
459
|
-
} else {
|
460
|
-
Inst::movzx_rm_r(ext_mode, RegMem::reg(from_reg), to_reg)
|
461
|
-
}
|
462
|
-
}
|
463
|
-
|
464
|
-
fn gen_args(args: Vec<ArgPair>) -> Inst {
|
465
|
-
Inst::Args { args }
|
466
|
-
}
|
467
|
-
|
468
|
-
fn gen_rets(rets: Vec<RetPair>) -> Inst {
|
469
|
-
Inst::Rets { rets }
|
470
|
-
}
|
471
|
-
|
472
|
-
fn gen_add_imm(
|
473
|
-
_call_conv: isa::CallConv,
|
474
|
-
into_reg: Writable<Reg>,
|
475
|
-
from_reg: Reg,
|
476
|
-
imm: u32,
|
477
|
-
) -> SmallInstVec<Self::I> {
|
478
|
-
let mut ret = SmallVec::new();
|
479
|
-
if from_reg != into_reg.to_reg() {
|
480
|
-
ret.push(Inst::gen_move(into_reg, from_reg, I64));
|
481
|
-
}
|
482
|
-
ret.push(Inst::alu_rmi_r(
|
483
|
-
OperandSize::Size64,
|
484
|
-
AluRmiROpcode::Add,
|
485
|
-
RegMemImm::imm(imm),
|
486
|
-
into_reg,
|
487
|
-
));
|
488
|
-
ret
|
489
|
-
}
|
490
|
-
|
491
|
-
fn gen_stack_lower_bound_trap(limit_reg: Reg) -> SmallInstVec<Self::I> {
|
492
|
-
smallvec![
|
493
|
-
Inst::cmp_rmi_r(OperandSize::Size64, limit_reg, RegMemImm::reg(regs::rsp())),
|
494
|
-
Inst::TrapIf {
|
495
|
-
// NBE == "> unsigned"; args above are reversed; this tests limit_reg > rsp.
|
496
|
-
cc: CC::NBE,
|
497
|
-
trap_code: TrapCode::StackOverflow,
|
498
|
-
},
|
499
|
-
]
|
500
|
-
}
|
501
|
-
|
502
|
-
fn gen_get_stack_addr(mem: StackAMode, into_reg: Writable<Reg>) -> Self::I {
|
503
|
-
let mem: SyntheticAmode = mem.into();
|
504
|
-
Inst::lea(mem, into_reg)
|
505
|
-
}
|
506
|
-
|
507
|
-
fn get_stacklimit_reg(_call_conv: isa::CallConv) -> Reg {
|
508
|
-
// As per comment on trait definition, we must return a caller-save
|
509
|
-
// register that is not used as an argument here.
|
510
|
-
debug_assert!(!is_callee_save_systemv(
|
511
|
-
regs::r10().to_real_reg().unwrap(),
|
512
|
-
false
|
513
|
-
));
|
514
|
-
regs::r10()
|
515
|
-
}
|
516
|
-
|
517
|
-
fn gen_load_base_offset(into_reg: Writable<Reg>, base: Reg, offset: i32, ty: Type) -> Self::I {
|
518
|
-
// Only ever used for I64s and vectors; if that changes, see if the
|
519
|
-
// ExtKind below needs to be changed.
|
520
|
-
assert!(ty == I64 || ty.is_vector());
|
521
|
-
let mem = Amode::imm_reg(offset, base);
|
522
|
-
Inst::load(ty, mem, into_reg, ExtKind::None)
|
523
|
-
}
|
524
|
-
|
525
|
-
fn gen_store_base_offset(base: Reg, offset: i32, from_reg: Reg, ty: Type) -> Self::I {
|
526
|
-
let ty = match ty {
|
527
|
-
// See `gen_load_stack`.
|
528
|
-
types::F16 => types::F32,
|
529
|
-
_ => ty,
|
530
|
-
};
|
531
|
-
let mem = Amode::imm_reg(offset, base);
|
532
|
-
Inst::store(ty, from_reg, mem)
|
533
|
-
}
|
534
|
-
|
535
|
-
fn gen_sp_reg_adjust(amount: i32) -> SmallInstVec<Self::I> {
|
536
|
-
let (alu_op, amount) = if amount >= 0 {
|
537
|
-
(AluRmiROpcode::Add, amount)
|
538
|
-
} else {
|
539
|
-
(AluRmiROpcode::Sub, -amount)
|
540
|
-
};
|
541
|
-
|
542
|
-
let amount = amount as u32;
|
543
|
-
|
544
|
-
smallvec![Inst::alu_rmi_r(
|
545
|
-
OperandSize::Size64,
|
546
|
-
alu_op,
|
547
|
-
RegMemImm::imm(amount),
|
548
|
-
Writable::from_reg(regs::rsp()),
|
549
|
-
)]
|
550
|
-
}
|
551
|
-
|
552
|
-
fn gen_prologue_frame_setup(
|
553
|
-
_call_conv: isa::CallConv,
|
554
|
-
flags: &settings::Flags,
|
555
|
-
_isa_flags: &x64_settings::Flags,
|
556
|
-
frame_layout: &FrameLayout,
|
557
|
-
) -> SmallInstVec<Self::I> {
|
558
|
-
let r_rsp = regs::rsp();
|
559
|
-
let r_rbp = regs::rbp();
|
560
|
-
let w_rbp = Writable::from_reg(r_rbp);
|
561
|
-
let mut insts = SmallVec::new();
|
562
|
-
// `push %rbp`
|
563
|
-
// RSP before the call will be 0 % 16. So here, it is 8 % 16.
|
564
|
-
insts.push(Inst::push64(RegMemImm::reg(r_rbp)));
|
565
|
-
|
566
|
-
if flags.unwind_info() {
|
567
|
-
insts.push(Inst::Unwind {
|
568
|
-
inst: UnwindInst::PushFrameRegs {
|
569
|
-
offset_upward_to_caller_sp: frame_layout.setup_area_size,
|
570
|
-
},
|
571
|
-
});
|
572
|
-
}
|
573
|
-
|
574
|
-
// `mov %rsp, %rbp`
|
575
|
-
// RSP is now 0 % 16
|
576
|
-
insts.push(Inst::mov_r_r(OperandSize::Size64, r_rsp, w_rbp));
|
577
|
-
|
578
|
-
insts
|
579
|
-
}
|
580
|
-
|
581
|
-
fn gen_epilogue_frame_restore(
|
582
|
-
_call_conv: isa::CallConv,
|
583
|
-
_flags: &settings::Flags,
|
584
|
-
_isa_flags: &x64_settings::Flags,
|
585
|
-
_frame_layout: &FrameLayout,
|
586
|
-
) -> SmallInstVec<Self::I> {
|
587
|
-
let mut insts = SmallVec::new();
|
588
|
-
// `mov %rbp, %rsp`
|
589
|
-
insts.push(Inst::mov_r_r(
|
590
|
-
OperandSize::Size64,
|
591
|
-
regs::rbp(),
|
592
|
-
Writable::from_reg(regs::rsp()),
|
593
|
-
));
|
594
|
-
// `pop %rbp`
|
595
|
-
insts.push(Inst::pop64(Writable::from_reg(regs::rbp())));
|
596
|
-
insts
|
597
|
-
}
|
598
|
-
|
599
|
-
fn gen_return(
|
600
|
-
call_conv: isa::CallConv,
|
601
|
-
_isa_flags: &x64_settings::Flags,
|
602
|
-
frame_layout: &FrameLayout,
|
603
|
-
) -> SmallInstVec<Self::I> {
|
604
|
-
// Emit return instruction.
|
605
|
-
let stack_bytes_to_pop = if call_conv == isa::CallConv::Tail {
|
606
|
-
frame_layout.tail_args_size
|
607
|
-
} else {
|
608
|
-
0
|
609
|
-
};
|
610
|
-
smallvec![Inst::ret(stack_bytes_to_pop)]
|
611
|
-
}
|
612
|
-
|
613
|
-
fn gen_probestack(insts: &mut SmallInstVec<Self::I>, frame_size: u32) {
|
614
|
-
insts.push(Inst::imm(
|
615
|
-
OperandSize::Size32,
|
616
|
-
frame_size as u64,
|
617
|
-
Writable::from_reg(regs::rax()),
|
618
|
-
));
|
619
|
-
insts.push(Inst::CallKnown {
|
620
|
-
dest: ExternalName::LibCall(LibCall::Probestack),
|
621
|
-
info: Some(Box::new(CallInfo {
|
622
|
-
// No need to include arg here: we are post-regalloc
|
623
|
-
// so no constraints will be seen anyway.
|
624
|
-
uses: smallvec![],
|
625
|
-
defs: smallvec![],
|
626
|
-
clobbers: PRegSet::empty(),
|
627
|
-
callee_pop_size: 0,
|
628
|
-
callee_conv: CallConv::Probestack,
|
629
|
-
})),
|
630
|
-
});
|
631
|
-
}
|
632
|
-
|
633
|
-
fn gen_inline_probestack(
|
634
|
-
insts: &mut SmallInstVec<Self::I>,
|
635
|
-
call_conv: isa::CallConv,
|
636
|
-
frame_size: u32,
|
637
|
-
guard_size: u32,
|
638
|
-
) {
|
639
|
-
// Unroll at most n consecutive probes, before falling back to using a loop
|
640
|
-
//
|
641
|
-
// This was number was picked because the loop version is 38 bytes long. We can fit
|
642
|
-
// 4 inline probes in that space, so unroll if its beneficial in terms of code size.
|
643
|
-
const PROBE_MAX_UNROLL: u32 = 4;
|
644
|
-
|
645
|
-
// Number of probes that we need to perform
|
646
|
-
let probe_count = align_to(frame_size, guard_size) / guard_size;
|
647
|
-
|
648
|
-
if probe_count <= PROBE_MAX_UNROLL {
|
649
|
-
Self::gen_probestack_unroll(insts, guard_size, probe_count)
|
650
|
-
} else {
|
651
|
-
Self::gen_probestack_loop(insts, call_conv, frame_size, guard_size)
|
652
|
-
}
|
653
|
-
}
|
654
|
-
|
655
|
-
fn gen_clobber_save(
|
656
|
-
_call_conv: isa::CallConv,
|
657
|
-
flags: &settings::Flags,
|
658
|
-
frame_layout: &FrameLayout,
|
659
|
-
) -> SmallVec<[Self::I; 16]> {
|
660
|
-
let mut insts = SmallVec::new();
|
661
|
-
|
662
|
-
// When a return_call within this function required more stack arguments than we have
|
663
|
-
// present, resize the incoming argument area of the frame to accommodate those arguments.
|
664
|
-
let incoming_args_diff = frame_layout.tail_args_size - frame_layout.incoming_args_size;
|
665
|
-
if incoming_args_diff > 0 {
|
666
|
-
// Decrement the stack pointer to make space for the new arguments
|
667
|
-
insts.push(Inst::alu_rmi_r(
|
668
|
-
OperandSize::Size64,
|
669
|
-
AluRmiROpcode::Sub,
|
670
|
-
RegMemImm::imm(incoming_args_diff),
|
671
|
-
Writable::from_reg(regs::rsp()),
|
672
|
-
));
|
673
|
-
|
674
|
-
// Make sure to keep the frame pointer and stack pointer in sync at this point
|
675
|
-
insts.push(Inst::mov_r_r(
|
676
|
-
OperandSize::Size64,
|
677
|
-
regs::rsp(),
|
678
|
-
Writable::from_reg(regs::rbp()),
|
679
|
-
));
|
680
|
-
|
681
|
-
let incoming_args_diff = i32::try_from(incoming_args_diff).unwrap();
|
682
|
-
|
683
|
-
// Move the saved frame pointer down by `incoming_args_diff`
|
684
|
-
insts.push(Inst::mov64_m_r(
|
685
|
-
Amode::imm_reg(incoming_args_diff, regs::rsp()),
|
686
|
-
Writable::from_reg(regs::r11()),
|
687
|
-
));
|
688
|
-
insts.push(Inst::mov_r_m(
|
689
|
-
OperandSize::Size64,
|
690
|
-
regs::r11(),
|
691
|
-
Amode::imm_reg(0, regs::rsp()),
|
692
|
-
));
|
693
|
-
|
694
|
-
// Move the saved return address down by `incoming_args_diff`
|
695
|
-
insts.push(Inst::mov64_m_r(
|
696
|
-
Amode::imm_reg(incoming_args_diff + 8, regs::rsp()),
|
697
|
-
Writable::from_reg(regs::r11()),
|
698
|
-
));
|
699
|
-
insts.push(Inst::mov_r_m(
|
700
|
-
OperandSize::Size64,
|
701
|
-
regs::r11(),
|
702
|
-
Amode::imm_reg(8, regs::rsp()),
|
703
|
-
));
|
704
|
-
}
|
705
|
-
|
706
|
-
// We need to factor `incoming_args_diff` into the offset upward here, as we have grown
|
707
|
-
// the argument area -- `setup_area_size` alone will not be the correct offset up to the
|
708
|
-
// original caller's SP.
|
709
|
-
let offset_upward_to_caller_sp = frame_layout.setup_area_size + incoming_args_diff;
|
710
|
-
if flags.unwind_info() && offset_upward_to_caller_sp > 0 {
|
711
|
-
// Emit unwind info: start the frame. The frame (from unwind
|
712
|
-
// consumers' point of view) starts at clobbbers, just below
|
713
|
-
// the FP and return address. Spill slots and stack slots are
|
714
|
-
// part of our actual frame but do not concern the unwinder.
|
715
|
-
insts.push(Inst::Unwind {
|
716
|
-
inst: UnwindInst::DefineNewFrame {
|
717
|
-
offset_downward_to_clobbers: frame_layout.clobber_size,
|
718
|
-
offset_upward_to_caller_sp,
|
719
|
-
},
|
720
|
-
});
|
721
|
-
}
|
722
|
-
|
723
|
-
// Adjust the stack pointer downward for clobbers and the function fixed
|
724
|
-
// frame (spillslots, storage slots, and argument area).
|
725
|
-
let stack_size = frame_layout.fixed_frame_storage_size
|
726
|
-
+ frame_layout.clobber_size
|
727
|
-
+ frame_layout.outgoing_args_size;
|
728
|
-
if stack_size > 0 {
|
729
|
-
insts.push(Inst::alu_rmi_r(
|
730
|
-
OperandSize::Size64,
|
731
|
-
AluRmiROpcode::Sub,
|
732
|
-
RegMemImm::imm(stack_size),
|
733
|
-
Writable::from_reg(regs::rsp()),
|
734
|
-
));
|
735
|
-
}
|
736
|
-
|
737
|
-
// Store each clobbered register in order at offsets from RSP,
|
738
|
-
// placing them above the fixed frame slots.
|
739
|
-
let clobber_offset =
|
740
|
-
frame_layout.fixed_frame_storage_size + frame_layout.outgoing_args_size;
|
741
|
-
let mut cur_offset = 0;
|
742
|
-
for reg in &frame_layout.clobbered_callee_saves {
|
743
|
-
let r_reg = reg.to_reg();
|
744
|
-
let ty = match r_reg.class() {
|
745
|
-
RegClass::Int => types::I64,
|
746
|
-
RegClass::Float => types::I8X16,
|
747
|
-
RegClass::Vector => unreachable!(),
|
748
|
-
};
|
749
|
-
|
750
|
-
// Align to 8 or 16 bytes as required by the storage type of the clobber.
|
751
|
-
cur_offset = align_to(cur_offset, ty.bytes());
|
752
|
-
let off = cur_offset;
|
753
|
-
cur_offset += ty.bytes();
|
754
|
-
|
755
|
-
insts.push(Inst::store(
|
756
|
-
ty,
|
757
|
-
r_reg.into(),
|
758
|
-
Amode::imm_reg(i32::try_from(off + clobber_offset).unwrap(), regs::rsp()),
|
759
|
-
));
|
760
|
-
|
761
|
-
if flags.unwind_info() {
|
762
|
-
insts.push(Inst::Unwind {
|
763
|
-
inst: UnwindInst::SaveReg {
|
764
|
-
clobber_offset: off,
|
765
|
-
reg: r_reg,
|
766
|
-
},
|
767
|
-
});
|
768
|
-
}
|
769
|
-
}
|
770
|
-
|
771
|
-
insts
|
772
|
-
}
|
773
|
-
|
774
|
-
fn gen_clobber_restore(
|
775
|
-
_call_conv: isa::CallConv,
|
776
|
-
_flags: &settings::Flags,
|
777
|
-
frame_layout: &FrameLayout,
|
778
|
-
) -> SmallVec<[Self::I; 16]> {
|
779
|
-
let mut insts = SmallVec::new();
|
780
|
-
|
781
|
-
// Restore regs by loading from offsets of RSP. We compute the offset from
|
782
|
-
// the same base as above in clobber_save, as RSP won't change between the
|
783
|
-
// prologue and epilogue.
|
784
|
-
let mut cur_offset =
|
785
|
-
frame_layout.fixed_frame_storage_size + frame_layout.outgoing_args_size;
|
786
|
-
for reg in &frame_layout.clobbered_callee_saves {
|
787
|
-
let rreg = reg.to_reg();
|
788
|
-
let ty = match rreg.class() {
|
789
|
-
RegClass::Int => types::I64,
|
790
|
-
RegClass::Float => types::I8X16,
|
791
|
-
RegClass::Vector => unreachable!(),
|
792
|
-
};
|
793
|
-
|
794
|
-
// Align to 8 or 16 bytes as required by the storage type of the clobber.
|
795
|
-
cur_offset = align_to(cur_offset, ty.bytes());
|
796
|
-
|
797
|
-
insts.push(Inst::load(
|
798
|
-
ty,
|
799
|
-
Amode::imm_reg(cur_offset.try_into().unwrap(), regs::rsp()),
|
800
|
-
Writable::from_reg(rreg.into()),
|
801
|
-
ExtKind::None,
|
802
|
-
));
|
803
|
-
|
804
|
-
cur_offset += ty.bytes();
|
805
|
-
}
|
806
|
-
|
807
|
-
let stack_size = frame_layout.fixed_frame_storage_size
|
808
|
-
+ frame_layout.clobber_size
|
809
|
-
+ frame_layout.outgoing_args_size;
|
810
|
-
|
811
|
-
// Adjust RSP back upward.
|
812
|
-
if stack_size > 0 {
|
813
|
-
insts.push(Inst::alu_rmi_r(
|
814
|
-
OperandSize::Size64,
|
815
|
-
AluRmiROpcode::Add,
|
816
|
-
RegMemImm::imm(stack_size),
|
817
|
-
Writable::from_reg(regs::rsp()),
|
818
|
-
));
|
819
|
-
}
|
820
|
-
|
821
|
-
insts
|
822
|
-
}
|
823
|
-
|
824
|
-
/// Generate a call instruction/sequence.
|
825
|
-
fn gen_call(
|
826
|
-
dest: &CallDest,
|
827
|
-
uses: CallArgList,
|
828
|
-
defs: CallRetList,
|
829
|
-
clobbers: PRegSet,
|
830
|
-
tmp: Writable<Reg>,
|
831
|
-
callee_conv: isa::CallConv,
|
832
|
-
_caller_conv: isa::CallConv,
|
833
|
-
callee_pop_size: u32,
|
834
|
-
) -> SmallVec<[Self::I; 2]> {
|
835
|
-
let mut insts = SmallVec::new();
|
836
|
-
match dest {
|
837
|
-
&CallDest::ExtName(ref name, RelocDistance::Near) => {
|
838
|
-
insts.push(Inst::call_known(
|
839
|
-
name.clone(),
|
840
|
-
uses,
|
841
|
-
defs,
|
842
|
-
clobbers,
|
843
|
-
callee_pop_size,
|
844
|
-
callee_conv,
|
845
|
-
));
|
846
|
-
}
|
847
|
-
&CallDest::ExtName(ref name, RelocDistance::Far) => {
|
848
|
-
insts.push(Inst::LoadExtName {
|
849
|
-
dst: tmp,
|
850
|
-
name: Box::new(name.clone()),
|
851
|
-
offset: 0,
|
852
|
-
distance: RelocDistance::Far,
|
853
|
-
});
|
854
|
-
insts.push(Inst::call_unknown(
|
855
|
-
RegMem::reg(tmp.to_reg()),
|
856
|
-
uses,
|
857
|
-
defs,
|
858
|
-
clobbers,
|
859
|
-
callee_pop_size,
|
860
|
-
callee_conv,
|
861
|
-
));
|
862
|
-
}
|
863
|
-
&CallDest::Reg(reg) => {
|
864
|
-
insts.push(Inst::call_unknown(
|
865
|
-
RegMem::reg(reg),
|
866
|
-
uses,
|
867
|
-
defs,
|
868
|
-
clobbers,
|
869
|
-
callee_pop_size,
|
870
|
-
callee_conv,
|
871
|
-
));
|
872
|
-
}
|
873
|
-
}
|
874
|
-
insts
|
875
|
-
}
|
876
|
-
|
877
|
-
fn gen_memcpy<F: FnMut(Type) -> Writable<Reg>>(
|
878
|
-
call_conv: isa::CallConv,
|
879
|
-
dst: Reg,
|
880
|
-
src: Reg,
|
881
|
-
size: usize,
|
882
|
-
mut alloc_tmp: F,
|
883
|
-
) -> SmallVec<[Self::I; 8]> {
|
884
|
-
let mut insts = SmallVec::new();
|
885
|
-
let arg0 = get_intreg_for_arg(&call_conv, 0, 0).unwrap();
|
886
|
-
let arg1 = get_intreg_for_arg(&call_conv, 1, 1).unwrap();
|
887
|
-
let arg2 = get_intreg_for_arg(&call_conv, 2, 2).unwrap();
|
888
|
-
let temp = alloc_tmp(Self::word_type());
|
889
|
-
let temp2 = alloc_tmp(Self::word_type());
|
890
|
-
insts.push(Inst::imm(OperandSize::Size64, size as u64, temp));
|
891
|
-
// We use an indirect call and a full LoadExtName because we do not have
|
892
|
-
// information about the libcall `RelocDistance` here, so we
|
893
|
-
// conservatively use the more flexible calling sequence.
|
894
|
-
insts.push(Inst::LoadExtName {
|
895
|
-
dst: temp2,
|
896
|
-
name: Box::new(ExternalName::LibCall(LibCall::Memcpy)),
|
897
|
-
offset: 0,
|
898
|
-
distance: RelocDistance::Far,
|
899
|
-
});
|
900
|
-
let callee_pop_size = 0;
|
901
|
-
insts.push(Inst::call_unknown(
|
902
|
-
RegMem::reg(temp2.to_reg()),
|
903
|
-
/* uses = */
|
904
|
-
smallvec![
|
905
|
-
CallArgPair {
|
906
|
-
vreg: dst,
|
907
|
-
preg: arg0
|
908
|
-
},
|
909
|
-
CallArgPair {
|
910
|
-
vreg: src,
|
911
|
-
preg: arg1
|
912
|
-
},
|
913
|
-
CallArgPair {
|
914
|
-
vreg: temp.to_reg(),
|
915
|
-
preg: arg2
|
916
|
-
},
|
917
|
-
],
|
918
|
-
/* defs = */ smallvec![],
|
919
|
-
/* clobbers = */ Self::get_regs_clobbered_by_call(call_conv),
|
920
|
-
callee_pop_size,
|
921
|
-
call_conv,
|
922
|
-
));
|
923
|
-
insts
|
924
|
-
}
|
925
|
-
|
926
|
-
fn get_number_of_spillslots_for_value(
|
927
|
-
rc: RegClass,
|
928
|
-
vector_scale: u32,
|
929
|
-
_isa_flags: &Self::F,
|
930
|
-
) -> u32 {
|
931
|
-
// We allocate in terms of 8-byte slots.
|
932
|
-
match rc {
|
933
|
-
RegClass::Int => 1,
|
934
|
-
RegClass::Float => vector_scale / 8,
|
935
|
-
RegClass::Vector => unreachable!(),
|
936
|
-
}
|
937
|
-
}
|
938
|
-
|
939
|
-
fn get_machine_env(flags: &settings::Flags, _call_conv: isa::CallConv) -> &MachineEnv {
|
940
|
-
if flags.enable_pinned_reg() {
|
941
|
-
static MACHINE_ENV: OnceLock<MachineEnv> = OnceLock::new();
|
942
|
-
MACHINE_ENV.get_or_init(|| create_reg_env_systemv(true))
|
943
|
-
} else {
|
944
|
-
static MACHINE_ENV: OnceLock<MachineEnv> = OnceLock::new();
|
945
|
-
MACHINE_ENV.get_or_init(|| create_reg_env_systemv(false))
|
946
|
-
}
|
947
|
-
}
|
948
|
-
|
949
|
-
fn get_regs_clobbered_by_call(call_conv_of_callee: isa::CallConv) -> PRegSet {
|
950
|
-
match call_conv_of_callee {
|
951
|
-
isa::CallConv::Winch => ALL_CLOBBERS,
|
952
|
-
_ if call_conv_of_callee.extends_windows_fastcall() => WINDOWS_CLOBBERS,
|
953
|
-
_ => SYSV_CLOBBERS,
|
954
|
-
}
|
955
|
-
}
|
956
|
-
|
957
|
-
fn get_ext_mode(
|
958
|
-
_call_conv: isa::CallConv,
|
959
|
-
specified: ir::ArgumentExtension,
|
960
|
-
) -> ir::ArgumentExtension {
|
961
|
-
specified
|
962
|
-
}
|
963
|
-
|
964
|
-
fn compute_frame_layout(
|
965
|
-
call_conv: CallConv,
|
966
|
-
flags: &settings::Flags,
|
967
|
-
_sig: &Signature,
|
968
|
-
regs: &[Writable<RealReg>],
|
969
|
-
_is_leaf: bool,
|
970
|
-
incoming_args_size: u32,
|
971
|
-
tail_args_size: u32,
|
972
|
-
fixed_frame_storage_size: u32,
|
973
|
-
outgoing_args_size: u32,
|
974
|
-
) -> FrameLayout {
|
975
|
-
debug_assert!(tail_args_size >= incoming_args_size);
|
976
|
-
|
977
|
-
let mut regs: Vec<Writable<RealReg>> = match call_conv {
|
978
|
-
// The `winch` calling convention doesn't have any callee-save
|
979
|
-
// registers.
|
980
|
-
CallConv::Winch => vec![],
|
981
|
-
CallConv::Fast | CallConv::Cold | CallConv::SystemV | CallConv::Tail => regs
|
982
|
-
.iter()
|
983
|
-
.cloned()
|
984
|
-
.filter(|r| is_callee_save_systemv(r.to_reg(), flags.enable_pinned_reg()))
|
985
|
-
.collect(),
|
986
|
-
CallConv::WindowsFastcall => regs
|
987
|
-
.iter()
|
988
|
-
.cloned()
|
989
|
-
.filter(|r| is_callee_save_fastcall(r.to_reg(), flags.enable_pinned_reg()))
|
990
|
-
.collect(),
|
991
|
-
CallConv::Probestack => todo!("probestack?"),
|
992
|
-
CallConv::WasmtimeSystemV | CallConv::AppleAarch64 => unreachable!(),
|
993
|
-
};
|
994
|
-
// Sort registers for deterministic code output. We can do an unstable sort because the
|
995
|
-
// registers will be unique (there are no dups).
|
996
|
-
regs.sort_unstable();
|
997
|
-
|
998
|
-
// Compute clobber size.
|
999
|
-
let clobber_size = compute_clobber_size(®s);
|
1000
|
-
|
1001
|
-
// Compute setup area size.
|
1002
|
-
let setup_area_size = 16; // RBP, return address
|
1003
|
-
|
1004
|
-
// Return FrameLayout structure.
|
1005
|
-
FrameLayout {
|
1006
|
-
incoming_args_size,
|
1007
|
-
tail_args_size: align_to(tail_args_size, 16),
|
1008
|
-
setup_area_size,
|
1009
|
-
clobber_size,
|
1010
|
-
fixed_frame_storage_size,
|
1011
|
-
outgoing_args_size,
|
1012
|
-
clobbered_callee_saves: regs,
|
1013
|
-
}
|
1014
|
-
}
|
1015
|
-
}
|
1016
|
-
|
1017
|
-
impl X64CallSite {
|
1018
|
-
pub fn emit_return_call(mut self, ctx: &mut Lower<Inst>, args: isle::ValueSlice) {
|
1019
|
-
let new_stack_arg_size =
|
1020
|
-
u32::try_from(self.sig(ctx.sigs()).sized_stack_arg_space()).unwrap();
|
1021
|
-
|
1022
|
-
ctx.abi_mut().accumulate_tail_args_size(new_stack_arg_size);
|
1023
|
-
|
1024
|
-
// Put all arguments in registers and stack slots (within that newly
|
1025
|
-
// allocated stack space).
|
1026
|
-
self.emit_args(ctx, args);
|
1027
|
-
self.emit_stack_ret_arg_for_tail_call(ctx);
|
1028
|
-
|
1029
|
-
// Finally, do the actual tail call!
|
1030
|
-
let dest = self.dest().clone();
|
1031
|
-
let info = Box::new(ReturnCallInfo {
|
1032
|
-
new_stack_arg_size,
|
1033
|
-
uses: self.take_uses(),
|
1034
|
-
tmp: ctx.temp_writable_gpr(),
|
1035
|
-
});
|
1036
|
-
match dest {
|
1037
|
-
CallDest::ExtName(callee, RelocDistance::Near) => {
|
1038
|
-
ctx.emit(Inst::ReturnCallKnown { callee, info });
|
1039
|
-
}
|
1040
|
-
CallDest::ExtName(callee, RelocDistance::Far) => {
|
1041
|
-
let tmp2 = ctx.temp_writable_gpr();
|
1042
|
-
ctx.emit(Inst::LoadExtName {
|
1043
|
-
dst: tmp2.to_writable_reg(),
|
1044
|
-
name: Box::new(callee),
|
1045
|
-
offset: 0,
|
1046
|
-
distance: RelocDistance::Far,
|
1047
|
-
});
|
1048
|
-
ctx.emit(Inst::ReturnCallUnknown {
|
1049
|
-
callee: tmp2.to_reg().to_reg(),
|
1050
|
-
info,
|
1051
|
-
});
|
1052
|
-
}
|
1053
|
-
CallDest::Reg(callee) => ctx.emit(Inst::ReturnCallUnknown {
|
1054
|
-
callee: callee.into(),
|
1055
|
-
info,
|
1056
|
-
}),
|
1057
|
-
}
|
1058
|
-
}
|
1059
|
-
}
|
1060
|
-
|
1061
|
-
impl From<StackAMode> for SyntheticAmode {
|
1062
|
-
fn from(amode: StackAMode) -> Self {
|
1063
|
-
// We enforce a 128 MB stack-frame size limit above, so these
|
1064
|
-
// `expect()`s should never fail.
|
1065
|
-
match amode {
|
1066
|
-
StackAMode::IncomingArg(off, stack_args_size) => {
|
1067
|
-
let offset = u32::try_from(off).expect(
|
1068
|
-
"Offset in IncomingArg is greater than 4GB; should hit impl limit first",
|
1069
|
-
);
|
1070
|
-
SyntheticAmode::IncomingArg {
|
1071
|
-
offset: stack_args_size - offset,
|
1072
|
-
}
|
1073
|
-
}
|
1074
|
-
StackAMode::Slot(off) => {
|
1075
|
-
let off = i32::try_from(off)
|
1076
|
-
.expect("Offset in Slot is greater than 2GB; should hit impl limit first");
|
1077
|
-
SyntheticAmode::slot_offset(off)
|
1078
|
-
}
|
1079
|
-
StackAMode::OutgoingArg(off) => {
|
1080
|
-
let off = i32::try_from(off).expect(
|
1081
|
-
"Offset in OutgoingArg is greater than 2GB; should hit impl limit first",
|
1082
|
-
);
|
1083
|
-
SyntheticAmode::Real(Amode::ImmReg {
|
1084
|
-
simm32: off,
|
1085
|
-
base: regs::rsp(),
|
1086
|
-
flags: MemFlags::trusted(),
|
1087
|
-
})
|
1088
|
-
}
|
1089
|
-
}
|
1090
|
-
}
|
1091
|
-
}
|
1092
|
-
|
1093
|
-
fn get_intreg_for_arg(call_conv: &CallConv, idx: usize, arg_idx: usize) -> Option<Reg> {
|
1094
|
-
let is_fastcall = call_conv.extends_windows_fastcall();
|
1095
|
-
|
1096
|
-
// Fastcall counts by absolute argument number; SysV counts by argument of
|
1097
|
-
// this (integer) class.
|
1098
|
-
let i = if is_fastcall { arg_idx } else { idx };
|
1099
|
-
match (i, is_fastcall) {
|
1100
|
-
(0, false) => Some(regs::rdi()),
|
1101
|
-
(1, false) => Some(regs::rsi()),
|
1102
|
-
(2, false) => Some(regs::rdx()),
|
1103
|
-
(3, false) => Some(regs::rcx()),
|
1104
|
-
(4, false) => Some(regs::r8()),
|
1105
|
-
(5, false) => Some(regs::r9()),
|
1106
|
-
(0, true) => Some(regs::rcx()),
|
1107
|
-
(1, true) => Some(regs::rdx()),
|
1108
|
-
(2, true) => Some(regs::r8()),
|
1109
|
-
(3, true) => Some(regs::r9()),
|
1110
|
-
_ => None,
|
1111
|
-
}
|
1112
|
-
}
|
1113
|
-
|
1114
|
-
fn get_fltreg_for_arg(call_conv: &CallConv, idx: usize, arg_idx: usize) -> Option<Reg> {
|
1115
|
-
let is_fastcall = call_conv.extends_windows_fastcall();
|
1116
|
-
|
1117
|
-
// Fastcall counts by absolute argument number; SysV counts by argument of
|
1118
|
-
// this (floating-point) class.
|
1119
|
-
let i = if is_fastcall { arg_idx } else { idx };
|
1120
|
-
match (i, is_fastcall) {
|
1121
|
-
(0, false) => Some(regs::xmm0()),
|
1122
|
-
(1, false) => Some(regs::xmm1()),
|
1123
|
-
(2, false) => Some(regs::xmm2()),
|
1124
|
-
(3, false) => Some(regs::xmm3()),
|
1125
|
-
(4, false) => Some(regs::xmm4()),
|
1126
|
-
(5, false) => Some(regs::xmm5()),
|
1127
|
-
(6, false) => Some(regs::xmm6()),
|
1128
|
-
(7, false) => Some(regs::xmm7()),
|
1129
|
-
(0, true) => Some(regs::xmm0()),
|
1130
|
-
(1, true) => Some(regs::xmm1()),
|
1131
|
-
(2, true) => Some(regs::xmm2()),
|
1132
|
-
(3, true) => Some(regs::xmm3()),
|
1133
|
-
_ => None,
|
1134
|
-
}
|
1135
|
-
}
|
1136
|
-
|
1137
|
-
fn get_intreg_for_retval(
|
1138
|
-
call_conv: &CallConv,
|
1139
|
-
flags: &settings::Flags,
|
1140
|
-
intreg_idx: usize,
|
1141
|
-
is_last: bool,
|
1142
|
-
) -> Option<Reg> {
|
1143
|
-
match call_conv {
|
1144
|
-
CallConv::Tail => match intreg_idx {
|
1145
|
-
0 => Some(regs::rax()),
|
1146
|
-
1 => Some(regs::rcx()),
|
1147
|
-
2 => Some(regs::rdx()),
|
1148
|
-
3 => Some(regs::rsi()),
|
1149
|
-
4 => Some(regs::rdi()),
|
1150
|
-
5 => Some(regs::r8()),
|
1151
|
-
6 => Some(regs::r9()),
|
1152
|
-
7 => Some(regs::r10()),
|
1153
|
-
8 => Some(regs::r11()),
|
1154
|
-
// NB: `r15` is reserved as a scratch register.
|
1155
|
-
_ => None,
|
1156
|
-
},
|
1157
|
-
CallConv::Fast | CallConv::Cold | CallConv::SystemV => match intreg_idx {
|
1158
|
-
0 => Some(regs::rax()),
|
1159
|
-
1 => Some(regs::rdx()),
|
1160
|
-
2 if flags.enable_llvm_abi_extensions() => Some(regs::rcx()),
|
1161
|
-
_ => None,
|
1162
|
-
},
|
1163
|
-
CallConv::WindowsFastcall => match intreg_idx {
|
1164
|
-
0 => Some(regs::rax()),
|
1165
|
-
1 => Some(regs::rdx()), // The Rust ABI for i128s needs this.
|
1166
|
-
_ => None,
|
1167
|
-
},
|
1168
|
-
|
1169
|
-
CallConv::Winch => {
|
1170
|
-
// TODO: Once Winch supports SIMD, this will need to be updated to support values
|
1171
|
-
// returned in more than one register.
|
1172
|
-
// https://github.com/bytecodealliance/wasmtime/issues/8093
|
1173
|
-
is_last.then(|| regs::rax())
|
1174
|
-
}
|
1175
|
-
CallConv::Probestack => todo!(),
|
1176
|
-
CallConv::WasmtimeSystemV | CallConv::AppleAarch64 => unreachable!(),
|
1177
|
-
}
|
1178
|
-
}
|
1179
|
-
|
1180
|
-
fn get_fltreg_for_retval(call_conv: &CallConv, fltreg_idx: usize, is_last: bool) -> Option<Reg> {
|
1181
|
-
match call_conv {
|
1182
|
-
CallConv::Tail => match fltreg_idx {
|
1183
|
-
0 => Some(regs::xmm0()),
|
1184
|
-
1 => Some(regs::xmm1()),
|
1185
|
-
2 => Some(regs::xmm2()),
|
1186
|
-
3 => Some(regs::xmm3()),
|
1187
|
-
4 => Some(regs::xmm4()),
|
1188
|
-
5 => Some(regs::xmm5()),
|
1189
|
-
6 => Some(regs::xmm6()),
|
1190
|
-
7 => Some(regs::xmm7()),
|
1191
|
-
_ => None,
|
1192
|
-
},
|
1193
|
-
CallConv::Fast | CallConv::Cold | CallConv::SystemV => match fltreg_idx {
|
1194
|
-
0 => Some(regs::xmm0()),
|
1195
|
-
1 => Some(regs::xmm1()),
|
1196
|
-
_ => None,
|
1197
|
-
},
|
1198
|
-
CallConv::WindowsFastcall => match fltreg_idx {
|
1199
|
-
0 => Some(regs::xmm0()),
|
1200
|
-
_ => None,
|
1201
|
-
},
|
1202
|
-
CallConv::Winch => is_last.then(|| regs::xmm0()),
|
1203
|
-
CallConv::Probestack => todo!(),
|
1204
|
-
CallConv::WasmtimeSystemV | CallConv::AppleAarch64 => unreachable!(),
|
1205
|
-
}
|
1206
|
-
}
|
1207
|
-
|
1208
|
-
fn is_callee_save_systemv(r: RealReg, enable_pinned_reg: bool) -> bool {
|
1209
|
-
use regs::*;
|
1210
|
-
match r.class() {
|
1211
|
-
RegClass::Int => match r.hw_enc() {
|
1212
|
-
ENC_RBX | ENC_RBP | ENC_R12 | ENC_R13 | ENC_R14 => true,
|
1213
|
-
// R15 is the pinned register; if we're using it that way,
|
1214
|
-
// it is effectively globally-allocated, and is not
|
1215
|
-
// callee-saved.
|
1216
|
-
ENC_R15 => !enable_pinned_reg,
|
1217
|
-
_ => false,
|
1218
|
-
},
|
1219
|
-
RegClass::Float => false,
|
1220
|
-
RegClass::Vector => unreachable!(),
|
1221
|
-
}
|
1222
|
-
}
|
1223
|
-
|
1224
|
-
fn is_callee_save_fastcall(r: RealReg, enable_pinned_reg: bool) -> bool {
|
1225
|
-
use regs::*;
|
1226
|
-
match r.class() {
|
1227
|
-
RegClass::Int => match r.hw_enc() {
|
1228
|
-
ENC_RBX | ENC_RBP | ENC_RSI | ENC_RDI | ENC_R12 | ENC_R13 | ENC_R14 => true,
|
1229
|
-
// See above for SysV: we must treat the pinned reg specially.
|
1230
|
-
ENC_R15 => !enable_pinned_reg,
|
1231
|
-
_ => false,
|
1232
|
-
},
|
1233
|
-
RegClass::Float => match r.hw_enc() {
|
1234
|
-
6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 => true,
|
1235
|
-
_ => false,
|
1236
|
-
},
|
1237
|
-
RegClass::Vector => unreachable!(),
|
1238
|
-
}
|
1239
|
-
}
|
1240
|
-
|
1241
|
-
fn compute_clobber_size(clobbers: &[Writable<RealReg>]) -> u32 {
|
1242
|
-
let mut clobbered_size = 0;
|
1243
|
-
for reg in clobbers {
|
1244
|
-
match reg.to_reg().class() {
|
1245
|
-
RegClass::Int => {
|
1246
|
-
clobbered_size += 8;
|
1247
|
-
}
|
1248
|
-
RegClass::Float => {
|
1249
|
-
clobbered_size = align_to(clobbered_size, 16);
|
1250
|
-
clobbered_size += 16;
|
1251
|
-
}
|
1252
|
-
RegClass::Vector => unreachable!(),
|
1253
|
-
}
|
1254
|
-
}
|
1255
|
-
align_to(clobbered_size, 16)
|
1256
|
-
}
|
1257
|
-
|
1258
|
-
const WINDOWS_CLOBBERS: PRegSet = windows_clobbers();
|
1259
|
-
const SYSV_CLOBBERS: PRegSet = sysv_clobbers();
|
1260
|
-
const ALL_CLOBBERS: PRegSet = all_clobbers();
|
1261
|
-
|
1262
|
-
const fn windows_clobbers() -> PRegSet {
|
1263
|
-
PRegSet::empty()
|
1264
|
-
.with(regs::gpr_preg(regs::ENC_RAX))
|
1265
|
-
.with(regs::gpr_preg(regs::ENC_RCX))
|
1266
|
-
.with(regs::gpr_preg(regs::ENC_RDX))
|
1267
|
-
.with(regs::gpr_preg(regs::ENC_R8))
|
1268
|
-
.with(regs::gpr_preg(regs::ENC_R9))
|
1269
|
-
.with(regs::gpr_preg(regs::ENC_R10))
|
1270
|
-
.with(regs::gpr_preg(regs::ENC_R11))
|
1271
|
-
.with(regs::fpr_preg(0))
|
1272
|
-
.with(regs::fpr_preg(1))
|
1273
|
-
.with(regs::fpr_preg(2))
|
1274
|
-
.with(regs::fpr_preg(3))
|
1275
|
-
.with(regs::fpr_preg(4))
|
1276
|
-
.with(regs::fpr_preg(5))
|
1277
|
-
}
|
1278
|
-
|
1279
|
-
const fn sysv_clobbers() -> PRegSet {
|
1280
|
-
PRegSet::empty()
|
1281
|
-
.with(regs::gpr_preg(regs::ENC_RAX))
|
1282
|
-
.with(regs::gpr_preg(regs::ENC_RCX))
|
1283
|
-
.with(regs::gpr_preg(regs::ENC_RDX))
|
1284
|
-
.with(regs::gpr_preg(regs::ENC_RSI))
|
1285
|
-
.with(regs::gpr_preg(regs::ENC_RDI))
|
1286
|
-
.with(regs::gpr_preg(regs::ENC_R8))
|
1287
|
-
.with(regs::gpr_preg(regs::ENC_R9))
|
1288
|
-
.with(regs::gpr_preg(regs::ENC_R10))
|
1289
|
-
.with(regs::gpr_preg(regs::ENC_R11))
|
1290
|
-
.with(regs::fpr_preg(0))
|
1291
|
-
.with(regs::fpr_preg(1))
|
1292
|
-
.with(regs::fpr_preg(2))
|
1293
|
-
.with(regs::fpr_preg(3))
|
1294
|
-
.with(regs::fpr_preg(4))
|
1295
|
-
.with(regs::fpr_preg(5))
|
1296
|
-
.with(regs::fpr_preg(6))
|
1297
|
-
.with(regs::fpr_preg(7))
|
1298
|
-
.with(regs::fpr_preg(8))
|
1299
|
-
.with(regs::fpr_preg(9))
|
1300
|
-
.with(regs::fpr_preg(10))
|
1301
|
-
.with(regs::fpr_preg(11))
|
1302
|
-
.with(regs::fpr_preg(12))
|
1303
|
-
.with(regs::fpr_preg(13))
|
1304
|
-
.with(regs::fpr_preg(14))
|
1305
|
-
.with(regs::fpr_preg(15))
|
1306
|
-
}
|
1307
|
-
|
1308
|
-
/// For calling conventions that clobber all registers.
|
1309
|
-
const fn all_clobbers() -> PRegSet {
|
1310
|
-
PRegSet::empty()
|
1311
|
-
.with(regs::gpr_preg(regs::ENC_RAX))
|
1312
|
-
.with(regs::gpr_preg(regs::ENC_RCX))
|
1313
|
-
.with(regs::gpr_preg(regs::ENC_RDX))
|
1314
|
-
.with(regs::gpr_preg(regs::ENC_RBX))
|
1315
|
-
.with(regs::gpr_preg(regs::ENC_RSI))
|
1316
|
-
.with(regs::gpr_preg(regs::ENC_RDI))
|
1317
|
-
.with(regs::gpr_preg(regs::ENC_R8))
|
1318
|
-
.with(regs::gpr_preg(regs::ENC_R9))
|
1319
|
-
.with(regs::gpr_preg(regs::ENC_R10))
|
1320
|
-
.with(regs::gpr_preg(regs::ENC_R11))
|
1321
|
-
.with(regs::gpr_preg(regs::ENC_R12))
|
1322
|
-
.with(regs::gpr_preg(regs::ENC_R13))
|
1323
|
-
.with(regs::gpr_preg(regs::ENC_R14))
|
1324
|
-
.with(regs::gpr_preg(regs::ENC_R15))
|
1325
|
-
.with(regs::fpr_preg(0))
|
1326
|
-
.with(regs::fpr_preg(1))
|
1327
|
-
.with(regs::fpr_preg(2))
|
1328
|
-
.with(regs::fpr_preg(3))
|
1329
|
-
.with(regs::fpr_preg(4))
|
1330
|
-
.with(regs::fpr_preg(5))
|
1331
|
-
.with(regs::fpr_preg(6))
|
1332
|
-
.with(regs::fpr_preg(7))
|
1333
|
-
.with(regs::fpr_preg(8))
|
1334
|
-
.with(regs::fpr_preg(9))
|
1335
|
-
.with(regs::fpr_preg(10))
|
1336
|
-
.with(regs::fpr_preg(11))
|
1337
|
-
.with(regs::fpr_preg(12))
|
1338
|
-
.with(regs::fpr_preg(13))
|
1339
|
-
.with(regs::fpr_preg(14))
|
1340
|
-
.with(regs::fpr_preg(15))
|
1341
|
-
}
|
1342
|
-
|
1343
|
-
fn create_reg_env_systemv(enable_pinned_reg: bool) -> MachineEnv {
|
1344
|
-
fn preg(r: Reg) -> PReg {
|
1345
|
-
r.to_real_reg().unwrap().into()
|
1346
|
-
}
|
1347
|
-
|
1348
|
-
let mut env = MachineEnv {
|
1349
|
-
preferred_regs_by_class: [
|
1350
|
-
// Preferred GPRs: caller-saved in the SysV ABI.
|
1351
|
-
vec![
|
1352
|
-
preg(regs::rsi()),
|
1353
|
-
preg(regs::rdi()),
|
1354
|
-
preg(regs::rax()),
|
1355
|
-
preg(regs::rcx()),
|
1356
|
-
preg(regs::rdx()),
|
1357
|
-
preg(regs::r8()),
|
1358
|
-
preg(regs::r9()),
|
1359
|
-
preg(regs::r10()),
|
1360
|
-
preg(regs::r11()),
|
1361
|
-
],
|
1362
|
-
// Preferred XMMs: the first 8, which can have smaller encodings
|
1363
|
-
// with AVX instructions.
|
1364
|
-
vec![
|
1365
|
-
preg(regs::xmm0()),
|
1366
|
-
preg(regs::xmm1()),
|
1367
|
-
preg(regs::xmm2()),
|
1368
|
-
preg(regs::xmm3()),
|
1369
|
-
preg(regs::xmm4()),
|
1370
|
-
preg(regs::xmm5()),
|
1371
|
-
preg(regs::xmm6()),
|
1372
|
-
preg(regs::xmm7()),
|
1373
|
-
],
|
1374
|
-
// The Vector Regclass is unused
|
1375
|
-
vec![],
|
1376
|
-
],
|
1377
|
-
non_preferred_regs_by_class: [
|
1378
|
-
// Non-preferred GPRs: callee-saved in the SysV ABI.
|
1379
|
-
vec![
|
1380
|
-
preg(regs::rbx()),
|
1381
|
-
preg(regs::r12()),
|
1382
|
-
preg(regs::r13()),
|
1383
|
-
preg(regs::r14()),
|
1384
|
-
],
|
1385
|
-
// Non-preferred XMMs: the last 8 registers, which can have larger
|
1386
|
-
// encodings with AVX instructions.
|
1387
|
-
vec![
|
1388
|
-
preg(regs::xmm8()),
|
1389
|
-
preg(regs::xmm9()),
|
1390
|
-
preg(regs::xmm10()),
|
1391
|
-
preg(regs::xmm11()),
|
1392
|
-
preg(regs::xmm12()),
|
1393
|
-
preg(regs::xmm13()),
|
1394
|
-
preg(regs::xmm14()),
|
1395
|
-
preg(regs::xmm15()),
|
1396
|
-
],
|
1397
|
-
// The Vector Regclass is unused
|
1398
|
-
vec![],
|
1399
|
-
],
|
1400
|
-
fixed_stack_slots: vec![],
|
1401
|
-
scratch_by_class: [None, None, None],
|
1402
|
-
};
|
1403
|
-
|
1404
|
-
debug_assert_eq!(regs::r15(), regs::pinned_reg());
|
1405
|
-
if !enable_pinned_reg {
|
1406
|
-
env.non_preferred_regs_by_class[0].push(preg(regs::r15()));
|
1407
|
-
}
|
1408
|
-
|
1409
|
-
env
|
1410
|
-
}
|