wasmtime 24.0.0 → 25.0.0

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Files changed (2451) hide show
  1. checksums.yaml +4 -4
  2. data/Cargo.lock +112 -111
  3. data/ext/Cargo.toml +5 -5
  4. data/ext/cargo-vendor/cranelift-bforest-0.112.0/.cargo-checksum.json +1 -0
  5. data/ext/cargo-vendor/cranelift-bforest-0.112.0/Cargo.toml +59 -0
  6. data/ext/cargo-vendor/cranelift-bforest-0.112.0/src/node.rs +806 -0
  7. data/ext/cargo-vendor/cranelift-bforest-0.112.0/src/path.rs +830 -0
  8. data/ext/cargo-vendor/cranelift-bforest-0.112.0/src/pool.rs +219 -0
  9. data/ext/cargo-vendor/cranelift-bitset-0.112.0/.cargo-checksum.json +1 -0
  10. data/ext/cargo-vendor/cranelift-bitset-0.112.0/Cargo.toml +74 -0
  11. data/ext/cargo-vendor/cranelift-bitset-0.112.0/src/scalar.rs +626 -0
  12. data/ext/cargo-vendor/cranelift-codegen-0.112.0/.cargo-checksum.json +1 -0
  13. data/ext/cargo-vendor/cranelift-codegen-0.112.0/Cargo.toml +222 -0
  14. data/ext/cargo-vendor/cranelift-codegen-0.112.0/build.rs +267 -0
  15. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/binemit/mod.rs +168 -0
  16. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/cfg_printer.rs +83 -0
  17. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/data_value.rs +402 -0
  18. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/dbg.rs +28 -0
  19. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/egraph.rs +835 -0
  20. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/incremental_cache.rs +256 -0
  21. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/inst_predicates.rs +207 -0
  22. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/ir/constant.rs +485 -0
  23. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/ir/dfg.rs +1802 -0
  24. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/ir/entities.rs +564 -0
  25. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/ir/extfunc.rs +408 -0
  26. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/ir/extname.rs +333 -0
  27. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/ir/function.rs +500 -0
  28. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/ir/globalvalue.rs +147 -0
  29. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/ir/immediates.rs +1941 -0
  30. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/ir/instructions.rs +1021 -0
  31. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/ir/memtype.rs +190 -0
  32. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/ir/progpoint.rs +75 -0
  33. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/ir/trapcode.rs +148 -0
  34. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/ir/types.rs +624 -0
  35. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/ir/user_stack_maps.rs +199 -0
  36. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/aarch64/abi.rs +1520 -0
  37. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/aarch64/inst/args.rs +711 -0
  38. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/aarch64/inst/emit.rs +3567 -0
  39. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/aarch64/inst/emit_tests.rs +7972 -0
  40. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/aarch64/inst/imms.rs +1244 -0
  41. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/aarch64/inst/mod.rs +3051 -0
  42. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/aarch64/inst/regs.rs +269 -0
  43. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/aarch64/inst/unwind/systemv.rs +174 -0
  44. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/aarch64/inst.isle +4267 -0
  45. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/aarch64/lower/isle.rs +811 -0
  46. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/aarch64/lower.isle +2968 -0
  47. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/aarch64/pcc.rs +570 -0
  48. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/aarch64/settings.rs +9 -0
  49. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/mod.rs +471 -0
  50. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/pulley32.rs +13 -0
  51. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/pulley64.rs +13 -0
  52. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/pulley_shared/abi.rs +798 -0
  53. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/pulley_shared/inst/args.rs +192 -0
  54. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/pulley_shared/inst/emit.rs +482 -0
  55. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/pulley_shared/inst/mod.rs +905 -0
  56. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/pulley_shared/inst/regs.rs +164 -0
  57. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/pulley_shared/inst.isle +543 -0
  58. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/pulley_shared/lower/isle/generated_code.rs +17 -0
  59. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/pulley_shared/lower/isle.rs +195 -0
  60. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/pulley_shared/lower.isle +178 -0
  61. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/pulley_shared/lower.rs +36 -0
  62. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/pulley_shared/mod.rs +281 -0
  63. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/pulley_shared/settings.rs +16 -0
  64. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/riscv64/abi.rs +993 -0
  65. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/riscv64/inst/args.rs +1957 -0
  66. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/riscv64/inst/emit.rs +2685 -0
  67. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/riscv64/inst/emit_tests.rs +2277 -0
  68. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/riscv64/inst/encode.rs +721 -0
  69. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/riscv64/inst/mod.rs +1865 -0
  70. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/riscv64/inst/unwind/systemv.rs +170 -0
  71. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/riscv64/inst/vector.rs +1150 -0
  72. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/riscv64/inst.isle +3128 -0
  73. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/riscv64/inst_vector.isle +1907 -0
  74. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/riscv64/lower/isle.rs +721 -0
  75. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/riscv64/lower.isle +2940 -0
  76. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/s390x/abi.rs +1348 -0
  77. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/s390x/inst/emit.rs +3470 -0
  78. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/s390x/inst/emit_tests.rs +13370 -0
  79. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/s390x/inst/mod.rs +3461 -0
  80. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/s390x/inst/regs.rs +169 -0
  81. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/s390x/inst/unwind/systemv.rs +212 -0
  82. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/s390x/inst.isle +5071 -0
  83. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/s390x/lower/isle.rs +1109 -0
  84. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/s390x/lower.isle +3981 -0
  85. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/unwind/systemv.rs +276 -0
  86. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/x64/abi.rs +1390 -0
  87. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/x64/encoding/evex.rs +747 -0
  88. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/x64/inst/args.rs +2318 -0
  89. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/x64/inst/emit.rs +4400 -0
  90. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/x64/inst/emit_state.rs +55 -0
  91. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/x64/inst/emit_tests.rs +5146 -0
  92. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/x64/inst/mod.rs +2811 -0
  93. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/x64/inst/regs.rs +275 -0
  94. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/x64/inst/stack_switch.rs +52 -0
  95. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/x64/inst/unwind/systemv.rs +198 -0
  96. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/x64/inst.isle +5382 -0
  97. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/x64/lower/isle.rs +1047 -0
  98. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/x64/lower.isle +4919 -0
  99. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/x64/lower.rs +338 -0
  100. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/x64/mod.rs +239 -0
  101. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isa/x64/pcc.rs +1022 -0
  102. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/isle_prelude.rs +1144 -0
  103. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/lib.rs +106 -0
  104. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/machinst/abi.rs +2417 -0
  105. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/machinst/buffer.rs +2492 -0
  106. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/machinst/isle.rs +890 -0
  107. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/machinst/lower.rs +1590 -0
  108. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/machinst/mod.rs +560 -0
  109. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/machinst/reg.rs +484 -0
  110. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/machinst/vcode.rs +1762 -0
  111. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/opts/extends.isle +95 -0
  112. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/opts/icmp.isle +258 -0
  113. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/opts/selects.isle +88 -0
  114. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/prelude.isle +751 -0
  115. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/prelude_lower.isle +1081 -0
  116. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/print_errors.rs +223 -0
  117. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/remove_constant_phis.rs +419 -0
  118. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/result.rs +111 -0
  119. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/settings.rs +591 -0
  120. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/timing.rs +296 -0
  121. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/verifier/mod.rs +1941 -0
  122. data/ext/cargo-vendor/cranelift-codegen-0.112.0/src/write.rs +694 -0
  123. data/ext/cargo-vendor/cranelift-codegen-meta-0.112.0/.cargo-checksum.json +1 -0
  124. data/ext/cargo-vendor/cranelift-codegen-meta-0.112.0/Cargo.toml +54 -0
  125. data/ext/cargo-vendor/cranelift-codegen-meta-0.112.0/src/cdsl/settings.rs +429 -0
  126. data/ext/cargo-vendor/cranelift-codegen-meta-0.112.0/src/cdsl/types.rs +420 -0
  127. data/ext/cargo-vendor/cranelift-codegen-meta-0.112.0/src/cdsl/typevar.rs +946 -0
  128. data/ext/cargo-vendor/cranelift-codegen-meta-0.112.0/src/error.rs +48 -0
  129. data/ext/cargo-vendor/cranelift-codegen-meta-0.112.0/src/gen_inst.rs +1274 -0
  130. data/ext/cargo-vendor/cranelift-codegen-meta-0.112.0/src/gen_isle.rs +519 -0
  131. data/ext/cargo-vendor/cranelift-codegen-meta-0.112.0/src/gen_settings.rs +505 -0
  132. data/ext/cargo-vendor/cranelift-codegen-meta-0.112.0/src/gen_types.rs +70 -0
  133. data/ext/cargo-vendor/cranelift-codegen-meta-0.112.0/src/isa/arm64.rs +59 -0
  134. data/ext/cargo-vendor/cranelift-codegen-meta-0.112.0/src/isa/mod.rs +81 -0
  135. data/ext/cargo-vendor/cranelift-codegen-meta-0.112.0/src/isa/pulley.rs +14 -0
  136. data/ext/cargo-vendor/cranelift-codegen-meta-0.112.0/src/isa/riscv64.rs +181 -0
  137. data/ext/cargo-vendor/cranelift-codegen-meta-0.112.0/src/isa/x86.rs +414 -0
  138. data/ext/cargo-vendor/cranelift-codegen-meta-0.112.0/src/isle.rs +142 -0
  139. data/ext/cargo-vendor/cranelift-codegen-meta-0.112.0/src/lib.rs +98 -0
  140. data/ext/cargo-vendor/cranelift-codegen-meta-0.112.0/src/shared/instructions.rs +3801 -0
  141. data/ext/cargo-vendor/cranelift-codegen-meta-0.112.0/src/shared/mod.rs +87 -0
  142. data/ext/cargo-vendor/cranelift-codegen-meta-0.112.0/src/shared/settings.rs +361 -0
  143. data/ext/cargo-vendor/cranelift-codegen-meta-0.112.0/src/shared/types.rs +103 -0
  144. data/ext/cargo-vendor/cranelift-codegen-meta-0.112.0/src/srcgen.rs +464 -0
  145. data/ext/cargo-vendor/cranelift-codegen-shared-0.112.0/.cargo-checksum.json +1 -0
  146. data/ext/cargo-vendor/cranelift-codegen-shared-0.112.0/Cargo.toml +32 -0
  147. data/ext/cargo-vendor/cranelift-control-0.112.0/.cargo-checksum.json +1 -0
  148. data/ext/cargo-vendor/cranelift-control-0.112.0/Cargo.toml +43 -0
  149. data/ext/cargo-vendor/cranelift-entity-0.112.0/.cargo-checksum.json +1 -0
  150. data/ext/cargo-vendor/cranelift-entity-0.112.0/Cargo.toml +75 -0
  151. data/ext/cargo-vendor/cranelift-entity-0.112.0/src/lib.rs +381 -0
  152. data/ext/cargo-vendor/cranelift-entity-0.112.0/src/packed_option.rs +173 -0
  153. data/ext/cargo-vendor/cranelift-entity-0.112.0/src/sparse.rs +367 -0
  154. data/ext/cargo-vendor/cranelift-frontend-0.112.0/.cargo-checksum.json +1 -0
  155. data/ext/cargo-vendor/cranelift-frontend-0.112.0/Cargo.toml +97 -0
  156. data/ext/cargo-vendor/cranelift-frontend-0.112.0/src/frontend.rs +1963 -0
  157. data/ext/cargo-vendor/cranelift-frontend-0.112.0/src/ssa.rs +1325 -0
  158. data/ext/cargo-vendor/cranelift-frontend-0.112.0/src/switch.rs +676 -0
  159. data/ext/cargo-vendor/cranelift-isle-0.112.0/.cargo-checksum.json +1 -0
  160. data/ext/cargo-vendor/cranelift-isle-0.112.0/Cargo.toml +69 -0
  161. data/ext/cargo-vendor/cranelift-isle-0.112.0/build.rs +35 -0
  162. data/ext/cargo-vendor/cranelift-isle-0.112.0/src/ast.rs +412 -0
  163. data/ext/cargo-vendor/cranelift-isle-0.112.0/src/codegen.rs +922 -0
  164. data/ext/cargo-vendor/cranelift-isle-0.112.0/src/compile.rs +65 -0
  165. data/ext/cargo-vendor/cranelift-isle-0.112.0/src/error.rs +318 -0
  166. data/ext/cargo-vendor/cranelift-isle-0.112.0/src/files.rs +133 -0
  167. data/ext/cargo-vendor/cranelift-isle-0.112.0/src/lexer.rs +343 -0
  168. data/ext/cargo-vendor/cranelift-isle-0.112.0/src/lib.rs +34 -0
  169. data/ext/cargo-vendor/cranelift-isle-0.112.0/src/overlap.rs +130 -0
  170. data/ext/cargo-vendor/cranelift-isle-0.112.0/src/parser.rs +551 -0
  171. data/ext/cargo-vendor/cranelift-isle-0.112.0/src/sema.rs +2482 -0
  172. data/ext/cargo-vendor/cranelift-isle-0.112.0/src/trie_again.rs +696 -0
  173. data/ext/cargo-vendor/cranelift-isle-0.112.0/tests/run_tests.rs +77 -0
  174. data/ext/cargo-vendor/cranelift-native-0.112.0/.cargo-checksum.json +1 -0
  175. data/ext/cargo-vendor/cranelift-native-0.112.0/Cargo.toml +52 -0
  176. data/ext/cargo-vendor/cranelift-native-0.112.0/src/lib.rs +192 -0
  177. data/ext/cargo-vendor/cranelift-wasm-0.112.0/.cargo-checksum.json +1 -0
  178. data/ext/cargo-vendor/cranelift-wasm-0.112.0/Cargo.toml +128 -0
  179. data/ext/cargo-vendor/cranelift-wasm-0.112.0/src/code_translator.rs +3723 -0
  180. data/ext/cargo-vendor/cranelift-wasm-0.112.0/src/environ/dummy.rs +897 -0
  181. data/ext/cargo-vendor/cranelift-wasm-0.112.0/src/environ/spec.rs +922 -0
  182. data/ext/cargo-vendor/cranelift-wasm-0.112.0/src/func_translator.rs +283 -0
  183. data/ext/cargo-vendor/cranelift-wasm-0.112.0/src/module_translator.rs +120 -0
  184. data/ext/cargo-vendor/cranelift-wasm-0.112.0/src/sections_translator.rs +332 -0
  185. data/ext/cargo-vendor/cranelift-wasm-0.112.0/src/translation_utils.rs +95 -0
  186. data/ext/cargo-vendor/deterministic-wasi-ctx-0.1.25/.cargo-checksum.json +1 -0
  187. data/ext/cargo-vendor/deterministic-wasi-ctx-0.1.25/Cargo.toml +69 -0
  188. data/ext/cargo-vendor/pulley-interpreter-0.1.0/.cargo-checksum.json +1 -0
  189. data/ext/cargo-vendor/pulley-interpreter-0.1.0/Cargo.toml +85 -0
  190. data/ext/cargo-vendor/pulley-interpreter-0.1.0/README.md +109 -0
  191. data/ext/cargo-vendor/pulley-interpreter-0.1.0/src/decode.rs +657 -0
  192. data/ext/cargo-vendor/pulley-interpreter-0.1.0/src/disas.rs +256 -0
  193. data/ext/cargo-vendor/pulley-interpreter-0.1.0/src/encode.rs +198 -0
  194. data/ext/cargo-vendor/pulley-interpreter-0.1.0/src/imms.rs +31 -0
  195. data/ext/cargo-vendor/pulley-interpreter-0.1.0/src/interp.rs +1113 -0
  196. data/ext/cargo-vendor/pulley-interpreter-0.1.0/src/lib.rs +215 -0
  197. data/ext/cargo-vendor/pulley-interpreter-0.1.0/src/op.rs +256 -0
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  1292. /data/ext/cargo-vendor/{cranelift-bitset-0.111.0 → cranelift-bitset-0.112.0}/src/compound.rs +0 -0
  1293. /data/ext/cargo-vendor/{cranelift-bitset-0.111.0 → cranelift-bitset-0.112.0}/src/lib.rs +0 -0
  1294. /data/ext/cargo-vendor/{cranelift-bitset-0.111.0 → cranelift-bitset-0.112.0}/tests/bitset.rs +0 -0
  1295. /data/ext/cargo-vendor/{cranelift-codegen-0.111.0 → cranelift-codegen-0.112.0}/LICENSE +0 -0
  1296. /data/ext/cargo-vendor/{cranelift-codegen-0.111.0 → cranelift-codegen-0.112.0}/README.md +0 -0
  1297. /data/ext/cargo-vendor/{cranelift-codegen-0.111.0 → cranelift-codegen-0.112.0}/benches/x64-evex-encoding.rs +0 -0
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  1351. /data/ext/cargo-vendor/{cranelift-codegen-0.111.0 → cranelift-codegen-0.112.0}/src/legalizer/globalvalue.rs +0 -0
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  1377. /data/ext/cargo-vendor/{cranelift-codegen-0.111.0 → cranelift-codegen-0.112.0}/src/unionfind.rs +0 -0
  1378. /data/ext/cargo-vendor/{cranelift-codegen-0.111.0 → cranelift-codegen-0.112.0}/src/unreachable_code.rs +0 -0
  1379. /data/ext/cargo-vendor/{cranelift-codegen-0.111.0 → cranelift-codegen-0.112.0}/src/value_label.rs +0 -0
  1380. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.111.0 → cranelift-codegen-meta-0.112.0}/LICENSE +0 -0
  1381. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.111.0 → cranelift-codegen-meta-0.112.0}/README.md +0 -0
  1382. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.111.0 → cranelift-codegen-meta-0.112.0}/src/cdsl/formats.rs +0 -0
  1383. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.111.0 → cranelift-codegen-meta-0.112.0}/src/cdsl/instructions.rs +0 -0
  1384. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.111.0 → cranelift-codegen-meta-0.112.0}/src/cdsl/isa.rs +0 -0
  1385. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.111.0 → cranelift-codegen-meta-0.112.0}/src/cdsl/mod.rs +0 -0
  1386. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.111.0 → cranelift-codegen-meta-0.112.0}/src/cdsl/operands.rs +0 -0
  1387. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.111.0 → cranelift-codegen-meta-0.112.0}/src/constant_hash.rs +0 -0
  1388. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.111.0 → cranelift-codegen-meta-0.112.0}/src/isa/s390x.rs +0 -0
  1389. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.111.0 → cranelift-codegen-meta-0.112.0}/src/shared/entities.rs +0 -0
  1390. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.111.0 → cranelift-codegen-meta-0.112.0}/src/shared/formats.rs +0 -0
  1391. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.111.0 → cranelift-codegen-meta-0.112.0}/src/shared/immediates.rs +0 -0
  1392. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.111.0 → cranelift-codegen-meta-0.112.0}/src/unique_table.rs +0 -0
  1393. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.111.0 → cranelift-codegen-shared-0.112.0}/LICENSE +0 -0
  1394. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.111.0 → cranelift-codegen-shared-0.112.0}/README.md +0 -0
  1395. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.111.0 → cranelift-codegen-shared-0.112.0}/src/constant_hash.rs +0 -0
  1396. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.111.0 → cranelift-codegen-shared-0.112.0}/src/constants.rs +0 -0
  1397. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.111.0 → cranelift-codegen-shared-0.112.0}/src/lib.rs +0 -0
  1398. /data/ext/cargo-vendor/{cranelift-control-0.111.0 → cranelift-control-0.112.0}/LICENSE +0 -0
  1399. /data/ext/cargo-vendor/{cranelift-control-0.111.0 → cranelift-control-0.112.0}/README.md +0 -0
  1400. /data/ext/cargo-vendor/{cranelift-control-0.111.0 → cranelift-control-0.112.0}/src/chaos.rs +0 -0
  1401. /data/ext/cargo-vendor/{cranelift-control-0.111.0 → cranelift-control-0.112.0}/src/lib.rs +0 -0
  1402. /data/ext/cargo-vendor/{cranelift-control-0.111.0 → cranelift-control-0.112.0}/src/zero_sized.rs +0 -0
  1403. /data/ext/cargo-vendor/{cranelift-entity-0.111.0 → cranelift-entity-0.112.0}/LICENSE +0 -0
  1404. /data/ext/cargo-vendor/{cranelift-entity-0.111.0 → cranelift-entity-0.112.0}/README.md +0 -0
  1405. /data/ext/cargo-vendor/{cranelift-entity-0.111.0 → cranelift-entity-0.112.0}/src/boxed_slice.rs +0 -0
  1406. /data/ext/cargo-vendor/{cranelift-entity-0.111.0 → cranelift-entity-0.112.0}/src/iter.rs +0 -0
  1407. /data/ext/cargo-vendor/{cranelift-entity-0.111.0 → cranelift-entity-0.112.0}/src/keys.rs +0 -0
  1408. /data/ext/cargo-vendor/{cranelift-entity-0.111.0 → cranelift-entity-0.112.0}/src/list.rs +0 -0
  1409. /data/ext/cargo-vendor/{cranelift-entity-0.111.0 → cranelift-entity-0.112.0}/src/map.rs +0 -0
  1410. /data/ext/cargo-vendor/{cranelift-entity-0.111.0 → cranelift-entity-0.112.0}/src/primary.rs +0 -0
  1411. /data/ext/cargo-vendor/{cranelift-entity-0.111.0 → cranelift-entity-0.112.0}/src/set.rs +0 -0
  1412. /data/ext/cargo-vendor/{cranelift-entity-0.111.0 → cranelift-entity-0.112.0}/src/unsigned.rs +0 -0
  1413. /data/ext/cargo-vendor/{cranelift-frontend-0.111.0 → cranelift-frontend-0.112.0}/LICENSE +0 -0
  1414. /data/ext/cargo-vendor/{cranelift-frontend-0.111.0 → cranelift-frontend-0.112.0}/README.md +0 -0
  1415. /data/ext/cargo-vendor/{cranelift-frontend-0.111.0 → cranelift-frontend-0.112.0}/src/frontend/safepoints.rs +0 -0
  1416. /data/ext/cargo-vendor/{cranelift-frontend-0.111.0 → cranelift-frontend-0.112.0}/src/lib.rs +0 -0
  1417. /data/ext/cargo-vendor/{cranelift-frontend-0.111.0 → cranelift-frontend-0.112.0}/src/variable.rs +0 -0
  1418. /data/ext/cargo-vendor/{cranelift-isle-0.111.0 → cranelift-isle-0.112.0}/README.md +0 -0
  1419. /data/ext/cargo-vendor/{cranelift-isle-0.111.0 → cranelift-isle-0.112.0}/isle_examples/fail/bad_converters.isle +0 -0
  1420. /data/ext/cargo-vendor/{cranelift-isle-0.111.0 → cranelift-isle-0.112.0}/isle_examples/fail/bound_var_type_mismatch.isle +0 -0
  1421. /data/ext/cargo-vendor/{cranelift-isle-0.111.0 → cranelift-isle-0.112.0}/isle_examples/fail/converter_extractor_constructor.isle +0 -0
  1422. /data/ext/cargo-vendor/{cranelift-isle-0.111.0 → cranelift-isle-0.112.0}/isle_examples/fail/error1.isle +0 -0
  1423. /data/ext/cargo-vendor/{cranelift-isle-0.111.0 → cranelift-isle-0.112.0}/isle_examples/fail/extra_parens.isle +0 -0
  1424. /data/ext/cargo-vendor/{cranelift-isle-0.111.0 → cranelift-isle-0.112.0}/isle_examples/fail/impure_expression.isle +0 -0
  1425. /data/ext/cargo-vendor/{cranelift-isle-0.111.0 → cranelift-isle-0.112.0}/isle_examples/fail/impure_rhs.isle +0 -0
  1426. /data/ext/cargo-vendor/{cranelift-isle-0.111.0 → cranelift-isle-0.112.0}/isle_examples/fail/multi_internal_etor.isle +0 -0
  1427. /data/ext/cargo-vendor/{cranelift-isle-0.111.0 → cranelift-isle-0.112.0}/isle_examples/fail/multi_prio.isle +0 -0
  1428. /data/ext/cargo-vendor/{cranelift-isle-0.111.0 → cranelift-isle-0.112.0}/isle_examples/link/borrows.isle +0 -0
  1429. /data/ext/cargo-vendor/{cranelift-isle-0.111.0 → cranelift-isle-0.112.0}/isle_examples/link/borrows_main.rs +0 -0
  1430. /data/ext/cargo-vendor/{cranelift-isle-0.111.0 → cranelift-isle-0.112.0}/isle_examples/link/iflets.isle +0 -0
  1431. /data/ext/cargo-vendor/{cranelift-isle-0.111.0 → cranelift-isle-0.112.0}/isle_examples/link/iflets_main.rs +0 -0
  1432. /data/ext/cargo-vendor/{cranelift-isle-0.111.0 → cranelift-isle-0.112.0}/isle_examples/link/multi_constructor.isle +0 -0
  1433. /data/ext/cargo-vendor/{cranelift-isle-0.111.0 → cranelift-isle-0.112.0}/isle_examples/link/multi_constructor_main.rs +0 -0
  1434. /data/ext/cargo-vendor/{cranelift-isle-0.111.0 → cranelift-isle-0.112.0}/isle_examples/link/multi_extractor.isle +0 -0
  1435. /data/ext/cargo-vendor/{cranelift-isle-0.111.0 → cranelift-isle-0.112.0}/isle_examples/link/multi_extractor_main.rs +0 -0
  1436. /data/ext/cargo-vendor/{cranelift-isle-0.111.0 → cranelift-isle-0.112.0}/isle_examples/link/test.isle +0 -0
  1437. /data/ext/cargo-vendor/{cranelift-isle-0.111.0 → cranelift-isle-0.112.0}/isle_examples/link/test_main.rs +0 -0
  1438. /data/ext/cargo-vendor/{cranelift-isle-0.111.0 → cranelift-isle-0.112.0}/isle_examples/pass/bound_var.isle +0 -0
  1439. /data/ext/cargo-vendor/{cranelift-isle-0.111.0 → cranelift-isle-0.112.0}/isle_examples/pass/construct_and_extract.isle +0 -0
  1440. /data/ext/cargo-vendor/{cranelift-isle-0.111.0 → cranelift-isle-0.112.0}/isle_examples/pass/conversions.isle +0 -0
  1441. /data/ext/cargo-vendor/{cranelift-isle-0.111.0 → cranelift-isle-0.112.0}/isle_examples/pass/conversions_extern.isle +0 -0
  1442. /data/ext/cargo-vendor/{cranelift-isle-0.111.0 → cranelift-isle-0.112.0}/isle_examples/pass/let.isle +0 -0
  1443. /data/ext/cargo-vendor/{cranelift-isle-0.111.0 → cranelift-isle-0.112.0}/isle_examples/pass/nodebug.isle +0 -0
  1444. /data/ext/cargo-vendor/{cranelift-isle-0.111.0 → cranelift-isle-0.112.0}/isle_examples/pass/prio_trie_bug.isle +0 -0
  1445. /data/ext/cargo-vendor/{cranelift-isle-0.111.0 → cranelift-isle-0.112.0}/isle_examples/pass/test2.isle +0 -0
  1446. /data/ext/cargo-vendor/{cranelift-isle-0.111.0 → cranelift-isle-0.112.0}/isle_examples/pass/test3.isle +0 -0
  1447. /data/ext/cargo-vendor/{cranelift-isle-0.111.0 → cranelift-isle-0.112.0}/isle_examples/pass/test4.isle +0 -0
  1448. /data/ext/cargo-vendor/{cranelift-isle-0.111.0 → cranelift-isle-0.112.0}/isle_examples/pass/tutorial.isle +0 -0
  1449. /data/ext/cargo-vendor/{cranelift-isle-0.111.0 → cranelift-isle-0.112.0}/isle_examples/run/iconst.isle +0 -0
  1450. /data/ext/cargo-vendor/{cranelift-isle-0.111.0 → cranelift-isle-0.112.0}/isle_examples/run/iconst_main.rs +0 -0
  1451. /data/ext/cargo-vendor/{cranelift-isle-0.111.0 → cranelift-isle-0.112.0}/isle_examples/run/let_shadowing.isle +0 -0
  1452. /data/ext/cargo-vendor/{cranelift-isle-0.111.0 → cranelift-isle-0.112.0}/isle_examples/run/let_shadowing_main.rs +0 -0
  1453. /data/ext/cargo-vendor/{cranelift-isle-0.111.0 → cranelift-isle-0.112.0}/src/disjointsets.rs +0 -0
  1454. /data/ext/cargo-vendor/{cranelift-isle-0.111.0 → cranelift-isle-0.112.0}/src/log.rs +0 -0
  1455. /data/ext/cargo-vendor/{cranelift-isle-0.111.0 → cranelift-isle-0.112.0}/src/serialize.rs +0 -0
  1456. /data/ext/cargo-vendor/{cranelift-isle-0.111.0 → cranelift-isle-0.112.0}/src/stablemapset.rs +0 -0
  1457. /data/ext/cargo-vendor/{cranelift-native-0.111.0 → cranelift-native-0.112.0}/LICENSE +0 -0
  1458. /data/ext/cargo-vendor/{cranelift-native-0.111.0 → cranelift-native-0.112.0}/README.md +0 -0
  1459. /data/ext/cargo-vendor/{cranelift-native-0.111.0 → cranelift-native-0.112.0}/src/riscv.rs +0 -0
  1460. /data/ext/cargo-vendor/{cranelift-wasm-0.111.0 → cranelift-wasm-0.112.0}/LICENSE +0 -0
  1461. /data/ext/cargo-vendor/{cranelift-wasm-0.111.0 → cranelift-wasm-0.112.0}/README.md +0 -0
  1462. /data/ext/cargo-vendor/{cranelift-wasm-0.111.0 → cranelift-wasm-0.112.0}/src/code_translator/bounds_checks.rs +0 -0
  1463. /data/ext/cargo-vendor/{cranelift-wasm-0.111.0 → cranelift-wasm-0.112.0}/src/environ/mod.rs +0 -0
  1464. /data/ext/cargo-vendor/{cranelift-wasm-0.111.0 → cranelift-wasm-0.112.0}/src/heap.rs +0 -0
  1465. /data/ext/cargo-vendor/{cranelift-wasm-0.111.0 → cranelift-wasm-0.112.0}/src/lib.rs +0 -0
  1466. /data/ext/cargo-vendor/{cranelift-wasm-0.111.0 → cranelift-wasm-0.112.0}/src/state.rs +0 -0
  1467. /data/ext/cargo-vendor/{cranelift-wasm-0.111.0 → cranelift-wasm-0.112.0}/src/table.rs +0 -0
  1468. /data/ext/cargo-vendor/{deterministic-wasi-ctx-0.1.24 → deterministic-wasi-ctx-0.1.25}/README.md +0 -0
  1469. /data/ext/cargo-vendor/{deterministic-wasi-ctx-0.1.24 → deterministic-wasi-ctx-0.1.25}/src/clocks.rs +0 -0
  1470. /data/ext/cargo-vendor/{deterministic-wasi-ctx-0.1.24 → deterministic-wasi-ctx-0.1.25}/src/lib.rs +0 -0
  1471. /data/ext/cargo-vendor/{deterministic-wasi-ctx-0.1.24 → deterministic-wasi-ctx-0.1.25}/src/noop_scheduler.rs +0 -0
  1472. /data/ext/cargo-vendor/{deterministic-wasi-ctx-0.1.24 → deterministic-wasi-ctx-0.1.25}/tests/clocks.rs +0 -0
  1473. /data/ext/cargo-vendor/{deterministic-wasi-ctx-0.1.24 → deterministic-wasi-ctx-0.1.25}/tests/common/mod.rs +0 -0
  1474. /data/ext/cargo-vendor/{deterministic-wasi-ctx-0.1.24 → deterministic-wasi-ctx-0.1.25}/tests/random.rs +0 -0
  1475. /data/ext/cargo-vendor/{deterministic-wasi-ctx-0.1.24 → deterministic-wasi-ctx-0.1.25}/tests/scheduler.rs +0 -0
  1476. /data/ext/cargo-vendor/{regalloc2-0.9.3 → regalloc2-0.10.2}/LICENSE +0 -0
  1477. /data/ext/cargo-vendor/{regalloc2-0.9.3 → regalloc2-0.10.2}/README.md +0 -0
  1478. /data/ext/cargo-vendor/{regalloc2-0.9.3 → regalloc2-0.10.2}/deny.toml +0 -0
  1479. /data/ext/cargo-vendor/{regalloc2-0.9.3 → regalloc2-0.10.2}/doc/TODO +0 -0
  1480. /data/ext/cargo-vendor/{regalloc2-0.9.3 → regalloc2-0.10.2}/src/domtree.rs +0 -0
  1481. /data/ext/cargo-vendor/{regalloc2-0.9.3 → regalloc2-0.10.2}/src/indexset.rs +0 -0
  1482. /data/ext/cargo-vendor/{regalloc2-0.9.3 → regalloc2-0.10.2}/src/ion/dump.rs +0 -0
  1483. /data/ext/cargo-vendor/{regalloc2-0.9.3 → regalloc2-0.10.2}/src/ion/redundant_moves.rs +0 -0
  1484. /data/ext/cargo-vendor/{regalloc2-0.9.3 → regalloc2-0.10.2}/src/ion/reg_traversal.rs +0 -0
  1485. /data/ext/cargo-vendor/{regalloc2-0.9.3 → regalloc2-0.10.2}/src/ion/spill.rs +0 -0
  1486. /data/ext/cargo-vendor/{regalloc2-0.9.3 → regalloc2-0.10.2}/src/moves.rs +0 -0
  1487. /data/ext/cargo-vendor/{regalloc2-0.9.3 → regalloc2-0.10.2}/src/postorder.rs +0 -0
  1488. /data/ext/cargo-vendor/{regalloc2-0.9.3 → regalloc2-0.10.2}/src/ssa.rs +0 -0
  1489. /data/ext/cargo-vendor/{wasi-common-24.0.0 → wasi-common-25.0.0}/LICENSE +0 -0
  1490. /data/ext/cargo-vendor/{wasi-common-24.0.0 → wasi-common-25.0.0}/README.md +0 -0
  1491. /data/ext/cargo-vendor/{wasi-common-24.0.0 → wasi-common-25.0.0}/src/clocks.rs +0 -0
  1492. /data/ext/cargo-vendor/{wasi-common-24.0.0 → wasi-common-25.0.0}/src/dir.rs +0 -0
  1493. /data/ext/cargo-vendor/{wasi-common-24.0.0 → wasi-common-25.0.0}/src/error.rs +0 -0
  1494. /data/ext/cargo-vendor/{wasi-common-24.0.0 → wasi-common-25.0.0}/src/file.rs +0 -0
  1495. /data/ext/cargo-vendor/{wasi-common-24.0.0 → wasi-common-25.0.0}/src/pipe.rs +0 -0
  1496. /data/ext/cargo-vendor/{wasi-common-24.0.0 → wasi-common-25.0.0}/src/random.rs +0 -0
  1497. /data/ext/cargo-vendor/{wasi-common-24.0.0 → wasi-common-25.0.0}/src/sched/subscription.rs +0 -0
  1498. /data/ext/cargo-vendor/{wasi-common-24.0.0 → wasi-common-25.0.0}/src/sched.rs +0 -0
  1499. /data/ext/cargo-vendor/{wasi-common-24.0.0 → wasi-common-25.0.0}/src/snapshots/preview_0.rs +0 -0
  1500. /data/ext/cargo-vendor/{wasi-common-24.0.0 → wasi-common-25.0.0}/src/snapshots/preview_1/error.rs +0 -0
  1501. /data/ext/cargo-vendor/{wasi-common-24.0.0 → wasi-common-25.0.0}/src/snapshots/preview_1.rs +0 -0
  1502. /data/ext/cargo-vendor/{wasi-common-24.0.0 → wasi-common-25.0.0}/src/string_array.rs +0 -0
  1503. /data/ext/cargo-vendor/{wasi-common-24.0.0 → wasi-common-25.0.0}/src/sync/clocks.rs +0 -0
  1504. /data/ext/cargo-vendor/{wasi-common-24.0.0 → wasi-common-25.0.0}/src/sync/file.rs +0 -0
  1505. /data/ext/cargo-vendor/{wasi-common-24.0.0 → wasi-common-25.0.0}/src/sync/mod.rs +0 -0
  1506. /data/ext/cargo-vendor/{wasi-common-24.0.0 → wasi-common-25.0.0}/src/sync/net.rs +0 -0
  1507. /data/ext/cargo-vendor/{wasi-common-24.0.0 → wasi-common-25.0.0}/src/sync/sched/unix.rs +0 -0
  1508. /data/ext/cargo-vendor/{wasi-common-24.0.0 → wasi-common-25.0.0}/src/sync/sched/windows.rs +0 -0
  1509. /data/ext/cargo-vendor/{wasi-common-24.0.0 → wasi-common-25.0.0}/src/sync/sched.rs +0 -0
  1510. /data/ext/cargo-vendor/{wasi-common-24.0.0 → wasi-common-25.0.0}/src/sync/stdio.rs +0 -0
  1511. /data/ext/cargo-vendor/{wasi-common-24.0.0 → wasi-common-25.0.0}/src/table.rs +0 -0
  1512. /data/ext/cargo-vendor/{wasi-common-24.0.0 → wasi-common-25.0.0}/src/tokio/file.rs +0 -0
  1513. /data/ext/cargo-vendor/{wasi-common-24.0.0 → wasi-common-25.0.0}/src/tokio/mod.rs +0 -0
  1514. /data/ext/cargo-vendor/{wasi-common-24.0.0 → wasi-common-25.0.0}/src/tokio/net.rs +0 -0
  1515. /data/ext/cargo-vendor/{wasi-common-24.0.0 → wasi-common-25.0.0}/src/tokio/sched/unix.rs +0 -0
  1516. /data/ext/cargo-vendor/{wasi-common-24.0.0 → wasi-common-25.0.0}/src/tokio/sched/windows.rs +0 -0
  1517. /data/ext/cargo-vendor/{wasi-common-24.0.0 → wasi-common-25.0.0}/src/tokio/sched.rs +0 -0
  1518. /data/ext/cargo-vendor/{wasi-common-24.0.0 → wasi-common-25.0.0}/src/tokio/stdio.rs +0 -0
  1519. /data/ext/cargo-vendor/{wasi-common-24.0.0 → wasi-common-25.0.0}/witx/preview0/typenames.witx +0 -0
  1520. /data/ext/cargo-vendor/{wasi-common-24.0.0 → wasi-common-25.0.0}/witx/preview0/wasi_unstable.witx +0 -0
  1521. /data/ext/cargo-vendor/{wasi-common-24.0.0 → wasi-common-25.0.0}/witx/preview1/typenames.witx +0 -0
  1522. /data/ext/cargo-vendor/{wasi-common-24.0.0 → wasi-common-25.0.0}/witx/preview1/wasi_snapshot_preview1.witx +0 -0
  1523. /data/ext/cargo-vendor/{wasm-encoder-0.215.0 → wasm-encoder-0.217.0}/README.md +0 -0
  1524. /data/ext/cargo-vendor/{wasm-encoder-0.215.0 → wasm-encoder-0.217.0}/src/component/aliases.rs +0 -0
  1525. /data/ext/cargo-vendor/{wasm-encoder-0.215.0 → wasm-encoder-0.217.0}/src/component/canonicals.rs +0 -0
  1526. /data/ext/cargo-vendor/{wasm-encoder-0.215.0 → wasm-encoder-0.217.0}/src/component/components.rs +0 -0
  1527. /data/ext/cargo-vendor/{wasm-encoder-0.215.0 → wasm-encoder-0.217.0}/src/component/modules.rs +0 -0
  1528. /data/ext/cargo-vendor/{wasm-encoder-0.216.0 → wasm-encoder-0.217.0}/src/component/names.rs +0 -0
  1529. /data/ext/cargo-vendor/{wasm-encoder-0.215.0 → wasm-encoder-0.217.0}/src/component/start.rs +0 -0
  1530. /data/ext/cargo-vendor/{wasm-encoder-0.215.0 → wasm-encoder-0.217.0}/src/component.rs +0 -0
  1531. /data/ext/cargo-vendor/{wasm-encoder-0.215.0 → wasm-encoder-0.217.0}/src/core/custom.rs +0 -0
  1532. /data/ext/cargo-vendor/{wasm-encoder-0.215.0 → wasm-encoder-0.217.0}/src/core/data.rs +0 -0
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  1550. /data/ext/cargo-vendor/{wasm-encoder-0.216.0 → wasm-encoder-0.217.0}/src/reencode/component.rs +0 -0
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  1579. /data/ext/cargo-vendor/{wasmparser-0.215.0 → wasmparser-0.217.0}/tests/big-module.rs +0 -0
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  1691. /data/ext/cargo-vendor/{wasmtime-24.0.0 → wasmtime-25.0.0}/src/runtime/vm/sys/windows/mod.rs +0 -0
  1692. /data/ext/cargo-vendor/{wasmtime-24.0.0 → wasmtime-25.0.0}/src/runtime/vm/sys/windows/unwind.rs +0 -0
  1693. /data/ext/cargo-vendor/{wasmtime-24.0.0 → wasmtime-25.0.0}/src/runtime/vm/sys/windows/vm.rs +0 -0
  1694. /data/ext/cargo-vendor/{wasmtime-24.0.0 → wasmtime-25.0.0}/src/runtime/vm/table.rs +0 -0
  1695. /data/ext/cargo-vendor/{wasmtime-24.0.0 → wasmtime-25.0.0}/src/runtime/vm/threads/mod.rs +0 -0
  1696. /data/ext/cargo-vendor/{wasmtime-24.0.0 → wasmtime-25.0.0}/src/runtime/vm/threads/shared_memory.rs +0 -0
  1697. /data/ext/cargo-vendor/{wasmtime-24.0.0 → wasmtime-25.0.0}/src/runtime/vm/threads/shared_memory_disabled.rs +0 -0
  1698. /data/ext/cargo-vendor/{wasmtime-24.0.0 → wasmtime-25.0.0}/src/runtime/vm/traphandlers/backtrace.rs +0 -0
  1699. /data/ext/cargo-vendor/{wasmtime-24.0.0 → wasmtime-25.0.0}/src/runtime/vm/traphandlers/coredump_disabled.rs +0 -0
  1700. /data/ext/cargo-vendor/{wasmtime-24.0.0 → wasmtime-25.0.0}/src/runtime/vm/traphandlers/coredump_enabled.rs +0 -0
  1701. /data/ext/cargo-vendor/{wasmtime-24.0.0 → wasmtime-25.0.0}/src/runtime/vm/vmcontext/vm_host_func_context.rs +0 -0
  1702. /data/ext/cargo-vendor/{wasmtime-24.0.0 → wasmtime-25.0.0}/src/runtime/vm.rs +0 -0
  1703. /data/ext/cargo-vendor/{wasmtime-24.0.0 → wasmtime-25.0.0}/src/runtime/windows.rs +0 -0
  1704. /data/ext/cargo-vendor/{wasmtime-24.0.0 → wasmtime-25.0.0}/src/runtime.rs +0 -0
  1705. /data/ext/cargo-vendor/{wasmtime-24.0.0 → wasmtime-25.0.0}/src/sync_nostd.rs +0 -0
  1706. /data/ext/cargo-vendor/{wasmtime-24.0.0 → wasmtime-25.0.0}/src/sync_std.rs +0 -0
  1707. /data/ext/cargo-vendor/{wasmtime-asm-macros-24.0.0 → wasmtime-asm-macros-25.0.0}/src/lib.rs +0 -0
  1708. /data/ext/cargo-vendor/{wasmtime-cache-24.0.0 → wasmtime-cache-25.0.0}/LICENSE +0 -0
  1709. /data/ext/cargo-vendor/{wasmtime-cache-24.0.0 → wasmtime-cache-25.0.0}/src/config/tests.rs +0 -0
  1710. /data/ext/cargo-vendor/{wasmtime-cache-24.0.0 → wasmtime-cache-25.0.0}/src/tests.rs +0 -0
  1711. /data/ext/cargo-vendor/{wasmtime-cache-24.0.0 → wasmtime-cache-25.0.0}/src/worker/tests/system_time_stub.rs +0 -0
  1712. /data/ext/cargo-vendor/{wasmtime-cache-24.0.0 → wasmtime-cache-25.0.0}/tests/cache_write_default_config.rs +0 -0
  1713. /data/ext/cargo-vendor/{wasmtime-component-macro-24.0.0 → wasmtime-component-macro-25.0.0}/build.rs +0 -0
  1714. /data/ext/cargo-vendor/{wasmtime-component-macro-24.0.0 → wasmtime-component-macro-25.0.0}/src/lib.rs +0 -0
  1715. /data/ext/cargo-vendor/{wasmtime-component-macro-24.0.0 → wasmtime-component-macro-25.0.0}/tests/codegen/char.wit +0 -0
  1716. /data/ext/cargo-vendor/{wasmtime-component-macro-24.0.0 → wasmtime-component-macro-25.0.0}/tests/codegen/conventions.wit +0 -0
  1717. /data/ext/cargo-vendor/{wasmtime-component-macro-24.0.0 → wasmtime-component-macro-25.0.0}/tests/codegen/dead-code.wit +0 -0
  1718. /data/ext/cargo-vendor/{wasmtime-component-macro-24.0.0 → wasmtime-component-macro-25.0.0}/tests/codegen/direct-import.wit +0 -0
  1719. /data/ext/cargo-vendor/{wasmtime-component-macro-24.0.0 → wasmtime-component-macro-25.0.0}/tests/codegen/empty.wit +0 -0
  1720. /data/ext/cargo-vendor/{wasmtime-component-macro-24.0.0 → wasmtime-component-macro-25.0.0}/tests/codegen/flags.wit +0 -0
  1721. /data/ext/cargo-vendor/{wasmtime-component-macro-24.0.0 → wasmtime-component-macro-25.0.0}/tests/codegen/floats.wit +0 -0
  1722. /data/ext/cargo-vendor/{wasmtime-component-macro-24.0.0 → wasmtime-component-macro-25.0.0}/tests/codegen/function-new.wit +0 -0
  1723. /data/ext/cargo-vendor/{wasmtime-component-macro-24.0.0 → wasmtime-component-macro-25.0.0}/tests/codegen/integers.wit +0 -0
  1724. /data/ext/cargo-vendor/{wasmtime-component-macro-24.0.0 → wasmtime-component-macro-25.0.0}/tests/codegen/lists.wit +0 -0
  1725. /data/ext/cargo-vendor/{wasmtime-component-macro-24.0.0 → wasmtime-component-macro-25.0.0}/tests/codegen/many-arguments.wit +0 -0
  1726. /data/ext/cargo-vendor/{wasmtime-component-macro-24.0.0 → wasmtime-component-macro-25.0.0}/tests/codegen/multi-return.wit +0 -0
  1727. /data/ext/cargo-vendor/{wasmtime-component-macro-24.0.0 → wasmtime-component-macro-25.0.0}/tests/codegen/multiversion/deps/v1/root.wit +0 -0
  1728. /data/ext/cargo-vendor/{wasmtime-component-macro-24.0.0 → wasmtime-component-macro-25.0.0}/tests/codegen/multiversion/deps/v2/root.wit +0 -0
  1729. /data/ext/cargo-vendor/{wasmtime-component-macro-24.0.0 → wasmtime-component-macro-25.0.0}/tests/codegen/multiversion/root.wit +0 -0
  1730. /data/ext/cargo-vendor/{wasmtime-component-macro-24.0.0 → wasmtime-component-macro-25.0.0}/tests/codegen/records.wit +0 -0
  1731. /data/ext/cargo-vendor/{wasmtime-component-macro-24.0.0 → wasmtime-component-macro-25.0.0}/tests/codegen/rename.wit +0 -0
  1732. /data/ext/cargo-vendor/{wasmtime-component-macro-24.0.0 → wasmtime-component-macro-25.0.0}/tests/codegen/resources-export.wit +0 -0
  1733. /data/ext/cargo-vendor/{wasmtime-component-macro-24.0.0 → wasmtime-component-macro-25.0.0}/tests/codegen/resources-import.wit +0 -0
  1734. /data/ext/cargo-vendor/{wasmtime-component-macro-24.0.0 → wasmtime-component-macro-25.0.0}/tests/codegen/share-types.wit +0 -0
  1735. /data/ext/cargo-vendor/{wasmtime-component-macro-24.0.0 → wasmtime-component-macro-25.0.0}/tests/codegen/simple-functions.wit +0 -0
  1736. /data/ext/cargo-vendor/{wasmtime-component-macro-24.0.0 → wasmtime-component-macro-25.0.0}/tests/codegen/simple-lists.wit +0 -0
  1737. /data/ext/cargo-vendor/{wasmtime-component-macro-24.0.0 → wasmtime-component-macro-25.0.0}/tests/codegen/simple-wasi.wit +0 -0
  1738. /data/ext/cargo-vendor/{wasmtime-component-macro-24.0.0 → wasmtime-component-macro-25.0.0}/tests/codegen/small-anonymous.wit +0 -0
  1739. /data/ext/cargo-vendor/{wasmtime-component-macro-24.0.0 → wasmtime-component-macro-25.0.0}/tests/codegen/smoke-default.wit +0 -0
  1740. /data/ext/cargo-vendor/{wasmtime-component-macro-24.0.0 → wasmtime-component-macro-25.0.0}/tests/codegen/smoke-export.wit +0 -0
  1741. /data/ext/cargo-vendor/{wasmtime-component-macro-24.0.0 → wasmtime-component-macro-25.0.0}/tests/codegen/smoke.wit +0 -0
  1742. /data/ext/cargo-vendor/{wasmtime-component-macro-24.0.0 → wasmtime-component-macro-25.0.0}/tests/codegen/strings.wit +0 -0
  1743. /data/ext/cargo-vendor/{wasmtime-component-macro-24.0.0 → wasmtime-component-macro-25.0.0}/tests/codegen/unversioned-foo.wit +0 -0
  1744. /data/ext/cargo-vendor/{wasmtime-component-macro-24.0.0 → wasmtime-component-macro-25.0.0}/tests/codegen/use-paths.wit +0 -0
  1745. /data/ext/cargo-vendor/{wasmtime-component-macro-24.0.0 → wasmtime-component-macro-25.0.0}/tests/codegen/variants.wit +0 -0
  1746. /data/ext/cargo-vendor/{wasmtime-component-macro-24.0.0 → wasmtime-component-macro-25.0.0}/tests/codegen/wat.wit +0 -0
  1747. /data/ext/cargo-vendor/{wasmtime-component-macro-24.0.0 → wasmtime-component-macro-25.0.0}/tests/codegen/worlds-with-types.wit +0 -0
  1748. /data/ext/cargo-vendor/{wasmtime-component-macro-24.0.0 → wasmtime-component-macro-25.0.0}/tests/codegen_no_std.rs +0 -0
  1749. /data/ext/cargo-vendor/{wasmtime-component-util-24.0.0 → wasmtime-component-util-25.0.0}/src/lib.rs +0 -0
  1750. /data/ext/cargo-vendor/{wasmtime-cranelift-24.0.0 → wasmtime-cranelift-25.0.0}/LICENSE +0 -0
  1751. /data/ext/cargo-vendor/{wasmtime-cranelift-24.0.0 → wasmtime-cranelift-25.0.0}/SECURITY.md +0 -0
  1752. /data/ext/cargo-vendor/{wasmtime-cranelift-24.0.0 → wasmtime-cranelift-25.0.0}/src/builder.rs +0 -0
  1753. /data/ext/cargo-vendor/{wasmtime-cranelift-24.0.0 → wasmtime-cranelift-25.0.0}/src/compiled_function.rs +0 -0
  1754. /data/ext/cargo-vendor/{wasmtime-cranelift-24.0.0 → wasmtime-cranelift-25.0.0}/src/compiler/component.rs +0 -0
  1755. /data/ext/cargo-vendor/{wasmtime-cranelift-24.0.0 → wasmtime-cranelift-25.0.0}/src/debug/gc.rs +0 -0
  1756. /data/ext/cargo-vendor/{wasmtime-cranelift-24.0.0 → wasmtime-cranelift-25.0.0}/src/debug/transform/address_transform.rs +0 -0
  1757. /data/ext/cargo-vendor/{wasmtime-cranelift-24.0.0 → wasmtime-cranelift-25.0.0}/src/debug/transform/expression.rs +0 -0
  1758. /data/ext/cargo-vendor/{wasmtime-cranelift-24.0.0 → wasmtime-cranelift-25.0.0}/src/debug/transform/refs.rs +0 -0
  1759. /data/ext/cargo-vendor/{wasmtime-cranelift-24.0.0 → wasmtime-cranelift-25.0.0}/src/debug/transform/utils.rs +0 -0
  1760. /data/ext/cargo-vendor/{wasmtime-cranelift-24.0.0 → wasmtime-cranelift-25.0.0}/src/debug/write_debuginfo.rs +0 -0
  1761. /data/ext/cargo-vendor/{wasmtime-cranelift-24.0.0 → wasmtime-cranelift-25.0.0}/src/debug.rs +0 -0
  1762. /data/ext/cargo-vendor/{wasmtime-cranelift-24.0.0 → wasmtime-cranelift-25.0.0}/src/gc/disabled.rs +0 -0
  1763. /data/ext/cargo-vendor/{wasmtime-cranelift-24.0.0 → wasmtime-cranelift-25.0.0}/src/isa_builder.rs +0 -0
  1764. /data/ext/cargo-vendor/{wasmtime-cranelift-24.0.0 → wasmtime-cranelift-25.0.0}/src/obj.rs +0 -0
  1765. /data/ext/cargo-vendor/{wasmtime-environ-24.0.0 → wasmtime-environ-25.0.0}/LICENSE +0 -0
  1766. /data/ext/cargo-vendor/{wasmtime-environ-24.0.0 → wasmtime-environ-25.0.0}/examples/factc.rs +0 -0
  1767. /data/ext/cargo-vendor/{wasmtime-environ-24.0.0 → wasmtime-environ-25.0.0}/src/address_map.rs +0 -0
  1768. /data/ext/cargo-vendor/{wasmtime-environ-24.0.0 → wasmtime-environ-25.0.0}/src/compile/address_map.rs +0 -0
  1769. /data/ext/cargo-vendor/{wasmtime-environ-24.0.0 → wasmtime-environ-25.0.0}/src/compile/module_artifacts.rs +0 -0
  1770. /data/ext/cargo-vendor/{wasmtime-environ-24.0.0 → wasmtime-environ-25.0.0}/src/compile/module_types.rs +0 -0
  1771. /data/ext/cargo-vendor/{wasmtime-environ-24.0.0 → wasmtime-environ-25.0.0}/src/compile/trap_encoding.rs +0 -0
  1772. /data/ext/cargo-vendor/{wasmtime-environ-24.0.0 → wasmtime-environ-25.0.0}/src/component/artifacts.rs +0 -0
  1773. /data/ext/cargo-vendor/{wasmtime-environ-24.0.0 → wasmtime-environ-25.0.0}/src/component/compiler.rs +0 -0
  1774. /data/ext/cargo-vendor/{wasmtime-environ-24.0.0 → wasmtime-environ-25.0.0}/src/component/dfg.rs +0 -0
  1775. /data/ext/cargo-vendor/{wasmtime-environ-24.0.0 → wasmtime-environ-25.0.0}/src/component/info.rs +0 -0
  1776. /data/ext/cargo-vendor/{wasmtime-environ-24.0.0 → wasmtime-environ-25.0.0}/src/component/names.rs +0 -0
  1777. /data/ext/cargo-vendor/{wasmtime-environ-24.0.0 → wasmtime-environ-25.0.0}/src/component/translate/adapt.rs +0 -0
  1778. /data/ext/cargo-vendor/{wasmtime-environ-24.0.0 → wasmtime-environ-25.0.0}/src/component/translate/inline.rs +0 -0
  1779. /data/ext/cargo-vendor/{wasmtime-environ-24.0.0 → wasmtime-environ-25.0.0}/src/component/translate.rs +0 -0
  1780. /data/ext/cargo-vendor/{wasmtime-environ-24.0.0 → wasmtime-environ-25.0.0}/src/component/types_builder/resources.rs +0 -0
  1781. /data/ext/cargo-vendor/{wasmtime-environ-24.0.0 → wasmtime-environ-25.0.0}/src/component/types_builder.rs +0 -0
  1782. /data/ext/cargo-vendor/{wasmtime-environ-24.0.0 → wasmtime-environ-25.0.0}/src/component/vmcomponent_offsets.rs +0 -0
  1783. /data/ext/cargo-vendor/{wasmtime-environ-24.0.0 → wasmtime-environ-25.0.0}/src/component.rs +0 -0
  1784. /data/ext/cargo-vendor/{wasmtime-environ-24.0.0 → wasmtime-environ-25.0.0}/src/fact/core_types.rs +0 -0
  1785. /data/ext/cargo-vendor/{wasmtime-environ-24.0.0 → wasmtime-environ-25.0.0}/src/fact/signature.rs +0 -0
  1786. /data/ext/cargo-vendor/{wasmtime-environ-24.0.0 → wasmtime-environ-25.0.0}/src/fact/transcode.rs +0 -0
  1787. /data/ext/cargo-vendor/{wasmtime-environ-24.0.0 → wasmtime-environ-25.0.0}/src/fact.rs +0 -0
  1788. /data/ext/cargo-vendor/{wasmtime-environ-24.0.0 → wasmtime-environ-25.0.0}/src/gc.rs +0 -0
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  1792. /data/ext/cargo-vendor/{wasmtime-environ-24.0.0 → wasmtime-environ-25.0.0}/src/module_types.rs +0 -0
  1793. /data/ext/cargo-vendor/{wasmtime-environ-24.0.0 → wasmtime-environ-25.0.0}/src/obj.rs +0 -0
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  1795. /data/ext/cargo-vendor/{wasmtime-environ-24.0.0 → wasmtime-environ-25.0.0}/src/scopevec.rs +0 -0
  1796. /data/ext/cargo-vendor/{wasmtime-environ-24.0.0 → wasmtime-environ-25.0.0}/src/tunables.rs +0 -0
  1797. /data/ext/cargo-vendor/{wasmtime-environ-24.0.0 → wasmtime-environ-25.0.0}/src/vmoffsets.rs +0 -0
  1798. /data/ext/cargo-vendor/{wasmtime-fiber-24.0.0 → wasmtime-fiber-25.0.0}/LICENSE +0 -0
  1799. /data/ext/cargo-vendor/{wasmtime-fiber-24.0.0 → wasmtime-fiber-25.0.0}/src/unix/aarch64.rs +0 -0
  1800. /data/ext/cargo-vendor/{wasmtime-fiber-24.0.0 → wasmtime-fiber-25.0.0}/src/unix/arm.rs +0 -0
  1801. /data/ext/cargo-vendor/{wasmtime-fiber-24.0.0 → wasmtime-fiber-25.0.0}/src/unix/riscv64.rs +0 -0
  1802. /data/ext/cargo-vendor/{wasmtime-fiber-24.0.0 → wasmtime-fiber-25.0.0}/src/unix/s390x.S +0 -0
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  1806. /data/ext/cargo-vendor/{wasmtime-fiber-24.0.0 → wasmtime-fiber-25.0.0}/src/windows.c +0 -0
  1807. /data/ext/cargo-vendor/{wasmtime-fiber-24.0.0 → wasmtime-fiber-25.0.0}/src/windows.rs +0 -0
  1808. /data/ext/cargo-vendor/{wasmtime-jit-debug-24.0.0 → wasmtime-jit-debug-25.0.0}/README.md +0 -0
  1809. /data/ext/cargo-vendor/{wasmtime-jit-debug-24.0.0 → wasmtime-jit-debug-25.0.0}/src/gdb_jit_int.rs +0 -0
  1810. /data/ext/cargo-vendor/{wasmtime-jit-debug-24.0.0 → wasmtime-jit-debug-25.0.0}/src/lib.rs +0 -0
  1811. /data/ext/cargo-vendor/{wasmtime-jit-debug-24.0.0 → wasmtime-jit-debug-25.0.0}/src/perf_jitdump.rs +0 -0
  1812. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-24.0.0 → wasmtime-jit-icache-coherence-25.0.0}/src/lib.rs +0 -0
  1813. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-24.0.0 → wasmtime-jit-icache-coherence-25.0.0}/src/libc.rs +0 -0
  1814. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-24.0.0 → wasmtime-jit-icache-coherence-25.0.0}/src/miri.rs +0 -0
  1815. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-24.0.0 → wasmtime-jit-icache-coherence-25.0.0}/src/win.rs +0 -0
  1816. /data/ext/cargo-vendor/{wasmtime-slab-24.0.0 → wasmtime-slab-25.0.0}/src/lib.rs +0 -0
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  1818. /data/ext/cargo-vendor/{wasmtime-types-24.0.0 → wasmtime-types-25.0.0}/src/error.rs +0 -0
  1819. /data/ext/cargo-vendor/{wasmtime-types-24.0.0 → wasmtime-types-25.0.0}/src/prelude.rs +0 -0
  1820. /data/ext/cargo-vendor/{wasmtime-versioned-export-macros-24.0.0 → wasmtime-versioned-export-macros-25.0.0}/src/lib.rs +0 -0
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  1822. /data/ext/cargo-vendor/{wasmtime-wasi-24.0.0 → wasmtime-wasi-25.0.0}/README.md +0 -0
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  1825. /data/ext/cargo-vendor/{wasmtime-wasi-24.0.0 → wasmtime-wasi-25.0.0}/src/ctx.rs +0 -0
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  1835. /data/ext/cargo-vendor/{wasmtime-wasi-24.0.0 → wasmtime-wasi-25.0.0}/src/host/tcp.rs +0 -0
  1836. /data/ext/cargo-vendor/{wasmtime-wasi-24.0.0 → wasmtime-wasi-25.0.0}/src/host/tcp_create_socket.rs +0 -0
  1837. /data/ext/cargo-vendor/{wasmtime-wasi-24.0.0 → wasmtime-wasi-25.0.0}/src/host/udp.rs +0 -0
  1838. /data/ext/cargo-vendor/{wasmtime-wasi-24.0.0 → wasmtime-wasi-25.0.0}/src/host/udp_create_socket.rs +0 -0
  1839. /data/ext/cargo-vendor/{wasmtime-wasi-24.0.0 → wasmtime-wasi-25.0.0}/src/ip_name_lookup.rs +0 -0
  1840. /data/ext/cargo-vendor/{wasmtime-wasi-24.0.0 → wasmtime-wasi-25.0.0}/src/lib.rs +0 -0
  1841. /data/ext/cargo-vendor/{wasmtime-wasi-24.0.0 → wasmtime-wasi-25.0.0}/src/network.rs +0 -0
  1842. /data/ext/cargo-vendor/{wasmtime-wasi-24.0.0 → wasmtime-wasi-25.0.0}/src/poll.rs +0 -0
  1843. /data/ext/cargo-vendor/{wasmtime-wasi-24.0.0 → wasmtime-wasi-25.0.0}/src/preview0.rs +0 -0
  1844. /data/ext/cargo-vendor/{wasmtime-wasi-24.0.0 → wasmtime-wasi-25.0.0}/src/random.rs +0 -0
  1845. /data/ext/cargo-vendor/{wasmtime-wasi-24.0.0 → wasmtime-wasi-25.0.0}/src/stdio/worker_thread_stdin.rs +0 -0
  1846. /data/ext/cargo-vendor/{wasmtime-wasi-24.0.0 → wasmtime-wasi-25.0.0}/src/udp.rs +0 -0
  1847. /data/ext/cargo-vendor/{wasmtime-wasi-24.0.0 → wasmtime-wasi-25.0.0}/tests/all/api.rs +0 -0
  1848. /data/ext/cargo-vendor/{wasmtime-wasi-24.0.0 → wasmtime-wasi-25.0.0}/tests/all/async_.rs +0 -0
  1849. /data/ext/cargo-vendor/{wasmtime-wasi-24.0.0 → wasmtime-wasi-25.0.0}/tests/all/preview1.rs +0 -0
  1850. /data/ext/cargo-vendor/{wasmtime-wasi-24.0.0 → wasmtime-wasi-25.0.0}/tests/all/sync.rs +0 -0
  1851. /data/ext/cargo-vendor/{wasmtime-wasi-24.0.0 → wasmtime-wasi-25.0.0}/witx/preview0/typenames.witx +0 -0
  1852. /data/ext/cargo-vendor/{wasmtime-wasi-24.0.0 → wasmtime-wasi-25.0.0}/witx/preview0/wasi_unstable.witx +0 -0
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  1855. /data/ext/cargo-vendor/{wasmtime-winch-24.0.0 → wasmtime-winch-25.0.0}/LICENSE +0 -0
  1856. /data/ext/cargo-vendor/{wasmtime-winch-24.0.0 → wasmtime-winch-25.0.0}/src/builder.rs +0 -0
  1857. /data/ext/cargo-vendor/{wasmtime-winch-24.0.0 → wasmtime-winch-25.0.0}/src/compiler.rs +0 -0
  1858. /data/ext/cargo-vendor/{wasmtime-winch-24.0.0 → wasmtime-winch-25.0.0}/src/lib.rs +0 -0
  1859. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-24.0.0 → wasmtime-wit-bindgen-25.0.0}/src/source.rs +0 -0
  1860. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-24.0.0 → wasmtime-wit-bindgen-25.0.0}/src/types.rs +0 -0
  1861. /data/ext/cargo-vendor/{wast-216.0.0 → wast-217.0.0}/README.md +0 -0
  1862. /data/ext/cargo-vendor/{wast-216.0.0 → wast-217.0.0}/src/component/alias.rs +0 -0
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  1995. /data/ext/cargo-vendor/{wast-216.0.0 → wast-217.0.0}/tests/parse-fail/string7.wat.err +0 -0
  1996. /data/ext/cargo-vendor/{wast-216.0.0 → wast-217.0.0}/tests/parse-fail/string8.wat +0 -0
  1997. /data/ext/cargo-vendor/{wast-216.0.0 → wast-217.0.0}/tests/parse-fail/string8.wat.err +0 -0
  1998. /data/ext/cargo-vendor/{wast-216.0.0 → wast-217.0.0}/tests/parse-fail/string9.wat +0 -0
  1999. /data/ext/cargo-vendor/{wast-216.0.0 → wast-217.0.0}/tests/parse-fail/string9.wat.err +0 -0
  2000. /data/ext/cargo-vendor/{wast-216.0.0 → wast-217.0.0}/tests/parse-fail/unbalanced.wat +0 -0
  2001. /data/ext/cargo-vendor/{wast-216.0.0 → wast-217.0.0}/tests/parse-fail/unbalanced.wat.err +0 -0
  2002. /data/ext/cargo-vendor/{wast-216.0.0 → wast-217.0.0}/tests/parse-fail.rs +0 -0
  2003. /data/ext/cargo-vendor/{wast-216.0.0 → wast-217.0.0}/tests/recursive.rs +0 -0
  2004. /data/ext/cargo-vendor/{wat-1.216.0 → wat-1.217.0}/README.md +0 -0
  2005. /data/ext/cargo-vendor/{wat-1.216.0 → wat-1.217.0}/src/lib.rs +0 -0
  2006. /data/ext/cargo-vendor/{wiggle-24.0.0 → wiggle-25.0.0}/LICENSE +0 -0
  2007. /data/ext/cargo-vendor/{wiggle-24.0.0 → wiggle-25.0.0}/README.md +0 -0
  2008. /data/ext/cargo-vendor/{wiggle-24.0.0 → wiggle-25.0.0}/src/error.rs +0 -0
  2009. /data/ext/cargo-vendor/{wiggle-24.0.0 → wiggle-25.0.0}/src/guest_type.rs +0 -0
  2010. /data/ext/cargo-vendor/{wiggle-24.0.0 → wiggle-25.0.0}/src/region.rs +0 -0
  2011. /data/ext/cargo-vendor/{wiggle-generate-24.0.0 → wiggle-generate-25.0.0}/LICENSE +0 -0
  2012. /data/ext/cargo-vendor/{wiggle-generate-24.0.0 → wiggle-generate-25.0.0}/README.md +0 -0
  2013. /data/ext/cargo-vendor/{wiggle-generate-24.0.0 → wiggle-generate-25.0.0}/src/codegen_settings.rs +0 -0
  2014. /data/ext/cargo-vendor/{wiggle-generate-24.0.0 → wiggle-generate-25.0.0}/src/config.rs +0 -0
  2015. /data/ext/cargo-vendor/{wiggle-generate-24.0.0 → wiggle-generate-25.0.0}/src/lifetimes.rs +0 -0
  2016. /data/ext/cargo-vendor/{wiggle-generate-24.0.0 → wiggle-generate-25.0.0}/src/module_trait.rs +0 -0
  2017. /data/ext/cargo-vendor/{wiggle-generate-24.0.0 → wiggle-generate-25.0.0}/src/types/error.rs +0 -0
  2018. /data/ext/cargo-vendor/{wiggle-generate-24.0.0 → wiggle-generate-25.0.0}/src/types/flags.rs +0 -0
  2019. /data/ext/cargo-vendor/{wiggle-generate-24.0.0 → wiggle-generate-25.0.0}/src/types/handle.rs +0 -0
  2020. /data/ext/cargo-vendor/{wiggle-generate-24.0.0 → wiggle-generate-25.0.0}/src/types/mod.rs +0 -0
  2021. /data/ext/cargo-vendor/{wiggle-generate-24.0.0 → wiggle-generate-25.0.0}/src/types/record.rs +0 -0
  2022. /data/ext/cargo-vendor/{wiggle-generate-24.0.0 → wiggle-generate-25.0.0}/src/types/variant.rs +0 -0
  2023. /data/ext/cargo-vendor/{wiggle-macro-24.0.0 → wiggle-macro-25.0.0}/LICENSE +0 -0
  2024. /data/ext/cargo-vendor/{wiggle-macro-24.0.0 → wiggle-macro-25.0.0}/build.rs +0 -0
  2025. /data/ext/cargo-vendor/{wiggle-macro-24.0.0 → wiggle-macro-25.0.0}/src/lib.rs +0 -0
  2026. /data/ext/cargo-vendor/{winch-codegen-0.22.0 → winch-codegen-0.23.0}/LICENSE +0 -0
  2027. /data/ext/cargo-vendor/{winch-codegen-0.22.0 → winch-codegen-0.23.0}/build.rs +0 -0
  2028. /data/ext/cargo-vendor/{winch-codegen-0.22.0 → winch-codegen-0.23.0}/src/codegen/builtin.rs +0 -0
  2029. /data/ext/cargo-vendor/{winch-codegen-0.22.0 → winch-codegen-0.23.0}/src/codegen/call.rs +0 -0
  2030. /data/ext/cargo-vendor/{winch-codegen-0.22.0 → winch-codegen-0.23.0}/src/codegen/control.rs +0 -0
  2031. /data/ext/cargo-vendor/{winch-codegen-0.22.0 → winch-codegen-0.23.0}/src/codegen/env.rs +0 -0
  2032. /data/ext/cargo-vendor/{winch-codegen-0.22.0 → winch-codegen-0.23.0}/src/frame/mod.rs +0 -0
  2033. /data/ext/cargo-vendor/{winch-codegen-0.22.0 → winch-codegen-0.23.0}/src/isa/aarch64/mod.rs +0 -0
  2034. /data/ext/cargo-vendor/{winch-codegen-0.22.0 → winch-codegen-0.23.0}/src/isa/aarch64/regs.rs +0 -0
  2035. /data/ext/cargo-vendor/{winch-codegen-0.22.0 → winch-codegen-0.23.0}/src/isa/reg.rs +0 -0
  2036. /data/ext/cargo-vendor/{winch-codegen-0.22.0 → winch-codegen-0.23.0}/src/isa/x64/address.rs +0 -0
  2037. /data/ext/cargo-vendor/{winch-codegen-0.22.0 → winch-codegen-0.23.0}/src/isa/x64/mod.rs +0 -0
  2038. /data/ext/cargo-vendor/{winch-codegen-0.22.0 → winch-codegen-0.23.0}/src/isa/x64/regs.rs +0 -0
  2039. /data/ext/cargo-vendor/{winch-codegen-0.22.0 → winch-codegen-0.23.0}/src/lib.rs +0 -0
  2040. /data/ext/cargo-vendor/{winch-codegen-0.22.0 → winch-codegen-0.23.0}/src/regset.rs +0 -0
  2041. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/README.md +0 -0
  2042. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/src/abi.rs +0 -0
  2043. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/src/ast/lex.rs +0 -0
  2044. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/src/ast/toposort.rs +0 -0
  2045. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/src/live.rs +0 -0
  2046. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/src/metadata.rs +0 -0
  2047. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/src/resolve.rs +0 -0
  2048. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/src/serde_.rs +0 -0
  2049. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/comments.wit +0 -0
  2050. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/comments.wit.json +0 -0
  2051. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/complex-include/deps/bar/root.wit +0 -0
  2052. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/complex-include/deps/baz/root.wit +0 -0
  2053. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/complex-include/root.wit +0 -0
  2054. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/complex-include.wit.json +0 -0
  2055. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/cross-package-resource/deps/foo/foo.wit +0 -0
  2056. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/cross-package-resource/foo.wit +0 -0
  2057. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/cross-package-resource.wit.json +0 -0
  2058. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/diamond1/deps/dep1/types.wit +0 -0
  2059. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/diamond1/deps/dep2/types.wit +0 -0
  2060. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/diamond1/join.wit +0 -0
  2061. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/diamond1.wit.json +0 -0
  2062. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/disambiguate-diamond/shared1.wit +0 -0
  2063. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/disambiguate-diamond/shared2.wit +0 -0
  2064. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/disambiguate-diamond/world.wit +0 -0
  2065. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/disambiguate-diamond.wit.json +0 -0
  2066. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/empty.wit +0 -0
  2067. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/empty.wit.json +0 -0
  2068. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/feature-gates.wit +0 -0
  2069. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/feature-gates.wit.json +0 -0
  2070. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/foreign-deps/deps/another-pkg/other-doc.wit +0 -0
  2071. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/foreign-deps/deps/corp/saas.wit +0 -0
  2072. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/foreign-deps/deps/different-pkg/the-doc.wit +0 -0
  2073. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/foreign-deps/deps/foreign-pkg/the-doc.wit +0 -0
  2074. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/foreign-deps/deps/some-pkg/some-doc.wit +0 -0
  2075. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/foreign-deps/deps/wasi/clocks.wit +0 -0
  2076. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/foreign-deps/deps/wasi/filesystem.wit +0 -0
  2077. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/foreign-deps/root.wit +0 -0
  2078. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/foreign-deps-union/deps/another-pkg/other-doc.wit +0 -0
  2079. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/foreign-deps-union/deps/corp/saas.wit +0 -0
  2080. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/foreign-deps-union/deps/different-pkg/the-doc.wit +0 -0
  2081. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/foreign-deps-union/deps/foreign-pkg/the-doc.wit +0 -0
  2082. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/foreign-deps-union/deps/some-pkg/some-doc.wit +0 -0
  2083. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/foreign-deps-union/deps/wasi/clocks.wit +0 -0
  2084. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/foreign-deps-union/deps/wasi/filesystem.wit +0 -0
  2085. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/foreign-deps-union/deps/wasi/wasi.wit +0 -0
  2086. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/foreign-deps-union/root.wit +0 -0
  2087. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/foreign-deps-union.wit.json +0 -0
  2088. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/foreign-deps.wit.json +0 -0
  2089. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/functions.wit +0 -0
  2090. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/functions.wit.json +0 -0
  2091. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/ignore-files-deps/deps/bar/types.wit +0 -0
  2092. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/ignore-files-deps/deps/ignore-me.txt +0 -0
  2093. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/ignore-files-deps/world.wit +0 -0
  2094. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/ignore-files-deps.wit.json +0 -0
  2095. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/import-export-overlap1.wit +0 -0
  2096. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/import-export-overlap1.wit.json +0 -0
  2097. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/import-export-overlap2.wit +0 -0
  2098. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/import-export-overlap2.wit.json +0 -0
  2099. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/include-reps.wit +0 -0
  2100. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/include-reps.wit.json +0 -0
  2101. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/kebab-name-include-with.wit +0 -0
  2102. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/kebab-name-include-with.wit.json +0 -0
  2103. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/kinds-of-deps/a.wit +0 -0
  2104. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/kinds-of-deps/deps/b/root.wit +0 -0
  2105. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/kinds-of-deps/deps/c.wit +0 -0
  2106. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/kinds-of-deps/deps/d.wat +0 -0
  2107. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/kinds-of-deps/deps/e.wasm +0 -0
  2108. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/kinds-of-deps.wit.json +0 -0
  2109. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/many-names/a.wit +0 -0
  2110. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/many-names/b.wit +0 -0
  2111. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/many-names.wit.json +0 -0
  2112. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/multi-file/bar.wit +0 -0
  2113. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/multi-file/cycle-a.wit +0 -0
  2114. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/multi-file/cycle-b.wit +0 -0
  2115. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/multi-file/foo.wit +0 -0
  2116. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/multi-file-multi-package/a.wit +0 -0
  2117. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/multi-file-multi-package/b.wit +0 -0
  2118. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/multi-file-multi-package.wit.json +0 -0
  2119. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/multi-file.wit.json +0 -0
  2120. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/multi-package-deps/deps/dep.wit +0 -0
  2121. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/multi-package-deps/root.wit +0 -0
  2122. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/multi-package-deps.wit.json +0 -0
  2123. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/multi-package-shared-deps/deps/dep1/types.wit +0 -0
  2124. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/multi-package-shared-deps/deps/dep2/types.wit +0 -0
  2125. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/multi-package-shared-deps/packages.wit +0 -0
  2126. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/multi-package-shared-deps.wit.json +0 -0
  2127. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/multi-package-transitive-deps/deps/dep1/types.wit +0 -0
  2128. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/multi-package-transitive-deps/deps/dep2/types.wit +0 -0
  2129. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/multi-package-transitive-deps/packages.wit +0 -0
  2130. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/multi-package-transitive-deps.wit.json +0 -0
  2131. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/name-both-resource-and-type/deps/dep/foo.wit +0 -0
  2132. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/name-both-resource-and-type/foo.wit +0 -0
  2133. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/name-both-resource-and-type.wit.json +0 -0
  2134. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/package-syntax1.wit +0 -0
  2135. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/package-syntax1.wit.json +0 -0
  2136. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/package-syntax3.wit +0 -0
  2137. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/package-syntax3.wit.json +0 -0
  2138. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/package-syntax4.wit +0 -0
  2139. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/package-syntax4.wit.json +0 -0
  2140. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/packages-multiple-nested.wit +0 -0
  2141. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/packages-multiple-nested.wit.json +0 -0
  2142. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/packages-nested-colliding-decl-names.wit +0 -0
  2143. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/packages-nested-colliding-decl-names.wit.json +0 -0
  2144. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/packages-nested-internal-references.wit +0 -0
  2145. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/packages-nested-internal-references.wit.json +0 -0
  2146. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/packages-nested-with-semver.wit +0 -0
  2147. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/packages-nested-with-semver.wit.json +0 -0
  2148. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/packages-single-nested.wit +0 -0
  2149. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/packages-single-nested.wit.json +0 -0
  2150. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/alias-no-type.wit +0 -0
  2151. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/alias-no-type.wit.result +0 -0
  2152. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/async.wit.result +0 -0
  2153. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/async1.wit.result +0 -0
  2154. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-deprecated1.wit +0 -0
  2155. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-deprecated1.wit.result +0 -0
  2156. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-deprecated2.wit +0 -0
  2157. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-deprecated2.wit.result +0 -0
  2158. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-deprecated3.wit +0 -0
  2159. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-deprecated3.wit.result +0 -0
  2160. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-deprecated4.wit +0 -0
  2161. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-deprecated4.wit.result +0 -0
  2162. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-function.wit +0 -0
  2163. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-function.wit.result +0 -0
  2164. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-function2.wit +0 -0
  2165. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-function2.wit.result +0 -0
  2166. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-gate1.wit +0 -0
  2167. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-gate1.wit.result +0 -0
  2168. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-gate2.wit +0 -0
  2169. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-gate2.wit.result +0 -0
  2170. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-gate3.wit +0 -0
  2171. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-gate4.wit +0 -0
  2172. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-gate5.wit +0 -0
  2173. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-include1.wit +0 -0
  2174. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-include1.wit.result +0 -0
  2175. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-include2.wit +0 -0
  2176. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-include2.wit.result +0 -0
  2177. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-include3.wit +0 -0
  2178. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-include3.wit.result +0 -0
  2179. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-list.wit +0 -0
  2180. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-list.wit.result +0 -0
  2181. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-pkg1/root.wit +0 -0
  2182. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-pkg2/deps/bar/empty.wit +0 -0
  2183. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-pkg2/root.wit +0 -0
  2184. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-pkg3/deps/bar/baz.wit +0 -0
  2185. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-pkg3/root.wit +0 -0
  2186. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-pkg4/deps/bar/baz.wit +0 -0
  2187. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-pkg4/root.wit +0 -0
  2188. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-pkg5/deps/bar/baz.wit +0 -0
  2189. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-pkg5/root.wit +0 -0
  2190. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-pkg6/deps/bar/baz.wit +0 -0
  2191. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-pkg6/root.wit +0 -0
  2192. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-resource1.wit +0 -0
  2193. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-resource1.wit.result +0 -0
  2194. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-resource10.wit +0 -0
  2195. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-resource10.wit.result +0 -0
  2196. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-resource11.wit +0 -0
  2197. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-resource11.wit.result +0 -0
  2198. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-resource12.wit +0 -0
  2199. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-resource12.wit.result +0 -0
  2200. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-resource13.wit +0 -0
  2201. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-resource13.wit.result +0 -0
  2202. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-resource14.wit +0 -0
  2203. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-resource14.wit.result +0 -0
  2204. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-resource15/deps/foo/foo.wit +0 -0
  2205. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-resource15/foo.wit +0 -0
  2206. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-resource2.wit +0 -0
  2207. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-resource2.wit.result +0 -0
  2208. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-resource3.wit +0 -0
  2209. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-resource3.wit.result +0 -0
  2210. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-resource4.wit +0 -0
  2211. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-resource4.wit.result +0 -0
  2212. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-resource5.wit +0 -0
  2213. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-resource5.wit.result +0 -0
  2214. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-resource6.wit +0 -0
  2215. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-resource6.wit.result +0 -0
  2216. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-resource7.wit +0 -0
  2217. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-resource7.wit.result +0 -0
  2218. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-resource8.wit +0 -0
  2219. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-resource8.wit.result +0 -0
  2220. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-resource9.wit +0 -0
  2221. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-resource9.wit.result +0 -0
  2222. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-since1.wit +0 -0
  2223. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-since1.wit.result +0 -0
  2224. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-since3.wit +0 -0
  2225. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-since3.wit.result +0 -0
  2226. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-world-type1.wit +0 -0
  2227. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/bad-world-type1.wit.result +0 -0
  2228. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/conflicting-package/a.wit +0 -0
  2229. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/conflicting-package/b.wit +0 -0
  2230. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/cycle.wit +0 -0
  2231. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/cycle.wit.result +0 -0
  2232. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/cycle2.wit +0 -0
  2233. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/cycle2.wit.result +0 -0
  2234. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/cycle3.wit +0 -0
  2235. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/cycle3.wit.result +0 -0
  2236. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/cycle4.wit +0 -0
  2237. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/cycle4.wit.result +0 -0
  2238. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/cycle5.wit +0 -0
  2239. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/cycle5.wit.result +0 -0
  2240. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/dangling-type.wit +0 -0
  2241. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/dangling-type.wit.result +0 -0
  2242. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/duplicate-function-params.wit +0 -0
  2243. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/duplicate-function-params.wit.result +0 -0
  2244. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/duplicate-functions.wit +0 -0
  2245. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/duplicate-functions.wit.result +0 -0
  2246. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/duplicate-interface.wit +0 -0
  2247. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/duplicate-interface.wit.result +0 -0
  2248. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/duplicate-interface2/foo.wit +0 -0
  2249. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/duplicate-interface2/foo2.wit +0 -0
  2250. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/duplicate-type.wit +0 -0
  2251. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/duplicate-type.wit.result +0 -0
  2252. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/empty-enum.wit +0 -0
  2253. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/empty-enum.wit.result +0 -0
  2254. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/empty-variant1.wit +0 -0
  2255. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/empty-variant1.wit.result +0 -0
  2256. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/export-twice.wit +0 -0
  2257. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/export-twice.wit.result +0 -0
  2258. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/import-and-export1.wit +0 -0
  2259. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/import-and-export1.wit.result +0 -0
  2260. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/import-and-export2.wit +0 -0
  2261. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/import-and-export2.wit.result +0 -0
  2262. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/import-and-export3.wit +0 -0
  2263. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/import-and-export3.wit.result +0 -0
  2264. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/import-and-export4.wit +0 -0
  2265. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/import-and-export4.wit.result +0 -0
  2266. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/import-and-export5.wit +0 -0
  2267. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/import-and-export5.wit.result +0 -0
  2268. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/import-twice.wit +0 -0
  2269. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/import-twice.wit.result +0 -0
  2270. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/include-cycle.wit +0 -0
  2271. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/include-cycle.wit.result +0 -0
  2272. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/include-foreign/deps/bar/empty.wit +0 -0
  2273. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/include-foreign/root.wit +0 -0
  2274. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/include-with-id.wit +0 -0
  2275. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/include-with-id.wit.result +0 -0
  2276. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/include-with-on-id.wit +0 -0
  2277. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/include-with-on-id.wit.result +0 -0
  2278. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/invalid-toplevel.wit +0 -0
  2279. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/invalid-toplevel.wit.result +0 -0
  2280. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/invalid-type-reference.wit +0 -0
  2281. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/invalid-type-reference.wit.result +0 -0
  2282. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/invalid-type-reference2.wit +0 -0
  2283. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/invalid-type-reference2.wit.result +0 -0
  2284. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/kebab-name-include-not-found.wit +0 -0
  2285. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/kebab-name-include-not-found.wit.result +0 -0
  2286. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/kebab-name-include.wit +0 -0
  2287. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/kebab-name-include.wit.result +0 -0
  2288. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/keyword.wit +0 -0
  2289. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/keyword.wit.result +0 -0
  2290. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/missing-main-declaration-initial-main.wit +0 -0
  2291. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/missing-main-declaration-initial-main.wit.result +0 -0
  2292. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/missing-main-declaration-initial-nested.wit +0 -0
  2293. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/missing-main-declaration-initial-nested.wit.result +0 -0
  2294. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/missing-package.wit +0 -0
  2295. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/missing-package.wit.result +0 -0
  2296. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/multi-file-missing-delimiter/observe.wit +0 -0
  2297. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/multi-file-missing-delimiter/world.wit +0 -0
  2298. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/multi-package-deps-share-nest/deps/dep1/types.wit +0 -0
  2299. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/multi-package-deps-share-nest/deps/dep2/types.wit +0 -0
  2300. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/multi-package-deps-share-nest/root.wit +0 -0
  2301. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/multiple-package-docs/a.wit +0 -0
  2302. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/multiple-package-docs/b.wit +0 -0
  2303. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/multiple-package-inline-cycle.wit +0 -0
  2304. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/multiple-package-inline-cycle.wit.result +0 -0
  2305. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/multiple-packages-no-scope-blocks.wit +0 -0
  2306. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/multiple-packages-no-scope-blocks.wit.result +0 -0
  2307. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/nested-packages-colliding-names.wit +0 -0
  2308. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/nested-packages-colliding-names.wit.result +0 -0
  2309. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/nested-packages-with-error.wit +0 -0
  2310. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/nested-packages-with-error.wit.result +0 -0
  2311. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/no-access-to-sibling-use/bar.wit +0 -0
  2312. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/no-access-to-sibling-use/foo.wit +0 -0
  2313. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/non-existance-world-include/deps/bar/baz.wit +0 -0
  2314. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/non-existance-world-include/root.wit +0 -0
  2315. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/pkg-cycle/deps/a1/root.wit +0 -0
  2316. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/pkg-cycle/root.wit +0 -0
  2317. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/pkg-cycle2/deps/a1/root.wit +0 -0
  2318. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/pkg-cycle2/deps/a2/root.wit +0 -0
  2319. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/pkg-cycle2/root.wit +0 -0
  2320. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/resources-multiple-returns-borrow.wit +0 -0
  2321. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/resources-return-borrow.wit +0 -0
  2322. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/return-borrow1.wit +0 -0
  2323. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/return-borrow2.wit +0 -0
  2324. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/return-borrow3.wit +0 -0
  2325. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/return-borrow3.wit.result +0 -0
  2326. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/return-borrow4.wit +0 -0
  2327. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/return-borrow4.wit.result +0 -0
  2328. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/return-borrow5.wit +0 -0
  2329. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/return-borrow5.wit.result +0 -0
  2330. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/return-borrow6.wit +0 -0
  2331. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/return-borrow7.wit +0 -0
  2332. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/return-borrow8/deps/baz.wit +0 -0
  2333. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/return-borrow8/foo.wit +0 -0
  2334. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/type-and-resource-same-name/deps/dep/foo.wit +0 -0
  2335. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/type-and-resource-same-name/foo.wit +0 -0
  2336. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/undefined-typed.wit +0 -0
  2337. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/undefined-typed.wit.result +0 -0
  2338. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/unknown-interface.wit +0 -0
  2339. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/unknown-interface.wit.result +0 -0
  2340. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/unresolved-interface1.wit +0 -0
  2341. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/unresolved-interface1.wit.result +0 -0
  2342. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/unresolved-interface2.wit +0 -0
  2343. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/unresolved-interface2.wit.result +0 -0
  2344. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/unresolved-interface3.wit +0 -0
  2345. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/unresolved-interface3.wit.result +0 -0
  2346. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/unresolved-interface4.wit +0 -0
  2347. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/unresolved-interface4.wit.result +0 -0
  2348. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/unresolved-use1.wit +0 -0
  2349. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/unresolved-use1.wit.result +0 -0
  2350. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/unresolved-use10/bar.wit +0 -0
  2351. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/unresolved-use10/foo.wit +0 -0
  2352. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/unresolved-use2.wit +0 -0
  2353. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/unresolved-use2.wit.result +0 -0
  2354. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/unresolved-use3.wit +0 -0
  2355. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/unresolved-use3.wit.result +0 -0
  2356. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/unresolved-use7.wit +0 -0
  2357. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/unresolved-use7.wit.result +0 -0
  2358. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/unresolved-use8.wit +0 -0
  2359. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/unresolved-use8.wit.result +0 -0
  2360. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/unresolved-use9.wit +0 -0
  2361. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/unresolved-use9.wit.result +0 -0
  2362. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/unterminated-string.wit.result +0 -0
  2363. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/use-and-include-world/deps/bar/baz.wit +0 -0
  2364. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/use-and-include-world/root.wit +0 -0
  2365. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/use-conflict.wit +0 -0
  2366. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/use-conflict.wit.result +0 -0
  2367. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/use-conflict2.wit +0 -0
  2368. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/use-conflict2.wit.result +0 -0
  2369. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/use-conflict3.wit +0 -0
  2370. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/use-conflict3.wit.result +0 -0
  2371. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/use-cycle1.wit +0 -0
  2372. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/use-cycle1.wit.result +0 -0
  2373. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/use-cycle4.wit +0 -0
  2374. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/use-cycle4.wit.result +0 -0
  2375. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/use-shadow1.wit +0 -0
  2376. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/use-shadow1.wit.result +0 -0
  2377. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/use-world/deps/bar/baz.wit +0 -0
  2378. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/use-world/root.wit +0 -0
  2379. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/very-nested-packages.wit +0 -0
  2380. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/world-interface-clash.wit +0 -0
  2381. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/world-interface-clash.wit.result +0 -0
  2382. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/world-same-fields2.wit +0 -0
  2383. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/world-same-fields2.wit.result +0 -0
  2384. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/world-same-fields3.wit +0 -0
  2385. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/world-same-fields3.wit.result +0 -0
  2386. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/world-top-level-func.wit +0 -0
  2387. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/world-top-level-func.wit.result +0 -0
  2388. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/world-top-level-func2.wit +0 -0
  2389. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/parse-fail/world-top-level-func2.wit.result +0 -0
  2390. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/random.wit +0 -0
  2391. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/random.wit.json +0 -0
  2392. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/resources-empty.wit +0 -0
  2393. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/resources-empty.wit.json +0 -0
  2394. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/resources-multiple-returns-own.wit +0 -0
  2395. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/resources-multiple-returns-own.wit.json +0 -0
  2396. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/resources-multiple.wit +0 -0
  2397. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/resources-multiple.wit.json +0 -0
  2398. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/resources-return-own.wit +0 -0
  2399. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/resources-return-own.wit.json +0 -0
  2400. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/resources.wit +0 -0
  2401. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/resources.wit.json +0 -0
  2402. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/resources1.wit +0 -0
  2403. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/resources1.wit.json +0 -0
  2404. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/same-name-import-export.wit +0 -0
  2405. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/same-name-import-export.wit.json +0 -0
  2406. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/shared-types.wit +0 -0
  2407. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/shared-types.wit.json +0 -0
  2408. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/simple-wasm-text.wat +0 -0
  2409. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/simple-wasm-text.wit.json +0 -0
  2410. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/stress-export-elaborate.wit +0 -0
  2411. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/stress-export-elaborate.wit.json +0 -0
  2412. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/type-then-eof.wit +0 -0
  2413. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/type-then-eof.wit.json +0 -0
  2414. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/types.wit +0 -0
  2415. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/types.wit.json +0 -0
  2416. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/union-fuzz-1.wit +0 -0
  2417. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/union-fuzz-1.wit.json +0 -0
  2418. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/union-fuzz-2.wit +0 -0
  2419. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/union-fuzz-2.wit.json +0 -0
  2420. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/use-chain.wit +0 -0
  2421. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/use-chain.wit.json +0 -0
  2422. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/use.wit +0 -0
  2423. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/use.wit.json +0 -0
  2424. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/version-syntax.wit +0 -0
  2425. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/version-syntax.wit.json +0 -0
  2426. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/versions/deps/a1/foo.wit +0 -0
  2427. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/versions/deps/a2/foo.wit +0 -0
  2428. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/versions/foo.wit +0 -0
  2429. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/versions.wit.json +0 -0
  2430. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/wasi.wit +0 -0
  2431. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/wasi.wit.json +0 -0
  2432. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/world-diamond.wit +0 -0
  2433. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/world-diamond.wit.json +0 -0
  2434. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/world-iface-no-collide.wit +0 -0
  2435. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/world-iface-no-collide.wit.json +0 -0
  2436. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/world-implicit-import1.wit +0 -0
  2437. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/world-implicit-import1.wit.json +0 -0
  2438. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/world-implicit-import2.wit +0 -0
  2439. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/world-implicit-import2.wit.json +0 -0
  2440. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/world-implicit-import3.wit +0 -0
  2441. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/world-implicit-import3.wit.json +0 -0
  2442. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/world-same-fields4.wit +0 -0
  2443. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/world-same-fields4.wit.json +0 -0
  2444. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/world-top-level-funcs.wit +0 -0
  2445. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/world-top-level-funcs.wit.json +0 -0
  2446. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/world-top-level-resources.wit +0 -0
  2447. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/world-top-level-resources.wit.json +0 -0
  2448. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/worlds-union-dedup.wit +0 -0
  2449. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/worlds-union-dedup.wit.json +0 -0
  2450. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/worlds-with-types.wit +0 -0
  2451. /data/ext/cargo-vendor/{wit-parser-0.215.0 → wit-parser-0.217.0}/tests/ui/worlds-with-types.wit.json +0 -0
@@ -0,0 +1,3051 @@
1
+ //! This module defines aarch64-specific machine instruction types.
2
+
3
+ use crate::binemit::{Addend, CodeOffset, Reloc};
4
+ use crate::ir::types::{F128, F16, F32, F64, I128, I16, I32, I64, I8, I8X16};
5
+ use crate::ir::{types, MemFlags, Type};
6
+ use crate::isa::{CallConv, FunctionAlignment};
7
+ use crate::machinst::*;
8
+ use crate::{settings, CodegenError, CodegenResult};
9
+
10
+ use crate::machinst::{PrettyPrint, Reg, RegClass, Writable};
11
+
12
+ use alloc::vec::Vec;
13
+ use smallvec::{smallvec, SmallVec};
14
+ use std::fmt::Write;
15
+ use std::string::{String, ToString};
16
+
17
+ pub(crate) mod regs;
18
+ pub(crate) use self::regs::*;
19
+ pub mod imms;
20
+ pub use self::imms::*;
21
+ pub mod args;
22
+ pub use self::args::*;
23
+ pub mod emit;
24
+ pub(crate) use self::emit::*;
25
+ use crate::isa::aarch64::abi::AArch64MachineDeps;
26
+
27
+ pub(crate) mod unwind;
28
+
29
+ #[cfg(test)]
30
+ mod emit_tests;
31
+
32
+ //=============================================================================
33
+ // Instructions (top level): definition
34
+
35
+ pub use crate::isa::aarch64::lower::isle::generated_code::{
36
+ ALUOp, ALUOp3, AMode, APIKey, AtomicRMWLoopOp, AtomicRMWOp, BitOp, BranchTargetType, FPUOp1,
37
+ FPUOp2, FPUOp3, FpuRoundMode, FpuToIntOp, IntToFpuOp, MInst as Inst, MoveWideOp, VecALUModOp,
38
+ VecALUOp, VecExtendOp, VecLanesOp, VecMisc2, VecPairOp, VecRRLongOp, VecRRNarrowOp,
39
+ VecRRPairLongOp, VecRRRLongModOp, VecRRRLongOp, VecShiftImmModOp, VecShiftImmOp,
40
+ };
41
+
42
+ /// A floating-point unit (FPU) operation with two args, a register and an immediate.
43
+ #[derive(Copy, Clone, Debug)]
44
+ pub enum FPUOpRI {
45
+ /// Unsigned right shift. Rd = Rn << #imm
46
+ UShr32(FPURightShiftImm),
47
+ /// Unsigned right shift. Rd = Rn << #imm
48
+ UShr64(FPURightShiftImm),
49
+ }
50
+
51
+ /// A floating-point unit (FPU) operation with two args, a register and
52
+ /// an immediate that modifies its dest (so takes that input value as a
53
+ /// separate virtual register).
54
+ #[derive(Copy, Clone, Debug)]
55
+ pub enum FPUOpRIMod {
56
+ /// Shift left and insert. Rd |= Rn << #imm
57
+ Sli32(FPULeftShiftImm),
58
+ /// Shift left and insert. Rd |= Rn << #imm
59
+ Sli64(FPULeftShiftImm),
60
+ }
61
+
62
+ impl BitOp {
63
+ /// Get the assembly mnemonic for this opcode.
64
+ pub fn op_str(&self) -> &'static str {
65
+ match self {
66
+ BitOp::RBit => "rbit",
67
+ BitOp::Clz => "clz",
68
+ BitOp::Cls => "cls",
69
+ BitOp::Rev16 => "rev16",
70
+ BitOp::Rev32 => "rev32",
71
+ BitOp::Rev64 => "rev64",
72
+ }
73
+ }
74
+ }
75
+
76
+ /// Additional information for `return_call[_ind]` instructions, left out of
77
+ /// line to lower the size of the `Inst` enum.
78
+ #[derive(Clone, Debug)]
79
+ pub struct ReturnCallInfo<T> {
80
+ /// Where this call is going to
81
+ pub dest: T,
82
+ /// Arguments to the call instruction.
83
+ pub uses: CallArgList,
84
+ /// The size of the new stack frame's stack arguments. This is necessary
85
+ /// for copying the frame over our current frame. It must already be
86
+ /// allocated on the stack.
87
+ pub new_stack_arg_size: u32,
88
+ /// API key to use to restore the return address, if any.
89
+ pub key: Option<APIKey>,
90
+ }
91
+
92
+ fn count_zero_half_words(mut value: u64, num_half_words: u8) -> usize {
93
+ let mut count = 0;
94
+ for _ in 0..num_half_words {
95
+ if value & 0xffff == 0 {
96
+ count += 1;
97
+ }
98
+ value >>= 16;
99
+ }
100
+
101
+ count
102
+ }
103
+
104
+ #[test]
105
+ fn inst_size_test() {
106
+ // This test will help with unintentionally growing the size
107
+ // of the Inst enum.
108
+ assert_eq!(32, std::mem::size_of::<Inst>());
109
+ }
110
+
111
+ impl Inst {
112
+ /// Create an instruction that loads a constant, using one of several options (MOVZ, MOVN,
113
+ /// logical immediate, or constant pool).
114
+ pub fn load_constant<F: FnMut(Type) -> Writable<Reg>>(
115
+ rd: Writable<Reg>,
116
+ value: u64,
117
+ alloc_tmp: &mut F,
118
+ ) -> SmallVec<[Inst; 4]> {
119
+ // NB: this is duplicated in `lower/isle.rs` and `inst.isle` right now,
120
+ // if modifications are made here before this is deleted after moving to
121
+ // ISLE then those locations should be updated as well.
122
+
123
+ if let Some(imm) = MoveWideConst::maybe_from_u64(value) {
124
+ // 16-bit immediate (shifted by 0, 16, 32 or 48 bits) in MOVZ
125
+ smallvec![Inst::MovWide {
126
+ op: MoveWideOp::MovZ,
127
+ rd,
128
+ imm,
129
+ size: OperandSize::Size64
130
+ }]
131
+ } else if let Some(imm) = MoveWideConst::maybe_from_u64(!value) {
132
+ // 16-bit immediate (shifted by 0, 16, 32 or 48 bits) in MOVN
133
+ smallvec![Inst::MovWide {
134
+ op: MoveWideOp::MovN,
135
+ rd,
136
+ imm,
137
+ size: OperandSize::Size64
138
+ }]
139
+ } else if let Some(imml) = ImmLogic::maybe_from_u64(value, I64) {
140
+ // Weird logical-instruction immediate in ORI using zero register
141
+ smallvec![Inst::AluRRImmLogic {
142
+ alu_op: ALUOp::Orr,
143
+ size: OperandSize::Size64,
144
+ rd,
145
+ rn: zero_reg(),
146
+ imml,
147
+ }]
148
+ } else {
149
+ let mut insts = smallvec![];
150
+
151
+ // If the top 32 bits are zero, use 32-bit `mov` operations.
152
+ let (num_half_words, size, negated) = if value >> 32 == 0 {
153
+ (2, OperandSize::Size32, (!value << 32) >> 32)
154
+ } else {
155
+ (4, OperandSize::Size64, !value)
156
+ };
157
+
158
+ // If the number of 0xffff half words is greater than the number of 0x0000 half words
159
+ // it is more efficient to use `movn` for the first instruction.
160
+ let first_is_inverted = count_zero_half_words(negated, num_half_words)
161
+ > count_zero_half_words(value, num_half_words);
162
+
163
+ // Either 0xffff or 0x0000 half words can be skipped, depending on the first
164
+ // instruction used.
165
+ let ignored_halfword = if first_is_inverted { 0xffff } else { 0 };
166
+
167
+ let halfwords: SmallVec<[_; 4]> = (0..num_half_words)
168
+ .filter_map(|i| {
169
+ let imm16 = (value >> (16 * i)) & 0xffff;
170
+ if imm16 == ignored_halfword {
171
+ None
172
+ } else {
173
+ Some((i, imm16))
174
+ }
175
+ })
176
+ .collect();
177
+
178
+ let mut prev_result = None;
179
+ let last_index = halfwords.last().unwrap().0;
180
+ for (i, imm16) in halfwords {
181
+ let shift = i * 16;
182
+ let rd = if i == last_index { rd } else { alloc_tmp(I16) };
183
+
184
+ if let Some(rn) = prev_result {
185
+ let imm = MoveWideConst::maybe_with_shift(imm16 as u16, shift).unwrap();
186
+ insts.push(Inst::MovK { rd, rn, imm, size });
187
+ } else {
188
+ if first_is_inverted {
189
+ let imm =
190
+ MoveWideConst::maybe_with_shift(((!imm16) & 0xffff) as u16, shift)
191
+ .unwrap();
192
+ insts.push(Inst::MovWide {
193
+ op: MoveWideOp::MovN,
194
+ rd,
195
+ imm,
196
+ size,
197
+ });
198
+ } else {
199
+ let imm = MoveWideConst::maybe_with_shift(imm16 as u16, shift).unwrap();
200
+ insts.push(Inst::MovWide {
201
+ op: MoveWideOp::MovZ,
202
+ rd,
203
+ imm,
204
+ size,
205
+ });
206
+ }
207
+ }
208
+
209
+ prev_result = Some(rd.to_reg());
210
+ }
211
+
212
+ assert!(prev_result.is_some());
213
+
214
+ insts
215
+ }
216
+ }
217
+
218
+ /// Generic constructor for a load (zero-extending where appropriate).
219
+ pub fn gen_load(into_reg: Writable<Reg>, mem: AMode, ty: Type, flags: MemFlags) -> Inst {
220
+ match ty {
221
+ I8 => Inst::ULoad8 {
222
+ rd: into_reg,
223
+ mem,
224
+ flags,
225
+ },
226
+ I16 => Inst::ULoad16 {
227
+ rd: into_reg,
228
+ mem,
229
+ flags,
230
+ },
231
+ I32 => Inst::ULoad32 {
232
+ rd: into_reg,
233
+ mem,
234
+ flags,
235
+ },
236
+ I64 => Inst::ULoad64 {
237
+ rd: into_reg,
238
+ mem,
239
+ flags,
240
+ },
241
+ F16 => Inst::FpuLoad16 {
242
+ rd: into_reg,
243
+ mem,
244
+ flags,
245
+ },
246
+ F32 => Inst::FpuLoad32 {
247
+ rd: into_reg,
248
+ mem,
249
+ flags,
250
+ },
251
+ F64 => Inst::FpuLoad64 {
252
+ rd: into_reg,
253
+ mem,
254
+ flags,
255
+ },
256
+ _ => {
257
+ if ty.is_vector() || ty.is_float() {
258
+ let bits = ty_bits(ty);
259
+ let rd = into_reg;
260
+
261
+ if bits == 128 {
262
+ Inst::FpuLoad128 { rd, mem, flags }
263
+ } else {
264
+ assert_eq!(bits, 64);
265
+ Inst::FpuLoad64 { rd, mem, flags }
266
+ }
267
+ } else {
268
+ unimplemented!("gen_load({})", ty);
269
+ }
270
+ }
271
+ }
272
+ }
273
+
274
+ /// Generic constructor for a store.
275
+ pub fn gen_store(mem: AMode, from_reg: Reg, ty: Type, flags: MemFlags) -> Inst {
276
+ match ty {
277
+ I8 => Inst::Store8 {
278
+ rd: from_reg,
279
+ mem,
280
+ flags,
281
+ },
282
+ I16 => Inst::Store16 {
283
+ rd: from_reg,
284
+ mem,
285
+ flags,
286
+ },
287
+ I32 => Inst::Store32 {
288
+ rd: from_reg,
289
+ mem,
290
+ flags,
291
+ },
292
+ I64 => Inst::Store64 {
293
+ rd: from_reg,
294
+ mem,
295
+ flags,
296
+ },
297
+ F16 => Inst::FpuStore16 {
298
+ rd: from_reg,
299
+ mem,
300
+ flags,
301
+ },
302
+ F32 => Inst::FpuStore32 {
303
+ rd: from_reg,
304
+ mem,
305
+ flags,
306
+ },
307
+ F64 => Inst::FpuStore64 {
308
+ rd: from_reg,
309
+ mem,
310
+ flags,
311
+ },
312
+ _ => {
313
+ if ty.is_vector() || ty.is_float() {
314
+ let bits = ty_bits(ty);
315
+ let rd = from_reg;
316
+
317
+ if bits == 128 {
318
+ Inst::FpuStore128 { rd, mem, flags }
319
+ } else {
320
+ assert_eq!(bits, 64);
321
+ Inst::FpuStore64 { rd, mem, flags }
322
+ }
323
+ } else {
324
+ unimplemented!("gen_store({})", ty);
325
+ }
326
+ }
327
+ }
328
+ }
329
+
330
+ /// What type does this load or store instruction access in memory? When
331
+ /// uimm12 encoding is used, the size of this type is the amount that
332
+ /// immediate offsets are scaled by.
333
+ pub fn mem_type(&self) -> Option<Type> {
334
+ match self {
335
+ Inst::ULoad8 { .. } => Some(I8),
336
+ Inst::SLoad8 { .. } => Some(I8),
337
+ Inst::ULoad16 { .. } => Some(I16),
338
+ Inst::SLoad16 { .. } => Some(I16),
339
+ Inst::ULoad32 { .. } => Some(I32),
340
+ Inst::SLoad32 { .. } => Some(I32),
341
+ Inst::ULoad64 { .. } => Some(I64),
342
+ Inst::FpuLoad16 { .. } => Some(F16),
343
+ Inst::FpuLoad32 { .. } => Some(F32),
344
+ Inst::FpuLoad64 { .. } => Some(F64),
345
+ Inst::FpuLoad128 { .. } => Some(I8X16),
346
+ Inst::Store8 { .. } => Some(I8),
347
+ Inst::Store16 { .. } => Some(I16),
348
+ Inst::Store32 { .. } => Some(I32),
349
+ Inst::Store64 { .. } => Some(I64),
350
+ Inst::FpuStore16 { .. } => Some(F16),
351
+ Inst::FpuStore32 { .. } => Some(F32),
352
+ Inst::FpuStore64 { .. } => Some(F64),
353
+ Inst::FpuStore128 { .. } => Some(I8X16),
354
+ _ => None,
355
+ }
356
+ }
357
+ }
358
+
359
+ //=============================================================================
360
+ // Instructions: get_regs
361
+
362
+ fn memarg_operands(memarg: &mut AMode, collector: &mut impl OperandVisitor) {
363
+ match memarg {
364
+ AMode::Unscaled { rn, .. } | AMode::UnsignedOffset { rn, .. } => {
365
+ collector.reg_use(rn);
366
+ }
367
+ AMode::RegReg { rn, rm, .. }
368
+ | AMode::RegScaled { rn, rm, .. }
369
+ | AMode::RegScaledExtended { rn, rm, .. }
370
+ | AMode::RegExtended { rn, rm, .. } => {
371
+ collector.reg_use(rn);
372
+ collector.reg_use(rm);
373
+ }
374
+ AMode::Label { .. } => {}
375
+ AMode::SPPreIndexed { .. } | AMode::SPPostIndexed { .. } => {}
376
+ AMode::FPOffset { .. } | AMode::IncomingArg { .. } => {}
377
+ AMode::SPOffset { .. } | AMode::SlotOffset { .. } => {}
378
+ AMode::RegOffset { rn, .. } => {
379
+ collector.reg_use(rn);
380
+ }
381
+ AMode::Const { .. } => {}
382
+ }
383
+ }
384
+
385
+ fn pairmemarg_operands(pairmemarg: &mut PairAMode, collector: &mut impl OperandVisitor) {
386
+ match pairmemarg {
387
+ PairAMode::SignedOffset { reg, .. } => {
388
+ collector.reg_use(reg);
389
+ }
390
+ PairAMode::SPPreIndexed { .. } | PairAMode::SPPostIndexed { .. } => {}
391
+ }
392
+ }
393
+
394
+ fn aarch64_get_operands(inst: &mut Inst, collector: &mut impl OperandVisitor) {
395
+ match inst {
396
+ Inst::AluRRR { rd, rn, rm, .. } => {
397
+ collector.reg_def(rd);
398
+ collector.reg_use(rn);
399
+ collector.reg_use(rm);
400
+ }
401
+ Inst::AluRRRR { rd, rn, rm, ra, .. } => {
402
+ collector.reg_def(rd);
403
+ collector.reg_use(rn);
404
+ collector.reg_use(rm);
405
+ collector.reg_use(ra);
406
+ }
407
+ Inst::AluRRImm12 { rd, rn, .. } => {
408
+ collector.reg_def(rd);
409
+ collector.reg_use(rn);
410
+ }
411
+ Inst::AluRRImmLogic { rd, rn, .. } => {
412
+ collector.reg_def(rd);
413
+ collector.reg_use(rn);
414
+ }
415
+ Inst::AluRRImmShift { rd, rn, .. } => {
416
+ collector.reg_def(rd);
417
+ collector.reg_use(rn);
418
+ }
419
+ Inst::AluRRRShift { rd, rn, rm, .. } => {
420
+ collector.reg_def(rd);
421
+ collector.reg_use(rn);
422
+ collector.reg_use(rm);
423
+ }
424
+ Inst::AluRRRExtend { rd, rn, rm, .. } => {
425
+ collector.reg_def(rd);
426
+ collector.reg_use(rn);
427
+ collector.reg_use(rm);
428
+ }
429
+ Inst::BitRR { rd, rn, .. } => {
430
+ collector.reg_def(rd);
431
+ collector.reg_use(rn);
432
+ }
433
+ Inst::ULoad8 { rd, mem, .. }
434
+ | Inst::SLoad8 { rd, mem, .. }
435
+ | Inst::ULoad16 { rd, mem, .. }
436
+ | Inst::SLoad16 { rd, mem, .. }
437
+ | Inst::ULoad32 { rd, mem, .. }
438
+ | Inst::SLoad32 { rd, mem, .. }
439
+ | Inst::ULoad64 { rd, mem, .. } => {
440
+ collector.reg_def(rd);
441
+ memarg_operands(mem, collector);
442
+ }
443
+ Inst::Store8 { rd, mem, .. }
444
+ | Inst::Store16 { rd, mem, .. }
445
+ | Inst::Store32 { rd, mem, .. }
446
+ | Inst::Store64 { rd, mem, .. } => {
447
+ collector.reg_use(rd);
448
+ memarg_operands(mem, collector);
449
+ }
450
+ Inst::StoreP64 { rt, rt2, mem, .. } => {
451
+ collector.reg_use(rt);
452
+ collector.reg_use(rt2);
453
+ pairmemarg_operands(mem, collector);
454
+ }
455
+ Inst::LoadP64 { rt, rt2, mem, .. } => {
456
+ collector.reg_def(rt);
457
+ collector.reg_def(rt2);
458
+ pairmemarg_operands(mem, collector);
459
+ }
460
+ Inst::Mov { rd, rm, .. } => {
461
+ collector.reg_def(rd);
462
+ collector.reg_use(rm);
463
+ }
464
+ Inst::MovFromPReg { rd, rm } => {
465
+ debug_assert!(rd.to_reg().is_virtual());
466
+ collector.reg_def(rd);
467
+ collector.reg_fixed_nonallocatable(*rm);
468
+ }
469
+ Inst::MovToPReg { rd, rm } => {
470
+ debug_assert!(rm.is_virtual());
471
+ collector.reg_fixed_nonallocatable(*rd);
472
+ collector.reg_use(rm);
473
+ }
474
+ Inst::MovK { rd, rn, .. } => {
475
+ collector.reg_use(rn);
476
+ collector.reg_reuse_def(rd, 0); // `rn` == `rd`.
477
+ }
478
+ Inst::MovWide { rd, .. } => {
479
+ collector.reg_def(rd);
480
+ }
481
+ Inst::CSel { rd, rn, rm, .. } => {
482
+ collector.reg_def(rd);
483
+ collector.reg_use(rn);
484
+ collector.reg_use(rm);
485
+ }
486
+ Inst::CSNeg { rd, rn, rm, .. } => {
487
+ collector.reg_def(rd);
488
+ collector.reg_use(rn);
489
+ collector.reg_use(rm);
490
+ }
491
+ Inst::CSet { rd, .. } | Inst::CSetm { rd, .. } => {
492
+ collector.reg_def(rd);
493
+ }
494
+ Inst::CCmp { rn, rm, .. } => {
495
+ collector.reg_use(rn);
496
+ collector.reg_use(rm);
497
+ }
498
+ Inst::CCmpImm { rn, .. } => {
499
+ collector.reg_use(rn);
500
+ }
501
+ Inst::AtomicRMWLoop {
502
+ op,
503
+ addr,
504
+ operand,
505
+ oldval,
506
+ scratch1,
507
+ scratch2,
508
+ ..
509
+ } => {
510
+ collector.reg_fixed_use(addr, xreg(25));
511
+ collector.reg_fixed_use(operand, xreg(26));
512
+ collector.reg_fixed_def(oldval, xreg(27));
513
+ collector.reg_fixed_def(scratch1, xreg(24));
514
+ if *op != AtomicRMWLoopOp::Xchg {
515
+ collector.reg_fixed_def(scratch2, xreg(28));
516
+ }
517
+ }
518
+ Inst::AtomicRMW { rs, rt, rn, .. } => {
519
+ collector.reg_use(rs);
520
+ collector.reg_def(rt);
521
+ collector.reg_use(rn);
522
+ }
523
+ Inst::AtomicCAS { rd, rs, rt, rn, .. } => {
524
+ collector.reg_reuse_def(rd, 1); // reuse `rs`.
525
+ collector.reg_use(rs);
526
+ collector.reg_use(rt);
527
+ collector.reg_use(rn);
528
+ }
529
+ Inst::AtomicCASLoop {
530
+ addr,
531
+ expected,
532
+ replacement,
533
+ oldval,
534
+ scratch,
535
+ ..
536
+ } => {
537
+ collector.reg_fixed_use(addr, xreg(25));
538
+ collector.reg_fixed_use(expected, xreg(26));
539
+ collector.reg_fixed_use(replacement, xreg(28));
540
+ collector.reg_fixed_def(oldval, xreg(27));
541
+ collector.reg_fixed_def(scratch, xreg(24));
542
+ }
543
+ Inst::LoadAcquire { rt, rn, .. } => {
544
+ collector.reg_use(rn);
545
+ collector.reg_def(rt);
546
+ }
547
+ Inst::StoreRelease { rt, rn, .. } => {
548
+ collector.reg_use(rn);
549
+ collector.reg_use(rt);
550
+ }
551
+ Inst::Fence {} | Inst::Csdb {} => {}
552
+ Inst::FpuMove32 { rd, rn } => {
553
+ collector.reg_def(rd);
554
+ collector.reg_use(rn);
555
+ }
556
+ Inst::FpuMove64 { rd, rn } => {
557
+ collector.reg_def(rd);
558
+ collector.reg_use(rn);
559
+ }
560
+ Inst::FpuMove128 { rd, rn } => {
561
+ collector.reg_def(rd);
562
+ collector.reg_use(rn);
563
+ }
564
+ Inst::FpuMoveFromVec { rd, rn, .. } => {
565
+ collector.reg_def(rd);
566
+ collector.reg_use(rn);
567
+ }
568
+ Inst::FpuExtend { rd, rn, .. } => {
569
+ collector.reg_def(rd);
570
+ collector.reg_use(rn);
571
+ }
572
+ Inst::FpuRR { rd, rn, .. } => {
573
+ collector.reg_def(rd);
574
+ collector.reg_use(rn);
575
+ }
576
+ Inst::FpuRRR { rd, rn, rm, .. } => {
577
+ collector.reg_def(rd);
578
+ collector.reg_use(rn);
579
+ collector.reg_use(rm);
580
+ }
581
+ Inst::FpuRRI { rd, rn, .. } => {
582
+ collector.reg_def(rd);
583
+ collector.reg_use(rn);
584
+ }
585
+ Inst::FpuRRIMod { rd, ri, rn, .. } => {
586
+ collector.reg_reuse_def(rd, 1); // reuse `ri`.
587
+ collector.reg_use(ri);
588
+ collector.reg_use(rn);
589
+ }
590
+ Inst::FpuRRRR { rd, rn, rm, ra, .. } => {
591
+ collector.reg_def(rd);
592
+ collector.reg_use(rn);
593
+ collector.reg_use(rm);
594
+ collector.reg_use(ra);
595
+ }
596
+ Inst::VecMisc { rd, rn, .. } => {
597
+ collector.reg_def(rd);
598
+ collector.reg_use(rn);
599
+ }
600
+
601
+ Inst::VecLanes { rd, rn, .. } => {
602
+ collector.reg_def(rd);
603
+ collector.reg_use(rn);
604
+ }
605
+ Inst::VecShiftImm { rd, rn, .. } => {
606
+ collector.reg_def(rd);
607
+ collector.reg_use(rn);
608
+ }
609
+ Inst::VecShiftImmMod { rd, ri, rn, .. } => {
610
+ collector.reg_reuse_def(rd, 1); // `rd` == `ri`.
611
+ collector.reg_use(ri);
612
+ collector.reg_use(rn);
613
+ }
614
+ Inst::VecExtract { rd, rn, rm, .. } => {
615
+ collector.reg_def(rd);
616
+ collector.reg_use(rn);
617
+ collector.reg_use(rm);
618
+ }
619
+ Inst::VecTbl { rd, rn, rm } => {
620
+ collector.reg_use(rn);
621
+ collector.reg_use(rm);
622
+ collector.reg_def(rd);
623
+ }
624
+ Inst::VecTblExt { rd, ri, rn, rm } => {
625
+ collector.reg_use(rn);
626
+ collector.reg_use(rm);
627
+ collector.reg_reuse_def(rd, 3); // `rd` == `ri`.
628
+ collector.reg_use(ri);
629
+ }
630
+
631
+ Inst::VecTbl2 { rd, rn, rn2, rm } => {
632
+ // Constrain to v30 / v31 so that we satisfy the "adjacent
633
+ // registers" constraint without use of pinned vregs in
634
+ // lowering.
635
+ collector.reg_fixed_use(rn, vreg(30));
636
+ collector.reg_fixed_use(rn2, vreg(31));
637
+ collector.reg_use(rm);
638
+ collector.reg_def(rd);
639
+ }
640
+ Inst::VecTbl2Ext {
641
+ rd,
642
+ ri,
643
+ rn,
644
+ rn2,
645
+ rm,
646
+ } => {
647
+ // Constrain to v30 / v31 so that we satisfy the "adjacent
648
+ // registers" constraint without use of pinned vregs in
649
+ // lowering.
650
+ collector.reg_fixed_use(rn, vreg(30));
651
+ collector.reg_fixed_use(rn2, vreg(31));
652
+ collector.reg_use(rm);
653
+ collector.reg_reuse_def(rd, 4); // `rd` == `ri`.
654
+ collector.reg_use(ri);
655
+ }
656
+ Inst::VecLoadReplicate { rd, rn, .. } => {
657
+ collector.reg_def(rd);
658
+ collector.reg_use(rn);
659
+ }
660
+ Inst::VecCSel { rd, rn, rm, .. } => {
661
+ collector.reg_def(rd);
662
+ collector.reg_use(rn);
663
+ collector.reg_use(rm);
664
+ }
665
+ Inst::FpuCmp { rn, rm, .. } => {
666
+ collector.reg_use(rn);
667
+ collector.reg_use(rm);
668
+ }
669
+ Inst::FpuLoad16 { rd, mem, .. } => {
670
+ collector.reg_def(rd);
671
+ memarg_operands(mem, collector);
672
+ }
673
+ Inst::FpuLoad32 { rd, mem, .. } => {
674
+ collector.reg_def(rd);
675
+ memarg_operands(mem, collector);
676
+ }
677
+ Inst::FpuLoad64 { rd, mem, .. } => {
678
+ collector.reg_def(rd);
679
+ memarg_operands(mem, collector);
680
+ }
681
+ Inst::FpuLoad128 { rd, mem, .. } => {
682
+ collector.reg_def(rd);
683
+ memarg_operands(mem, collector);
684
+ }
685
+ Inst::FpuStore16 { rd, mem, .. } => {
686
+ collector.reg_use(rd);
687
+ memarg_operands(mem, collector);
688
+ }
689
+ Inst::FpuStore32 { rd, mem, .. } => {
690
+ collector.reg_use(rd);
691
+ memarg_operands(mem, collector);
692
+ }
693
+ Inst::FpuStore64 { rd, mem, .. } => {
694
+ collector.reg_use(rd);
695
+ memarg_operands(mem, collector);
696
+ }
697
+ Inst::FpuStore128 { rd, mem, .. } => {
698
+ collector.reg_use(rd);
699
+ memarg_operands(mem, collector);
700
+ }
701
+ Inst::FpuLoadP64 { rt, rt2, mem, .. } => {
702
+ collector.reg_def(rt);
703
+ collector.reg_def(rt2);
704
+ pairmemarg_operands(mem, collector);
705
+ }
706
+ Inst::FpuStoreP64 { rt, rt2, mem, .. } => {
707
+ collector.reg_use(rt);
708
+ collector.reg_use(rt2);
709
+ pairmemarg_operands(mem, collector);
710
+ }
711
+ Inst::FpuLoadP128 { rt, rt2, mem, .. } => {
712
+ collector.reg_def(rt);
713
+ collector.reg_def(rt2);
714
+ pairmemarg_operands(mem, collector);
715
+ }
716
+ Inst::FpuStoreP128 { rt, rt2, mem, .. } => {
717
+ collector.reg_use(rt);
718
+ collector.reg_use(rt2);
719
+ pairmemarg_operands(mem, collector);
720
+ }
721
+ Inst::FpuToInt { rd, rn, .. } => {
722
+ collector.reg_def(rd);
723
+ collector.reg_use(rn);
724
+ }
725
+ Inst::IntToFpu { rd, rn, .. } => {
726
+ collector.reg_def(rd);
727
+ collector.reg_use(rn);
728
+ }
729
+ Inst::FpuCSel16 { rd, rn, rm, .. }
730
+ | Inst::FpuCSel32 { rd, rn, rm, .. }
731
+ | Inst::FpuCSel64 { rd, rn, rm, .. } => {
732
+ collector.reg_def(rd);
733
+ collector.reg_use(rn);
734
+ collector.reg_use(rm);
735
+ }
736
+ Inst::FpuRound { rd, rn, .. } => {
737
+ collector.reg_def(rd);
738
+ collector.reg_use(rn);
739
+ }
740
+ Inst::MovToFpu { rd, rn, .. } => {
741
+ collector.reg_def(rd);
742
+ collector.reg_use(rn);
743
+ }
744
+ Inst::FpuMoveFPImm { rd, .. } => {
745
+ collector.reg_def(rd);
746
+ }
747
+ Inst::MovToVec { rd, ri, rn, .. } => {
748
+ collector.reg_reuse_def(rd, 1); // `rd` == `ri`.
749
+ collector.reg_use(ri);
750
+ collector.reg_use(rn);
751
+ }
752
+ Inst::MovFromVec { rd, rn, .. } | Inst::MovFromVecSigned { rd, rn, .. } => {
753
+ collector.reg_def(rd);
754
+ collector.reg_use(rn);
755
+ }
756
+ Inst::VecDup { rd, rn, .. } => {
757
+ collector.reg_def(rd);
758
+ collector.reg_use(rn);
759
+ }
760
+ Inst::VecDupFromFpu { rd, rn, .. } => {
761
+ collector.reg_def(rd);
762
+ collector.reg_use(rn);
763
+ }
764
+ Inst::VecDupFPImm { rd, .. } => {
765
+ collector.reg_def(rd);
766
+ }
767
+ Inst::VecDupImm { rd, .. } => {
768
+ collector.reg_def(rd);
769
+ }
770
+ Inst::VecExtend { rd, rn, .. } => {
771
+ collector.reg_def(rd);
772
+ collector.reg_use(rn);
773
+ }
774
+ Inst::VecMovElement { rd, ri, rn, .. } => {
775
+ collector.reg_reuse_def(rd, 1); // `rd` == `ri`.
776
+ collector.reg_use(ri);
777
+ collector.reg_use(rn);
778
+ }
779
+ Inst::VecRRLong { rd, rn, .. } => {
780
+ collector.reg_def(rd);
781
+ collector.reg_use(rn);
782
+ }
783
+ Inst::VecRRNarrowLow { rd, rn, .. } => {
784
+ collector.reg_use(rn);
785
+ collector.reg_def(rd);
786
+ }
787
+ Inst::VecRRNarrowHigh { rd, ri, rn, .. } => {
788
+ collector.reg_use(rn);
789
+ collector.reg_reuse_def(rd, 2); // `rd` == `ri`.
790
+ collector.reg_use(ri);
791
+ }
792
+ Inst::VecRRPair { rd, rn, .. } => {
793
+ collector.reg_def(rd);
794
+ collector.reg_use(rn);
795
+ }
796
+ Inst::VecRRRLong { rd, rn, rm, .. } => {
797
+ collector.reg_def(rd);
798
+ collector.reg_use(rn);
799
+ collector.reg_use(rm);
800
+ }
801
+ Inst::VecRRRLongMod { rd, ri, rn, rm, .. } => {
802
+ collector.reg_reuse_def(rd, 1); // `rd` == `ri`.
803
+ collector.reg_use(ri);
804
+ collector.reg_use(rn);
805
+ collector.reg_use(rm);
806
+ }
807
+ Inst::VecRRPairLong { rd, rn, .. } => {
808
+ collector.reg_def(rd);
809
+ collector.reg_use(rn);
810
+ }
811
+ Inst::VecRRR { rd, rn, rm, .. } => {
812
+ collector.reg_def(rd);
813
+ collector.reg_use(rn);
814
+ collector.reg_use(rm);
815
+ }
816
+ Inst::VecRRRMod { rd, ri, rn, rm, .. } | Inst::VecFmlaElem { rd, ri, rn, rm, .. } => {
817
+ collector.reg_reuse_def(rd, 1); // `rd` == `ri`.
818
+ collector.reg_use(ri);
819
+ collector.reg_use(rn);
820
+ collector.reg_use(rm);
821
+ }
822
+ Inst::MovToNZCV { rn } => {
823
+ collector.reg_use(rn);
824
+ }
825
+ Inst::MovFromNZCV { rd } => {
826
+ collector.reg_def(rd);
827
+ }
828
+ Inst::Extend { rd, rn, .. } => {
829
+ collector.reg_def(rd);
830
+ collector.reg_use(rn);
831
+ }
832
+ Inst::Args { args } => {
833
+ for ArgPair { vreg, preg } in args {
834
+ collector.reg_fixed_def(vreg, *preg);
835
+ }
836
+ }
837
+ Inst::Rets { rets } => {
838
+ for RetPair { vreg, preg } in rets {
839
+ collector.reg_fixed_use(vreg, *preg);
840
+ }
841
+ }
842
+ Inst::Ret { .. } | Inst::AuthenticatedRet { .. } => {}
843
+ Inst::Jump { .. } => {}
844
+ Inst::Call { info, .. } => {
845
+ let CallInfo { uses, defs, .. } = &mut **info;
846
+ for CallArgPair { vreg, preg } in uses {
847
+ collector.reg_fixed_use(vreg, *preg);
848
+ }
849
+ for CallRetPair { vreg, preg } in defs {
850
+ collector.reg_fixed_def(vreg, *preg);
851
+ }
852
+ collector.reg_clobbers(info.clobbers);
853
+ }
854
+ Inst::CallInd { info, .. } => {
855
+ let CallInfo {
856
+ dest, uses, defs, ..
857
+ } = &mut **info;
858
+ collector.reg_use(dest);
859
+ for CallArgPair { vreg, preg } in uses {
860
+ collector.reg_fixed_use(vreg, *preg);
861
+ }
862
+ for CallRetPair { vreg, preg } in defs {
863
+ collector.reg_fixed_def(vreg, *preg);
864
+ }
865
+ collector.reg_clobbers(info.clobbers);
866
+ }
867
+ Inst::ReturnCall { info } => {
868
+ for CallArgPair { vreg, preg } in &mut info.uses {
869
+ collector.reg_fixed_use(vreg, *preg);
870
+ }
871
+ }
872
+ Inst::ReturnCallInd { info } => {
873
+ // TODO(https://github.com/bytecodealliance/regalloc2/issues/145):
874
+ // This shouldn't be a fixed register constraint, but it's not clear how to pick a
875
+ // register that won't be clobbered by the callee-save restore code emitted with a
876
+ // return_call_indirect.
877
+ collector.reg_fixed_use(&mut info.dest, xreg(1));
878
+ for CallArgPair { vreg, preg } in &mut info.uses {
879
+ collector.reg_fixed_use(vreg, *preg);
880
+ }
881
+ }
882
+ Inst::CondBr { kind, .. } => match kind {
883
+ CondBrKind::Zero(rt) | CondBrKind::NotZero(rt) => collector.reg_use(rt),
884
+ CondBrKind::Cond(_) => {}
885
+ },
886
+ Inst::TestBitAndBranch { rn, .. } => {
887
+ collector.reg_use(rn);
888
+ }
889
+ Inst::IndirectBr { rn, .. } => {
890
+ collector.reg_use(rn);
891
+ }
892
+ Inst::Nop0 | Inst::Nop4 => {}
893
+ Inst::Brk => {}
894
+ Inst::Udf { .. } => {}
895
+ Inst::TrapIf { kind, .. } => match kind {
896
+ CondBrKind::Zero(rt) | CondBrKind::NotZero(rt) => collector.reg_use(rt),
897
+ CondBrKind::Cond(_) => {}
898
+ },
899
+ Inst::Adr { rd, .. } | Inst::Adrp { rd, .. } => {
900
+ collector.reg_def(rd);
901
+ }
902
+ Inst::Word4 { .. } | Inst::Word8 { .. } => {}
903
+ Inst::JTSequence {
904
+ ridx, rtmp1, rtmp2, ..
905
+ } => {
906
+ collector.reg_use(ridx);
907
+ collector.reg_early_def(rtmp1);
908
+ collector.reg_early_def(rtmp2);
909
+ }
910
+ Inst::LoadExtName { rd, .. } => {
911
+ collector.reg_def(rd);
912
+ }
913
+ Inst::LoadAddr { rd, mem } => {
914
+ collector.reg_def(rd);
915
+ memarg_operands(mem, collector);
916
+ }
917
+ Inst::Paci { .. } | Inst::Xpaclri => {
918
+ // Neither LR nor SP is an allocatable register, so there is no need
919
+ // to do anything.
920
+ }
921
+ Inst::Bti { .. } => {}
922
+
923
+ Inst::ElfTlsGetAddr { rd, tmp, .. } => {
924
+ // TLSDESC has a very neat calling convention. It is required to preserve
925
+ // all registers except x0 and x30. X30 is non allocatable in cranelift since
926
+ // its the link register.
927
+ //
928
+ // Additionally we need a second register as a temporary register for the
929
+ // TLSDESC sequence. This register can be any register other than x0 (and x30).
930
+ collector.reg_fixed_def(rd, regs::xreg(0));
931
+ collector.reg_early_def(tmp);
932
+ }
933
+ Inst::MachOTlsGetAddr { rd, .. } => {
934
+ collector.reg_fixed_def(rd, regs::xreg(0));
935
+ let mut clobbers =
936
+ AArch64MachineDeps::get_regs_clobbered_by_call(CallConv::AppleAarch64);
937
+ clobbers.remove(regs::xreg_preg(0));
938
+ collector.reg_clobbers(clobbers);
939
+ }
940
+ Inst::Unwind { .. } => {}
941
+ Inst::EmitIsland { .. } => {}
942
+ Inst::DummyUse { reg } => {
943
+ collector.reg_use(reg);
944
+ }
945
+ Inst::StackProbeLoop { start, end, .. } => {
946
+ collector.reg_early_def(start);
947
+ collector.reg_use(end);
948
+ }
949
+ }
950
+ }
951
+
952
+ //=============================================================================
953
+ // Instructions: misc functions and external interface
954
+
955
+ impl MachInst for Inst {
956
+ type ABIMachineSpec = AArch64MachineDeps;
957
+ type LabelUse = LabelUse;
958
+
959
+ // "CLIF" in hex, to make the trap recognizable during
960
+ // debugging.
961
+ const TRAP_OPCODE: &'static [u8] = &0xc11f_u32.to_le_bytes();
962
+
963
+ fn get_operands(&mut self, collector: &mut impl OperandVisitor) {
964
+ aarch64_get_operands(self, collector);
965
+ }
966
+
967
+ fn is_move(&self) -> Option<(Writable<Reg>, Reg)> {
968
+ match self {
969
+ &Inst::Mov {
970
+ size: OperandSize::Size64,
971
+ rd,
972
+ rm,
973
+ } => Some((rd, rm)),
974
+ &Inst::FpuMove64 { rd, rn } => Some((rd, rn)),
975
+ &Inst::FpuMove128 { rd, rn } => Some((rd, rn)),
976
+ _ => None,
977
+ }
978
+ }
979
+
980
+ fn is_included_in_clobbers(&self) -> bool {
981
+ let (caller, callee) = match self {
982
+ Inst::Args { .. } => return false,
983
+ Inst::Call { info } => (info.caller_conv, info.callee_conv),
984
+ Inst::CallInd { info } => (info.caller_conv, info.callee_conv),
985
+ _ => return true,
986
+ };
987
+
988
+ // We exclude call instructions from the clobber-set when they are calls
989
+ // from caller to callee that both clobber the same register (such as
990
+ // using the same or similar ABIs). Such calls cannot possibly force any
991
+ // new registers to be saved in the prologue, because anything that the
992
+ // callee clobbers, the caller is also allowed to clobber. This both
993
+ // saves work and enables us to more precisely follow the
994
+ // half-caller-save, half-callee-save SysV ABI for some vector
995
+ // registers.
996
+ //
997
+ // See the note in [crate::isa::aarch64::abi::is_caller_save_reg] for
998
+ // more information on this ABI-implementation hack.
999
+ let caller_clobbers = AArch64MachineDeps::get_regs_clobbered_by_call(caller);
1000
+ let callee_clobbers = AArch64MachineDeps::get_regs_clobbered_by_call(callee);
1001
+
1002
+ let mut all_clobbers = caller_clobbers;
1003
+ all_clobbers.union_from(callee_clobbers);
1004
+ all_clobbers != caller_clobbers
1005
+ }
1006
+
1007
+ fn is_trap(&self) -> bool {
1008
+ match self {
1009
+ Self::Udf { .. } => true,
1010
+ _ => false,
1011
+ }
1012
+ }
1013
+
1014
+ fn is_args(&self) -> bool {
1015
+ match self {
1016
+ Self::Args { .. } => true,
1017
+ _ => false,
1018
+ }
1019
+ }
1020
+
1021
+ fn is_term(&self) -> MachTerminator {
1022
+ match self {
1023
+ &Inst::Rets { .. } => MachTerminator::Ret,
1024
+ &Inst::ReturnCall { .. } | &Inst::ReturnCallInd { .. } => MachTerminator::RetCall,
1025
+ &Inst::Jump { .. } => MachTerminator::Uncond,
1026
+ &Inst::CondBr { .. } => MachTerminator::Cond,
1027
+ &Inst::TestBitAndBranch { .. } => MachTerminator::Cond,
1028
+ &Inst::IndirectBr { .. } => MachTerminator::Indirect,
1029
+ &Inst::JTSequence { .. } => MachTerminator::Indirect,
1030
+ _ => MachTerminator::None,
1031
+ }
1032
+ }
1033
+
1034
+ fn is_mem_access(&self) -> bool {
1035
+ match self {
1036
+ &Inst::ULoad8 { .. }
1037
+ | &Inst::SLoad8 { .. }
1038
+ | &Inst::ULoad16 { .. }
1039
+ | &Inst::SLoad16 { .. }
1040
+ | &Inst::ULoad32 { .. }
1041
+ | &Inst::SLoad32 { .. }
1042
+ | &Inst::ULoad64 { .. }
1043
+ | &Inst::LoadP64 { .. }
1044
+ | &Inst::FpuLoad16 { .. }
1045
+ | &Inst::FpuLoad32 { .. }
1046
+ | &Inst::FpuLoad64 { .. }
1047
+ | &Inst::FpuLoad128 { .. }
1048
+ | &Inst::FpuLoadP64 { .. }
1049
+ | &Inst::FpuLoadP128 { .. }
1050
+ | &Inst::Store8 { .. }
1051
+ | &Inst::Store16 { .. }
1052
+ | &Inst::Store32 { .. }
1053
+ | &Inst::Store64 { .. }
1054
+ | &Inst::StoreP64 { .. }
1055
+ | &Inst::FpuStore16 { .. }
1056
+ | &Inst::FpuStore32 { .. }
1057
+ | &Inst::FpuStore64 { .. }
1058
+ | &Inst::FpuStore128 { .. } => true,
1059
+ // TODO: verify this carefully
1060
+ _ => false,
1061
+ }
1062
+ }
1063
+
1064
+ fn gen_move(to_reg: Writable<Reg>, from_reg: Reg, ty: Type) -> Inst {
1065
+ let bits = ty.bits();
1066
+
1067
+ assert!(bits <= 128);
1068
+ assert!(to_reg.to_reg().class() == from_reg.class());
1069
+ match from_reg.class() {
1070
+ RegClass::Int => Inst::Mov {
1071
+ size: OperandSize::Size64,
1072
+ rd: to_reg,
1073
+ rm: from_reg,
1074
+ },
1075
+ RegClass::Float => {
1076
+ if bits > 64 {
1077
+ Inst::FpuMove128 {
1078
+ rd: to_reg,
1079
+ rn: from_reg,
1080
+ }
1081
+ } else {
1082
+ Inst::FpuMove64 {
1083
+ rd: to_reg,
1084
+ rn: from_reg,
1085
+ }
1086
+ }
1087
+ }
1088
+ RegClass::Vector => unreachable!(),
1089
+ }
1090
+ }
1091
+
1092
+ fn is_safepoint(&self) -> bool {
1093
+ match self {
1094
+ Inst::Call { .. } | Inst::CallInd { .. } => true,
1095
+ _ => false,
1096
+ }
1097
+ }
1098
+
1099
+ fn gen_dummy_use(reg: Reg) -> Inst {
1100
+ Inst::DummyUse { reg }
1101
+ }
1102
+
1103
+ fn gen_nop(preferred_size: usize) -> Inst {
1104
+ if preferred_size == 0 {
1105
+ return Inst::Nop0;
1106
+ }
1107
+ // We can't give a NOP (or any insn) < 4 bytes.
1108
+ assert!(preferred_size >= 4);
1109
+ Inst::Nop4
1110
+ }
1111
+
1112
+ fn rc_for_type(ty: Type) -> CodegenResult<(&'static [RegClass], &'static [Type])> {
1113
+ match ty {
1114
+ I8 => Ok((&[RegClass::Int], &[I8])),
1115
+ I16 => Ok((&[RegClass::Int], &[I16])),
1116
+ I32 => Ok((&[RegClass::Int], &[I32])),
1117
+ I64 => Ok((&[RegClass::Int], &[I64])),
1118
+ F16 => Ok((&[RegClass::Float], &[F16])),
1119
+ F32 => Ok((&[RegClass::Float], &[F32])),
1120
+ F64 => Ok((&[RegClass::Float], &[F64])),
1121
+ F128 => Ok((&[RegClass::Float], &[F128])),
1122
+ I128 => Ok((&[RegClass::Int, RegClass::Int], &[I64, I64])),
1123
+ _ if ty.is_vector() => {
1124
+ assert!(ty.bits() <= 128);
1125
+ Ok((&[RegClass::Float], &[I8X16]))
1126
+ }
1127
+ _ if ty.is_dynamic_vector() => Ok((&[RegClass::Float], &[I8X16])),
1128
+ _ => Err(CodegenError::Unsupported(format!(
1129
+ "Unexpected SSA-value type: {ty}"
1130
+ ))),
1131
+ }
1132
+ }
1133
+
1134
+ fn canonical_type_for_rc(rc: RegClass) -> Type {
1135
+ match rc {
1136
+ RegClass::Float => types::I8X16,
1137
+ RegClass::Int => types::I64,
1138
+ RegClass::Vector => unreachable!(),
1139
+ }
1140
+ }
1141
+
1142
+ fn gen_jump(target: MachLabel) -> Inst {
1143
+ Inst::Jump {
1144
+ dest: BranchTarget::Label(target),
1145
+ }
1146
+ }
1147
+
1148
+ fn worst_case_size() -> CodeOffset {
1149
+ // The maximum size, in bytes, of any `Inst`'s emitted code. We have at least one case of
1150
+ // an 8-instruction sequence (saturating int-to-float conversions) with three embedded
1151
+ // 64-bit f64 constants.
1152
+ //
1153
+ // Note that inline jump-tables handle island/pool insertion separately, so we do not need
1154
+ // to account for them here (otherwise the worst case would be 2^31 * 4, clearly not
1155
+ // feasible for other reasons).
1156
+ 44
1157
+ }
1158
+
1159
+ fn ref_type_regclass(_: &settings::Flags) -> RegClass {
1160
+ RegClass::Int
1161
+ }
1162
+
1163
+ fn gen_block_start(
1164
+ is_indirect_branch_target: bool,
1165
+ is_forward_edge_cfi_enabled: bool,
1166
+ ) -> Option<Self> {
1167
+ if is_indirect_branch_target && is_forward_edge_cfi_enabled {
1168
+ Some(Inst::Bti {
1169
+ targets: BranchTargetType::J,
1170
+ })
1171
+ } else {
1172
+ None
1173
+ }
1174
+ }
1175
+
1176
+ fn function_alignment() -> FunctionAlignment {
1177
+ // We use 32-byte alignment for performance reasons, but for correctness
1178
+ // we would only need 4-byte alignment.
1179
+ FunctionAlignment {
1180
+ minimum: 4,
1181
+ preferred: 32,
1182
+ }
1183
+ }
1184
+ }
1185
+
1186
+ //=============================================================================
1187
+ // Pretty-printing of instructions.
1188
+
1189
+ fn mem_finalize_for_show(mem: &AMode, access_ty: Type, state: &EmitState) -> (String, String) {
1190
+ let (mem_insts, mem) = mem_finalize(None, mem, access_ty, state);
1191
+ let mut mem_str = mem_insts
1192
+ .into_iter()
1193
+ .map(|inst| inst.print_with_state(&mut EmitState::default()))
1194
+ .collect::<Vec<_>>()
1195
+ .join(" ; ");
1196
+ if !mem_str.is_empty() {
1197
+ mem_str += " ; ";
1198
+ }
1199
+
1200
+ let mem = mem.pretty_print(access_ty.bytes() as u8);
1201
+ (mem_str, mem)
1202
+ }
1203
+
1204
+ impl Inst {
1205
+ fn print_with_state(&self, state: &mut EmitState) -> String {
1206
+ fn op_name(alu_op: ALUOp) -> &'static str {
1207
+ match alu_op {
1208
+ ALUOp::Add => "add",
1209
+ ALUOp::Sub => "sub",
1210
+ ALUOp::Orr => "orr",
1211
+ ALUOp::And => "and",
1212
+ ALUOp::AndS => "ands",
1213
+ ALUOp::Eor => "eor",
1214
+ ALUOp::AddS => "adds",
1215
+ ALUOp::SubS => "subs",
1216
+ ALUOp::SMulH => "smulh",
1217
+ ALUOp::UMulH => "umulh",
1218
+ ALUOp::SDiv => "sdiv",
1219
+ ALUOp::UDiv => "udiv",
1220
+ ALUOp::AndNot => "bic",
1221
+ ALUOp::OrrNot => "orn",
1222
+ ALUOp::EorNot => "eon",
1223
+ ALUOp::RotR => "ror",
1224
+ ALUOp::Lsr => "lsr",
1225
+ ALUOp::Asr => "asr",
1226
+ ALUOp::Lsl => "lsl",
1227
+ ALUOp::Adc => "adc",
1228
+ ALUOp::AdcS => "adcs",
1229
+ ALUOp::Sbc => "sbc",
1230
+ ALUOp::SbcS => "sbcs",
1231
+ }
1232
+ }
1233
+
1234
+ match self {
1235
+ &Inst::Nop0 => "nop-zero-len".to_string(),
1236
+ &Inst::Nop4 => "nop".to_string(),
1237
+ &Inst::AluRRR {
1238
+ alu_op,
1239
+ size,
1240
+ rd,
1241
+ rn,
1242
+ rm,
1243
+ } => {
1244
+ let op = op_name(alu_op);
1245
+ let rd = pretty_print_ireg(rd.to_reg(), size);
1246
+ let rn = pretty_print_ireg(rn, size);
1247
+ let rm = pretty_print_ireg(rm, size);
1248
+ format!("{op} {rd}, {rn}, {rm}")
1249
+ }
1250
+ &Inst::AluRRRR {
1251
+ alu_op,
1252
+ size,
1253
+ rd,
1254
+ rn,
1255
+ rm,
1256
+ ra,
1257
+ } => {
1258
+ let (op, da_size) = match alu_op {
1259
+ ALUOp3::MAdd => ("madd", size),
1260
+ ALUOp3::MSub => ("msub", size),
1261
+ ALUOp3::UMAddL => ("umaddl", OperandSize::Size64),
1262
+ ALUOp3::SMAddL => ("smaddl", OperandSize::Size64),
1263
+ };
1264
+ let rd = pretty_print_ireg(rd.to_reg(), da_size);
1265
+ let rn = pretty_print_ireg(rn, size);
1266
+ let rm = pretty_print_ireg(rm, size);
1267
+ let ra = pretty_print_ireg(ra, da_size);
1268
+
1269
+ format!("{op} {rd}, {rn}, {rm}, {ra}")
1270
+ }
1271
+ &Inst::AluRRImm12 {
1272
+ alu_op,
1273
+ size,
1274
+ rd,
1275
+ rn,
1276
+ ref imm12,
1277
+ } => {
1278
+ let op = op_name(alu_op);
1279
+ let rd = pretty_print_ireg(rd.to_reg(), size);
1280
+ let rn = pretty_print_ireg(rn, size);
1281
+
1282
+ if imm12.bits == 0 && alu_op == ALUOp::Add && size.is64() {
1283
+ // special-case MOV (used for moving into SP).
1284
+ format!("mov {rd}, {rn}")
1285
+ } else {
1286
+ let imm12 = imm12.pretty_print(0);
1287
+ format!("{op} {rd}, {rn}, {imm12}")
1288
+ }
1289
+ }
1290
+ &Inst::AluRRImmLogic {
1291
+ alu_op,
1292
+ size,
1293
+ rd,
1294
+ rn,
1295
+ ref imml,
1296
+ } => {
1297
+ let op = op_name(alu_op);
1298
+ let rd = pretty_print_ireg(rd.to_reg(), size);
1299
+ let rn = pretty_print_ireg(rn, size);
1300
+ let imml = imml.pretty_print(0);
1301
+ format!("{op} {rd}, {rn}, {imml}")
1302
+ }
1303
+ &Inst::AluRRImmShift {
1304
+ alu_op,
1305
+ size,
1306
+ rd,
1307
+ rn,
1308
+ ref immshift,
1309
+ } => {
1310
+ let op = op_name(alu_op);
1311
+ let rd = pretty_print_ireg(rd.to_reg(), size);
1312
+ let rn = pretty_print_ireg(rn, size);
1313
+ let immshift = immshift.pretty_print(0);
1314
+ format!("{op} {rd}, {rn}, {immshift}")
1315
+ }
1316
+ &Inst::AluRRRShift {
1317
+ alu_op,
1318
+ size,
1319
+ rd,
1320
+ rn,
1321
+ rm,
1322
+ ref shiftop,
1323
+ } => {
1324
+ let op = op_name(alu_op);
1325
+ let rd = pretty_print_ireg(rd.to_reg(), size);
1326
+ let rn = pretty_print_ireg(rn, size);
1327
+ let rm = pretty_print_ireg(rm, size);
1328
+ let shiftop = shiftop.pretty_print(0);
1329
+ format!("{op} {rd}, {rn}, {rm}, {shiftop}")
1330
+ }
1331
+ &Inst::AluRRRExtend {
1332
+ alu_op,
1333
+ size,
1334
+ rd,
1335
+ rn,
1336
+ rm,
1337
+ ref extendop,
1338
+ } => {
1339
+ let op = op_name(alu_op);
1340
+ let rd = pretty_print_ireg(rd.to_reg(), size);
1341
+ let rn = pretty_print_ireg(rn, size);
1342
+ let rm = pretty_print_ireg(rm, size);
1343
+ let extendop = extendop.pretty_print(0);
1344
+ format!("{op} {rd}, {rn}, {rm}, {extendop}")
1345
+ }
1346
+ &Inst::BitRR { op, size, rd, rn } => {
1347
+ let op = op.op_str();
1348
+ let rd = pretty_print_ireg(rd.to_reg(), size);
1349
+ let rn = pretty_print_ireg(rn, size);
1350
+ format!("{op} {rd}, {rn}")
1351
+ }
1352
+ &Inst::ULoad8 { rd, ref mem, .. }
1353
+ | &Inst::SLoad8 { rd, ref mem, .. }
1354
+ | &Inst::ULoad16 { rd, ref mem, .. }
1355
+ | &Inst::SLoad16 { rd, ref mem, .. }
1356
+ | &Inst::ULoad32 { rd, ref mem, .. }
1357
+ | &Inst::SLoad32 { rd, ref mem, .. }
1358
+ | &Inst::ULoad64 { rd, ref mem, .. } => {
1359
+ let is_unscaled = match &mem {
1360
+ &AMode::Unscaled { .. } => true,
1361
+ _ => false,
1362
+ };
1363
+ let (op, size) = match (self, is_unscaled) {
1364
+ (&Inst::ULoad8 { .. }, false) => ("ldrb", OperandSize::Size32),
1365
+ (&Inst::ULoad8 { .. }, true) => ("ldurb", OperandSize::Size32),
1366
+ (&Inst::SLoad8 { .. }, false) => ("ldrsb", OperandSize::Size64),
1367
+ (&Inst::SLoad8 { .. }, true) => ("ldursb", OperandSize::Size64),
1368
+ (&Inst::ULoad16 { .. }, false) => ("ldrh", OperandSize::Size32),
1369
+ (&Inst::ULoad16 { .. }, true) => ("ldurh", OperandSize::Size32),
1370
+ (&Inst::SLoad16 { .. }, false) => ("ldrsh", OperandSize::Size64),
1371
+ (&Inst::SLoad16 { .. }, true) => ("ldursh", OperandSize::Size64),
1372
+ (&Inst::ULoad32 { .. }, false) => ("ldr", OperandSize::Size32),
1373
+ (&Inst::ULoad32 { .. }, true) => ("ldur", OperandSize::Size32),
1374
+ (&Inst::SLoad32 { .. }, false) => ("ldrsw", OperandSize::Size64),
1375
+ (&Inst::SLoad32 { .. }, true) => ("ldursw", OperandSize::Size64),
1376
+ (&Inst::ULoad64 { .. }, false) => ("ldr", OperandSize::Size64),
1377
+ (&Inst::ULoad64 { .. }, true) => ("ldur", OperandSize::Size64),
1378
+ _ => unreachable!(),
1379
+ };
1380
+
1381
+ let rd = pretty_print_ireg(rd.to_reg(), size);
1382
+ let mem = mem.clone();
1383
+ let access_ty = self.mem_type().unwrap();
1384
+ let (mem_str, mem) = mem_finalize_for_show(&mem, access_ty, state);
1385
+
1386
+ format!("{mem_str}{op} {rd}, {mem}")
1387
+ }
1388
+ &Inst::Store8 { rd, ref mem, .. }
1389
+ | &Inst::Store16 { rd, ref mem, .. }
1390
+ | &Inst::Store32 { rd, ref mem, .. }
1391
+ | &Inst::Store64 { rd, ref mem, .. } => {
1392
+ let is_unscaled = match &mem {
1393
+ &AMode::Unscaled { .. } => true,
1394
+ _ => false,
1395
+ };
1396
+ let (op, size) = match (self, is_unscaled) {
1397
+ (&Inst::Store8 { .. }, false) => ("strb", OperandSize::Size32),
1398
+ (&Inst::Store8 { .. }, true) => ("sturb", OperandSize::Size32),
1399
+ (&Inst::Store16 { .. }, false) => ("strh", OperandSize::Size32),
1400
+ (&Inst::Store16 { .. }, true) => ("sturh", OperandSize::Size32),
1401
+ (&Inst::Store32 { .. }, false) => ("str", OperandSize::Size32),
1402
+ (&Inst::Store32 { .. }, true) => ("stur", OperandSize::Size32),
1403
+ (&Inst::Store64 { .. }, false) => ("str", OperandSize::Size64),
1404
+ (&Inst::Store64 { .. }, true) => ("stur", OperandSize::Size64),
1405
+ _ => unreachable!(),
1406
+ };
1407
+
1408
+ let rd = pretty_print_ireg(rd, size);
1409
+ let mem = mem.clone();
1410
+ let access_ty = self.mem_type().unwrap();
1411
+ let (mem_str, mem) = mem_finalize_for_show(&mem, access_ty, state);
1412
+
1413
+ format!("{mem_str}{op} {rd}, {mem}")
1414
+ }
1415
+ &Inst::StoreP64 {
1416
+ rt, rt2, ref mem, ..
1417
+ } => {
1418
+ let rt = pretty_print_ireg(rt, OperandSize::Size64);
1419
+ let rt2 = pretty_print_ireg(rt2, OperandSize::Size64);
1420
+ let mem = mem.clone();
1421
+ let mem = mem.pretty_print_default();
1422
+ format!("stp {rt}, {rt2}, {mem}")
1423
+ }
1424
+ &Inst::LoadP64 {
1425
+ rt, rt2, ref mem, ..
1426
+ } => {
1427
+ let rt = pretty_print_ireg(rt.to_reg(), OperandSize::Size64);
1428
+ let rt2 = pretty_print_ireg(rt2.to_reg(), OperandSize::Size64);
1429
+ let mem = mem.clone();
1430
+ let mem = mem.pretty_print_default();
1431
+ format!("ldp {rt}, {rt2}, {mem}")
1432
+ }
1433
+ &Inst::Mov { size, rd, rm } => {
1434
+ let rd = pretty_print_ireg(rd.to_reg(), size);
1435
+ let rm = pretty_print_ireg(rm, size);
1436
+ format!("mov {rd}, {rm}")
1437
+ }
1438
+ &Inst::MovFromPReg { rd, rm } => {
1439
+ let rd = pretty_print_ireg(rd.to_reg(), OperandSize::Size64);
1440
+ let rm = show_ireg_sized(rm.into(), OperandSize::Size64);
1441
+ format!("mov {rd}, {rm}")
1442
+ }
1443
+ &Inst::MovToPReg { rd, rm } => {
1444
+ let rd = show_ireg_sized(rd.into(), OperandSize::Size64);
1445
+ let rm = pretty_print_ireg(rm, OperandSize::Size64);
1446
+ format!("mov {rd}, {rm}")
1447
+ }
1448
+ &Inst::MovWide {
1449
+ op,
1450
+ rd,
1451
+ ref imm,
1452
+ size,
1453
+ } => {
1454
+ let op_str = match op {
1455
+ MoveWideOp::MovZ => "movz",
1456
+ MoveWideOp::MovN => "movn",
1457
+ };
1458
+ let rd = pretty_print_ireg(rd.to_reg(), size);
1459
+ let imm = imm.pretty_print(0);
1460
+ format!("{op_str} {rd}, {imm}")
1461
+ }
1462
+ &Inst::MovK {
1463
+ rd,
1464
+ rn,
1465
+ ref imm,
1466
+ size,
1467
+ } => {
1468
+ let rn = pretty_print_ireg(rn, size);
1469
+ let rd = pretty_print_ireg(rd.to_reg(), size);
1470
+ let imm = imm.pretty_print(0);
1471
+ format!("movk {rd}, {rn}, {imm}")
1472
+ }
1473
+ &Inst::CSel { rd, rn, rm, cond } => {
1474
+ let rd = pretty_print_ireg(rd.to_reg(), OperandSize::Size64);
1475
+ let rn = pretty_print_ireg(rn, OperandSize::Size64);
1476
+ let rm = pretty_print_ireg(rm, OperandSize::Size64);
1477
+ let cond = cond.pretty_print(0);
1478
+ format!("csel {rd}, {rn}, {rm}, {cond}")
1479
+ }
1480
+ &Inst::CSNeg { rd, rn, rm, cond } => {
1481
+ let rd = pretty_print_ireg(rd.to_reg(), OperandSize::Size64);
1482
+ let rn = pretty_print_ireg(rn, OperandSize::Size64);
1483
+ let rm = pretty_print_ireg(rm, OperandSize::Size64);
1484
+ let cond = cond.pretty_print(0);
1485
+ format!("csneg {rd}, {rn}, {rm}, {cond}")
1486
+ }
1487
+ &Inst::CSet { rd, cond } => {
1488
+ let rd = pretty_print_ireg(rd.to_reg(), OperandSize::Size64);
1489
+ let cond = cond.pretty_print(0);
1490
+ format!("cset {rd}, {cond}")
1491
+ }
1492
+ &Inst::CSetm { rd, cond } => {
1493
+ let rd = pretty_print_ireg(rd.to_reg(), OperandSize::Size64);
1494
+ let cond = cond.pretty_print(0);
1495
+ format!("csetm {rd}, {cond}")
1496
+ }
1497
+ &Inst::CCmp {
1498
+ size,
1499
+ rn,
1500
+ rm,
1501
+ nzcv,
1502
+ cond,
1503
+ } => {
1504
+ let rn = pretty_print_ireg(rn, size);
1505
+ let rm = pretty_print_ireg(rm, size);
1506
+ let nzcv = nzcv.pretty_print(0);
1507
+ let cond = cond.pretty_print(0);
1508
+ format!("ccmp {rn}, {rm}, {nzcv}, {cond}")
1509
+ }
1510
+ &Inst::CCmpImm {
1511
+ size,
1512
+ rn,
1513
+ imm,
1514
+ nzcv,
1515
+ cond,
1516
+ } => {
1517
+ let rn = pretty_print_ireg(rn, size);
1518
+ let imm = imm.pretty_print(0);
1519
+ let nzcv = nzcv.pretty_print(0);
1520
+ let cond = cond.pretty_print(0);
1521
+ format!("ccmp {rn}, {imm}, {nzcv}, {cond}")
1522
+ }
1523
+ &Inst::AtomicRMW {
1524
+ rs, rt, rn, ty, op, ..
1525
+ } => {
1526
+ let op = match op {
1527
+ AtomicRMWOp::Add => "ldaddal",
1528
+ AtomicRMWOp::Clr => "ldclral",
1529
+ AtomicRMWOp::Eor => "ldeoral",
1530
+ AtomicRMWOp::Set => "ldsetal",
1531
+ AtomicRMWOp::Smax => "ldsmaxal",
1532
+ AtomicRMWOp::Umax => "ldumaxal",
1533
+ AtomicRMWOp::Smin => "ldsminal",
1534
+ AtomicRMWOp::Umin => "lduminal",
1535
+ AtomicRMWOp::Swp => "swpal",
1536
+ };
1537
+
1538
+ let size = OperandSize::from_ty(ty);
1539
+ let rs = pretty_print_ireg(rs, size);
1540
+ let rt = pretty_print_ireg(rt.to_reg(), size);
1541
+ let rn = pretty_print_ireg(rn, OperandSize::Size64);
1542
+
1543
+ let ty_suffix = match ty {
1544
+ I8 => "b",
1545
+ I16 => "h",
1546
+ _ => "",
1547
+ };
1548
+ format!("{op}{ty_suffix} {rs}, {rt}, [{rn}]")
1549
+ }
1550
+ &Inst::AtomicRMWLoop {
1551
+ ty,
1552
+ op,
1553
+ addr,
1554
+ operand,
1555
+ oldval,
1556
+ scratch1,
1557
+ scratch2,
1558
+ ..
1559
+ } => {
1560
+ let op = match op {
1561
+ AtomicRMWLoopOp::Add => "add",
1562
+ AtomicRMWLoopOp::Sub => "sub",
1563
+ AtomicRMWLoopOp::Eor => "eor",
1564
+ AtomicRMWLoopOp::Orr => "orr",
1565
+ AtomicRMWLoopOp::And => "and",
1566
+ AtomicRMWLoopOp::Nand => "nand",
1567
+ AtomicRMWLoopOp::Smin => "smin",
1568
+ AtomicRMWLoopOp::Smax => "smax",
1569
+ AtomicRMWLoopOp::Umin => "umin",
1570
+ AtomicRMWLoopOp::Umax => "umax",
1571
+ AtomicRMWLoopOp::Xchg => "xchg",
1572
+ };
1573
+ let addr = pretty_print_ireg(addr, OperandSize::Size64);
1574
+ let operand = pretty_print_ireg(operand, OperandSize::Size64);
1575
+ let oldval = pretty_print_ireg(oldval.to_reg(), OperandSize::Size64);
1576
+ let scratch1 = pretty_print_ireg(scratch1.to_reg(), OperandSize::Size64);
1577
+ let scratch2 = pretty_print_ireg(scratch2.to_reg(), OperandSize::Size64);
1578
+ format!(
1579
+ "atomic_rmw_loop_{}_{} addr={} operand={} oldval={} scratch1={} scratch2={}",
1580
+ op,
1581
+ ty.bits(),
1582
+ addr,
1583
+ operand,
1584
+ oldval,
1585
+ scratch1,
1586
+ scratch2,
1587
+ )
1588
+ }
1589
+ &Inst::AtomicCAS {
1590
+ rd, rs, rt, rn, ty, ..
1591
+ } => {
1592
+ let op = match ty {
1593
+ I8 => "casalb",
1594
+ I16 => "casalh",
1595
+ I32 | I64 => "casal",
1596
+ _ => panic!("Unsupported type: {ty}"),
1597
+ };
1598
+ let size = OperandSize::from_ty(ty);
1599
+ let rd = pretty_print_ireg(rd.to_reg(), size);
1600
+ let rs = pretty_print_ireg(rs, size);
1601
+ let rt = pretty_print_ireg(rt, size);
1602
+ let rn = pretty_print_ireg(rn, OperandSize::Size64);
1603
+
1604
+ format!("{op} {rd}, {rs}, {rt}, [{rn}]")
1605
+ }
1606
+ &Inst::AtomicCASLoop {
1607
+ ty,
1608
+ addr,
1609
+ expected,
1610
+ replacement,
1611
+ oldval,
1612
+ scratch,
1613
+ ..
1614
+ } => {
1615
+ let addr = pretty_print_ireg(addr, OperandSize::Size64);
1616
+ let expected = pretty_print_ireg(expected, OperandSize::Size64);
1617
+ let replacement = pretty_print_ireg(replacement, OperandSize::Size64);
1618
+ let oldval = pretty_print_ireg(oldval.to_reg(), OperandSize::Size64);
1619
+ let scratch = pretty_print_ireg(scratch.to_reg(), OperandSize::Size64);
1620
+ format!(
1621
+ "atomic_cas_loop_{} addr={}, expect={}, replacement={}, oldval={}, scratch={}",
1622
+ ty.bits(),
1623
+ addr,
1624
+ expected,
1625
+ replacement,
1626
+ oldval,
1627
+ scratch,
1628
+ )
1629
+ }
1630
+ &Inst::LoadAcquire {
1631
+ access_ty, rt, rn, ..
1632
+ } => {
1633
+ let (op, ty) = match access_ty {
1634
+ I8 => ("ldarb", I32),
1635
+ I16 => ("ldarh", I32),
1636
+ I32 => ("ldar", I32),
1637
+ I64 => ("ldar", I64),
1638
+ _ => panic!("Unsupported type: {access_ty}"),
1639
+ };
1640
+ let size = OperandSize::from_ty(ty);
1641
+ let rn = pretty_print_ireg(rn, OperandSize::Size64);
1642
+ let rt = pretty_print_ireg(rt.to_reg(), size);
1643
+ format!("{op} {rt}, [{rn}]")
1644
+ }
1645
+ &Inst::StoreRelease {
1646
+ access_ty, rt, rn, ..
1647
+ } => {
1648
+ let (op, ty) = match access_ty {
1649
+ I8 => ("stlrb", I32),
1650
+ I16 => ("stlrh", I32),
1651
+ I32 => ("stlr", I32),
1652
+ I64 => ("stlr", I64),
1653
+ _ => panic!("Unsupported type: {access_ty}"),
1654
+ };
1655
+ let size = OperandSize::from_ty(ty);
1656
+ let rn = pretty_print_ireg(rn, OperandSize::Size64);
1657
+ let rt = pretty_print_ireg(rt, size);
1658
+ format!("{op} {rt}, [{rn}]")
1659
+ }
1660
+ &Inst::Fence {} => {
1661
+ format!("dmb ish")
1662
+ }
1663
+ &Inst::Csdb {} => {
1664
+ format!("csdb")
1665
+ }
1666
+ &Inst::FpuMove32 { rd, rn } => {
1667
+ let rd = pretty_print_vreg_scalar(rd.to_reg(), ScalarSize::Size32);
1668
+ let rn = pretty_print_vreg_scalar(rn, ScalarSize::Size32);
1669
+ format!("fmov {rd}, {rn}")
1670
+ }
1671
+ &Inst::FpuMove64 { rd, rn } => {
1672
+ let rd = pretty_print_vreg_scalar(rd.to_reg(), ScalarSize::Size64);
1673
+ let rn = pretty_print_vreg_scalar(rn, ScalarSize::Size64);
1674
+ format!("fmov {rd}, {rn}")
1675
+ }
1676
+ &Inst::FpuMove128 { rd, rn } => {
1677
+ let rd = pretty_print_reg(rd.to_reg());
1678
+ let rn = pretty_print_reg(rn);
1679
+ format!("mov {rd}.16b, {rn}.16b")
1680
+ }
1681
+ &Inst::FpuMoveFromVec { rd, rn, idx, size } => {
1682
+ let rd = pretty_print_vreg_scalar(rd.to_reg(), size.lane_size());
1683
+ let rn = pretty_print_vreg_element(rn, idx as usize, size.lane_size());
1684
+ format!("mov {rd}, {rn}")
1685
+ }
1686
+ &Inst::FpuExtend { rd, rn, size } => {
1687
+ let rd = pretty_print_vreg_scalar(rd.to_reg(), size);
1688
+ let rn = pretty_print_vreg_scalar(rn, size);
1689
+ format!("fmov {rd}, {rn}")
1690
+ }
1691
+ &Inst::FpuRR {
1692
+ fpu_op,
1693
+ size,
1694
+ rd,
1695
+ rn,
1696
+ } => {
1697
+ let op = match fpu_op {
1698
+ FPUOp1::Abs => "fabs",
1699
+ FPUOp1::Neg => "fneg",
1700
+ FPUOp1::Sqrt => "fsqrt",
1701
+ FPUOp1::Cvt32To64 | FPUOp1::Cvt64To32 => "fcvt",
1702
+ };
1703
+ let dst_size = match fpu_op {
1704
+ FPUOp1::Cvt32To64 => ScalarSize::Size64,
1705
+ FPUOp1::Cvt64To32 => ScalarSize::Size32,
1706
+ _ => size,
1707
+ };
1708
+ let rd = pretty_print_vreg_scalar(rd.to_reg(), dst_size);
1709
+ let rn = pretty_print_vreg_scalar(rn, size);
1710
+ format!("{op} {rd}, {rn}")
1711
+ }
1712
+ &Inst::FpuRRR {
1713
+ fpu_op,
1714
+ size,
1715
+ rd,
1716
+ rn,
1717
+ rm,
1718
+ } => {
1719
+ let op = match fpu_op {
1720
+ FPUOp2::Add => "fadd",
1721
+ FPUOp2::Sub => "fsub",
1722
+ FPUOp2::Mul => "fmul",
1723
+ FPUOp2::Div => "fdiv",
1724
+ FPUOp2::Max => "fmax",
1725
+ FPUOp2::Min => "fmin",
1726
+ };
1727
+ let rd = pretty_print_vreg_scalar(rd.to_reg(), size);
1728
+ let rn = pretty_print_vreg_scalar(rn, size);
1729
+ let rm = pretty_print_vreg_scalar(rm, size);
1730
+ format!("{op} {rd}, {rn}, {rm}")
1731
+ }
1732
+ &Inst::FpuRRI { fpu_op, rd, rn } => {
1733
+ let (op, imm, vector) = match fpu_op {
1734
+ FPUOpRI::UShr32(imm) => ("ushr", imm.pretty_print(0), true),
1735
+ FPUOpRI::UShr64(imm) => ("ushr", imm.pretty_print(0), false),
1736
+ };
1737
+
1738
+ let (rd, rn) = if vector {
1739
+ (
1740
+ pretty_print_vreg_vector(rd.to_reg(), VectorSize::Size32x2),
1741
+ pretty_print_vreg_vector(rn, VectorSize::Size32x2),
1742
+ )
1743
+ } else {
1744
+ (
1745
+ pretty_print_vreg_scalar(rd.to_reg(), ScalarSize::Size64),
1746
+ pretty_print_vreg_scalar(rn, ScalarSize::Size64),
1747
+ )
1748
+ };
1749
+ format!("{op} {rd}, {rn}, {imm}")
1750
+ }
1751
+ &Inst::FpuRRIMod { fpu_op, rd, ri, rn } => {
1752
+ let (op, imm, vector) = match fpu_op {
1753
+ FPUOpRIMod::Sli32(imm) => ("sli", imm.pretty_print(0), true),
1754
+ FPUOpRIMod::Sli64(imm) => ("sli", imm.pretty_print(0), false),
1755
+ };
1756
+
1757
+ let (rd, ri, rn) = if vector {
1758
+ (
1759
+ pretty_print_vreg_vector(rd.to_reg(), VectorSize::Size32x2),
1760
+ pretty_print_vreg_vector(ri, VectorSize::Size32x2),
1761
+ pretty_print_vreg_vector(rn, VectorSize::Size32x2),
1762
+ )
1763
+ } else {
1764
+ (
1765
+ pretty_print_vreg_scalar(rd.to_reg(), ScalarSize::Size64),
1766
+ pretty_print_vreg_scalar(ri, ScalarSize::Size64),
1767
+ pretty_print_vreg_scalar(rn, ScalarSize::Size64),
1768
+ )
1769
+ };
1770
+ format!("{op} {rd}, {ri}, {rn}, {imm}")
1771
+ }
1772
+ &Inst::FpuRRRR {
1773
+ fpu_op,
1774
+ size,
1775
+ rd,
1776
+ rn,
1777
+ rm,
1778
+ ra,
1779
+ } => {
1780
+ let op = match fpu_op {
1781
+ FPUOp3::MAdd => "fmadd",
1782
+ FPUOp3::MSub => "fmsub",
1783
+ FPUOp3::NMAdd => "fnmadd",
1784
+ FPUOp3::NMSub => "fnmsub",
1785
+ };
1786
+ let rd = pretty_print_vreg_scalar(rd.to_reg(), size);
1787
+ let rn = pretty_print_vreg_scalar(rn, size);
1788
+ let rm = pretty_print_vreg_scalar(rm, size);
1789
+ let ra = pretty_print_vreg_scalar(ra, size);
1790
+ format!("{op} {rd}, {rn}, {rm}, {ra}")
1791
+ }
1792
+ &Inst::FpuCmp { size, rn, rm } => {
1793
+ let rn = pretty_print_vreg_scalar(rn, size);
1794
+ let rm = pretty_print_vreg_scalar(rm, size);
1795
+ format!("fcmp {rn}, {rm}")
1796
+ }
1797
+ &Inst::FpuLoad16 { rd, ref mem, .. } => {
1798
+ let rd = pretty_print_vreg_scalar(rd.to_reg(), ScalarSize::Size16);
1799
+ let mem = mem.clone();
1800
+ let access_ty = self.mem_type().unwrap();
1801
+ let (mem_str, mem) = mem_finalize_for_show(&mem, access_ty, state);
1802
+ format!("{mem_str}ldr {rd}, {mem}")
1803
+ }
1804
+ &Inst::FpuLoad32 { rd, ref mem, .. } => {
1805
+ let rd = pretty_print_vreg_scalar(rd.to_reg(), ScalarSize::Size32);
1806
+ let mem = mem.clone();
1807
+ let access_ty = self.mem_type().unwrap();
1808
+ let (mem_str, mem) = mem_finalize_for_show(&mem, access_ty, state);
1809
+ format!("{mem_str}ldr {rd}, {mem}")
1810
+ }
1811
+ &Inst::FpuLoad64 { rd, ref mem, .. } => {
1812
+ let rd = pretty_print_vreg_scalar(rd.to_reg(), ScalarSize::Size64);
1813
+ let mem = mem.clone();
1814
+ let access_ty = self.mem_type().unwrap();
1815
+ let (mem_str, mem) = mem_finalize_for_show(&mem, access_ty, state);
1816
+ format!("{mem_str}ldr {rd}, {mem}")
1817
+ }
1818
+ &Inst::FpuLoad128 { rd, ref mem, .. } => {
1819
+ let rd = pretty_print_reg(rd.to_reg());
1820
+ let rd = "q".to_string() + &rd[1..];
1821
+ let mem = mem.clone();
1822
+ let access_ty = self.mem_type().unwrap();
1823
+ let (mem_str, mem) = mem_finalize_for_show(&mem, access_ty, state);
1824
+ format!("{mem_str}ldr {rd}, {mem}")
1825
+ }
1826
+ &Inst::FpuStore16 { rd, ref mem, .. } => {
1827
+ let rd = pretty_print_vreg_scalar(rd, ScalarSize::Size16);
1828
+ let mem = mem.clone();
1829
+ let access_ty = self.mem_type().unwrap();
1830
+ let (mem_str, mem) = mem_finalize_for_show(&mem, access_ty, state);
1831
+ format!("{mem_str}str {rd}, {mem}")
1832
+ }
1833
+ &Inst::FpuStore32 { rd, ref mem, .. } => {
1834
+ let rd = pretty_print_vreg_scalar(rd, ScalarSize::Size32);
1835
+ let mem = mem.clone();
1836
+ let access_ty = self.mem_type().unwrap();
1837
+ let (mem_str, mem) = mem_finalize_for_show(&mem, access_ty, state);
1838
+ format!("{mem_str}str {rd}, {mem}")
1839
+ }
1840
+ &Inst::FpuStore64 { rd, ref mem, .. } => {
1841
+ let rd = pretty_print_vreg_scalar(rd, ScalarSize::Size64);
1842
+ let mem = mem.clone();
1843
+ let access_ty = self.mem_type().unwrap();
1844
+ let (mem_str, mem) = mem_finalize_for_show(&mem, access_ty, state);
1845
+ format!("{mem_str}str {rd}, {mem}")
1846
+ }
1847
+ &Inst::FpuStore128 { rd, ref mem, .. } => {
1848
+ let rd = pretty_print_reg(rd);
1849
+ let rd = "q".to_string() + &rd[1..];
1850
+ let mem = mem.clone();
1851
+ let access_ty = self.mem_type().unwrap();
1852
+ let (mem_str, mem) = mem_finalize_for_show(&mem, access_ty, state);
1853
+ format!("{mem_str}str {rd}, {mem}")
1854
+ }
1855
+ &Inst::FpuLoadP64 {
1856
+ rt, rt2, ref mem, ..
1857
+ } => {
1858
+ let rt = pretty_print_vreg_scalar(rt.to_reg(), ScalarSize::Size64);
1859
+ let rt2 = pretty_print_vreg_scalar(rt2.to_reg(), ScalarSize::Size64);
1860
+ let mem = mem.clone();
1861
+ let mem = mem.pretty_print_default();
1862
+
1863
+ format!("ldp {rt}, {rt2}, {mem}")
1864
+ }
1865
+ &Inst::FpuStoreP64 {
1866
+ rt, rt2, ref mem, ..
1867
+ } => {
1868
+ let rt = pretty_print_vreg_scalar(rt, ScalarSize::Size64);
1869
+ let rt2 = pretty_print_vreg_scalar(rt2, ScalarSize::Size64);
1870
+ let mem = mem.clone();
1871
+ let mem = mem.pretty_print_default();
1872
+
1873
+ format!("stp {rt}, {rt2}, {mem}")
1874
+ }
1875
+ &Inst::FpuLoadP128 {
1876
+ rt, rt2, ref mem, ..
1877
+ } => {
1878
+ let rt = pretty_print_vreg_scalar(rt.to_reg(), ScalarSize::Size128);
1879
+ let rt2 = pretty_print_vreg_scalar(rt2.to_reg(), ScalarSize::Size128);
1880
+ let mem = mem.clone();
1881
+ let mem = mem.pretty_print_default();
1882
+
1883
+ format!("ldp {rt}, {rt2}, {mem}")
1884
+ }
1885
+ &Inst::FpuStoreP128 {
1886
+ rt, rt2, ref mem, ..
1887
+ } => {
1888
+ let rt = pretty_print_vreg_scalar(rt, ScalarSize::Size128);
1889
+ let rt2 = pretty_print_vreg_scalar(rt2, ScalarSize::Size128);
1890
+ let mem = mem.clone();
1891
+ let mem = mem.pretty_print_default();
1892
+
1893
+ format!("stp {rt}, {rt2}, {mem}")
1894
+ }
1895
+ &Inst::FpuToInt { op, rd, rn } => {
1896
+ let (op, sizesrc, sizedest) = match op {
1897
+ FpuToIntOp::F32ToI32 => ("fcvtzs", ScalarSize::Size32, OperandSize::Size32),
1898
+ FpuToIntOp::F32ToU32 => ("fcvtzu", ScalarSize::Size32, OperandSize::Size32),
1899
+ FpuToIntOp::F32ToI64 => ("fcvtzs", ScalarSize::Size32, OperandSize::Size64),
1900
+ FpuToIntOp::F32ToU64 => ("fcvtzu", ScalarSize::Size32, OperandSize::Size64),
1901
+ FpuToIntOp::F64ToI32 => ("fcvtzs", ScalarSize::Size64, OperandSize::Size32),
1902
+ FpuToIntOp::F64ToU32 => ("fcvtzu", ScalarSize::Size64, OperandSize::Size32),
1903
+ FpuToIntOp::F64ToI64 => ("fcvtzs", ScalarSize::Size64, OperandSize::Size64),
1904
+ FpuToIntOp::F64ToU64 => ("fcvtzu", ScalarSize::Size64, OperandSize::Size64),
1905
+ };
1906
+ let rd = pretty_print_ireg(rd.to_reg(), sizedest);
1907
+ let rn = pretty_print_vreg_scalar(rn, sizesrc);
1908
+ format!("{op} {rd}, {rn}")
1909
+ }
1910
+ &Inst::IntToFpu { op, rd, rn } => {
1911
+ let (op, sizesrc, sizedest) = match op {
1912
+ IntToFpuOp::I32ToF32 => ("scvtf", OperandSize::Size32, ScalarSize::Size32),
1913
+ IntToFpuOp::U32ToF32 => ("ucvtf", OperandSize::Size32, ScalarSize::Size32),
1914
+ IntToFpuOp::I64ToF32 => ("scvtf", OperandSize::Size64, ScalarSize::Size32),
1915
+ IntToFpuOp::U64ToF32 => ("ucvtf", OperandSize::Size64, ScalarSize::Size32),
1916
+ IntToFpuOp::I32ToF64 => ("scvtf", OperandSize::Size32, ScalarSize::Size64),
1917
+ IntToFpuOp::U32ToF64 => ("ucvtf", OperandSize::Size32, ScalarSize::Size64),
1918
+ IntToFpuOp::I64ToF64 => ("scvtf", OperandSize::Size64, ScalarSize::Size64),
1919
+ IntToFpuOp::U64ToF64 => ("ucvtf", OperandSize::Size64, ScalarSize::Size64),
1920
+ };
1921
+ let rd = pretty_print_vreg_scalar(rd.to_reg(), sizedest);
1922
+ let rn = pretty_print_ireg(rn, sizesrc);
1923
+ format!("{op} {rd}, {rn}")
1924
+ }
1925
+ &Inst::FpuCSel16 { rd, rn, rm, cond } => {
1926
+ let rd = pretty_print_vreg_scalar(rd.to_reg(), ScalarSize::Size16);
1927
+ let rn = pretty_print_vreg_scalar(rn, ScalarSize::Size16);
1928
+ let rm = pretty_print_vreg_scalar(rm, ScalarSize::Size16);
1929
+ let cond = cond.pretty_print(0);
1930
+ format!("fcsel {rd}, {rn}, {rm}, {cond}")
1931
+ }
1932
+ &Inst::FpuCSel32 { rd, rn, rm, cond } => {
1933
+ let rd = pretty_print_vreg_scalar(rd.to_reg(), ScalarSize::Size32);
1934
+ let rn = pretty_print_vreg_scalar(rn, ScalarSize::Size32);
1935
+ let rm = pretty_print_vreg_scalar(rm, ScalarSize::Size32);
1936
+ let cond = cond.pretty_print(0);
1937
+ format!("fcsel {rd}, {rn}, {rm}, {cond}")
1938
+ }
1939
+ &Inst::FpuCSel64 { rd, rn, rm, cond } => {
1940
+ let rd = pretty_print_vreg_scalar(rd.to_reg(), ScalarSize::Size64);
1941
+ let rn = pretty_print_vreg_scalar(rn, ScalarSize::Size64);
1942
+ let rm = pretty_print_vreg_scalar(rm, ScalarSize::Size64);
1943
+ let cond = cond.pretty_print(0);
1944
+ format!("fcsel {rd}, {rn}, {rm}, {cond}")
1945
+ }
1946
+ &Inst::FpuRound { op, rd, rn } => {
1947
+ let (inst, size) = match op {
1948
+ FpuRoundMode::Minus32 => ("frintm", ScalarSize::Size32),
1949
+ FpuRoundMode::Minus64 => ("frintm", ScalarSize::Size64),
1950
+ FpuRoundMode::Plus32 => ("frintp", ScalarSize::Size32),
1951
+ FpuRoundMode::Plus64 => ("frintp", ScalarSize::Size64),
1952
+ FpuRoundMode::Zero32 => ("frintz", ScalarSize::Size32),
1953
+ FpuRoundMode::Zero64 => ("frintz", ScalarSize::Size64),
1954
+ FpuRoundMode::Nearest32 => ("frintn", ScalarSize::Size32),
1955
+ FpuRoundMode::Nearest64 => ("frintn", ScalarSize::Size64),
1956
+ };
1957
+ let rd = pretty_print_vreg_scalar(rd.to_reg(), size);
1958
+ let rn = pretty_print_vreg_scalar(rn, size);
1959
+ format!("{inst} {rd}, {rn}")
1960
+ }
1961
+ &Inst::MovToFpu { rd, rn, size } => {
1962
+ let operand_size = size.operand_size();
1963
+ let rd = pretty_print_vreg_scalar(rd.to_reg(), size);
1964
+ let rn = pretty_print_ireg(rn, operand_size);
1965
+ format!("fmov {rd}, {rn}")
1966
+ }
1967
+ &Inst::FpuMoveFPImm { rd, imm, size } => {
1968
+ let imm = imm.pretty_print(0);
1969
+ let rd = pretty_print_vreg_scalar(rd.to_reg(), size);
1970
+
1971
+ format!("fmov {rd}, {imm}")
1972
+ }
1973
+ &Inst::MovToVec {
1974
+ rd,
1975
+ ri,
1976
+ rn,
1977
+ idx,
1978
+ size,
1979
+ } => {
1980
+ let rd = pretty_print_vreg_element(rd.to_reg(), idx as usize, size.lane_size());
1981
+ let ri = pretty_print_vreg_element(ri, idx as usize, size.lane_size());
1982
+ let rn = pretty_print_ireg(rn, size.operand_size());
1983
+ format!("mov {rd}, {ri}, {rn}")
1984
+ }
1985
+ &Inst::MovFromVec { rd, rn, idx, size } => {
1986
+ let op = match size {
1987
+ ScalarSize::Size8 => "umov",
1988
+ ScalarSize::Size16 => "umov",
1989
+ ScalarSize::Size32 => "mov",
1990
+ ScalarSize::Size64 => "mov",
1991
+ _ => unimplemented!(),
1992
+ };
1993
+ let rd = pretty_print_ireg(rd.to_reg(), size.operand_size());
1994
+ let rn = pretty_print_vreg_element(rn, idx as usize, size);
1995
+ format!("{op} {rd}, {rn}")
1996
+ }
1997
+ &Inst::MovFromVecSigned {
1998
+ rd,
1999
+ rn,
2000
+ idx,
2001
+ size,
2002
+ scalar_size,
2003
+ } => {
2004
+ let rd = pretty_print_ireg(rd.to_reg(), scalar_size);
2005
+ let rn = pretty_print_vreg_element(rn, idx as usize, size.lane_size());
2006
+ format!("smov {rd}, {rn}")
2007
+ }
2008
+ &Inst::VecDup { rd, rn, size } => {
2009
+ let rd = pretty_print_vreg_vector(rd.to_reg(), size);
2010
+ let rn = pretty_print_ireg(rn, size.operand_size());
2011
+ format!("dup {rd}, {rn}")
2012
+ }
2013
+ &Inst::VecDupFromFpu { rd, rn, size, lane } => {
2014
+ let rd = pretty_print_vreg_vector(rd.to_reg(), size);
2015
+ let rn = pretty_print_vreg_element(rn, lane.into(), size.lane_size());
2016
+ format!("dup {rd}, {rn}")
2017
+ }
2018
+ &Inst::VecDupFPImm { rd, imm, size } => {
2019
+ let imm = imm.pretty_print(0);
2020
+ let rd = pretty_print_vreg_vector(rd.to_reg(), size);
2021
+
2022
+ format!("fmov {rd}, {imm}")
2023
+ }
2024
+ &Inst::VecDupImm {
2025
+ rd,
2026
+ imm,
2027
+ invert,
2028
+ size,
2029
+ } => {
2030
+ let imm = imm.pretty_print(0);
2031
+ let op = if invert { "mvni" } else { "movi" };
2032
+ let rd = pretty_print_vreg_vector(rd.to_reg(), size);
2033
+
2034
+ format!("{op} {rd}, {imm}")
2035
+ }
2036
+ &Inst::VecExtend {
2037
+ t,
2038
+ rd,
2039
+ rn,
2040
+ high_half,
2041
+ lane_size,
2042
+ } => {
2043
+ let vec64 = VectorSize::from_lane_size(lane_size.narrow(), false);
2044
+ let vec128 = VectorSize::from_lane_size(lane_size.narrow(), true);
2045
+ let rd_size = VectorSize::from_lane_size(lane_size, true);
2046
+ let (op, rn_size) = match (t, high_half) {
2047
+ (VecExtendOp::Sxtl, false) => ("sxtl", vec64),
2048
+ (VecExtendOp::Sxtl, true) => ("sxtl2", vec128),
2049
+ (VecExtendOp::Uxtl, false) => ("uxtl", vec64),
2050
+ (VecExtendOp::Uxtl, true) => ("uxtl2", vec128),
2051
+ };
2052
+ let rd = pretty_print_vreg_vector(rd.to_reg(), rd_size);
2053
+ let rn = pretty_print_vreg_vector(rn, rn_size);
2054
+ format!("{op} {rd}, {rn}")
2055
+ }
2056
+ &Inst::VecMovElement {
2057
+ rd,
2058
+ ri,
2059
+ rn,
2060
+ dest_idx,
2061
+ src_idx,
2062
+ size,
2063
+ } => {
2064
+ let rd =
2065
+ pretty_print_vreg_element(rd.to_reg(), dest_idx as usize, size.lane_size());
2066
+ let ri = pretty_print_vreg_element(ri, dest_idx as usize, size.lane_size());
2067
+ let rn = pretty_print_vreg_element(rn, src_idx as usize, size.lane_size());
2068
+ format!("mov {rd}, {ri}, {rn}")
2069
+ }
2070
+ &Inst::VecRRLong {
2071
+ op,
2072
+ rd,
2073
+ rn,
2074
+ high_half,
2075
+ } => {
2076
+ let (op, rd_size, size, suffix) = match (op, high_half) {
2077
+ (VecRRLongOp::Fcvtl16, false) => {
2078
+ ("fcvtl", VectorSize::Size32x4, VectorSize::Size16x4, "")
2079
+ }
2080
+ (VecRRLongOp::Fcvtl16, true) => {
2081
+ ("fcvtl2", VectorSize::Size32x4, VectorSize::Size16x8, "")
2082
+ }
2083
+ (VecRRLongOp::Fcvtl32, false) => {
2084
+ ("fcvtl", VectorSize::Size64x2, VectorSize::Size32x2, "")
2085
+ }
2086
+ (VecRRLongOp::Fcvtl32, true) => {
2087
+ ("fcvtl2", VectorSize::Size64x2, VectorSize::Size32x4, "")
2088
+ }
2089
+ (VecRRLongOp::Shll8, false) => {
2090
+ ("shll", VectorSize::Size16x8, VectorSize::Size8x8, ", #8")
2091
+ }
2092
+ (VecRRLongOp::Shll8, true) => {
2093
+ ("shll2", VectorSize::Size16x8, VectorSize::Size8x16, ", #8")
2094
+ }
2095
+ (VecRRLongOp::Shll16, false) => {
2096
+ ("shll", VectorSize::Size32x4, VectorSize::Size16x4, ", #16")
2097
+ }
2098
+ (VecRRLongOp::Shll16, true) => {
2099
+ ("shll2", VectorSize::Size32x4, VectorSize::Size16x8, ", #16")
2100
+ }
2101
+ (VecRRLongOp::Shll32, false) => {
2102
+ ("shll", VectorSize::Size64x2, VectorSize::Size32x2, ", #32")
2103
+ }
2104
+ (VecRRLongOp::Shll32, true) => {
2105
+ ("shll2", VectorSize::Size64x2, VectorSize::Size32x4, ", #32")
2106
+ }
2107
+ };
2108
+ let rd = pretty_print_vreg_vector(rd.to_reg(), rd_size);
2109
+ let rn = pretty_print_vreg_vector(rn, size);
2110
+
2111
+ format!("{op} {rd}, {rn}{suffix}")
2112
+ }
2113
+ &Inst::VecRRNarrowLow {
2114
+ op,
2115
+ rd,
2116
+ rn,
2117
+ lane_size,
2118
+ ..
2119
+ }
2120
+ | &Inst::VecRRNarrowHigh {
2121
+ op,
2122
+ rd,
2123
+ rn,
2124
+ lane_size,
2125
+ ..
2126
+ } => {
2127
+ let vec64 = VectorSize::from_lane_size(lane_size, false);
2128
+ let vec128 = VectorSize::from_lane_size(lane_size, true);
2129
+ let rn_size = VectorSize::from_lane_size(lane_size.widen(), true);
2130
+ let high_half = match self {
2131
+ &Inst::VecRRNarrowLow { .. } => false,
2132
+ &Inst::VecRRNarrowHigh { .. } => true,
2133
+ _ => unreachable!(),
2134
+ };
2135
+ let (op, rd_size) = match (op, high_half) {
2136
+ (VecRRNarrowOp::Xtn, false) => ("xtn", vec64),
2137
+ (VecRRNarrowOp::Xtn, true) => ("xtn2", vec128),
2138
+ (VecRRNarrowOp::Sqxtn, false) => ("sqxtn", vec64),
2139
+ (VecRRNarrowOp::Sqxtn, true) => ("sqxtn2", vec128),
2140
+ (VecRRNarrowOp::Sqxtun, false) => ("sqxtun", vec64),
2141
+ (VecRRNarrowOp::Sqxtun, true) => ("sqxtun2", vec128),
2142
+ (VecRRNarrowOp::Uqxtn, false) => ("uqxtn", vec64),
2143
+ (VecRRNarrowOp::Uqxtn, true) => ("uqxtn2", vec128),
2144
+ (VecRRNarrowOp::Fcvtn, false) => ("fcvtn", vec64),
2145
+ (VecRRNarrowOp::Fcvtn, true) => ("fcvtn2", vec128),
2146
+ };
2147
+ let rn = pretty_print_vreg_vector(rn, rn_size);
2148
+ let rd = pretty_print_vreg_vector(rd.to_reg(), rd_size);
2149
+ let ri = match self {
2150
+ &Inst::VecRRNarrowLow { .. } => "".to_string(),
2151
+ &Inst::VecRRNarrowHigh { ri, .. } => {
2152
+ format!("{}, ", pretty_print_vreg_vector(ri, rd_size))
2153
+ }
2154
+ _ => unreachable!(),
2155
+ };
2156
+
2157
+ format!("{op} {rd}, {ri}{rn}")
2158
+ }
2159
+ &Inst::VecRRPair { op, rd, rn } => {
2160
+ let op = match op {
2161
+ VecPairOp::Addp => "addp",
2162
+ };
2163
+ let rd = pretty_print_vreg_scalar(rd.to_reg(), ScalarSize::Size64);
2164
+ let rn = pretty_print_vreg_vector(rn, VectorSize::Size64x2);
2165
+
2166
+ format!("{op} {rd}, {rn}")
2167
+ }
2168
+ &Inst::VecRRPairLong { op, rd, rn } => {
2169
+ let (op, dest, src) = match op {
2170
+ VecRRPairLongOp::Saddlp8 => {
2171
+ ("saddlp", VectorSize::Size16x8, VectorSize::Size8x16)
2172
+ }
2173
+ VecRRPairLongOp::Saddlp16 => {
2174
+ ("saddlp", VectorSize::Size32x4, VectorSize::Size16x8)
2175
+ }
2176
+ VecRRPairLongOp::Uaddlp8 => {
2177
+ ("uaddlp", VectorSize::Size16x8, VectorSize::Size8x16)
2178
+ }
2179
+ VecRRPairLongOp::Uaddlp16 => {
2180
+ ("uaddlp", VectorSize::Size32x4, VectorSize::Size16x8)
2181
+ }
2182
+ };
2183
+ let rd = pretty_print_vreg_vector(rd.to_reg(), dest);
2184
+ let rn = pretty_print_vreg_vector(rn, src);
2185
+
2186
+ format!("{op} {rd}, {rn}")
2187
+ }
2188
+ &Inst::VecRRR {
2189
+ rd,
2190
+ rn,
2191
+ rm,
2192
+ alu_op,
2193
+ size,
2194
+ } => {
2195
+ let (op, size) = match alu_op {
2196
+ VecALUOp::Sqadd => ("sqadd", size),
2197
+ VecALUOp::Uqadd => ("uqadd", size),
2198
+ VecALUOp::Sqsub => ("sqsub", size),
2199
+ VecALUOp::Uqsub => ("uqsub", size),
2200
+ VecALUOp::Cmeq => ("cmeq", size),
2201
+ VecALUOp::Cmge => ("cmge", size),
2202
+ VecALUOp::Cmgt => ("cmgt", size),
2203
+ VecALUOp::Cmhs => ("cmhs", size),
2204
+ VecALUOp::Cmhi => ("cmhi", size),
2205
+ VecALUOp::Fcmeq => ("fcmeq", size),
2206
+ VecALUOp::Fcmgt => ("fcmgt", size),
2207
+ VecALUOp::Fcmge => ("fcmge", size),
2208
+ VecALUOp::And => ("and", VectorSize::Size8x16),
2209
+ VecALUOp::Bic => ("bic", VectorSize::Size8x16),
2210
+ VecALUOp::Orr => ("orr", VectorSize::Size8x16),
2211
+ VecALUOp::Eor => ("eor", VectorSize::Size8x16),
2212
+ VecALUOp::Umaxp => ("umaxp", size),
2213
+ VecALUOp::Add => ("add", size),
2214
+ VecALUOp::Sub => ("sub", size),
2215
+ VecALUOp::Mul => ("mul", size),
2216
+ VecALUOp::Sshl => ("sshl", size),
2217
+ VecALUOp::Ushl => ("ushl", size),
2218
+ VecALUOp::Umin => ("umin", size),
2219
+ VecALUOp::Smin => ("smin", size),
2220
+ VecALUOp::Umax => ("umax", size),
2221
+ VecALUOp::Smax => ("smax", size),
2222
+ VecALUOp::Urhadd => ("urhadd", size),
2223
+ VecALUOp::Fadd => ("fadd", size),
2224
+ VecALUOp::Fsub => ("fsub", size),
2225
+ VecALUOp::Fdiv => ("fdiv", size),
2226
+ VecALUOp::Fmax => ("fmax", size),
2227
+ VecALUOp::Fmin => ("fmin", size),
2228
+ VecALUOp::Fmul => ("fmul", size),
2229
+ VecALUOp::Addp => ("addp", size),
2230
+ VecALUOp::Zip1 => ("zip1", size),
2231
+ VecALUOp::Zip2 => ("zip2", size),
2232
+ VecALUOp::Sqrdmulh => ("sqrdmulh", size),
2233
+ VecALUOp::Uzp1 => ("uzp1", size),
2234
+ VecALUOp::Uzp2 => ("uzp2", size),
2235
+ VecALUOp::Trn1 => ("trn1", size),
2236
+ VecALUOp::Trn2 => ("trn2", size),
2237
+ };
2238
+ let rd = pretty_print_vreg_vector(rd.to_reg(), size);
2239
+ let rn = pretty_print_vreg_vector(rn, size);
2240
+ let rm = pretty_print_vreg_vector(rm, size);
2241
+ format!("{op} {rd}, {rn}, {rm}")
2242
+ }
2243
+ &Inst::VecRRRMod {
2244
+ rd,
2245
+ ri,
2246
+ rn,
2247
+ rm,
2248
+ alu_op,
2249
+ size,
2250
+ } => {
2251
+ let (op, size) = match alu_op {
2252
+ VecALUModOp::Bsl => ("bsl", VectorSize::Size8x16),
2253
+ VecALUModOp::Fmla => ("fmla", size),
2254
+ VecALUModOp::Fmls => ("fmls", size),
2255
+ };
2256
+ let rd = pretty_print_vreg_vector(rd.to_reg(), size);
2257
+ let ri = pretty_print_vreg_vector(ri, size);
2258
+ let rn = pretty_print_vreg_vector(rn, size);
2259
+ let rm = pretty_print_vreg_vector(rm, size);
2260
+ format!("{op} {rd}, {ri}, {rn}, {rm}")
2261
+ }
2262
+ &Inst::VecFmlaElem {
2263
+ rd,
2264
+ ri,
2265
+ rn,
2266
+ rm,
2267
+ alu_op,
2268
+ size,
2269
+ idx,
2270
+ } => {
2271
+ let (op, size) = match alu_op {
2272
+ VecALUModOp::Fmla => ("fmla", size),
2273
+ VecALUModOp::Fmls => ("fmls", size),
2274
+ _ => unreachable!(),
2275
+ };
2276
+ let rd = pretty_print_vreg_vector(rd.to_reg(), size);
2277
+ let ri = pretty_print_vreg_vector(ri, size);
2278
+ let rn = pretty_print_vreg_vector(rn, size);
2279
+ let rm = pretty_print_vreg_element(rm, idx.into(), size.lane_size());
2280
+ format!("{op} {rd}, {ri}, {rn}, {rm}")
2281
+ }
2282
+ &Inst::VecRRRLong {
2283
+ rd,
2284
+ rn,
2285
+ rm,
2286
+ alu_op,
2287
+ high_half,
2288
+ } => {
2289
+ let (op, dest_size, src_size) = match (alu_op, high_half) {
2290
+ (VecRRRLongOp::Smull8, false) => {
2291
+ ("smull", VectorSize::Size16x8, VectorSize::Size8x8)
2292
+ }
2293
+ (VecRRRLongOp::Smull8, true) => {
2294
+ ("smull2", VectorSize::Size16x8, VectorSize::Size8x16)
2295
+ }
2296
+ (VecRRRLongOp::Smull16, false) => {
2297
+ ("smull", VectorSize::Size32x4, VectorSize::Size16x4)
2298
+ }
2299
+ (VecRRRLongOp::Smull16, true) => {
2300
+ ("smull2", VectorSize::Size32x4, VectorSize::Size16x8)
2301
+ }
2302
+ (VecRRRLongOp::Smull32, false) => {
2303
+ ("smull", VectorSize::Size64x2, VectorSize::Size32x2)
2304
+ }
2305
+ (VecRRRLongOp::Smull32, true) => {
2306
+ ("smull2", VectorSize::Size64x2, VectorSize::Size32x4)
2307
+ }
2308
+ (VecRRRLongOp::Umull8, false) => {
2309
+ ("umull", VectorSize::Size16x8, VectorSize::Size8x8)
2310
+ }
2311
+ (VecRRRLongOp::Umull8, true) => {
2312
+ ("umull2", VectorSize::Size16x8, VectorSize::Size8x16)
2313
+ }
2314
+ (VecRRRLongOp::Umull16, false) => {
2315
+ ("umull", VectorSize::Size32x4, VectorSize::Size16x4)
2316
+ }
2317
+ (VecRRRLongOp::Umull16, true) => {
2318
+ ("umull2", VectorSize::Size32x4, VectorSize::Size16x8)
2319
+ }
2320
+ (VecRRRLongOp::Umull32, false) => {
2321
+ ("umull", VectorSize::Size64x2, VectorSize::Size32x2)
2322
+ }
2323
+ (VecRRRLongOp::Umull32, true) => {
2324
+ ("umull2", VectorSize::Size64x2, VectorSize::Size32x4)
2325
+ }
2326
+ };
2327
+ let rd = pretty_print_vreg_vector(rd.to_reg(), dest_size);
2328
+ let rn = pretty_print_vreg_vector(rn, src_size);
2329
+ let rm = pretty_print_vreg_vector(rm, src_size);
2330
+ format!("{op} {rd}, {rn}, {rm}")
2331
+ }
2332
+ &Inst::VecRRRLongMod {
2333
+ rd,
2334
+ ri,
2335
+ rn,
2336
+ rm,
2337
+ alu_op,
2338
+ high_half,
2339
+ } => {
2340
+ let (op, dest_size, src_size) = match (alu_op, high_half) {
2341
+ (VecRRRLongModOp::Umlal8, false) => {
2342
+ ("umlal", VectorSize::Size16x8, VectorSize::Size8x8)
2343
+ }
2344
+ (VecRRRLongModOp::Umlal8, true) => {
2345
+ ("umlal2", VectorSize::Size16x8, VectorSize::Size8x16)
2346
+ }
2347
+ (VecRRRLongModOp::Umlal16, false) => {
2348
+ ("umlal", VectorSize::Size32x4, VectorSize::Size16x4)
2349
+ }
2350
+ (VecRRRLongModOp::Umlal16, true) => {
2351
+ ("umlal2", VectorSize::Size32x4, VectorSize::Size16x8)
2352
+ }
2353
+ (VecRRRLongModOp::Umlal32, false) => {
2354
+ ("umlal", VectorSize::Size64x2, VectorSize::Size32x2)
2355
+ }
2356
+ (VecRRRLongModOp::Umlal32, true) => {
2357
+ ("umlal2", VectorSize::Size64x2, VectorSize::Size32x4)
2358
+ }
2359
+ };
2360
+ let rd = pretty_print_vreg_vector(rd.to_reg(), dest_size);
2361
+ let ri = pretty_print_vreg_vector(ri, dest_size);
2362
+ let rn = pretty_print_vreg_vector(rn, src_size);
2363
+ let rm = pretty_print_vreg_vector(rm, src_size);
2364
+ format!("{op} {rd}, {ri}, {rn}, {rm}")
2365
+ }
2366
+ &Inst::VecMisc { op, rd, rn, size } => {
2367
+ let (op, size, suffix) = match op {
2368
+ VecMisc2::Not => (
2369
+ "mvn",
2370
+ if size.is_128bits() {
2371
+ VectorSize::Size8x16
2372
+ } else {
2373
+ VectorSize::Size8x8
2374
+ },
2375
+ "",
2376
+ ),
2377
+ VecMisc2::Neg => ("neg", size, ""),
2378
+ VecMisc2::Abs => ("abs", size, ""),
2379
+ VecMisc2::Fabs => ("fabs", size, ""),
2380
+ VecMisc2::Fneg => ("fneg", size, ""),
2381
+ VecMisc2::Fsqrt => ("fsqrt", size, ""),
2382
+ VecMisc2::Rev16 => ("rev16", size, ""),
2383
+ VecMisc2::Rev32 => ("rev32", size, ""),
2384
+ VecMisc2::Rev64 => ("rev64", size, ""),
2385
+ VecMisc2::Fcvtzs => ("fcvtzs", size, ""),
2386
+ VecMisc2::Fcvtzu => ("fcvtzu", size, ""),
2387
+ VecMisc2::Scvtf => ("scvtf", size, ""),
2388
+ VecMisc2::Ucvtf => ("ucvtf", size, ""),
2389
+ VecMisc2::Frintn => ("frintn", size, ""),
2390
+ VecMisc2::Frintz => ("frintz", size, ""),
2391
+ VecMisc2::Frintm => ("frintm", size, ""),
2392
+ VecMisc2::Frintp => ("frintp", size, ""),
2393
+ VecMisc2::Cnt => ("cnt", size, ""),
2394
+ VecMisc2::Cmeq0 => ("cmeq", size, ", #0"),
2395
+ VecMisc2::Cmge0 => ("cmge", size, ", #0"),
2396
+ VecMisc2::Cmgt0 => ("cmgt", size, ", #0"),
2397
+ VecMisc2::Cmle0 => ("cmle", size, ", #0"),
2398
+ VecMisc2::Cmlt0 => ("cmlt", size, ", #0"),
2399
+ VecMisc2::Fcmeq0 => ("fcmeq", size, ", #0.0"),
2400
+ VecMisc2::Fcmge0 => ("fcmge", size, ", #0.0"),
2401
+ VecMisc2::Fcmgt0 => ("fcmgt", size, ", #0.0"),
2402
+ VecMisc2::Fcmle0 => ("fcmle", size, ", #0.0"),
2403
+ VecMisc2::Fcmlt0 => ("fcmlt", size, ", #0.0"),
2404
+ };
2405
+ let rd = pretty_print_vreg_vector(rd.to_reg(), size);
2406
+ let rn = pretty_print_vreg_vector(rn, size);
2407
+ format!("{op} {rd}, {rn}{suffix}")
2408
+ }
2409
+ &Inst::VecLanes { op, rd, rn, size } => {
2410
+ let op = match op {
2411
+ VecLanesOp::Uminv => "uminv",
2412
+ VecLanesOp::Addv => "addv",
2413
+ };
2414
+ let rd = pretty_print_vreg_scalar(rd.to_reg(), size.lane_size());
2415
+ let rn = pretty_print_vreg_vector(rn, size);
2416
+ format!("{op} {rd}, {rn}")
2417
+ }
2418
+ &Inst::VecShiftImm {
2419
+ op,
2420
+ rd,
2421
+ rn,
2422
+ size,
2423
+ imm,
2424
+ } => {
2425
+ let op = match op {
2426
+ VecShiftImmOp::Shl => "shl",
2427
+ VecShiftImmOp::Ushr => "ushr",
2428
+ VecShiftImmOp::Sshr => "sshr",
2429
+ };
2430
+ let rd = pretty_print_vreg_vector(rd.to_reg(), size);
2431
+ let rn = pretty_print_vreg_vector(rn, size);
2432
+ format!("{op} {rd}, {rn}, #{imm}")
2433
+ }
2434
+ &Inst::VecShiftImmMod {
2435
+ op,
2436
+ rd,
2437
+ ri,
2438
+ rn,
2439
+ size,
2440
+ imm,
2441
+ } => {
2442
+ let op = match op {
2443
+ VecShiftImmModOp::Sli => "sli",
2444
+ };
2445
+ let rd = pretty_print_vreg_vector(rd.to_reg(), size);
2446
+ let ri = pretty_print_vreg_vector(ri, size);
2447
+ let rn = pretty_print_vreg_vector(rn, size);
2448
+ format!("{op} {rd}, {ri}, {rn}, #{imm}")
2449
+ }
2450
+ &Inst::VecExtract { rd, rn, rm, imm4 } => {
2451
+ let rd = pretty_print_vreg_vector(rd.to_reg(), VectorSize::Size8x16);
2452
+ let rn = pretty_print_vreg_vector(rn, VectorSize::Size8x16);
2453
+ let rm = pretty_print_vreg_vector(rm, VectorSize::Size8x16);
2454
+ format!("ext {rd}, {rn}, {rm}, #{imm4}")
2455
+ }
2456
+ &Inst::VecTbl { rd, rn, rm } => {
2457
+ let rn = pretty_print_vreg_vector(rn, VectorSize::Size8x16);
2458
+ let rm = pretty_print_vreg_vector(rm, VectorSize::Size8x16);
2459
+ let rd = pretty_print_vreg_vector(rd.to_reg(), VectorSize::Size8x16);
2460
+ format!("tbl {rd}, {{ {rn} }}, {rm}")
2461
+ }
2462
+ &Inst::VecTblExt { rd, ri, rn, rm } => {
2463
+ let rn = pretty_print_vreg_vector(rn, VectorSize::Size8x16);
2464
+ let rm = pretty_print_vreg_vector(rm, VectorSize::Size8x16);
2465
+ let rd = pretty_print_vreg_vector(rd.to_reg(), VectorSize::Size8x16);
2466
+ let ri = pretty_print_vreg_vector(ri, VectorSize::Size8x16);
2467
+ format!("tbx {rd}, {ri}, {{ {rn} }}, {rm}")
2468
+ }
2469
+ &Inst::VecTbl2 { rd, rn, rn2, rm } => {
2470
+ let rn = pretty_print_vreg_vector(rn, VectorSize::Size8x16);
2471
+ let rn2 = pretty_print_vreg_vector(rn2, VectorSize::Size8x16);
2472
+ let rm = pretty_print_vreg_vector(rm, VectorSize::Size8x16);
2473
+ let rd = pretty_print_vreg_vector(rd.to_reg(), VectorSize::Size8x16);
2474
+ format!("tbl {rd}, {{ {rn}, {rn2} }}, {rm}")
2475
+ }
2476
+ &Inst::VecTbl2Ext {
2477
+ rd,
2478
+ ri,
2479
+ rn,
2480
+ rn2,
2481
+ rm,
2482
+ } => {
2483
+ let rn = pretty_print_vreg_vector(rn, VectorSize::Size8x16);
2484
+ let rn2 = pretty_print_vreg_vector(rn2, VectorSize::Size8x16);
2485
+ let rm = pretty_print_vreg_vector(rm, VectorSize::Size8x16);
2486
+ let rd = pretty_print_vreg_vector(rd.to_reg(), VectorSize::Size8x16);
2487
+ let ri = pretty_print_vreg_vector(ri, VectorSize::Size8x16);
2488
+ format!("tbx {rd}, {ri}, {{ {rn}, {rn2} }}, {rm}")
2489
+ }
2490
+ &Inst::VecLoadReplicate { rd, rn, size, .. } => {
2491
+ let rd = pretty_print_vreg_vector(rd.to_reg(), size);
2492
+ let rn = pretty_print_reg(rn);
2493
+
2494
+ format!("ld1r {{ {rd} }}, [{rn}]")
2495
+ }
2496
+ &Inst::VecCSel { rd, rn, rm, cond } => {
2497
+ let rd = pretty_print_vreg_vector(rd.to_reg(), VectorSize::Size8x16);
2498
+ let rn = pretty_print_vreg_vector(rn, VectorSize::Size8x16);
2499
+ let rm = pretty_print_vreg_vector(rm, VectorSize::Size8x16);
2500
+ let cond = cond.pretty_print(0);
2501
+ format!("vcsel {rd}, {rn}, {rm}, {cond} (if-then-else diamond)")
2502
+ }
2503
+ &Inst::MovToNZCV { rn } => {
2504
+ let rn = pretty_print_reg(rn);
2505
+ format!("msr nzcv, {rn}")
2506
+ }
2507
+ &Inst::MovFromNZCV { rd } => {
2508
+ let rd = pretty_print_reg(rd.to_reg());
2509
+ format!("mrs {rd}, nzcv")
2510
+ }
2511
+ &Inst::Extend {
2512
+ rd,
2513
+ rn,
2514
+ signed: false,
2515
+ from_bits: 1,
2516
+ ..
2517
+ } => {
2518
+ let rd = pretty_print_ireg(rd.to_reg(), OperandSize::Size32);
2519
+ let rn = pretty_print_ireg(rn, OperandSize::Size32);
2520
+ format!("and {rd}, {rn}, #1")
2521
+ }
2522
+ &Inst::Extend {
2523
+ rd,
2524
+ rn,
2525
+ signed: false,
2526
+ from_bits: 32,
2527
+ to_bits: 64,
2528
+ } => {
2529
+ // The case of a zero extension from 32 to 64 bits, is implemented
2530
+ // with a "mov" to a 32-bit (W-reg) dest, because this zeroes
2531
+ // the top 32 bits.
2532
+ let rd = pretty_print_ireg(rd.to_reg(), OperandSize::Size32);
2533
+ let rn = pretty_print_ireg(rn, OperandSize::Size32);
2534
+ format!("mov {rd}, {rn}")
2535
+ }
2536
+ &Inst::Extend {
2537
+ rd,
2538
+ rn,
2539
+ signed,
2540
+ from_bits,
2541
+ to_bits,
2542
+ } => {
2543
+ assert!(from_bits <= to_bits);
2544
+ let op = match (signed, from_bits) {
2545
+ (false, 8) => "uxtb",
2546
+ (true, 8) => "sxtb",
2547
+ (false, 16) => "uxth",
2548
+ (true, 16) => "sxth",
2549
+ (true, 32) => "sxtw",
2550
+ (true, _) => "sbfx",
2551
+ (false, _) => "ubfx",
2552
+ };
2553
+ if op == "sbfx" || op == "ubfx" {
2554
+ let dest_size = OperandSize::from_bits(to_bits);
2555
+ let rd = pretty_print_ireg(rd.to_reg(), dest_size);
2556
+ let rn = pretty_print_ireg(rn, dest_size);
2557
+ format!("{op} {rd}, {rn}, #0, #{from_bits}")
2558
+ } else {
2559
+ let dest_size = if signed {
2560
+ OperandSize::from_bits(to_bits)
2561
+ } else {
2562
+ OperandSize::Size32
2563
+ };
2564
+ let rd = pretty_print_ireg(rd.to_reg(), dest_size);
2565
+ let rn = pretty_print_ireg(rn, OperandSize::from_bits(from_bits));
2566
+ format!("{op} {rd}, {rn}")
2567
+ }
2568
+ }
2569
+ &Inst::Call { .. } => format!("bl 0"),
2570
+ &Inst::CallInd { ref info } => {
2571
+ let rn = pretty_print_reg(info.dest);
2572
+ format!("blr {rn}")
2573
+ }
2574
+ &Inst::ReturnCall { ref info } => {
2575
+ let mut s = format!(
2576
+ "return_call {:?} new_stack_arg_size:{}",
2577
+ info.dest, info.new_stack_arg_size
2578
+ );
2579
+ for ret in &info.uses {
2580
+ let preg = pretty_print_reg(ret.preg);
2581
+ let vreg = pretty_print_reg(ret.vreg);
2582
+ write!(&mut s, " {vreg}={preg}").unwrap();
2583
+ }
2584
+ s
2585
+ }
2586
+ &Inst::ReturnCallInd { ref info } => {
2587
+ let callee = pretty_print_reg(info.dest);
2588
+ let mut s = format!(
2589
+ "return_call_ind {callee} new_stack_arg_size:{}",
2590
+ info.new_stack_arg_size
2591
+ );
2592
+ for ret in &info.uses {
2593
+ let preg = pretty_print_reg(ret.preg);
2594
+ let vreg = pretty_print_reg(ret.vreg);
2595
+ write!(&mut s, " {vreg}={preg}").unwrap();
2596
+ }
2597
+ s
2598
+ }
2599
+ &Inst::Args { ref args } => {
2600
+ let mut s = "args".to_string();
2601
+ for arg in args {
2602
+ let preg = pretty_print_reg(arg.preg);
2603
+ let def = pretty_print_reg(arg.vreg.to_reg());
2604
+ write!(&mut s, " {def}={preg}").unwrap();
2605
+ }
2606
+ s
2607
+ }
2608
+ &Inst::Rets { ref rets } => {
2609
+ let mut s = "rets".to_string();
2610
+ for ret in rets {
2611
+ let preg = pretty_print_reg(ret.preg);
2612
+ let vreg = pretty_print_reg(ret.vreg);
2613
+ write!(&mut s, " {vreg}={preg}").unwrap();
2614
+ }
2615
+ s
2616
+ }
2617
+ &Inst::Ret {} => "ret".to_string(),
2618
+ &Inst::AuthenticatedRet { key, is_hint } => {
2619
+ let key = match key {
2620
+ APIKey::AZ => "az",
2621
+ APIKey::BZ => "bz",
2622
+ APIKey::ASP => "asp",
2623
+ APIKey::BSP => "bsp",
2624
+ };
2625
+ match is_hint {
2626
+ false => format!("reta{key}"),
2627
+ true => format!("auti{key} ; ret"),
2628
+ }
2629
+ }
2630
+ &Inst::Jump { ref dest } => {
2631
+ let dest = dest.pretty_print(0);
2632
+ format!("b {dest}")
2633
+ }
2634
+ &Inst::CondBr {
2635
+ ref taken,
2636
+ ref not_taken,
2637
+ ref kind,
2638
+ } => {
2639
+ let taken = taken.pretty_print(0);
2640
+ let not_taken = not_taken.pretty_print(0);
2641
+ match kind {
2642
+ &CondBrKind::Zero(reg) => {
2643
+ let reg = pretty_print_reg(reg);
2644
+ format!("cbz {reg}, {taken} ; b {not_taken}")
2645
+ }
2646
+ &CondBrKind::NotZero(reg) => {
2647
+ let reg = pretty_print_reg(reg);
2648
+ format!("cbnz {reg}, {taken} ; b {not_taken}")
2649
+ }
2650
+ &CondBrKind::Cond(c) => {
2651
+ let c = c.pretty_print(0);
2652
+ format!("b.{c} {taken} ; b {not_taken}")
2653
+ }
2654
+ }
2655
+ }
2656
+ &Inst::TestBitAndBranch {
2657
+ kind,
2658
+ ref taken,
2659
+ ref not_taken,
2660
+ rn,
2661
+ bit,
2662
+ } => {
2663
+ let cond = match kind {
2664
+ TestBitAndBranchKind::Z => "z",
2665
+ TestBitAndBranchKind::NZ => "nz",
2666
+ };
2667
+ let taken = taken.pretty_print(0);
2668
+ let not_taken = not_taken.pretty_print(0);
2669
+ let rn = pretty_print_reg(rn);
2670
+ format!("tb{cond} {rn}, #{bit}, {taken} ; b {not_taken}")
2671
+ }
2672
+ &Inst::IndirectBr { rn, .. } => {
2673
+ let rn = pretty_print_reg(rn);
2674
+ format!("br {rn}")
2675
+ }
2676
+ &Inst::Brk => "brk #0".to_string(),
2677
+ &Inst::Udf { .. } => "udf #0xc11f".to_string(),
2678
+ &Inst::TrapIf {
2679
+ ref kind,
2680
+ trap_code,
2681
+ } => match kind {
2682
+ &CondBrKind::Zero(reg) => {
2683
+ let reg = pretty_print_reg(reg);
2684
+ format!("cbz {reg}, #trap={trap_code}")
2685
+ }
2686
+ &CondBrKind::NotZero(reg) => {
2687
+ let reg = pretty_print_reg(reg);
2688
+ format!("cbnz {reg}, #trap={trap_code}")
2689
+ }
2690
+ &CondBrKind::Cond(c) => {
2691
+ let c = c.pretty_print(0);
2692
+ format!("b.{c} #trap={trap_code}")
2693
+ }
2694
+ },
2695
+ &Inst::Adr { rd, off } => {
2696
+ let rd = pretty_print_reg(rd.to_reg());
2697
+ format!("adr {rd}, pc+{off}")
2698
+ }
2699
+ &Inst::Adrp { rd, off } => {
2700
+ let rd = pretty_print_reg(rd.to_reg());
2701
+ // This instruction addresses 4KiB pages, so multiply it by the page size.
2702
+ let byte_offset = off * 4096;
2703
+ format!("adrp {rd}, pc+{byte_offset}")
2704
+ }
2705
+ &Inst::Word4 { data } => format!("data.i32 {data}"),
2706
+ &Inst::Word8 { data } => format!("data.i64 {data}"),
2707
+ &Inst::JTSequence {
2708
+ default,
2709
+ ref targets,
2710
+ ridx,
2711
+ rtmp1,
2712
+ rtmp2,
2713
+ ..
2714
+ } => {
2715
+ let ridx = pretty_print_reg(ridx);
2716
+ let rtmp1 = pretty_print_reg(rtmp1.to_reg());
2717
+ let rtmp2 = pretty_print_reg(rtmp2.to_reg());
2718
+ let default_target = BranchTarget::Label(default).pretty_print(0);
2719
+ format!(
2720
+ concat!(
2721
+ "b.hs {} ; ",
2722
+ "csel {}, xzr, {}, hs ; ",
2723
+ "csdb ; ",
2724
+ "adr {}, pc+16 ; ",
2725
+ "ldrsw {}, [{}, {}, uxtw #2] ; ",
2726
+ "add {}, {}, {} ; ",
2727
+ "br {} ; ",
2728
+ "jt_entries {:?}"
2729
+ ),
2730
+ default_target,
2731
+ rtmp2,
2732
+ ridx,
2733
+ rtmp1,
2734
+ rtmp2,
2735
+ rtmp1,
2736
+ rtmp2,
2737
+ rtmp1,
2738
+ rtmp1,
2739
+ rtmp2,
2740
+ rtmp1,
2741
+ targets
2742
+ )
2743
+ }
2744
+ &Inst::LoadExtName {
2745
+ rd,
2746
+ ref name,
2747
+ offset,
2748
+ } => {
2749
+ let rd = pretty_print_reg(rd.to_reg());
2750
+ format!("load_ext_name {rd}, {name:?}+{offset}")
2751
+ }
2752
+ &Inst::LoadAddr { rd, ref mem } => {
2753
+ // TODO: we really should find a better way to avoid duplication of
2754
+ // this logic between `emit()` and `show_rru()` -- a separate 1-to-N
2755
+ // expansion stage (i.e., legalization, but without the slow edit-in-place
2756
+ // of the existing legalization framework).
2757
+ let mem = mem.clone();
2758
+ let (mem_insts, mem) = mem_finalize(None, &mem, I8, state);
2759
+ let mut ret = String::new();
2760
+ for inst in mem_insts.into_iter() {
2761
+ ret.push_str(&inst.print_with_state(&mut EmitState::default()));
2762
+ }
2763
+ let (reg, index_reg, offset) = match mem {
2764
+ AMode::RegExtended { rn, rm, extendop } => (rn, Some((rm, extendop)), 0),
2765
+ AMode::Unscaled { rn, simm9 } => (rn, None, simm9.value()),
2766
+ AMode::UnsignedOffset { rn, uimm12 } => (rn, None, uimm12.value() as i32),
2767
+ _ => panic!("Unsupported case for LoadAddr: {mem:?}"),
2768
+ };
2769
+ let abs_offset = if offset < 0 {
2770
+ -offset as u64
2771
+ } else {
2772
+ offset as u64
2773
+ };
2774
+ let alu_op = if offset < 0 { ALUOp::Sub } else { ALUOp::Add };
2775
+
2776
+ if let Some((idx, extendop)) = index_reg {
2777
+ let add = Inst::AluRRRExtend {
2778
+ alu_op: ALUOp::Add,
2779
+ size: OperandSize::Size64,
2780
+ rd,
2781
+ rn: reg,
2782
+ rm: idx,
2783
+ extendop,
2784
+ };
2785
+
2786
+ ret.push_str(&add.print_with_state(&mut EmitState::default()));
2787
+ } else if offset == 0 {
2788
+ let mov = Inst::gen_move(rd, reg, I64);
2789
+ ret.push_str(&mov.print_with_state(&mut EmitState::default()));
2790
+ } else if let Some(imm12) = Imm12::maybe_from_u64(abs_offset) {
2791
+ let add = Inst::AluRRImm12 {
2792
+ alu_op,
2793
+ size: OperandSize::Size64,
2794
+ rd,
2795
+ rn: reg,
2796
+ imm12,
2797
+ };
2798
+ ret.push_str(&add.print_with_state(&mut EmitState::default()));
2799
+ } else {
2800
+ let tmp = writable_spilltmp_reg();
2801
+ for inst in Inst::load_constant(tmp, abs_offset, &mut |_| tmp).into_iter() {
2802
+ ret.push_str(&inst.print_with_state(&mut EmitState::default()));
2803
+ }
2804
+ let add = Inst::AluRRR {
2805
+ alu_op,
2806
+ size: OperandSize::Size64,
2807
+ rd,
2808
+ rn: reg,
2809
+ rm: tmp.to_reg(),
2810
+ };
2811
+ ret.push_str(&add.print_with_state(&mut EmitState::default()));
2812
+ }
2813
+ ret
2814
+ }
2815
+ &Inst::Paci { key } => {
2816
+ let key = match key {
2817
+ APIKey::AZ => "az",
2818
+ APIKey::BZ => "bz",
2819
+ APIKey::ASP => "asp",
2820
+ APIKey::BSP => "bsp",
2821
+ };
2822
+
2823
+ "paci".to_string() + key
2824
+ }
2825
+ &Inst::Xpaclri => "xpaclri".to_string(),
2826
+ &Inst::Bti { targets } => {
2827
+ let targets = match targets {
2828
+ BranchTargetType::None => "",
2829
+ BranchTargetType::C => " c",
2830
+ BranchTargetType::J => " j",
2831
+ BranchTargetType::JC => " jc",
2832
+ };
2833
+
2834
+ "bti".to_string() + targets
2835
+ }
2836
+ &Inst::EmitIsland { needed_space } => format!("emit_island {needed_space}"),
2837
+
2838
+ &Inst::ElfTlsGetAddr {
2839
+ ref symbol,
2840
+ rd,
2841
+ tmp,
2842
+ } => {
2843
+ let rd = pretty_print_reg(rd.to_reg());
2844
+ let tmp = pretty_print_reg(tmp.to_reg());
2845
+ format!("elf_tls_get_addr {}, {}, {}", rd, tmp, symbol.display(None))
2846
+ }
2847
+ &Inst::MachOTlsGetAddr { ref symbol, rd } => {
2848
+ let rd = pretty_print_reg(rd.to_reg());
2849
+ format!("macho_tls_get_addr {}, {}", rd, symbol.display(None))
2850
+ }
2851
+ &Inst::Unwind { ref inst } => {
2852
+ format!("unwind {inst:?}")
2853
+ }
2854
+ &Inst::DummyUse { reg } => {
2855
+ let reg = pretty_print_reg(reg);
2856
+ format!("dummy_use {reg}")
2857
+ }
2858
+ &Inst::StackProbeLoop { start, end, step } => {
2859
+ let start = pretty_print_reg(start.to_reg());
2860
+ let end = pretty_print_reg(end);
2861
+ let step = step.pretty_print(0);
2862
+ format!("stack_probe_loop {start}, {end}, {step}")
2863
+ }
2864
+ }
2865
+ }
2866
+ }
2867
+
2868
+ //=============================================================================
2869
+ // Label fixups and jump veneers.
2870
+
2871
+ /// Different forms of label references for different instruction formats.
2872
+ #[derive(Clone, Copy, Debug, PartialEq, Eq)]
2873
+ pub enum LabelUse {
2874
+ /// 14-bit branch offset (conditional branches). PC-rel, offset is imm <<
2875
+ /// 2. Immediate is 14 signed bits, in bits 18:5. Used by tbz and tbnz.
2876
+ Branch14,
2877
+ /// 19-bit branch offset (conditional branches). PC-rel, offset is imm << 2. Immediate is 19
2878
+ /// signed bits, in bits 23:5. Used by cbz, cbnz, b.cond.
2879
+ Branch19,
2880
+ /// 26-bit branch offset (unconditional branches). PC-rel, offset is imm << 2. Immediate is 26
2881
+ /// signed bits, in bits 25:0. Used by b, bl.
2882
+ Branch26,
2883
+ #[allow(dead_code)]
2884
+ /// 19-bit offset for LDR (load literal). PC-rel, offset is imm << 2. Immediate is 19 signed bits,
2885
+ /// in bits 23:5.
2886
+ Ldr19,
2887
+ #[allow(dead_code)]
2888
+ /// 21-bit offset for ADR (get address of label). PC-rel, offset is not shifted. Immediate is
2889
+ /// 21 signed bits, with high 19 bits in bits 23:5 and low 2 bits in bits 30:29.
2890
+ Adr21,
2891
+ /// 32-bit PC relative constant offset (from address of constant itself),
2892
+ /// signed. Used in jump tables.
2893
+ PCRel32,
2894
+ }
2895
+
2896
+ impl MachInstLabelUse for LabelUse {
2897
+ /// Alignment for veneer code. Every AArch64 instruction must be 4-byte-aligned.
2898
+ const ALIGN: CodeOffset = 4;
2899
+
2900
+ /// Maximum PC-relative range (positive), inclusive.
2901
+ fn max_pos_range(self) -> CodeOffset {
2902
+ match self {
2903
+ // N-bit immediate, left-shifted by 2, for (N+2) bits of total
2904
+ // range. Signed, so +2^(N+1) from zero. Likewise for two other
2905
+ // shifted cases below.
2906
+ LabelUse::Branch14 => (1 << 15) - 1,
2907
+ LabelUse::Branch19 => (1 << 20) - 1,
2908
+ LabelUse::Branch26 => (1 << 27) - 1,
2909
+ LabelUse::Ldr19 => (1 << 20) - 1,
2910
+ // Adr does not shift its immediate, so the 21-bit immediate gives 21 bits of total
2911
+ // range.
2912
+ LabelUse::Adr21 => (1 << 20) - 1,
2913
+ LabelUse::PCRel32 => 0x7fffffff,
2914
+ }
2915
+ }
2916
+
2917
+ /// Maximum PC-relative range (negative).
2918
+ fn max_neg_range(self) -> CodeOffset {
2919
+ // All forms are twos-complement signed offsets, so negative limit is one more than
2920
+ // positive limit.
2921
+ self.max_pos_range() + 1
2922
+ }
2923
+
2924
+ /// Size of window into code needed to do the patch.
2925
+ fn patch_size(self) -> CodeOffset {
2926
+ // Patch is on one instruction only for all of these label reference types.
2927
+ 4
2928
+ }
2929
+
2930
+ /// Perform the patch.
2931
+ fn patch(self, buffer: &mut [u8], use_offset: CodeOffset, label_offset: CodeOffset) {
2932
+ let pc_rel = (label_offset as i64) - (use_offset as i64);
2933
+ debug_assert!(pc_rel <= self.max_pos_range() as i64);
2934
+ debug_assert!(pc_rel >= -(self.max_neg_range() as i64));
2935
+ let pc_rel = pc_rel as u32;
2936
+ let insn_word = u32::from_le_bytes([buffer[0], buffer[1], buffer[2], buffer[3]]);
2937
+ let mask = match self {
2938
+ LabelUse::Branch14 => 0x0007ffe0, // bits 18..5 inclusive
2939
+ LabelUse::Branch19 => 0x00ffffe0, // bits 23..5 inclusive
2940
+ LabelUse::Branch26 => 0x03ffffff, // bits 25..0 inclusive
2941
+ LabelUse::Ldr19 => 0x00ffffe0, // bits 23..5 inclusive
2942
+ LabelUse::Adr21 => 0x60ffffe0, // bits 30..29, 25..5 inclusive
2943
+ LabelUse::PCRel32 => 0xffffffff,
2944
+ };
2945
+ let pc_rel_shifted = match self {
2946
+ LabelUse::Adr21 | LabelUse::PCRel32 => pc_rel,
2947
+ _ => {
2948
+ debug_assert!(pc_rel & 3 == 0);
2949
+ pc_rel >> 2
2950
+ }
2951
+ };
2952
+ let pc_rel_inserted = match self {
2953
+ LabelUse::Branch14 => (pc_rel_shifted & 0x3fff) << 5,
2954
+ LabelUse::Branch19 | LabelUse::Ldr19 => (pc_rel_shifted & 0x7ffff) << 5,
2955
+ LabelUse::Branch26 => pc_rel_shifted & 0x3ffffff,
2956
+ LabelUse::Adr21 => (pc_rel_shifted & 0x7ffff) << 5 | (pc_rel_shifted & 0x180000) << 10,
2957
+ LabelUse::PCRel32 => pc_rel_shifted,
2958
+ };
2959
+ let is_add = match self {
2960
+ LabelUse::PCRel32 => true,
2961
+ _ => false,
2962
+ };
2963
+ let insn_word = if is_add {
2964
+ insn_word.wrapping_add(pc_rel_inserted)
2965
+ } else {
2966
+ (insn_word & !mask) | pc_rel_inserted
2967
+ };
2968
+ buffer[0..4].clone_from_slice(&u32::to_le_bytes(insn_word));
2969
+ }
2970
+
2971
+ /// Is a veneer supported for this label reference type?
2972
+ fn supports_veneer(self) -> bool {
2973
+ match self {
2974
+ LabelUse::Branch14 | LabelUse::Branch19 => true, // veneer is a Branch26
2975
+ LabelUse::Branch26 => true, // veneer is a PCRel32
2976
+ _ => false,
2977
+ }
2978
+ }
2979
+
2980
+ /// How large is the veneer, if supported?
2981
+ fn veneer_size(self) -> CodeOffset {
2982
+ match self {
2983
+ LabelUse::Branch14 | LabelUse::Branch19 => 4,
2984
+ LabelUse::Branch26 => 20,
2985
+ _ => unreachable!(),
2986
+ }
2987
+ }
2988
+
2989
+ fn worst_case_veneer_size() -> CodeOffset {
2990
+ 20
2991
+ }
2992
+
2993
+ /// Generate a veneer into the buffer, given that this veneer is at `veneer_offset`, and return
2994
+ /// an offset and label-use for the veneer's use of the original label.
2995
+ fn generate_veneer(
2996
+ self,
2997
+ buffer: &mut [u8],
2998
+ veneer_offset: CodeOffset,
2999
+ ) -> (CodeOffset, LabelUse) {
3000
+ match self {
3001
+ LabelUse::Branch14 | LabelUse::Branch19 => {
3002
+ // veneer is a Branch26 (unconditional branch). Just encode directly here -- don't
3003
+ // bother with constructing an Inst.
3004
+ let insn_word = 0b000101 << 26;
3005
+ buffer[0..4].clone_from_slice(&u32::to_le_bytes(insn_word));
3006
+ (veneer_offset, LabelUse::Branch26)
3007
+ }
3008
+
3009
+ // This is promoting a 26-bit call/jump to a 32-bit call/jump to
3010
+ // get a further range. This jump translates to a jump to a
3011
+ // relative location based on the address of the constant loaded
3012
+ // from here.
3013
+ //
3014
+ // If this path is taken from a call instruction then caller-saved
3015
+ // registers are available (minus arguments), so x16/x17 are
3016
+ // available. Otherwise for intra-function jumps we also reserve
3017
+ // x16/x17 as spill-style registers. In both cases these are
3018
+ // available for us to use.
3019
+ LabelUse::Branch26 => {
3020
+ let tmp1 = regs::spilltmp_reg();
3021
+ let tmp1_w = regs::writable_spilltmp_reg();
3022
+ let tmp2 = regs::tmp2_reg();
3023
+ let tmp2_w = regs::writable_tmp2_reg();
3024
+ // ldrsw x16, 16
3025
+ let ldr = emit::enc_ldst_imm19(0b1001_1000, 16 / 4, tmp1);
3026
+ // adr x17, 12
3027
+ let adr = emit::enc_adr(12, tmp2_w);
3028
+ // add x16, x16, x17
3029
+ let add = emit::enc_arith_rrr(0b10001011_000, 0, tmp1_w, tmp1, tmp2);
3030
+ // br x16
3031
+ let br = emit::enc_br(tmp1);
3032
+ buffer[0..4].clone_from_slice(&u32::to_le_bytes(ldr));
3033
+ buffer[4..8].clone_from_slice(&u32::to_le_bytes(adr));
3034
+ buffer[8..12].clone_from_slice(&u32::to_le_bytes(add));
3035
+ buffer[12..16].clone_from_slice(&u32::to_le_bytes(br));
3036
+ // the 4-byte signed immediate we'll load is after these
3037
+ // instructions, 16-bytes in.
3038
+ (veneer_offset + 16, LabelUse::PCRel32)
3039
+ }
3040
+
3041
+ _ => panic!("Unsupported label-reference type for veneer generation!"),
3042
+ }
3043
+ }
3044
+
3045
+ fn from_reloc(reloc: Reloc, addend: Addend) -> Option<LabelUse> {
3046
+ match (reloc, addend) {
3047
+ (Reloc::Arm64Call, 0) => Some(LabelUse::Branch26),
3048
+ _ => None,
3049
+ }
3050
+ }
3051
+ }