axi_tdl 0.0.2

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (1189) hide show
  1. checksums.yaml +7 -0
  2. data/.gitignore +8 -0
  3. data/CODE_OF_CONDUCT.md +74 -0
  4. data/Gemfile +6 -0
  5. data/Gemfile.lock +43 -0
  6. data/LICENSE +504 -0
  7. data/README.md +311 -0
  8. data/Rakefile +18 -0
  9. data/axi_tdl.gemspec +43 -0
  10. data/bin/console +14 -0
  11. data/bin/setup +8 -0
  12. data/lib/.rspec +1 -0
  13. data/lib/axi/AXI4/axi4_combin_wr_rd_batch.sv +59 -0
  14. data/lib/axi/AXI4/axi4_direct.sv +137 -0
  15. data/lib/axi/AXI4/axi4_direct_A1.sv +229 -0
  16. data/lib/axi/AXI4/axi4_direct_B1.sv +74 -0
  17. data/lib/axi/AXI4/axi4_direct_verb.sv +79 -0
  18. data/lib/axi/AXI4/axi4_direct_verc.sv +146 -0
  19. data/lib/axi/AXI4/axi4_dpram_cache.rb +106 -0
  20. data/lib/axi/AXI4/axi4_dpram_cache.sv +112 -0
  21. data/lib/axi/AXI4/axi4_long_to_axi4_wide.sv +85 -0
  22. data/lib/axi/AXI4/axi4_long_to_axi4_wide_A1.sv +96 -0
  23. data/lib/axi/AXI4/axi4_long_to_axi4_wide_track.sv +118 -0
  24. data/lib/axi/AXI4/axi4_long_to_axi4_wide_verb.sv +131 -0
  25. data/lib/axi/AXI4/axi4_pipe/axi4_pipe.sv +44 -0
  26. data/lib/axi/AXI4/axi4_pipe/axi4_pipe_verb.sv +45 -0
  27. data/lib/axi/AXI4/axi4_pipe/axi4_rd_pipe.sv +111 -0
  28. data/lib/axi/AXI4/axi4_pipe/axi4_rd_pipe_verb.sv +113 -0
  29. data/lib/axi/AXI4/axi4_pipe/axi4_wr_pipe.sv +142 -0
  30. data/lib/axi/AXI4/axi4_pipe/axi4_wr_pipe_verb.sv +146 -0
  31. data/lib/axi/AXI4/axi4_rd_auxiliary_batch_gen.sv +134 -0
  32. data/lib/axi/AXI4/axi4_rd_auxiliary_gen.sv +89 -0
  33. data/lib/axi/AXI4/axi4_rd_auxiliary_gen_A1.sv +109 -0
  34. data/lib/axi/AXI4/axi4_rd_burst_track.sv +164 -0
  35. data/lib/axi/AXI4/axi4_wr_aux_bind_data.sv +121 -0
  36. data/lib/axi/AXI4/axi4_wr_auxiliary_batch_gen.sv +140 -0
  37. data/lib/axi/AXI4/axi4_wr_auxiliary_gen.sv +102 -0
  38. data/lib/axi/AXI4/axi4_wr_auxiliary_gen_without_resp.sv +91 -0
  39. data/lib/axi/AXI4/axi4_wr_burst_track.sv +146 -0
  40. data/lib/axi/AXI4/axi_stream_add_addr_len.sv +50 -0
  41. data/lib/axi/AXI4/axi_stream_to_axi4_wr.sv +61 -0
  42. data/lib/axi/AXI4/axi_stream_to_axi4_wr_verb.sv.bak +123 -0
  43. data/lib/axi/AXI4/axis_to_axi4_wr.rb +149 -0
  44. data/lib/axi/AXI4/axis_to_axi4_wr.sv +141 -0
  45. data/lib/axi/AXI4/full_axi4_to_axis.sv +188 -0
  46. data/lib/axi/AXI4/full_axi4_to_axis_partition_wr_rd.sv +208 -0
  47. data/lib/axi/AXI4/id_record.sv +55 -0
  48. data/lib/axi/AXI4/idata_pool_axi4.sv +110 -0
  49. data/lib/axi/AXI4/interconnect/AXI4_interconnect_M2S.sv +291 -0
  50. data/lib/axi/AXI4/interconnect/axi4_mix_interconnect_M2S.sv +72 -0
  51. data/lib/axi/AXI4/interconnect/axi4_rd_interconnect_M2S.sv +148 -0
  52. data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S.sv +255 -0
  53. data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S.sv.bak +255 -0
  54. data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S_A1.sv +286 -0
  55. data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S_A2.sv +281 -0
  56. data/lib/axi/AXI4/interconnect/axi4_wr_interconnect_M2S.sv +235 -0
  57. data/lib/axi/AXI4/interconnect/axi4_wr_interconnect_M2S_A1.sv +283 -0
  58. data/lib/axi/AXI4/interconnect/axi4_wr_mix_interconnect_M2S.sv +32 -0
  59. data/lib/axi/AXI4/long_axi4_to_wide_axi4.sv.bak +251 -0
  60. data/lib/axi/AXI4/odata_pool_axi4.sv +134 -0
  61. data/lib/axi/AXI4/odata_pool_axi4_A1.sv +165 -0
  62. data/lib/axi/AXI4/odata_pool_axi4_A2.sv +159 -0
  63. data/lib/axi/AXI4/odata_pool_axi4_A3.sv +183 -0
  64. data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo.sv +61 -0
  65. data/lib/axi/AXI4/packet_fifo/axi4_rd_packet_fifo.sv +282 -0
  66. data/lib/axi/AXI4/packet_fifo/axi4_wr_packet_fifo.sv +181 -0
  67. data/lib/axi/AXI4/packet_merge/axi4_merge.sv +60 -0
  68. data/lib/axi/AXI4/packet_merge/axi4_merge_rd.sv +279 -0
  69. data/lib/axi/AXI4/packet_merge/axi4_merge_wr.sv +267 -0
  70. data/lib/axi/AXI4/packet_partition/axi4_partition.sv +36 -0
  71. data/lib/axi/AXI4/packet_partition/axi4_partition_OD.sv +66 -0
  72. data/lib/axi/AXI4/packet_partition/axi4_partition_rd.sv +211 -0
  73. data/lib/axi/AXI4/packet_partition/axi4_partition_rd_OD.sv +322 -0
  74. data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.rb +80 -0
  75. data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +93 -0
  76. data/lib/axi/AXI4/packet_partition/axi4_partition_wr.sv +239 -0
  77. data/lib/axi/AXI4/packet_partition/axi4_partition_wr_OD.sv +302 -0
  78. data/lib/axi/AXI4/packet_partition/data_inf_partition.rb +293 -0
  79. data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +307 -0
  80. data/lib/axi/AXI4/vcs_axi4_array_comptable.sv +35 -0
  81. data/lib/axi/AXI4/vcs_axi4_comptable.sv +330 -0
  82. data/lib/axi/AXI4/wide_axis_to_axi4_wr.rb +149 -0
  83. data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +140 -0
  84. data/lib/axi/AXI4/width_convert/axi4_data_combin_aflag_pipe.sv +239 -0
  85. data/lib/axi/AXI4/width_convert/axi4_data_combin_aflag_pipe_A1.sv +204 -0
  86. data/lib/axi/AXI4/width_convert/axi4_data_convert.sv +312 -0
  87. data/lib/axi/AXI4/width_convert/axi4_data_convert_A1.sv +217 -0
  88. data/lib/axi/AXI4/width_convert/data_combin.sv +366 -0
  89. data/lib/axi/AXI4/width_convert/data_combin.sv.bak +290 -0
  90. data/lib/axi/AXI4/width_convert/data_destruct.sv +304 -0
  91. data/lib/axi/AXI4/width_convert/feed_check.sv +94 -0
  92. data/lib/axi/AXI4/width_convert/len_convert.sv.bak +61 -0
  93. data/lib/axi/AXI4/width_convert/odd_width_convert.sv +229 -0
  94. data/lib/axi/AXI4/width_convert/odd_width_convert_verb.sv +105 -0
  95. data/lib/axi/AXI4/width_convert/simple_data_pipe.sv +40 -0
  96. data/lib/axi/AXI4/width_convert/simple_data_pipe_slaver.sv +33 -0
  97. data/lib/axi/AXI4/width_convert/width_combin.sv +113 -0
  98. data/lib/axi/AXI4/width_convert/width_convert.sv +87 -0
  99. data/lib/axi/AXI4/width_convert/width_convert_verb.sv +249 -0
  100. data/lib/axi/AXI4/width_convert/width_destruct.sv +206 -0
  101. data/lib/axi/AXI4/width_convert/width_destruct_A1.sv +251 -0
  102. data/lib/axi/AXI_BFM/AXI_BFM_PKG.sv +1039 -0
  103. data/lib/axi/AXI_BFM/Data_C_BFM_PKG.sv +97 -0
  104. data/lib/axi/AXI_BFM/axi4_error_chk.sv +298 -0
  105. data/lib/axi/AXI_BFM/axi4_illegal_bfm_pkg.sv +607 -0
  106. data/lib/axi/AXI_BFM/axi_lite_master.sv +102 -0
  107. data/lib/axi/AXI_BFM/axi_lite_tb.sv +23 -0
  108. data/lib/axi/AXI_BFM/axi_master.sv +185 -0
  109. data/lib/axi/AXI_BFM/axi_mirror.sv +266 -0
  110. data/lib/axi/AXI_BFM/axi_mm_tb.sv +134 -0
  111. data/lib/axi/AXI_BFM/axi_slaver.sv.bak +340 -0
  112. data/lib/axi/AXI_BFM/axistreambfm.sv +117 -0
  113. data/lib/axi/AXI_Lite/axi4_to_lite.sv +36 -0
  114. data/lib/axi/AXI_Lite/axi_lite_configure.sv +356 -0
  115. data/lib/axi/AXI_Lite/axi_lite_configure_inf2.sv +365 -0
  116. data/lib/axi/AXI_Lite/axi_lite_configure_verb.sv.bck +370 -0
  117. data/lib/axi/AXI_Lite/axi_lite_interconnect_M2S.sv +437 -0
  118. data/lib/axi/AXI_Lite/axi_lite_interconnect_S2M.sv +359 -0
  119. data/lib/axi/AXI_Lite/axi_lite_interconnect_S2M.sv.bak +359 -0
  120. data/lib/axi/AXI_Lite/axi_lite_master_empty.sv +30 -0
  121. data/lib/axi/AXI_Lite/axi_lite_slaver_empty.sv +27 -0
  122. data/lib/axi/AXI_Lite/axil_direct.sv +52 -0
  123. data/lib/axi/AXI_Lite/common_configure_reg_interface/common_configure_reg_interface.sv +230 -0
  124. data/lib/axi/AXI_Lite/common_configure_reg_interface/common_configure_reg_interface.sv.bak +109 -0
  125. data/lib/axi/AXI_Lite/common_configure_reg_interface/jtag_to_axilite_wrapper.sv +56 -0
  126. data/lib/axi/AXI_Lite/gen_axi_lite_ctrl.sv +515 -0
  127. data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_C1.sv +369 -0
  128. data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_verb.sv +365 -0
  129. data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_verc.sv +401 -0
  130. data/lib/axi/AXI_Lite/wr_lite_to_axis.sv +141 -0
  131. data/lib/axi/AXI_Lite/wr_lite_to_axis.sv.bak +141 -0
  132. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S.sv +76 -0
  133. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_A1.sv +77 -0
  134. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_A2.sv +71 -0
  135. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_bind_tuser.sv +72 -0
  136. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_noaddr.sv +151 -0
  137. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_with_addr.sv +87 -0
  138. data/lib/axi/AXI_stream/axi_stream_interconnect_S2M.sv +65 -0
  139. data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_auto.sv +50 -0
  140. data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_with_info.sv +64 -0
  141. data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_with_keep.sv.bak +64 -0
  142. data/lib/axi/AXI_stream/axi_stream_packet_fifo_with_info.sv.bak +49 -0
  143. data/lib/axi/AXI_stream/axi_stream_partition.sv +147 -0
  144. data/lib/axi/AXI_stream/axi_stream_partition_A1.sv +63 -0
  145. data/lib/axi/AXI_stream/axi_stream_planer.sv +51 -0
  146. data/lib/axi/AXI_stream/axi_stream_split_channel.rb +56 -0
  147. data/lib/axi/AXI_stream/axi_stream_split_channel.sv +149 -0
  148. data/lib/axi/AXI_stream/axi_streams_combin.sv +151 -0
  149. data/lib/axi/AXI_stream/axi_streams_combin_A1.sv +179 -0
  150. data/lib/axi/AXI_stream/axi_streams_scaler.sv +171 -0
  151. data/lib/axi/AXI_stream/axi_streams_scaler_A1.sv +179 -0
  152. data/lib/axi/AXI_stream/axis_append.sv +79 -0
  153. data/lib/axi/AXI_stream/axis_append_A1.sv +82 -0
  154. data/lib/axi/AXI_stream/axis_base_pipe.sv +184 -0
  155. data/lib/axi/AXI_stream/axis_combin_with_fifo.sv +69 -0
  156. data/lib/axi/AXI_stream/axis_connect_pipe.sv +86 -0
  157. data/lib/axi/AXI_stream/axis_connect_pipe_A1.sv.bak +170 -0
  158. data/lib/axi/AXI_stream/axis_connect_pipe_left_shift.sv +64 -0
  159. data/lib/axi/AXI_stream/axis_connect_pipe_right_shift.sv +64 -0
  160. data/lib/axi/AXI_stream/axis_connect_pipe_right_shift_verb.sv +70 -0
  161. data/lib/axi/AXI_stream/axis_connect_pipe_with_info.sv +93 -0
  162. data/lib/axi/AXI_stream/axis_direct.sv +55 -0
  163. data/lib/axi/AXI_stream/axis_direct_A1.sv +81 -0
  164. data/lib/axi/AXI_stream/axis_filter.sv +38 -0
  165. data/lib/axi/AXI_stream/axis_full_to_data_c.sv +26 -0
  166. data/lib/axi/AXI_stream/axis_head_cut.sv +67 -0
  167. data/lib/axi/AXI_stream/axis_head_cut_verb.sv +60 -0
  168. data/lib/axi/AXI_stream/axis_head_cut_verc.rb +175 -0
  169. data/lib/axi/AXI_stream/axis_head_cut_verc.sv +245 -0
  170. data/lib/axi/AXI_stream/axis_inct_s2m_with_flag.sv +84 -0
  171. data/lib/axi/AXI_stream/axis_insert_copy.rb +59 -0
  172. data/lib/axi/AXI_stream/axis_insert_copy.sv +66 -0
  173. data/lib/axi/AXI_stream/axis_intc_M2S_with_addr_inf.sv +114 -0
  174. data/lib/axi/AXI_stream/axis_intc_S2M_with_addr_inf.sv +85 -0
  175. data/lib/axi/AXI_stream/axis_interconnect_S2M_pipe.sv +75 -0
  176. data/lib/axi/AXI_stream/axis_length_cut.sv +64 -0
  177. data/lib/axi/AXI_stream/axis_length_fill.sv +194 -0
  178. data/lib/axi/AXI_stream/axis_length_split.sv +86 -0
  179. data/lib/axi/AXI_stream/axis_length_split_with_addr.sv +127 -0
  180. data/lib/axi/AXI_stream/axis_length_split_writh_user.sv +87 -0
  181. data/lib/axi/AXI_stream/axis_link_trigger.sv +81 -0
  182. data/lib/axi/AXI_stream/axis_master_empty.sv +26 -0
  183. data/lib/axi/AXI_stream/axis_mirror_to_master.sv +126 -0
  184. data/lib/axi/AXI_stream/axis_mirrors.sv +60 -0
  185. data/lib/axi/AXI_stream/axis_orthogonal.sv +66 -0
  186. data/lib/axi/AXI_stream/axis_ram_buffer.sv +118 -0
  187. data/lib/axi/AXI_stream/axis_rom_contect.rb +97 -0
  188. data/lib/axi/AXI_stream/axis_rom_contect.sv +110 -0
  189. data/lib/axi/AXI_stream/axis_rom_contect_sim.rb +102 -0
  190. data/lib/axi/AXI_stream/axis_rom_contect_sim.sv +113 -0
  191. data/lib/axi/AXI_stream/axis_slaver_empty.sv +22 -0
  192. data/lib/axi/AXI_stream/axis_slaver_pipe.sv +84 -0
  193. data/lib/axi/AXI_stream/axis_slaver_pipe_A1.sv +54 -0
  194. data/lib/axi/AXI_stream/axis_slaver_vector_empty.sv +27 -0
  195. data/lib/axi/AXI_stream/axis_split_channel_verb.rb +42 -0
  196. data/lib/axi/AXI_stream/axis_split_channel_verb.sv +62 -0
  197. data/lib/axi/AXI_stream/axis_to_axi4_or_lite.rb +127 -0
  198. data/lib/axi/AXI_stream/axis_to_axi4_or_lite.sv +153 -0
  199. data/lib/axi/AXI_stream/axis_to_data_inf.sv +34 -0
  200. data/lib/axi/AXI_stream/axis_to_lite_rd.sv +81 -0
  201. data/lib/axi/AXI_stream/axis_to_lite_wr.sv +71 -0
  202. data/lib/axi/AXI_stream/axis_uncompress.sv +147 -0
  203. data/lib/axi/AXI_stream/axis_uncompress_A1.sv +150 -0
  204. data/lib/axi/AXI_stream/axis_uncompress_verb.rb +32 -0
  205. data/lib/axi/AXI_stream/axis_uncompress_verb.sv +54 -0
  206. data/lib/axi/AXI_stream/axis_valve.sv +29 -0
  207. data/lib/axi/AXI_stream/axis_valve_with_pipe.sv +76 -0
  208. data/lib/axi/AXI_stream/axis_vector_master_empty.rb +11 -0
  209. data/lib/axi/AXI_stream/axis_vector_master_empty.sv +35 -0
  210. data/lib/axi/AXI_stream/axis_vector_slaver_empty.rb +11 -0
  211. data/lib/axi/AXI_stream/axis_vector_slaver_empty.sv +35 -0
  212. data/lib/axi/AXI_stream/check_stream_crc.sv +28 -0
  213. data/lib/axi/AXI_stream/data_c_to_axis_full.sv +23 -0
  214. data/lib/axi/AXI_stream/data_to_axis_inf.sv +103 -0
  215. data/lib/axi/AXI_stream/data_to_axis_inf_A1.sv +28 -0
  216. data/lib/axi/AXI_stream/data_width/axis_width_combin.sv +204 -0
  217. data/lib/axi/AXI_stream/data_width/axis_width_combin_A1.sv +220 -0
  218. data/lib/axi/AXI_stream/data_width/axis_width_convert.sv +49 -0
  219. data/lib/axi/AXI_stream/data_width/axis_width_destruct.sv +82 -0
  220. data/lib/axi/AXI_stream/data_width/axis_width_destruct_A1.sv +86 -0
  221. data/lib/axi/AXI_stream/ex_status/axis_ex_status.sv +97 -0
  222. data/lib/axi/AXI_stream/gen_big_field_table.sv +170 -0
  223. data/lib/axi/AXI_stream/gen_common_frame_table.sv +382 -0
  224. data/lib/axi/AXI_stream/gen_common_frame_table_bind_tuser.sv +428 -0
  225. data/lib/axi/AXI_stream/gen_origin_axis.sv +116 -0
  226. data/lib/axi/AXI_stream/gen_origin_axis_A1.sv +129 -0
  227. data/lib/axi/AXI_stream/gen_origin_axis_A2.sv +162 -0
  228. data/lib/axi/AXI_stream/gen_simple_axis.sv +164 -0
  229. data/lib/axi/AXI_stream/packet_fifo/axi_stream_long_fifo.sv +132 -0
  230. data/lib/axi/AXI_stream/packet_fifo/axi_stream_long_fifo_verb.sv +140 -0
  231. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo.sv +125 -0
  232. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1.sv +142 -0
  233. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1E.sv +198 -0
  234. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_verb.sv +120 -0
  235. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_with_info.sv +49 -0
  236. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_long_fifo.sv +197 -0
  237. data/lib/axi/AXI_stream/packet_fifo/axi_stream_wide_fifo.sv +141 -0
  238. data/lib/axi/AXI_stream/packet_fifo/axis_pkt_fifo_filter_keep.sv +164 -0
  239. data/lib/axi/AXI_stream/packet_fifo/axis_pkt_fifo_filter_keep_A1.sv +166 -0
  240. data/lib/axi/AXI_stream/parse_big_field_table.sv +164 -0
  241. data/lib/axi/AXI_stream/parse_big_field_table_A1.sv +162 -0
  242. data/lib/axi/AXI_stream/parse_big_field_table_A2.sv +165 -0
  243. data/lib/axi/AXI_stream/parse_big_field_table_verb.sv +118 -0
  244. data/lib/axi/AXI_stream/parse_common_frame_table.sv +202 -0
  245. data/lib/axi/AXI_stream/parse_common_frame_table_A1.sv +521 -0
  246. data/lib/axi/AXI_stream/parse_common_frame_table_A2.sv +561 -0
  247. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache.sv +46 -0
  248. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_35bit.sv +122 -0
  249. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_36_71bit.sv +71 -0
  250. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_72_95bit.sv +96 -0
  251. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_72_95bit_with_keep.sv +99 -0
  252. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_96_143bit.sv +119 -0
  253. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_A1.sv +49 -0
  254. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_B1.sv +82 -0
  255. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_mirror.sv +44 -0
  256. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_verb.sv +58 -0
  257. data/lib/axi/AXI_stream/stream_cache/axi_stream_long_cache.sv +55 -0
  258. data/lib/axi/AXI_stream/stream_crc.sv +67 -0
  259. data/lib/axi/AXI_stream/vcs_axis_comptable.sv +73 -0
  260. data/lib/axi/LICENSE +504 -0
  261. data/lib/axi/ReadME.md +6 -0
  262. data/lib/axi/SIM/tb_axi4_partition_20201105.sv +115 -0
  263. data/lib/axi/SIM/tb_axis_bfm_0504.sv +61 -0
  264. data/lib/axi/SIM/tb_axis_partitiom_0929.sv +102 -0
  265. data/lib/axi/SIM/tb_axis_s2m_pipe_1023.sv +163 -0
  266. data/lib/axi/SIM/tb_axis_to_axi4_0925.sv +107 -0
  267. data/lib/axi/SIM/tb_data_c_m2s_inf_20200114.sv +222 -0
  268. data/lib/axi/SIM/tb_data_c_m2s_inf_20201103.sv +245 -0
  269. data/lib/axi/SIM/tb_data_c_pipe_inf_20180417.sv +114 -0
  270. data/lib/axi/SIM/tb_wide_axis_to_axi4_wr.sv +81 -0
  271. data/lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip.sv +589 -0
  272. data/lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip_C1.sv +69 -0
  273. data/lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip_verb.sv +388 -0
  274. data/lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip_verc.sv +70 -0
  275. data/lib/axi/axi4_to_xilinx_ddr_native/ddr3_ip_native_to_axi4.sv +194 -0
  276. data/lib/axi/axi4_to_xilinx_ddr_native/ddr3_ip_wrapper_sim.sv +99 -0
  277. data/lib/axi/axi4_to_xilinx_ddr_native/ddr_axi4_to_axis.sv +188 -0
  278. data/lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo.sv +156 -0
  279. data/lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo_A1.sv +180 -0
  280. data/lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo_verb.sv +269 -0
  281. data/lib/axi/axi4_to_xilinx_ddr_native/model_ddr_ip_app.sv +303 -0
  282. data/lib/axi/axi4_to_xilinx_ddr_native/tb_ddr3_ip_wrapper_sim.sv +154 -0
  283. data/lib/axi/cfg.yml +15 -0
  284. data/lib/axi/common/ClockSameDomain.sv +128 -0
  285. data/lib/axi/common/common_ram_sim_wrapper.rb +66 -0
  286. data/lib/axi/common/common_ram_sim_wrapper.sv +75 -0
  287. data/lib/axi/common/common_ram_wrapper.rb +71 -0
  288. data/lib/axi/common/common_ram_wrapper.sv +82 -0
  289. data/lib/axi/common/data_c_interface_dram.rb +90 -0
  290. data/lib/axi/common/data_c_interface_dram.sv +106 -0
  291. data/lib/axi/common/mem_format.coe +60 -0
  292. data/lib/axi/common/pipe_vld.sv +45 -0
  293. data/lib/axi/common/test_write_mem.sv +22 -0
  294. data/lib/axi/common/xilinx_hdl_dpram.sv +142 -0
  295. data/lib/axi/common/xilinx_hdl_dpram_sim.sv +176 -0
  296. data/lib/axi/common_fifo/common_fifo.sv +165 -0
  297. data/lib/axi/common_fifo/common_stack.sv +56 -0
  298. data/lib/axi/common_fifo/independent_clock_fifo.sv +200 -0
  299. data/lib/axi/common_fifo/independent_clock_fifo_a1.sv +202 -0
  300. data/lib/axi/common_fifo/independent_stack.sv +85 -0
  301. data/lib/axi/data_interface/data_connect_pipe.sv +228 -0
  302. data/lib/axi/data_interface/data_inf_A2B.sv +21 -0
  303. data/lib/axi/data_interface/data_inf_B2A.sv +21 -0
  304. data/lib/axi/data_interface/data_inf_c/data_bind.sv +74 -0
  305. data/lib/axi/data_interface/data_inf_c/data_c_cache.sv +49 -0
  306. data/lib/axi/data_interface/data_inf_c/data_c_direct.sv +51 -0
  307. data/lib/axi/data_interface/data_inf_c/data_c_direct_mirror.sv +28 -0
  308. data/lib/axi/data_interface/data_inf_c/data_c_intc_M2S_force_robin.rb.bak +268 -0
  309. data/lib/axi/data_interface/data_inf_c/data_c_intc_M2S_force_robin.sv +301 -0
  310. data/lib/axi/data_interface/data_inf_c/data_c_pipe_force_vld.sv +57 -0
  311. data/lib/axi/data_interface/data_inf_c/data_c_pipe_force_vld_bind_data.sv +81 -0
  312. data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf.sv +130 -0
  313. data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf_A1.sv +135 -0
  314. data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf_left_shift.sv +158 -0
  315. data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf_right_shift.sv +155 -0
  316. data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf_right_shift_verb.sv +174 -0
  317. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_C1.sv +296 -0
  318. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_C1_with_id.sv +58 -0
  319. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_best_last.sv +319 -0
  320. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_best_robin.sv +293 -0
  321. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_robin.sv +296 -0
  322. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_robin_with_id.sv +46 -0
  323. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_verc.sv +405 -0
  324. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_verc_with_addr.sv +226 -0
  325. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_verc_with_id.sv +54 -0
  326. data/lib/axi/data_interface/data_inf_c/data_c_pipe_latency.sv +68 -0
  327. data/lib/axi/data_interface/data_inf_c/data_c_scaler.sv +326 -0
  328. data/lib/axi/data_interface/data_inf_c/data_c_scaler_A1.sv +333 -0
  329. data/lib/axi/data_interface/data_inf_c/data_c_tmp_cache.sv +44 -0
  330. data/lib/axi/data_interface/data_inf_c/data_condition_mirror.sv +64 -0
  331. data/lib/axi/data_interface/data_inf_c/data_condition_valve.sv +53 -0
  332. data/lib/axi/data_interface/data_inf_c/data_connect_pipe_inf.sv +73 -0
  333. data/lib/axi/data_interface/data_inf_c/data_inf_c_M2S_with_addr_and_id.sv +66 -0
  334. data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_M2S_with_id.sv +67 -0
  335. data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_S2M.sv +70 -0
  336. data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_S2M_A1.sv +72 -0
  337. data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_S2M_with_lazy.sv +49 -0
  338. data/lib/axi/data_interface/data_inf_c/data_inf_c_interconnect_M2S.sv +50 -0
  339. data/lib/axi/data_interface/data_inf_c/data_inf_c_pipe_condition.sv +33 -0
  340. data/lib/axi/data_interface/data_inf_c/data_inf_c_planer.sv +50 -0
  341. data/lib/axi/data_interface/data_inf_c/data_inf_c_planer_A1.sv +53 -0
  342. data/lib/axi/data_interface/data_inf_c/data_intc_M2S_force_robin.sv +31 -0
  343. data/lib/axi/data_interface/data_inf_c/data_mirrors.sv +108 -0
  344. data/lib/axi/data_interface/data_inf_c/data_mirrors_verb.sv.bak +101 -0
  345. data/lib/axi/data_interface/data_inf_c/data_uncompress.sv +150 -0
  346. data/lib/axi/data_interface/data_inf_c/data_valve.sv +26 -0
  347. data/lib/axi/data_interface/data_inf_c/next_prio.sv +42 -0
  348. data/lib/axi/data_interface/data_inf_c/trigger_data_inf_c.sv +51 -0
  349. data/lib/axi/data_interface/data_inf_c/trigger_data_inf_c_A1.sv +54 -0
  350. data/lib/axi/data_interface/data_inf_c/trigger_ready_ctrl.sv +33 -0
  351. data/lib/axi/data_interface/data_inf_c/vcs_data_c_comptable.sv +40 -0
  352. data/lib/axi/data_interface/data_inf_cross_clk.sv +40 -0
  353. data/lib/axi/data_interface/data_inf_intc_M2S_force_addr_with_id.sv +62 -0
  354. data/lib/axi/data_interface/data_inf_intc_M2S_prio.sv +152 -0
  355. data/lib/axi/data_interface/data_inf_intc_M2S_prio_with_id.sv +55 -0
  356. data/lib/axi/data_interface/data_inf_interconnect_M2S_noaddr.sv +136 -0
  357. data/lib/axi/data_interface/data_inf_interconnect_M2S_with_id_noaddr.sv +55 -0
  358. data/lib/axi/data_interface/data_inf_planer.sv +59 -0
  359. data/lib/axi/data_interface/data_inf_planer_A1.sv +66 -0
  360. data/lib/axi/data_interface/data_inf_ticktock.sv +154 -0
  361. data/lib/axi/data_interface/data_interface.sv +91 -0
  362. data/lib/axi/data_interface/data_interface_pkg.sv +79 -0
  363. data/lib/axi/data_interface/data_pair_map.sv +152 -0
  364. data/lib/axi/data_interface/data_pair_map_A1.sv +159 -0
  365. data/lib/axi/data_interface/data_pair_map_A2.sv +212 -0
  366. data/lib/axi/data_interface/data_pipe_intc_M2S_addr.sv.bak +231 -0
  367. data/lib/axi/data_interface/data_pipe_interconnect.sv +290 -0
  368. data/lib/axi/data_interface/data_pipe_interconnect_M2S.sv +236 -0
  369. data/lib/axi/data_interface/data_pipe_interconnect_M2S.sv.bak1012 +237 -0
  370. data/lib/axi/data_interface/data_pipe_interconnect_M2S_A1.sv +241 -0
  371. data/lib/axi/data_interface/data_pipe_interconnect_M2S_verb.sv +302 -0
  372. data/lib/axi/data_interface/data_pipe_interconnect_M2S_verb.sv.bad_work +280 -0
  373. data/lib/axi/data_interface/data_pipe_interconnect_S2M.sv +332 -0
  374. data/lib/axi/data_interface/data_pipe_interconnect_S2M_A1.sv +376 -0
  375. data/lib/axi/data_interface/data_pipe_interconnect_S2M_verb.sv +265 -0
  376. data/lib/axi/data_interface/data_streams_combin.sv +592 -0
  377. data/lib/axi/data_interface/data_streams_combin_A1.sv +621 -0
  378. data/lib/axi/data_interface/data_streams_scaler.sv +593 -0
  379. data/lib/axi/data_interface/datainf_c_master_empty.sv +22 -0
  380. data/lib/axi/data_interface/datainf_c_slaver_empty.sv +22 -0
  381. data/lib/axi/data_interface/datainf_master_empty.sv +22 -0
  382. data/lib/axi/data_interface/datainf_slaver_empty.sv +22 -0
  383. data/lib/axi/data_interface/part_data_pair_map.sv +111 -0
  384. data/lib/axi/interface_define/axi_aux_inf.sv +206 -0
  385. data/lib/axi/interface_define/axi_inf.sv +1256 -0
  386. data/lib/axi/interface_define/axi_inf_verb.sv +42 -0
  387. data/lib/axi/interface_define/axi_interface_instance.svo +13 -0
  388. data/lib/axi/interface_define/axi_lite_inf.sv +345 -0
  389. data/lib/axi/interface_define/axi_stream_inf.sv +108 -0
  390. data/lib/axi/interface_define/bak/axi_aux_inf.sv +206 -0
  391. data/lib/axi/interface_define/bak/axi_inf_verb.sv +42 -0
  392. data/lib/axi/interface_define/bak/axi_interface_instance.svo +13 -0
  393. data/lib/axi/interface_define/bak/microblaze_inf.sv +136 -0
  394. data/lib/axi/interface_define/bak/xilinx_axi4_to_axi4.sv +87 -0
  395. data/lib/axi/interface_define/bak/xilinx_lite_to_lite.sv +128 -0
  396. data/lib/axi/interface_define/lite_inf2_to_inf.sv +38 -0
  397. data/lib/axi/interface_define/xilinx_axi4_to_axi4.sv +87 -0
  398. data/lib/axi/interface_define/xilinx_lite_to_lite.sv +128 -0
  399. data/lib/axi/macro/axil_macro.sv +132 -0
  400. data/lib/axi/macro/bak/axi4_base_files_add_to_vivado.tcl +28 -0
  401. data/lib/axi/macro/bak/axi_macro.sv +15 -0
  402. data/lib/axi/macro/bak/axis_base_files_add_to_vivado.tcl +26 -0
  403. data/lib/axi/macro/bak/base_files_add_to_vivado.tcl +24 -0
  404. data/lib/axi/macro/bak/data_inf_base_files_add_to_vivado.tcl +22 -0
  405. data/lib/axi/macro/bak/lite_inf_base_files_add_to_vivado.tcl +4 -0
  406. data/lib/axi/macro/bak/standard_tcl.rb +28 -0
  407. data/lib/axi/macro/bak/system_macro.sv +19 -0
  408. data/lib/axi/macro/bak/tcl_axi4_base_files_add_to_vivado.tcl +28 -0
  409. data/lib/axi/macro/bak/tcl_axis_base_files_add_to_vivado.tcl +26 -0
  410. data/lib/axi/macro/bak/tcl_base_files_add_to_vivado.tcl +24 -0
  411. data/lib/axi/macro/bak/tcl_data_inf_base_files_add_to_vivado.tcl +22 -0
  412. data/lib/axi/macro/bak/tcl_lite_inf_base_files_add_to_vivado.tcl +4 -0
  413. data/lib/axi/macro/bak/tcl_tmp.tcl +12 -0
  414. data/lib/axi/macro/bak/tmp.tcl +13 -0
  415. data/lib/axi/platform_ip/fifo_10_18bit_long.sv +125 -0
  416. data/lib/axi/platform_ip/fifo_145_216bit_A1.sv +167 -0
  417. data/lib/axi/platform_ip/fifo_217_288bit_A1.sv +191 -0
  418. data/lib/axi/platform_ip/fifo_36bit.sv +77 -0
  419. data/lib/axi/platform_ip/fifo_36bit_A1.sv +113 -0
  420. data/lib/axi/platform_ip/fifo_36kb_long.sv +145 -0
  421. data/lib/axi/platform_ip/fifo_37_72bit.sv +77 -0
  422. data/lib/axi/platform_ip/fifo_505_576bit_A1.sv +141 -0
  423. data/lib/axi/platform_ip/fifo_73_96bit.sv +102 -0
  424. data/lib/axi/platform_ip/fifo_97_144bit.sv +102 -0
  425. data/lib/axi/platform_ip/fifo_97_144bit_A1.sv +133 -0
  426. data/lib/axi/platform_ip/fifo_ku.sv +212 -0
  427. data/lib/axi/platform_ip/fifo_ku.sv.bak +488 -0
  428. data/lib/axi/platform_ip/fifo_ku_18bit.sv +138 -0
  429. data/lib/axi/platform_ip/fifo_ku_36bit.sv +148 -0
  430. data/lib/axi/platform_ip/fifo_ku_36kb_long.sv +135 -0
  431. data/lib/axi/platform_ip/fifo_ku_xbit_8192.sv.bak +107 -0
  432. data/lib/axi/platform_ip/fifo_wr_rd_mark.sv +94 -0
  433. data/lib/axi/platform_ip/ku_long_fifo_4bit.sv +189 -0
  434. data/lib/axi/platform_ip/long_fifo.sv +72 -0
  435. data/lib/axi/platform_ip/long_fifo_4bit.sv +156 -0
  436. data/lib/axi/platform_ip/long_fifo_4bit_8192.sv +133 -0
  437. data/lib/axi/platform_ip/long_fifo_4bit_SL8192.sv +133 -0
  438. data/lib/axi/platform_ip/long_fifo_verb.sv +110 -0
  439. data/lib/axi/platform_ip/wide_fifo.sv +66 -0
  440. data/lib/axi/platform_ip/wide_fifo_7series.sv +136 -0
  441. data/lib/axi/platform_ip/xilinx_fifo.sv +174 -0
  442. data/lib/axi/platform_ip/xilinx_fifo_A1.sv +223 -0
  443. data/lib/axi/platform_ip/xilinx_fifo_verb.sv +87 -0
  444. data/lib/axi/platform_ip/xilinx_fifo_verc.sv +87 -0
  445. data/lib/axi/platform_ip/xilinx_stream_packet_fifo_ip.sv +40 -0
  446. data/lib/axi/top/axi4_data_convert_2_20_tb.sv +126 -0
  447. data/lib/axi/top/axi4_data_convert_5_24_tb.sv +156 -0
  448. data/lib/axi/top/axi4_interconnnect_2_24_tb.sv +143 -0
  449. data/lib/axi/top/axi4_interconnnect_5_23_tb.sv +155 -0
  450. data/lib/axi/top/axi4_merge_tb_0331.sv +120 -0
  451. data/lib/axi/top/axi4_packet_fifo_2_28_tb.sv +107 -0
  452. data/lib/axi/top/axi4_partition_2_23_tb.sv +93 -0
  453. data/lib/axi/top/axi_stream_packet_fifo_2_28_tb.sv +78 -0
  454. data/lib/axi/top/axis_length_cut_2_28_tb.sv +79 -0
  455. data/lib/axi/top/axis_length_fill_8_18_tb.sv +81 -0
  456. data/lib/axi/top/common_fifo_2_27_tb.sv +77 -0
  457. data/lib/axi/top/data_convert_2_16_tb.sv +162 -0
  458. data/lib/axi/top/independent_fifo_2_27_tb.sv +90 -0
  459. data/lib/axi/top/long_to_wide_3_1_tb.sv +142 -0
  460. data/lib/axi/top/odd_width_convert_tb_420.sv +83 -0
  461. data/lib/axi/top/tb_axis_m2s_A1_0115.sv +158 -0
  462. data/lib/axi/top/tb_axis_width_combin_0913.sv +57 -0
  463. data/lib/axi/top/tb_axis_width_test_0914.sv +115 -0
  464. data/lib/axi/top/tb_data_c_inf_M2S_0823.sv +154 -0
  465. data/lib/axi/top/tb_data_c_inf_M2S_addr_0824.sv +252 -0
  466. data/lib/axi/top/tb_data_c_pipe_force_vld_1228.sv +96 -0
  467. data/lib/axi/top/tb_data_c_scaler_20180413.sv +187 -0
  468. data/lib/axi/top/tb_data_intc_S2M_0807.sv +168 -0
  469. data/lib/axi/top/tb_test_ku_fifo_0919.sv +98 -0
  470. data/lib/axi/top/width_convert_verb_tb_523.sv +68 -0
  471. data/lib/axi/video/video_stream_2_axi_stream.sv +90 -0
  472. data/lib/axi/video_interface/video_interface.sv +173 -0
  473. data/lib/axi_tdl.rb +6 -0
  474. data/lib/axi_tdl/version.rb +3 -0
  475. data/lib/spec/spec_helper.rb +100 -0
  476. data/lib/tdl/LICENSE +504 -0
  477. data/lib/tdl/Logic/Logic.tar.gz +0 -0
  478. data/lib/tdl/Logic/clock_rst_verb_auto.rb +99 -0
  479. data/lib/tdl/Logic/logic_edge.rb +194 -0
  480. data/lib/tdl/Logic/logic_latency.rb +197 -0
  481. data/lib/tdl/Logic/logic_main.rb +188 -0
  482. data/lib/tdl/Logic/logic_operator.rb.bak +128 -0
  483. data/lib/tdl/Logic/mdio_model_auto.rb +77 -0
  484. data/lib/tdl/Logic/path_lib.rb +7 -0
  485. data/lib/tdl/Logic/redefine_operator.rb +28 -0
  486. data/lib/tdl/ReadMe.md +295 -0
  487. data/lib/tdl/SDL/axi4/AXI4_interconnect_M2S_sdl.rb +10 -0
  488. data/lib/tdl/SDL/axi4/axi4_combin_wr_rd_batch_sdl.rb +10 -0
  489. data/lib/tdl/SDL/axi4/axi4_data_combin_aflag_pipe_A1_sdl.rb +38 -0
  490. data/lib/tdl/SDL/axi4/axi4_data_combin_aflag_pipe_sdl.rb +37 -0
  491. data/lib/tdl/SDL/axi4/axi4_data_convert_A1_sdl.rb +9 -0
  492. data/lib/tdl/SDL/axi4/axi4_data_convert_sdl.rb +9 -0
  493. data/lib/tdl/SDL/axi4/axi4_direct_A1_sdl.rb +14 -0
  494. data/lib/tdl/SDL/axi4/axi4_direct_B1_sdl.rb +9 -0
  495. data/lib/tdl/SDL/axi4/axi4_direct_sdl.rb +14 -0
  496. data/lib/tdl/SDL/axi4/axi4_direct_verb_sdl.rb +9 -0
  497. data/lib/tdl/SDL/axi4/axi4_direct_verc_sdl.rb +16 -0
  498. data/lib/tdl/SDL/axi4/axi4_long_to_axi4_wide_A1_sdl.rb +10 -0
  499. data/lib/tdl/SDL/axi4/axi4_long_to_axi4_wide_sdl.rb +9 -0
  500. data/lib/tdl/SDL/axi4/axi4_long_to_axi4_wide_track_sdl.rb +9 -0
  501. data/lib/tdl/SDL/axi4/axi4_long_to_axi4_wide_verb_sdl.rb +11 -0
  502. data/lib/tdl/SDL/axi4/axi4_merge_rd_sdl.rb +10 -0
  503. data/lib/tdl/SDL/axi4/axi4_merge_sdl.rb +10 -0
  504. data/lib/tdl/SDL/axi4/axi4_merge_wr_sdl.rb +10 -0
  505. data/lib/tdl/SDL/axi4/axi4_mix_interconnect_M2S_sdl.rb +10 -0
  506. data/lib/tdl/SDL/axi4/axi4_packet_fifo_sdl.rb +12 -0
  507. data/lib/tdl/SDL/axi4/axi4_partition_OD_sdl.rb +11 -0
  508. data/lib/tdl/SDL/axi4/axi4_partition_rd_OD_sdl.rb +10 -0
  509. data/lib/tdl/SDL/axi4/axi4_partition_rd_sdl.rb +11 -0
  510. data/lib/tdl/SDL/axi4/axi4_partition_sdl.rb +11 -0
  511. data/lib/tdl/SDL/axi4/axi4_partition_wr_OD_sdl.rb +10 -0
  512. data/lib/tdl/SDL/axi4/axi4_partition_wr_sdl.rb +11 -0
  513. data/lib/tdl/SDL/axi4/axi4_pipe_sdl.rb +9 -0
  514. data/lib/tdl/SDL/axi4/axi4_pipe_verb_sdl.rb +9 -0
  515. data/lib/tdl/SDL/axi4/axi4_rd_auxiliary_batch_gen_sdl.rb +11 -0
  516. data/lib/tdl/SDL/axi4/axi4_rd_auxiliary_gen_A1_sdl.rb +9 -0
  517. data/lib/tdl/SDL/axi4/axi4_rd_auxiliary_gen_sdl.rb +9 -0
  518. data/lib/tdl/SDL/axi4/axi4_rd_burst_track_sdl.rb +10 -0
  519. data/lib/tdl/SDL/axi4/axi4_rd_interconnect_M2S_sdl.rb +10 -0
  520. data/lib/tdl/SDL/axi4/axi4_rd_mix_interconnect_M2S_A1_sdl.rb +10 -0
  521. data/lib/tdl/SDL/axi4/axi4_rd_mix_interconnect_M2S_A2_sdl.rb +10 -0
  522. data/lib/tdl/SDL/axi4/axi4_rd_mix_interconnect_M2S_sdl.rb +10 -0
  523. data/lib/tdl/SDL/axi4/axi4_rd_packet_fifo_sdl.rb +11 -0
  524. data/lib/tdl/SDL/axi4/axi4_rd_pipe_sdl.rb +9 -0
  525. data/lib/tdl/SDL/axi4/axi4_rd_pipe_verb_sdl.rb +9 -0
  526. data/lib/tdl/SDL/axi4/axi4_wr_aux_bind_data_sdl.rb +9 -0
  527. data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_batch_gen_sdl.rb +11 -0
  528. data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_gen_sdl.rb +10 -0
  529. data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_gen_without_resp_sdl.rb +10 -0
  530. data/lib/tdl/SDL/axi4/axi4_wr_burst_track_sdl.rb +10 -0
  531. data/lib/tdl/SDL/axi4/axi4_wr_interconnect_M2S_A1_sdl.rb +10 -0
  532. data/lib/tdl/SDL/axi4/axi4_wr_interconnect_M2S_sdl.rb +10 -0
  533. data/lib/tdl/SDL/axi4/axi4_wr_mix_interconnect_M2S_sdl.rb +10 -0
  534. data/lib/tdl/SDL/axi4/axi4_wr_packet_fifo_sdl.rb +11 -0
  535. data/lib/tdl/SDL/axi4/axi4_wr_pipe_sdl.rb +9 -0
  536. data/lib/tdl/SDL/axi4/axi4_wr_pipe_verb_sdl.rb +9 -0
  537. data/lib/tdl/SDL/axi4/axi_stream_add_addr_len_sdl.rb +11 -0
  538. data/lib/tdl/SDL/axi4/axi_stream_to_axi4_wr_sdl.rb +9 -0
  539. data/lib/tdl/SDL/axi4/data_combin_sdl.rb +20 -0
  540. data/lib/tdl/SDL/axi4/data_destruct_sdl.rb +19 -0
  541. data/lib/tdl/SDL/axi4/feed_check_sdl.rb +18 -0
  542. data/lib/tdl/SDL/axi4/full_axi4_to_axis_partition_wr_rd_sdl.rb +11 -0
  543. data/lib/tdl/SDL/axi4/full_axi4_to_axis_sdl.rb +10 -0
  544. data/lib/tdl/SDL/axi4/id_record_sdl.rb +19 -0
  545. data/lib/tdl/SDL/axi4/idata_pool_axi4_sdl.rb +18 -0
  546. data/lib/tdl/SDL/axi4/odata_pool_axi4_A1_sdl.rb +13 -0
  547. data/lib/tdl/SDL/axi4/odata_pool_axi4_A2_sdl.rb +10 -0
  548. data/lib/tdl/SDL/axi4/odata_pool_axi4_sdl.rb +19 -0
  549. data/lib/tdl/SDL/axi4/odd_width_convert_sdl.rb +19 -0
  550. data/lib/tdl/SDL/axi4/odd_width_convert_verb_sdl.rb +19 -0
  551. data/lib/tdl/SDL/axi4/simple_data_pipe_sdl.rb +16 -0
  552. data/lib/tdl/SDL/axi4/simple_data_pipe_slaver_sdl.rb +16 -0
  553. data/lib/tdl/SDL/axi4/vcs_axi4_array_comptable.rb +9 -0
  554. data/lib/tdl/SDL/axi4/vcs_axi4_array_comptable_sdl.rb +10 -0
  555. data/lib/tdl/SDL/axi4/vcs_axi4_comptable.rb +8 -0
  556. data/lib/tdl/SDL/axi4/vcs_axi4_comptable_sdl.rb +9 -0
  557. data/lib/tdl/SDL/axi4/width_combin_sdl.rb +20 -0
  558. data/lib/tdl/SDL/axi4/width_convert_sdl.rb +20 -0
  559. data/lib/tdl/SDL/axi4/width_convert_verb_sdl.rb +20 -0
  560. data/lib/tdl/SDL/axi4/width_destruct_A1_sdl.rb +22 -0
  561. data/lib/tdl/SDL/axi4/width_destruct_sdl.rb +19 -0
  562. data/lib/tdl/SDL/axistream/axi_stream_cache_35bit_sdl.rb +9 -0
  563. data/lib/tdl/SDL/axistream/axi_stream_cache_36_71bit_sdl.rb +9 -0
  564. data/lib/tdl/SDL/axistream/axi_stream_cache_72_95bit_sdl.rb +9 -0
  565. data/lib/tdl/SDL/axistream/axi_stream_cache_72_95bit_with_keep_sdl.rb +9 -0
  566. data/lib/tdl/SDL/axistream/axi_stream_cache_96_143bit_sdl.rb +9 -0
  567. data/lib/tdl/SDL/axistream/axi_stream_cache_B1_sdl.rb +9 -0
  568. data/lib/tdl/SDL/axistream/axi_stream_cache_mirror_sdl.rb +9 -0
  569. data/lib/tdl/SDL/axistream/axi_stream_cache_sdl.rb +9 -0
  570. data/lib/tdl/SDL/axistream/axi_stream_cache_verb_sdl.rb +9 -0
  571. data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_A1_sdl.rb +11 -0
  572. data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_A2_sdl.rb +13 -0
  573. data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_bind_tuser_sdl.rb +11 -0
  574. data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_noaddr_sdl.rb +11 -0
  575. data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_sdl.rb +12 -0
  576. data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_with_addr_sdl.rb +12 -0
  577. data/lib/tdl/SDL/axistream/axi_stream_interconnect_S2M_auto_sdl.rb +11 -0
  578. data/lib/tdl/SDL/axistream/axi_stream_interconnect_S2M_sdl.rb +12 -0
  579. data/lib/tdl/SDL/axistream/axi_stream_long_cache_sdl.rb +10 -0
  580. data/lib/tdl/SDL/axistream/axi_stream_long_fifo_sdl.rb +11 -0
  581. data/lib/tdl/SDL/axistream/axi_stream_long_fifo_verb_sdl.rb +11 -0
  582. data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_B1E_sdl.rb +16 -0
  583. data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_B1_sdl.rb +14 -0
  584. data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_sdl.rb +10 -0
  585. data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_verb_sdl.rb +13 -0
  586. data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_with_info_sdl.rb +13 -0
  587. data/lib/tdl/SDL/axistream/axi_stream_packet_long_fifo_sdl.rb +11 -0
  588. data/lib/tdl/SDL/axistream/axi_stream_partition_A1_sdl.rb +11 -0
  589. data/lib/tdl/SDL/axistream/axi_stream_partition_sdl.rb +12 -0
  590. data/lib/tdl/SDL/axistream/axi_stream_wide_fifo_sdl.rb +10 -0
  591. data/lib/tdl/SDL/axistream/axi_streams_combin_A1_sdl.rb +15 -0
  592. data/lib/tdl/SDL/axistream/axi_streams_combin_sdl.rb +16 -0
  593. data/lib/tdl/SDL/axistream/axi_streams_scaler_A1_sdl.rb +14 -0
  594. data/lib/tdl/SDL/axistream/axi_streams_scaler_sdl.rb +15 -0
  595. data/lib/tdl/SDL/axistream/axis_append_A1_sdl.rb +18 -0
  596. data/lib/tdl/SDL/axistream/axis_append_sdl.rb +17 -0
  597. data/lib/tdl/SDL/axistream/axis_base_pipe_sdl.rb +10 -0
  598. data/lib/tdl/SDL/axistream/axis_combin_with_fifo_sdl.rb +14 -0
  599. data/lib/tdl/SDL/axistream/axis_connect_pipe_right_shift_sdl.rb +10 -0
  600. data/lib/tdl/SDL/axistream/axis_connect_pipe_sdl.rb +9 -0
  601. data/lib/tdl/SDL/axistream/axis_connect_pipe_with_info_sdl.rb +12 -0
  602. data/lib/tdl/SDL/axistream/axis_direct_A1_sdl.rb +11 -0
  603. data/lib/tdl/SDL/axistream/axis_direct_sdl.rb +9 -0
  604. data/lib/tdl/SDL/axistream/axis_ex_status_sdl.rb +12 -0
  605. data/lib/tdl/SDL/axistream/axis_filter_sdl.rb +10 -0
  606. data/lib/tdl/SDL/axistream/axis_full_to_data_c_sdl.rb +9 -0
  607. data/lib/tdl/SDL/axistream/axis_head_cut_sdl.rb +10 -0
  608. data/lib/tdl/SDL/axistream/axis_inct_s2m_with_flag_sdl.rb +11 -0
  609. data/lib/tdl/SDL/axistream/axis_intc_M2S_with_addr_inf_sdl.rb +11 -0
  610. data/lib/tdl/SDL/axistream/axis_intc_S2M_with_addr_inf_sdl.rb +12 -0
  611. data/lib/tdl/SDL/axistream/axis_interconnect_S2M_pipe_sdl.rb +15 -0
  612. data/lib/tdl/SDL/axistream/axis_length_cut_sdl.rb +10 -0
  613. data/lib/tdl/SDL/axistream/axis_length_fill_sdl.rb +10 -0
  614. data/lib/tdl/SDL/axistream/axis_length_split_sdl.rb +10 -0
  615. data/lib/tdl/SDL/axistream/axis_length_split_with_addr_sdl.rb +13 -0
  616. data/lib/tdl/SDL/axistream/axis_length_split_writh_user_sdl.rb +10 -0
  617. data/lib/tdl/SDL/axistream/axis_link_trigger_sdl.rb +12 -0
  618. data/lib/tdl/SDL/axistream/axis_master_empty_sdl.rb +8 -0
  619. data/lib/tdl/SDL/axistream/axis_mirror_to_master_sdl.rb +10 -0
  620. data/lib/tdl/SDL/axistream/axis_mirrors_sdl.rb +14 -0
  621. data/lib/tdl/SDL/axistream/axis_orthogonal_sdl.rb +10 -0
  622. data/lib/tdl/SDL/axistream/axis_pkt_fifo_filter_keep_A1_sdl.rb +10 -0
  623. data/lib/tdl/SDL/axistream/axis_pkt_fifo_filter_keep_sdl.rb +10 -0
  624. data/lib/tdl/SDL/axistream/axis_ram_buffer_sdl.rb +13 -0
  625. data/lib/tdl/SDL/axistream/axis_slaver_empty_sdl.rb +8 -0
  626. data/lib/tdl/SDL/axistream/axis_slaver_pipe_A1_sdl.rb +10 -0
  627. data/lib/tdl/SDL/axistream/axis_slaver_pipe_sdl.rb +9 -0
  628. data/lib/tdl/SDL/axistream/axis_slaver_vector_empty_sdl.rb +9 -0
  629. data/lib/tdl/SDL/axistream/axis_to_data_inf_sdl.rb +10 -0
  630. data/lib/tdl/SDL/axistream/axis_to_lite_rd_sdl.rb +11 -0
  631. data/lib/tdl/SDL/axistream/axis_to_lite_wr_sdl.rb +10 -0
  632. data/lib/tdl/SDL/axistream/axis_uncompress_A1_sdl.rb +12 -0
  633. data/lib/tdl/SDL/axistream/axis_uncompress_sdl.rb +11 -0
  634. data/lib/tdl/SDL/axistream/axis_valve_sdl.rb +10 -0
  635. data/lib/tdl/SDL/axistream/axis_valve_with_pipe_sdl.rb +11 -0
  636. data/lib/tdl/SDL/axistream/axis_width_combin_A1_sdl.rb +9 -0
  637. data/lib/tdl/SDL/axistream/axis_width_combin_sdl.rb +9 -0
  638. data/lib/tdl/SDL/axistream/axis_width_convert_sdl.rb +9 -0
  639. data/lib/tdl/SDL/axistream/axis_width_destruct_A1_sdl.rb +9 -0
  640. data/lib/tdl/SDL/axistream/axis_width_destruct_sdl.rb +9 -0
  641. data/lib/tdl/SDL/axistream/check_stream_crc_sdl.rb +8 -0
  642. data/lib/tdl/SDL/axistream/data_c_to_axis_full_sdl.rb +9 -0
  643. data/lib/tdl/SDL/axistream/data_to_axis_inf_A1_sdl.rb +10 -0
  644. data/lib/tdl/SDL/axistream/data_to_axis_inf_sdl.rb +11 -0
  645. data/lib/tdl/SDL/axistream/gen_big_field_table_sdl.rb +14 -0
  646. data/lib/tdl/SDL/axistream/gen_common_frame_table_sdl.rb +60 -0
  647. data/lib/tdl/SDL/axistream/gen_origin_axis_A1_sdl.rb +13 -0
  648. data/lib/tdl/SDL/axistream/gen_origin_axis_sdl.rb +12 -0
  649. data/lib/tdl/SDL/axistream/gen_simple_axis_sdl.rb +13 -0
  650. data/lib/tdl/SDL/axistream/parse_big_field_table_A1_sdl.rb +17 -0
  651. data/lib/tdl/SDL/axistream/parse_big_field_table_A2_sdl.rb +17 -0
  652. data/lib/tdl/SDL/axistream/parse_big_field_table_sdl.rb +17 -0
  653. data/lib/tdl/SDL/axistream/stream_crc_sdl.rb +9 -0
  654. data/lib/tdl/SDL/axistream/vcs_axis_comptable.rb +16 -0
  655. data/lib/tdl/SDL/axistream/vcs_axis_comptable_sdl.rb +9 -0
  656. data/lib/tdl/SDL/data_inf_c/data_bind_sdl.rb +10 -0
  657. data/lib/tdl/SDL/data_inf_c/data_c_cache_sdl.rb +9 -0
  658. data/lib/tdl/SDL/data_inf_c/data_c_direct_mirror_sdl.rb +9 -0
  659. data/lib/tdl/SDL/data_inf_c/data_c_direct_sdl.rb +9 -0
  660. data/lib/tdl/SDL/data_inf_c/data_c_intc_M2S_force_robin_sdl.rb +10 -0
  661. data/lib/tdl/SDL/data_inf_c/data_c_pipe_force_vld_bind_data_sdl.rb +13 -0
  662. data/lib/tdl/SDL/data_inf_c/data_c_pipe_force_vld_sdl.rb +9 -0
  663. data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_A1_sdl.rb +10 -0
  664. data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_right_shift_sdl.rb +13 -0
  665. data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_sdl.rb +9 -0
  666. data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_C1_sdl.rb +14 -0
  667. data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_C1_with_id_sdl.rb +16 -0
  668. data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_sdl.rb +13 -0
  669. data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_with_addr_sdl.rb +13 -0
  670. data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_with_id_sdl.rb +15 -0
  671. data/lib/tdl/SDL/data_inf_c/data_c_pipe_latency_sdl.rb +10 -0
  672. data/lib/tdl/SDL/data_inf_c/data_c_scaler_A1_sdl.rb +16 -0
  673. data/lib/tdl/SDL/data_inf_c/data_c_scaler_sdl.rb +15 -0
  674. data/lib/tdl/SDL/data_inf_c/data_c_tmp_cache_sdl.rb +9 -0
  675. data/lib/tdl/SDL/data_inf_c/data_condition_mirror_sdl.rb +13 -0
  676. data/lib/tdl/SDL/data_inf_c/data_condition_valve_sdl.rb +13 -0
  677. data/lib/tdl/SDL/data_inf_c/data_connect_pipe_inf_sdl.rb +9 -0
  678. data/lib/tdl/SDL/data_inf_c/data_connect_pipe_sdl.rb +17 -0
  679. data/lib/tdl/SDL/data_inf_c/data_inf_A2B_sdl.rb +9 -0
  680. data/lib/tdl/SDL/data_inf_c/data_inf_B2A_sdl.rb +9 -0
  681. data/lib/tdl/SDL/data_inf_c/data_inf_c_M2S_with_addr_and_id_sdl.rb +17 -0
  682. data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_M2S_with_id_sdl.rb +15 -0
  683. data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_A1_sdl.rb +13 -0
  684. data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_sdl.rb +12 -0
  685. data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_with_lazy_sdl.rb +15 -0
  686. data/lib/tdl/SDL/data_inf_c/data_inf_c_interconnect_M2S_sdl.rb +12 -0
  687. data/lib/tdl/SDL/data_inf_c/data_inf_c_pipe_condition_sdl.rb +10 -0
  688. data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_A1.rb +12 -0
  689. data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_A1_sdl.rb +14 -0
  690. data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_sdl.rb +13 -0
  691. data/lib/tdl/SDL/data_inf_c/data_inf_cross_clk_sdl.rb +9 -0
  692. data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_force_addr_with_id_sdl.rb +19 -0
  693. data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_prio_sdl.rb +14 -0
  694. data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_prio_with_id_sdl.rb +17 -0
  695. data/lib/tdl/SDL/data_inf_c/data_inf_interconnect_M2S_noaddr_sdl.rb +14 -0
  696. data/lib/tdl/SDL/data_inf_c/data_inf_interconnect_M2S_with_id_noaddr_sdl.rb +17 -0
  697. data/lib/tdl/SDL/data_inf_c/data_inf_planer_A1_sdl.rb +15 -0
  698. data/lib/tdl/SDL/data_inf_c/data_inf_planer_sdl.rb +14 -0
  699. data/lib/tdl/SDL/data_inf_c/data_inf_ticktock_sdl.rb +18 -0
  700. data/lib/tdl/SDL/data_inf_c/data_intc_M2S_force_robin_sdl.rb +10 -0
  701. data/lib/tdl/SDL/data_inf_c/data_mirrors_sdl.rb +14 -0
  702. data/lib/tdl/SDL/data_inf_c/data_pair_map_A1_sdl.rb +16 -0
  703. data/lib/tdl/SDL/data_inf_c/data_pair_map_A2_sdl.rb +19 -0
  704. data/lib/tdl/SDL/data_inf_c/data_pair_map_sdl.rb +14 -0
  705. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_A1_sdl.rb +19 -0
  706. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_sdl.rb +17 -0
  707. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_verb_sdl.rb +16 -0
  708. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_A1_sdl.rb +19 -0
  709. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_sdl.rb +16 -0
  710. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_verb_sdl.rb +15 -0
  711. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_sdl.rb +23 -0
  712. data/lib/tdl/SDL/data_inf_c/data_streams_combin_A1_sdl.rb +20 -0
  713. data/lib/tdl/SDL/data_inf_c/data_streams_combin_sdl.rb +20 -0
  714. data/lib/tdl/SDL/data_inf_c/data_streams_scaler_sdl.rb +19 -0
  715. data/lib/tdl/SDL/data_inf_c/data_uncompress_sdl.rb +11 -0
  716. data/lib/tdl/SDL/data_inf_c/data_valve_sdl.rb +10 -0
  717. data/lib/tdl/SDL/data_inf_c/datainf_c_master_empty_sdl.rb +8 -0
  718. data/lib/tdl/SDL/data_inf_c/datainf_c_slaver_empty_sdl.rb +8 -0
  719. data/lib/tdl/SDL/data_inf_c/datainf_master_empty_sdl.rb +8 -0
  720. data/lib/tdl/SDL/data_inf_c/datainf_slaver_empty_sdl.rb +8 -0
  721. data/lib/tdl/SDL/data_inf_c/latency_sdl.rb +8 -0
  722. data/lib/tdl/SDL/data_inf_c/next_prio_sdl.rb +12 -0
  723. data/lib/tdl/SDL/data_inf_c/part_data_pair_map_sdl.rb +19 -0
  724. data/lib/tdl/SDL/data_inf_c/trigger_data_inf_c_A1_sdl.rb +11 -0
  725. data/lib/tdl/SDL/data_inf_c/trigger_data_inf_c_sdl.rb +11 -0
  726. data/lib/tdl/SDL/data_inf_c/trigger_ready_ctrl_sdl.rb +12 -0
  727. data/lib/tdl/SDL/data_inf_c/vcs_data_c_comptable.rb +8 -0
  728. data/lib/tdl/SDL/data_inf_c/vcs_data_c_comptable_sdl.rb +9 -0
  729. data/lib/tdl/SDL/fifo/common_fifo_sdl.rb +20 -0
  730. data/lib/tdl/SDL/fifo/common_stack_sdl.rb +14 -0
  731. data/lib/tdl/SDL/fifo/independent_clock_fifo_a1_sdl.rb +21 -0
  732. data/lib/tdl/SDL/fifo/independent_clock_fifo_sdl.rb +20 -0
  733. data/lib/tdl/SDL/fifo/independent_stack_sdl.rb +18 -0
  734. data/lib/tdl/SDL/path_lib.rb +6 -0
  735. data/lib/tdl/VideoInf/simple_video_gen.rb +46 -0
  736. data/lib/tdl/VideoInf/video_from_axi4.rb +108 -0
  737. data/lib/tdl/VideoInf/video_lib.rb +8 -0
  738. data/lib/tdl/VideoInf/video_stream_2_axi_stream.rb +67 -0
  739. data/lib/tdl/VideoInf/video_to_axi4.rb +75 -0
  740. data/lib/tdl/auto_script/auto_gen_tdl.rb +49 -0
  741. data/lib/tdl/auto_script/autogensdl.rb +289 -0
  742. data/lib/tdl/auto_script/autogentdl_a2.rb +452 -0
  743. data/lib/tdl/auto_script/import_hdl.rb +35 -0
  744. data/lib/tdl/auto_script/import_sdl.rb +26 -0
  745. data/lib/tdl/auto_script/test_autogensdl.rb +73 -0
  746. data/lib/tdl/auto_script/tmp.rb +6 -0
  747. data/lib/tdl/auto_script/tmp/hdl_test_sdl.rb +12 -0
  748. data/lib/tdl/axi4/axi4_combin_wr_rd_batch_auto.rb +79 -0
  749. data/lib/tdl/axi4/axi4_direct.rb +36 -0
  750. data/lib/tdl/axi4/axi4_direct_A1_auto.rb +137 -0
  751. data/lib/tdl/axi4/axi4_direct_auto.rb +79 -0
  752. data/lib/tdl/axi4/axi4_direct_verb_auto.rb +71 -0
  753. data/lib/tdl/axi4/axi4_interconnect_verb.rb +323 -0
  754. data/lib/tdl/axi4/axi4_lib.rb +9 -0
  755. data/lib/tdl/axi4/axi4_long_to_axi4_wide_A1_auto.rb +79 -0
  756. data/lib/tdl/axi4/axi4_long_to_axi4_wide_auto.rb +71 -0
  757. data/lib/tdl/axi4/axi4_long_to_axi4_wide_verb_auto.rb +86 -0
  758. data/lib/tdl/axi4/axi4_packet_fifo_auto.rb +155 -0
  759. data/lib/tdl/axi4/axi4_pipe_auto.rb +127 -0
  760. data/lib/tdl/axi4/axi4_pipe_verb_auto.rb +127 -0
  761. data/lib/tdl/axi4/axi4_rd_auxiliary_gen_auto.rb +71 -0
  762. data/lib/tdl/axi4/axi4_wr_auxiliary_gen_without_resp_auto.rb +78 -0
  763. data/lib/tdl/axi4/axis_to_axi4_wr_auto.rb +85 -0
  764. data/lib/tdl/axi4/bak/__axi4_wr_auxiliary_gen_without_resp.rb +175 -0
  765. data/lib/tdl/axi4/bak/axi4_combin_wr_rd_batch_auto.rb +153 -0
  766. data/lib/tdl/axi4/bak/axi4_data_convert.rb +74 -0
  767. data/lib/tdl/axi4/bak/axi4_direct_auto.rb +153 -0
  768. data/lib/tdl/axi4/bak/axi4_direct_verb_auto.rb +126 -0
  769. data/lib/tdl/axi4/bak/axi4_interconnect.rb.bak +91 -0
  770. data/lib/tdl/axi4/bak/axi4_long_to_axi4_wide_A1_auto.rb +153 -0
  771. data/lib/tdl/axi4/bak/axi4_long_to_axi4_wide_auto.rb +126 -0
  772. data/lib/tdl/axi4/bak/axi4_long_to_axi4_wide_verb_auto.rb +179 -0
  773. data/lib/tdl/axi4/bak/axi4_packet_fifo.rb.bak +75 -0
  774. data/lib/tdl/axi4/bak/axi4_packet_fifo_auto.rb +259 -0
  775. data/lib/tdl/axi4/bak/axi4_partition_od.rb +84 -0
  776. data/lib/tdl/axi4/bak/axi4_pipe_auto.rb +174 -0
  777. data/lib/tdl/axi4/bak/axi4_wr_auxiliary_gen_without_resp_auto.rb +152 -0
  778. data/lib/tdl/axi4/bak/axis_to_axi4_wr_auto.rb +178 -0
  779. data/lib/tdl/axi4/bak/ddr3.rb +40 -0
  780. data/lib/tdl/axi4/bak/idata_pool_axi4_auto.rb +396 -0
  781. data/lib/tdl/axi4/bak/odata_pool_axi4_A1_auto.rb +230 -0
  782. data/lib/tdl/axi4/bak/odata_pool_axi4_auto.rb +386 -0
  783. data/lib/tdl/axi4/idata_pool_axi4_auto.rb +176 -0
  784. data/lib/tdl/axi4/odata_pool_axi4_A1_auto.rb +99 -0
  785. data/lib/tdl/axi4/odata_pool_axi4_auto.rb +141 -0
  786. data/lib/tdl/axi4/wide_axis_to_axi4_wr.rb +84 -0
  787. data/lib/tdl/axi4/wide_axis_to_axi4_wr_auto.rb +84 -0
  788. data/lib/tdl/axi_lite/axi_lite_master_empty_auto.rb +85 -0
  789. data/lib/tdl/axi_lite/axi_lite_slaver_empty_auto.rb +68 -0
  790. data/lib/tdl/axi_lite/bak/axi_lite_master_empty_auto.rb +95 -0
  791. data/lib/tdl/axi_lite/bak/axi_lite_slaver_empty_auto.rb +88 -0
  792. data/lib/tdl/axi_lite/bak/jtag_to_axilite_wrapper_auto.rb +112 -0
  793. data/lib/tdl/axi_lite/jtag_to_axilite_wrapper_auto.rb +63 -0
  794. data/lib/tdl/axi_lite/lite_cmd.rb +154 -0
  795. data/lib/tdl/axi_lite/prj_lib.rb +6 -0
  796. data/lib/tdl/axi_stream/axi_stream_cache_35bit_auto.rb +127 -0
  797. data/lib/tdl/axi_stream/axi_stream_cache_72_95bit_with_keep_auto.rb +127 -0
  798. data/lib/tdl/axi_stream/axi_stream_cache_B1_auto.rb +127 -0
  799. data/lib/tdl/axi_stream/axi_stream_cache_auto.rb +134 -0
  800. data/lib/tdl/axi_stream/axi_stream_cache_mirror_auto.rb +127 -0
  801. data/lib/tdl/axi_stream/axi_stream_cache_verb_auto.rb +127 -0
  802. data/lib/tdl/axi_stream/axi_stream_interconnect.rb +214 -0
  803. data/lib/tdl/axi_stream/axi_stream_interconnect_M2S.rb +85 -0
  804. data/lib/tdl/axi_stream/axi_stream_interconnect_M2S_A1.rb +129 -0
  805. data/lib/tdl/axi_stream/axi_stream_interconnect_M2S_A1_auto.rb +137 -0
  806. data/lib/tdl/axi_stream/axi_stream_interconnect_M2S_auto.rb +93 -0
  807. data/lib/tdl/axi_stream/axi_stream_interconnect_M2S_bind_tuser_auto.rb +137 -0
  808. data/lib/tdl/axi_stream/axi_stream_interconnect_S2M.rb +86 -0
  809. data/lib/tdl/axi_stream/axi_stream_interconnect_S2M_auto.rb +86 -0
  810. data/lib/tdl/axi_stream/axi_stream_interconnect_S2M_auto_auto.rb +91 -0
  811. data/lib/tdl/axi_stream/axi_stream_interconnect_S2M_with_keep.sv_auto.rb +93 -0
  812. data/lib/tdl/axi_stream/axi_stream_lib.rb +18 -0
  813. data/lib/tdl/axi_stream/axi_stream_long_cache_auto.rb +137 -0
  814. data/lib/tdl/axi_stream/axi_stream_long_fifo_auto.rb +146 -0
  815. data/lib/tdl/axi_stream/axi_stream_long_fifo_verb_auto.rb +146 -0
  816. data/lib/tdl/axi_stream/axi_stream_packet_fifo_auto.rb +137 -0
  817. data/lib/tdl/axi_stream/axi_stream_packet_fifo_with_info_auto.rb +164 -0
  818. data/lib/tdl/axi_stream/axi_stream_partition_A1_auto.rb +145 -0
  819. data/lib/tdl/axi_stream/axi_stream_partition_auto.rb +154 -0
  820. data/lib/tdl/axi_stream/axi_stream_wide_fifo_auto.rb +137 -0
  821. data/lib/tdl/axi_stream/axi_streams_combin_A1_auto.rb +184 -0
  822. data/lib/tdl/axi_stream/axi_streams_combin_auto.rb +193 -0
  823. data/lib/tdl/axi_stream/axi_streams_scaler_A1_auto.rb +175 -0
  824. data/lib/tdl/axi_stream/axi_streams_scaler_auto.rb +184 -0
  825. data/lib/tdl/axi_stream/axis_append_A1_auto.rb +209 -0
  826. data/lib/tdl/axi_stream/axis_append_auto.rb +200 -0
  827. data/lib/tdl/axi_stream/axis_combin_with_fifo_auto.rb +175 -0
  828. data/lib/tdl/axi_stream/axis_connect_pipe_A1.sv_auto.rb +127 -0
  829. data/lib/tdl/axi_stream/axis_connect_pipe_auto.rb +127 -0
  830. data/lib/tdl/axi_stream/axis_connect_pipe_with_info_auto.rb +155 -0
  831. data/lib/tdl/axi_stream/axis_direct_auto.rb +127 -0
  832. data/lib/tdl/axi_stream/axis_filter_auto.rb +136 -0
  833. data/lib/tdl/axi_stream/axis_full_to_data_c_auto.rb +71 -0
  834. data/lib/tdl/axi_stream/axis_head_cut_auto.rb +137 -0
  835. data/lib/tdl/axi_stream/axis_length_fill_auto.rb +136 -0
  836. data/lib/tdl/axi_stream/axis_length_split_auto.rb +136 -0
  837. data/lib/tdl/axi_stream/axis_length_split_with_addr_auto.rb +164 -0
  838. data/lib/tdl/axi_stream/axis_length_split_writh_user_auto.rb +136 -0
  839. data/lib/tdl/axi_stream/axis_link_trigger_auto.rb +93 -0
  840. data/lib/tdl/axi_stream/axis_master_empty_auto.rb +85 -0
  841. data/lib/tdl/axi_stream/axis_mirror_to_master_auto.rb +137 -0
  842. data/lib/tdl/axi_stream/axis_mirrors_auto.rb +173 -0
  843. data/lib/tdl/axi_stream/axis_pkt_fifo_filter_keep_A1_auto.rb +137 -0
  844. data/lib/tdl/axi_stream/axis_pkt_fifo_filter_keep_auto.rb +137 -0
  845. data/lib/tdl/axi_stream/axis_ram_buffer_auto.rb +164 -0
  846. data/lib/tdl/axi_stream/axis_slaver_empty_auto.rb +68 -0
  847. data/lib/tdl/axi_stream/axis_slaver_pipe_A1_auto.rb +137 -0
  848. data/lib/tdl/axi_stream/axis_slaver_pipe_auto.rb +127 -0
  849. data/lib/tdl/axi_stream/axis_to_axi4_or_lite_auto.rb +87 -0
  850. data/lib/tdl/axi_stream/axis_to_data_inf_auto.rb +79 -0
  851. data/lib/tdl/axi_stream/axis_to_lite_rd_auto.rb +87 -0
  852. data/lib/tdl/axi_stream/axis_to_lite_wr_auto.rb +79 -0
  853. data/lib/tdl/axi_stream/axis_uncompress_auto.rb +86 -0
  854. data/lib/tdl/axi_stream/axis_valve_auto.rb +136 -0
  855. data/lib/tdl/axi_stream/axis_valve_with_pipe_auto.rb +153 -0
  856. data/lib/tdl/axi_stream/axis_width_combin_A1_auto.rb +127 -0
  857. data/lib/tdl/axi_stream/axis_width_combin_auto.rb +127 -0
  858. data/lib/tdl/axi_stream/axis_width_convert_auto.rb +127 -0
  859. data/lib/tdl/axi_stream/axis_width_destruct_A1.sv_auto.rb +127 -0
  860. data/lib/tdl/axi_stream/axis_width_destruct_auto.rb +127 -0
  861. data/lib/tdl/axi_stream/bak/__axi_stream_interconnect_S2M.rb +186 -0
  862. data/lib/tdl/axi_stream/bak/_axis_mirrors.rb +270 -0
  863. data/lib/tdl/axi_stream/bak/axi4_to_native_for_ddr_ip_verb_auto.rb +343 -0
  864. data/lib/tdl/axi_stream/bak/axi_stream_S2M.rb +63 -0
  865. data/lib/tdl/axi_stream/bak/axi_stream_cache_35bit_auto.rb +138 -0
  866. data/lib/tdl/axi_stream/bak/axi_stream_cache_72_95bit_with_keep_auto.rb +138 -0
  867. data/lib/tdl/axi_stream/bak/axi_stream_cache_B1_auto.rb +138 -0
  868. data/lib/tdl/axi_stream/bak/axi_stream_cache_auto.rb +138 -0
  869. data/lib/tdl/axi_stream/bak/axi_stream_cache_mirror_auto.rb +138 -0
  870. data/lib/tdl/axi_stream/bak/axi_stream_cache_verb_auto.rb +138 -0
  871. data/lib/tdl/axi_stream/bak/axi_stream_interconnect_S2M_auto.rb +147 -0
  872. data/lib/tdl/axi_stream/bak/axi_stream_interconnect_S2M_with_keep.sv_auto.rb +166 -0
  873. data/lib/tdl/axi_stream/bak/axi_stream_long_fifo_auto.rb +177 -0
  874. data/lib/tdl/axi_stream/bak/axi_stream_packet_fifo_auto.rb +158 -0
  875. data/lib/tdl/axi_stream/bak/axi_stream_packet_fifo_with_info_auto.rb +215 -0
  876. data/lib/tdl/axi_stream/bak/axi_stream_partition_A1_auto.rb +176 -0
  877. data/lib/tdl/axi_stream/bak/axi_stream_partition_auto.rb +195 -0
  878. data/lib/tdl/axi_stream/bak/axi_streams_combin_auto.rb +274 -0
  879. data/lib/tdl/axi_stream/bak/axi_streams_scaler.rb +300 -0
  880. data/lib/tdl/axi_stream/bak/axi_streams_scaler_auto.rb +255 -0
  881. data/lib/tdl/axi_stream/bak/axis_append_A1.rb +265 -0
  882. data/lib/tdl/axi_stream/bak/axis_append_A1_auto.rb +310 -0
  883. data/lib/tdl/axi_stream/bak/axis_append_auto.rb +291 -0
  884. data/lib/tdl/axi_stream/bak/axis_combin_with_fifo_auto.rb +236 -0
  885. data/lib/tdl/axi_stream/bak/axis_connect_pipe.rb.bak +207 -0
  886. data/lib/tdl/axi_stream/bak/axis_connect_pipe_A1.sv_auto.rb +138 -0
  887. data/lib/tdl/axi_stream/bak/axis_connect_pipe_auto.rb +138 -0
  888. data/lib/tdl/axi_stream/bak/axis_connect_pipe_with_info_auto.rb +196 -0
  889. data/lib/tdl/axi_stream/bak/axis_direct_auto.rb +138 -0
  890. data/lib/tdl/axi_stream/bak/axis_filter_auto.rb +157 -0
  891. data/lib/tdl/axi_stream/bak/axis_length_fill_auto.rb +157 -0
  892. data/lib/tdl/axi_stream/bak/axis_length_split_auto.rb +157 -0
  893. data/lib/tdl/axi_stream/bak/axis_length_split_with_addr_auto.rb +215 -0
  894. data/lib/tdl/axi_stream/bak/axis_master_empty_auto.rb +95 -0
  895. data/lib/tdl/axi_stream/bak/axis_mirrors_auto.rb +234 -0
  896. data/lib/tdl/axi_stream/bak/axis_pkt_fifo_filter_keep_auto.rb +158 -0
  897. data/lib/tdl/axi_stream/bak/axis_ram_buffer_auto.rb +215 -0
  898. data/lib/tdl/axi_stream/bak/axis_slaver_empty_auto.rb +88 -0
  899. data/lib/tdl/axi_stream/bak/axis_slaver_pipe_A1_auto.rb +158 -0
  900. data/lib/tdl/axi_stream/bak/axis_slaver_pipe_auto.rb +138 -0
  901. data/lib/tdl/axi_stream/bak/axis_to_axi4_wr_auto.rb +205 -0
  902. data/lib/tdl/axi_stream/bak/axis_to_data_inf_auto.rb +108 -0
  903. data/lib/tdl/axi_stream/bak/axis_uncompress_auto.rb +147 -0
  904. data/lib/tdl/axi_stream/bak/axis_valve_auto.rb +157 -0
  905. data/lib/tdl/axi_stream/bak/axis_valve_with_pipe_auto.rb +157 -0
  906. data/lib/tdl/axi_stream/bak/axis_width_combin_auto.rb +138 -0
  907. data/lib/tdl/axi_stream/bak/axis_width_convert_auto.rb +138 -0
  908. data/lib/tdl/axi_stream/bak/axis_width_destruct_auto.rb +138 -0
  909. data/lib/tdl/axi_stream/bak/axis_wrapper_oled_auto.rb +230 -0
  910. data/lib/tdl/axi_stream/bak/check_stream_crc_auto.rb +88 -0
  911. data/lib/tdl/axi_stream/bak/data_to_axis_inf_A1.rb +129 -0
  912. data/lib/tdl/axi_stream/bak/data_to_axis_inf_A1_auto.rb +127 -0
  913. data/lib/tdl/axi_stream/bak/data_to_axis_inf_auto.rb +146 -0
  914. data/lib/tdl/axi_stream/bak/datainf_c_master_empty_auto.rb +115 -0
  915. data/lib/tdl/axi_stream/bak/datainf_c_slaver_empty_auto.rb +108 -0
  916. data/lib/tdl/axi_stream/bak/datainf_master_empty_auto.rb +115 -0
  917. data/lib/tdl/axi_stream/bak/datainf_slaver_empty_auto.rb +108 -0
  918. data/lib/tdl/axi_stream/bak/dynamic_port_cfg_auto.rb +246 -0
  919. data/lib/tdl/axi_stream/bak/dynnamic_addr_cfg_auto.rb +200 -0
  920. data/lib/tdl/axi_stream/bak/gen_big_field_table_auto.rb +210 -0
  921. data/lib/tdl/axi_stream/bak/gen_origin_axis_auto.rb +172 -0
  922. data/lib/tdl/axi_stream/bak/gen_simple_axis_auto.rb +191 -0
  923. data/lib/tdl/axi_stream/bak/idata_pool_axi4_auto.rb +346 -0
  924. data/lib/tdl/axi_stream/bak/parse_big_field_table_A1_auto.rb +292 -0
  925. data/lib/tdl/axi_stream/bak/parse_big_field_table_A2_auto.rb +292 -0
  926. data/lib/tdl/axi_stream/bak/parse_big_field_table_auto.rb +292 -0
  927. data/lib/tdl/axi_stream/bak/part_data_pair_map_auto.rb +362 -0
  928. data/lib/tdl/axi_stream/bak/simple_video_gen_A2.rb +146 -0
  929. data/lib/tdl/axi_stream/bak/simple_video_gen_A2_auto.rb +151 -0
  930. data/lib/tdl/axi_stream/bak/stream_crc_auto.rb +107 -0
  931. data/lib/tdl/axi_stream/bak/udp_server_bfm_auto.rb +131 -0
  932. data/lib/tdl/axi_stream/bak/udp_server_ctrl_bfm_auto.rb +131 -0
  933. data/lib/tdl/axi_stream/bak/video_to_VDMA.rb +153 -0
  934. data/lib/tdl/axi_stream/bak/video_to_VDMA_auto.rb +158 -0
  935. data/lib/tdl/axi_stream/check_stream_crc_auto.rb +63 -0
  936. data/lib/tdl/axi_stream/data_c_to_axis_full_auto.rb +71 -0
  937. data/lib/tdl/axi_stream/data_to_axis_inf_A1_auto.rb +78 -0
  938. data/lib/tdl/axi_stream/data_to_axis_inf_auto.rb +85 -0
  939. data/lib/tdl/axi_stream/gen_big_field_table_auto.rb +140 -0
  940. data/lib/tdl/axi_stream/gen_origin_axis_A1_auto.rb +131 -0
  941. data/lib/tdl/axi_stream/gen_origin_axis_auto.rb +122 -0
  942. data/lib/tdl/axi_stream/gen_simple_axis_auto.rb +131 -0
  943. data/lib/tdl/axi_stream/parse_big_field_table_A1_auto.rb +201 -0
  944. data/lib/tdl/axi_stream/parse_big_field_table_A2_auto.rb +201 -0
  945. data/lib/tdl/axi_stream/parse_big_field_table_auto.rb +201 -0
  946. data/lib/tdl/axi_stream/stream_crc_auto.rb +70 -0
  947. data/lib/tdl/basefunc.rb +338 -0
  948. data/lib/tdl/bfm/axi4_illegal_bfm.rb +203 -0
  949. data/lib/tdl/bfm/axi_stream/axi_stream_bfm.rb +351 -0
  950. data/lib/tdl/bfm/axi_stream/axis_bfm_exp.yml +38 -0
  951. data/lib/tdl/bfm/axi_stream/axis_bfm_module_build.rb +120 -0
  952. data/lib/tdl/bfm/axi_stream/axis_bfm_parse.rb +10 -0
  953. data/lib/tdl/bfm/axi_stream/axis_slice_to_logic.rb +71 -0
  954. data/lib/tdl/bfm/bfm_lib.rb +7 -0
  955. data/lib/tdl/bfm/logic_initial_block.rb +52 -0
  956. data/lib/tdl/cfg.yml +4 -0
  957. data/lib/tdl/class_hdl/hdl_always_comb.rb +54 -0
  958. data/lib/tdl/class_hdl/hdl_always_ff.rb +175 -0
  959. data/lib/tdl/class_hdl/hdl_assign.rb +49 -0
  960. data/lib/tdl/class_hdl/hdl_block_ifelse.rb +349 -0
  961. data/lib/tdl/class_hdl/hdl_data.rb +24 -0
  962. data/lib/tdl/class_hdl/hdl_ex_defarraychain.rb +231 -0
  963. data/lib/tdl/class_hdl/hdl_foreach.rb +114 -0
  964. data/lib/tdl/class_hdl/hdl_function.rb +277 -0
  965. data/lib/tdl/class_hdl/hdl_generate.rb +218 -0
  966. data/lib/tdl/class_hdl/hdl_initial.rb +147 -0
  967. data/lib/tdl/class_hdl/hdl_module_def.rb +447 -0
  968. data/lib/tdl/class_hdl/hdl_package.rb +150 -0
  969. data/lib/tdl/class_hdl/hdl_parameter.rb +73 -0
  970. data/lib/tdl/class_hdl/hdl_random.rb +31 -0
  971. data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +653 -0
  972. data/lib/tdl/class_hdl/hdl_struct.rb +209 -0
  973. data/lib/tdl/class_hdl/hdl_verify.rb +136 -0
  974. data/lib/tdl/data_inf/_data_mirrors.rb +92 -0
  975. data/lib/tdl/data_inf/bak/_data_mirrors.rb +273 -0
  976. data/lib/tdl/data_inf/bak/common_fifo_auto.rb +279 -0
  977. data/lib/tdl/data_inf/bak/data_bind_auto.rb +128 -0
  978. data/lib/tdl/data_inf/bak/data_c_direct_auto.rb +138 -0
  979. data/lib/tdl/data_inf/bak/data_c_direct_mirror_auto.rb +138 -0
  980. data/lib/tdl/data_inf/bak/data_c_tmp_cache_auto.rb +138 -0
  981. data/lib/tdl/data_inf/bak/data_condition_mirror_auto.rb +216 -0
  982. data/lib/tdl/data_inf/bak/data_condition_valve_auto.rb +215 -0
  983. data/lib/tdl/data_inf/bak/data_connect_pipe.rb +80 -0
  984. data/lib/tdl/data_inf/bak/data_connect_pipe_inf_auto.rb +138 -0
  985. data/lib/tdl/data_inf/bak/data_inf_c_interconnect.rb +86 -0
  986. data/lib/tdl/data_inf/bak/data_inf_c_pipe_condition_auto.rb +157 -0
  987. data/lib/tdl/data_inf/bak/data_inf_cross_clk.rb +60 -0
  988. data/lib/tdl/data_inf/bak/data_inf_interconnect.rb +144 -0
  989. data/lib/tdl/data_inf/bak/data_inf_planer.rb +78 -0
  990. data/lib/tdl/data_inf/bak/data_inf_ticktack.rb +80 -0
  991. data/lib/tdl/data_inf/bak/data_inf_ticktock_auto.rb +0 -0
  992. data/lib/tdl/data_inf/bak/data_mirrors_auto.rb +234 -0
  993. data/lib/tdl/data_inf/bak/data_mirrors_verb.sv_auto.rb +234 -0
  994. data/lib/tdl/data_inf/bak/data_uncompress_auto.rb +177 -0
  995. data/lib/tdl/data_inf/bak/data_valve_auto.rb +127 -0
  996. data/lib/tdl/data_inf/bak/datainf_c_master_empty_auto.rb +95 -0
  997. data/lib/tdl/data_inf/bak/datainf_c_slaver_empty_auto.rb +88 -0
  998. data/lib/tdl/data_inf/bak/datainf_master_empty_auto.rb +95 -0
  999. data/lib/tdl/data_inf/bak/datainf_slaver_empty_auto.rb +88 -0
  1000. data/lib/tdl/data_inf/bak/independent_clock_fifo_auto.rb +298 -0
  1001. data/lib/tdl/data_inf/bak/part_data_pair_map_auto.rb +306 -0
  1002. data/lib/tdl/data_inf/common_fifo_auto.rb +141 -0
  1003. data/lib/tdl/data_inf/data_bind_auto.rb +79 -0
  1004. data/lib/tdl/data_inf/data_c_cache_auto.rb +135 -0
  1005. data/lib/tdl/data_inf/data_c_direct_auto.rb +127 -0
  1006. data/lib/tdl/data_inf/data_c_direct_mirror_auto.rb +127 -0
  1007. data/lib/tdl/data_inf/data_c_interconnect.rb +97 -0
  1008. data/lib/tdl/data_inf/data_c_pipe_force_vld_auto.rb +127 -0
  1009. data/lib/tdl/data_inf/data_c_pipe_inf_auto.rb +127 -0
  1010. data/lib/tdl/data_inf/data_c_pipe_intc_M2S_verc_auto.rb +123 -0
  1011. data/lib/tdl/data_inf/data_c_tmp_cache_auto.rb +127 -0
  1012. data/lib/tdl/data_inf/data_condition_mirror_auto.rb +165 -0
  1013. data/lib/tdl/data_inf/data_condition_valve_auto.rb +164 -0
  1014. data/lib/tdl/data_inf/data_connect_pipe_inf_auto.rb +127 -0
  1015. data/lib/tdl/data_inf/data_inf_c_pipe_condition_auto.rb +136 -0
  1016. data/lib/tdl/data_inf/data_mirrors_auto.rb +173 -0
  1017. data/lib/tdl/data_inf/data_mirrors_verb.sv_auto.rb +173 -0
  1018. data/lib/tdl/data_inf/data_uncompress_auto.rb +146 -0
  1019. data/lib/tdl/data_inf/data_valve_auto.rb +104 -0
  1020. data/lib/tdl/data_inf/datainf_c_master_empty_auto.rb +85 -0
  1021. data/lib/tdl/data_inf/datainf_c_slaver_empty_auto.rb +68 -0
  1022. data/lib/tdl/data_inf/datainf_master_empty_auto.rb +85 -0
  1023. data/lib/tdl/data_inf/datainf_slaver_empty_auto.rb +68 -0
  1024. data/lib/tdl/data_inf/independent_clock_fifo_auto.rb +141 -0
  1025. data/lib/tdl/data_inf/part_data_pair_map_auto.rb +149 -0
  1026. data/lib/tdl/data_inf/path_lib.rb +18 -0
  1027. data/lib/tdl/elements/Reset.rb +153 -0
  1028. data/lib/tdl/elements/axi4.rb +642 -0
  1029. data/lib/tdl/elements/axi_lite.rb +246 -0
  1030. data/lib/tdl/elements/axi_stream.rb +674 -0
  1031. data/lib/tdl/elements/clock.rb +193 -0
  1032. data/lib/tdl/elements/common_configure_reg.rb +135 -0
  1033. data/lib/tdl/elements/data_inf.rb +660 -0
  1034. data/lib/tdl/elements/logic.rb +356 -0
  1035. data/lib/tdl/elements/mail_box.rb +64 -0
  1036. data/lib/tdl/elements/originclass.rb +689 -0
  1037. data/lib/tdl/elements/parameter.rb +318 -0
  1038. data/lib/tdl/elements/track_inf.rb +163 -0
  1039. data/lib/tdl/elements/videoinf.rb +224 -0
  1040. data/lib/tdl/examples/10_random/exp_random.rb +13 -0
  1041. data/lib/tdl/examples/10_random/exp_random.sv +36 -0
  1042. data/lib/tdl/examples/11_test_unit/dve.tcl +64 -0
  1043. data/lib/tdl/examples/11_test_unit/exp_test_unit.rb +58 -0
  1044. data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +35 -0
  1045. data/lib/tdl/examples/11_test_unit/exp_test_unit_constraints.xdc +25 -0
  1046. data/lib/tdl/examples/11_test_unit/modules/sub_md0.rb +23 -0
  1047. data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +41 -0
  1048. data/lib/tdl/examples/11_test_unit/modules/sub_md1.rb +25 -0
  1049. data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv +41 -0
  1050. data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +28 -0
  1051. data/lib/tdl/examples/11_test_unit/tu0.sv +38 -0
  1052. data/lib/tdl/examples/11_test_unit/tu1.sv +28 -0
  1053. data/lib/tdl/examples/1_define_module/example1.rb +39 -0
  1054. data/lib/tdl/examples/1_define_module/exmple_md.sv +50 -0
  1055. data/lib/tdl/examples/2_hdl_class/always_comb.rb +99 -0
  1056. data/lib/tdl/examples/2_hdl_class/always_ff.rb +143 -0
  1057. data/lib/tdl/examples/2_hdl_class/case.rb +93 -0
  1058. data/lib/tdl/examples/2_hdl_class/foreach.rb +21 -0
  1059. data/lib/tdl/examples/2_hdl_class/function.rb +34 -0
  1060. data/lib/tdl/examples/2_hdl_class/generate.rb +62 -0
  1061. data/lib/tdl/examples/2_hdl_class/module_def.rb +33 -0
  1062. data/lib/tdl/examples/2_hdl_class/module_head_import_package.rb +36 -0
  1063. data/lib/tdl/examples/2_hdl_class/module_instance_test.rb +13 -0
  1064. data/lib/tdl/examples/2_hdl_class/package.rb +29 -0
  1065. data/lib/tdl/examples/2_hdl_class/package2.rb +21 -0
  1066. data/lib/tdl/examples/2_hdl_class/simple_assign.rb +39 -0
  1067. data/lib/tdl/examples/2_hdl_class/state_case.rb +65 -0
  1068. data/lib/tdl/examples/2_hdl_class/struct.rb +25 -0
  1069. data/lib/tdl/examples/2_hdl_class/struct_function.rb +28 -0
  1070. data/lib/tdl/examples/2_hdl_class/test_axi4_M2S.rb +16 -0
  1071. data/lib/tdl/examples/2_hdl_class/test_initial_assert.rb +11 -0
  1072. data/lib/tdl/examples/2_hdl_class/test_inst_sugar.rb +28 -0
  1073. data/lib/tdl/examples/2_hdl_class/test_module_port.rb +47 -0
  1074. data/lib/tdl/examples/2_hdl_class/test_module_var.rb +18 -0
  1075. data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv +108 -0
  1076. data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +35 -0
  1077. data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv +105 -0
  1078. data/lib/tdl/examples/2_hdl_class/tmp/head_pkg_module.sv +42 -0
  1079. data/lib/tdl/examples/2_hdl_class/tmp/init_module.sv +110 -0
  1080. data/lib/tdl/examples/2_hdl_class/tmp/module_instance_test.sv +31 -0
  1081. data/lib/tdl/examples/2_hdl_class/tmp/port_module.sv +99 -0
  1082. data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv +27 -0
  1083. data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv +78 -0
  1084. data/lib/tdl/examples/2_hdl_class/tmp/test_axi4_M2S.sv +30 -0
  1085. data/lib/tdl/examples/2_hdl_class/tmp/test_foreach.sv +34 -0
  1086. data/lib/tdl/examples/2_hdl_class/tmp/test_function.sv +52 -0
  1087. data/lib/tdl/examples/2_hdl_class/tmp/test_initial_assert.sv +31 -0
  1088. data/lib/tdl/examples/2_hdl_class/tmp/test_inst_sugar.sv +42 -0
  1089. data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +36 -0
  1090. data/lib/tdl/examples/2_hdl_class/tmp/test_module_port.sv +33 -0
  1091. data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +35 -0
  1092. data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +38 -0
  1093. data/lib/tdl/examples/2_hdl_class/tmp/test_package2.sv +36 -0
  1094. data/lib/tdl/examples/2_hdl_class/tmp/test_struct.sv +38 -0
  1095. data/lib/tdl/examples/2_hdl_class/tmp/test_struct_function.sv +44 -0
  1096. data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +27 -0
  1097. data/lib/tdl/examples/2_hdl_class/tmp/text_generate.sv +54 -0
  1098. data/lib/tdl/examples/2_hdl_class/vcs_string.rb +5 -0
  1099. data/lib/tdl/examples/3_hdl_sdl_instance/hdl_test.sv +13 -0
  1100. data/lib/tdl/examples/3_hdl_sdl_instance/main.rb +26 -0
  1101. data/lib/tdl/examples/3_hdl_sdl_instance/main_md.sv +42 -0
  1102. data/lib/tdl/examples/3_hdl_sdl_instance/sdl_md.sv +30 -0
  1103. data/lib/tdl/examples/3_hdl_sdl_instance/sdl_test.rb +9 -0
  1104. data/lib/tdl/examples/4_generate/example.rb +38 -0
  1105. data/lib/tdl/examples/4_generate/test_generate.sv +59 -0
  1106. data/lib/tdl/examples/5_logic_combin/login_combin.rb +22 -0
  1107. data/lib/tdl/examples/5_logic_combin/test_logic_combin.sv +36 -0
  1108. data/lib/tdl/examples/6_module_with_interface/example.rb +48 -0
  1109. data/lib/tdl/examples/6_module_with_interface/example_interface.sv +40 -0
  1110. data/lib/tdl/examples/6_module_with_interface/inf_collect.rb +54 -0
  1111. data/lib/tdl/examples/6_module_with_interface/inf_collect.sv +63 -0
  1112. data/lib/tdl/examples/7_module_with_package/body_package.rb +3 -0
  1113. data/lib/tdl/examples/7_module_with_package/body_package.sv +25 -0
  1114. data/lib/tdl/examples/7_module_with_package/example_pkg.rb +20 -0
  1115. data/lib/tdl/examples/7_module_with_package/example_pkg.sv +35 -0
  1116. data/lib/tdl/examples/7_module_with_package/head_package.rb +8 -0
  1117. data/lib/tdl/examples/7_module_with_package/head_package.sv +29 -0
  1118. data/lib/tdl/examples/8_top_module/dve.tcl +64 -0
  1119. data/lib/tdl/examples/8_top_module/example.rb +8 -0
  1120. data/lib/tdl/examples/8_top_module/pins.yml +7 -0
  1121. data/lib/tdl/examples/8_top_module/tb_test_top.sv +29 -0
  1122. data/lib/tdl/examples/8_top_module/test_top.sv +28 -0
  1123. data/lib/tdl/examples/8_top_module/test_top_constraints.xdc +37 -0
  1124. data/lib/tdl/examples/9_itegration/A_itgt/a_test_md.sv +29 -0
  1125. data/lib/tdl/examples/9_itegration/A_itgt/a_test_module.rb +6 -0
  1126. data/lib/tdl/examples/9_itegration/A_itgt/itgt_module_a_block.rb +34 -0
  1127. data/lib/tdl/examples/9_itegration/clock_manage/itgt_module_clock_manage.rb +33 -0
  1128. data/lib/tdl/examples/9_itegration/clock_manage/simple_clock.rb +7 -0
  1129. data/lib/tdl/examples/9_itegration/clock_manage/simple_clock.sv +29 -0
  1130. data/lib/tdl/examples/9_itegration/dve.tcl +64 -0
  1131. data/lib/tdl/examples/9_itegration/pins.yml +4 -0
  1132. data/lib/tdl/examples/9_itegration/tb_test_top.sv +29 -0
  1133. data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +29 -0
  1134. data/lib/tdl/examples/9_itegration/test_top.sv +40 -0
  1135. data/lib/tdl/examples/9_itegration/test_top_constraints.xdc +29 -0
  1136. data/lib/tdl/examples/9_itegration/test_tttop.sv +40 -0
  1137. data/lib/tdl/examples/9_itegration/test_tttop_constraints.xdc +29 -0
  1138. data/lib/tdl/examples/9_itegration/top.rb +11 -0
  1139. data/lib/tdl/examples/readme.md +31 -0
  1140. data/lib/tdl/exlib/common_cfg_reg_inf.rb +139 -0
  1141. data/lib/tdl/exlib/constraints.rb +286 -0
  1142. data/lib/tdl/exlib/constraints_verb.rb +304 -0
  1143. data/lib/tdl/exlib/dve_tcl.rb +162 -0
  1144. data/lib/tdl/exlib/element_class_vars.rb +106 -0
  1145. data/lib/tdl/exlib/global_param.rb +108 -0
  1146. data/lib/tdl/exlib/integral_test/bak/integral_test.rb +206 -0
  1147. data/lib/tdl/exlib/integral_test/clock_itest.rb +28 -0
  1148. data/lib/tdl/exlib/integral_test/diff_clock_itest.rb +30 -0
  1149. data/lib/tdl/exlib/integral_test/io_itest.rb +41 -0
  1150. data/lib/tdl/exlib/integral_test/reset_itest.rb +31 -0
  1151. data/lib/tdl/exlib/integral_test/simple_logic_itest.rb +19 -0
  1152. data/lib/tdl/exlib/itegration.rb +307 -0
  1153. data/lib/tdl/exlib/itegration_verb.rb +913 -0
  1154. data/lib/tdl/exlib/parse_argv.rb +43 -0
  1155. data/lib/tdl/exlib/sdlmodule_sim.bak.rb +375 -0
  1156. data/lib/tdl/exlib/test_point.rb +287 -0
  1157. data/lib/tdl/global_scan.rb +134 -0
  1158. data/lib/tdl/rebuild_ele/axi4.rb +141 -0
  1159. data/lib/tdl/rebuild_ele/axi_lite.rb +56 -0
  1160. data/lib/tdl/rebuild_ele/axi_stream.rb +121 -0
  1161. data/lib/tdl/rebuild_ele/cm_ram_inf.sv +105 -0
  1162. data/lib/tdl/rebuild_ele/cm_ram_inf_define.rb +44 -0
  1163. data/lib/tdl/rebuild_ele/data_inf.rb +27 -0
  1164. data/lib/tdl/rebuild_ele/data_inf_c.rb +83 -0
  1165. data/lib/tdl/rebuild_ele/ele_base.rb +822 -0
  1166. data/lib/tdl/rebuild_ele/readme.md +1 -0
  1167. data/lib/tdl/sdlimplement/resource.yml +154 -0
  1168. data/lib/tdl/sdlimplement/sdl_impl_module.rb +391 -0
  1169. data/lib/tdl/sdlimplement/sdl_impl_param.rb +26 -0
  1170. data/lib/tdl/sdlimplement/test.rb +64 -0
  1171. data/lib/tdl/sdlmodule/bak/sdlmodule_varible_ex.rb +120 -0
  1172. data/lib/tdl/sdlmodule/generator_block_module.rb +84 -0
  1173. data/lib/tdl/sdlmodule/sdlmodule.rb +407 -0
  1174. data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb +333 -0
  1175. data/lib/tdl/sdlmodule/sdlmodule_draw.rb +272 -0
  1176. data/lib/tdl/sdlmodule/sdlmodule_head_logo.txt +10 -0
  1177. data/lib/tdl/sdlmodule/sdlmodule_instance.rb +623 -0
  1178. data/lib/tdl/sdlmodule/sdlmodule_port_define.rb +374 -0
  1179. data/lib/tdl/sdlmodule/sdlmodule_varible.rb +160 -0
  1180. data/lib/tdl/sdlmodule/sdlmodule_vcs_comptable.rb +140 -0
  1181. data/lib/tdl/sdlmodule/techbench_module.rb +14 -0
  1182. data/lib/tdl/sdlmodule/test_unit_module.rb +138 -0
  1183. data/lib/tdl/sdlmodule/top_module.rb +543 -0
  1184. data/lib/tdl/tdl.rb +265 -0
  1185. data/lib/tdl/tdlerror/tdlerror.rb +8 -0
  1186. data/lib/tdl/testunit/test_all.rb +4 -0
  1187. data/lib/tdl/testunit/test_array_chain.rb +89 -0
  1188. data/lib/tdl/testunit/test_tmp.rb +47 -0
  1189. metadata +1301 -0
data/lib/axi/data_interface/datainf_c_master_empty.sv ADDED
@@ -0,0 +1,22 @@
1
+ /**********************************************
2
+ _______________________________________
3
+ ___________ Cook Darwin __________
4
+ _______________________________________
5
+ descript:
6
+ author : Cook.Darwin
7
+ Version: VERA.0.0
8
+ creaded: 2017/6/13
9
+ madified:
10
+ ***********************************************/
11
+ `timescale 1ns/1ps
12
+ (* datainf_c = "true" *)
13
+ module datainf_c_master_empty (
14
+ (* data_down = "true" *)
15
+ data_inf_c.master master
16
+ );
17
+
18
+
19
+ assign master.valid = 1'b0;
20
+ assign master.data = '0;
21
+
22
+ endmodule
data/lib/axi/data_interface/datainf_c_slaver_empty.sv ADDED
@@ -0,0 +1,22 @@
1
+ /**********************************************
2
+ _______________________________________
3
+ ___________ Cook Darwin __________
4
+ _______________________________________
5
+ descript:
6
+ author : Cook.Darwin
7
+ Version: VERA.0.0
8
+ creaded: 2017/6/13
9
+ madified:
10
+ ***********************************************/
11
+ `timescale 1ns/1ps
12
+ (* datainf_c = "true" *)
13
+ module datainf_c_slaver_empty (
14
+ (* data_up = "true" *)
15
+ data_inf_c.slaver slaver
16
+ );
17
+
18
+ assign slaver.ready = 1'b1;
19
+ // assign master.valid = 1'b0;
20
+ // assign master.data = '0;
21
+
22
+ endmodule
data/lib/axi/data_interface/datainf_master_empty.sv ADDED
@@ -0,0 +1,22 @@
1
+ /**********************************************
2
+ _______________________________________
3
+ ___________ Cook Darwin __________
4
+ _______________________________________
5
+ descript:
6
+ author : Cook.Darwin
7
+ Version: VERA.0.0
8
+ creaded: 2017/6/13
9
+ madified:
10
+ ***********************************************/
11
+ `timescale 1ns/1ps
12
+ (* datainf = "true" *)
13
+ module datainf_master_empty (
14
+ (* data_down = "true" *)
15
+ data_inf.master master
16
+ );
17
+
18
+
19
+ assign master.valid = 1'b0;
20
+ assign master.data = '0;
21
+
22
+ endmodule
data/lib/axi/data_interface/datainf_slaver_empty.sv ADDED
@@ -0,0 +1,22 @@
1
+ /**********************************************
2
+ _______________________________________
3
+ ___________ Cook Darwin __________
4
+ _______________________________________
5
+ descript:
6
+ author : Cook.Darwin
7
+ Version: VERA.0.0
8
+ creaded: 2017/6/13
9
+ madified:
10
+ ***********************************************/
11
+ `timescale 1ns/1ps
12
+ (* datainf = "true" *)
13
+ module datainf_slaver_empty (
14
+ (* data_up = "true" *)
15
+ data_inf.slaver slaver
16
+ );
17
+
18
+ assign slaver.ready = 1'b1;
19
+ // assign master.valid = 1'b0;
20
+ // assign master.data = '0;
21
+
22
+ endmodule
data/lib/axi/data_interface/part_data_pair_map.sv ADDED
@@ -0,0 +1,111 @@
1
+ /**********************************************
2
+ _______________________________________
3
+ ___________ Cook Darwin __________
4
+ _______________________________________
5
+ descript:
6
+ author : Cook.Darwin
7
+ Version: VERA.0.0
8
+ creaded: 2017/6/7
9
+ madified:
10
+ ***********************************************/
11
+ // `include "define_macro.sv"
12
+ `timescale 1ns/1ps
13
+ (* datainf_c = "true" *)
14
+ module part_data_pair_map #(
15
+ parameter NUM = 8,
16
+ parameter ISIZE = 8,
17
+ parameter OSIZE = 8
18
+ )(
19
+ //-->> WRITE
20
+ data_inf_c.slaver write_inf, //data -> [ISIZE-1:0][OSIZE-1:0]
21
+ //-->> READ <<----------------
22
+ data_inf_c.slaver ipart_inf, //data -> [ISIZE-1:0] + other
23
+ data_inf_c.slaver opart_inf, //data -> [OSIZE-1:0] + other
24
+ //-->> DELETE
25
+ data_inf_c.slaver idel_inf, //data -> [ISIZE-1:0]
26
+ data_inf_c.slaver odel_inf, //data -> [OSIZE-1:0]
27
+ //-->> OUT
28
+ data_inf_c.master Oipart_inf, //data -> [ISIZE-1:0][OSIZE-1:0] + other
29
+ data_inf_c.master Oopart_inf, //data -> [ISIZE-1:0][OSIZE-1:0] + other
30
+ //-->> err
31
+ data_inf_c.master ierr_inf, //data -> [ISIZE-1:0]
32
+ data_inf_c.master oerr_inf //data -> [OSIZE-1:0]
33
+ );
34
+
35
+ // `CheckParamPair(fid_addr_len_inf.DSIZE,96)
36
+
37
+ data_inf_c #(.DSIZE(ISIZE)) iread_inf (ipart_inf.clock,ipart_inf.rst_n);
38
+ data_inf_c #(.DSIZE(ISIZE)) tmp_iread_inf (ipart_inf.clock,ipart_inf.rst_n);
39
+ data_inf_c #(.DSIZE(OSIZE)) oread_inf (ipart_inf.clock,ipart_inf.rst_n);
40
+ data_inf_c #(.DSIZE(ISIZE+OSIZE)) Oiread_inf (ipart_inf.clock,ipart_inf.rst_n);
41
+ data_inf_c #(.DSIZE(ISIZE+OSIZE)) Ooread_inf (ipart_inf.clock,ipart_inf.rst_n);
42
+
43
+ assign iread_inf.data = ipart_inf.data[ipart_inf.DSIZE-1-:ISIZE];
44
+ // assign iread_inf.data = '1;
45
+ assign iread_inf.valid = ipart_inf.valid;
46
+ assign ipart_inf.ready = iread_inf.ready;
47
+
48
+ assign oread_inf.data = opart_inf.data[opart_inf.DSIZE-1-:OSIZE];
49
+ assign oread_inf.valid = opart_inf.valid;
50
+ assign opart_inf.ready = oread_inf.ready;
51
+
52
+ data_pair_map_A2 #(
53
+ .ISIZE (ISIZE ),
54
+ .OSIZE (OSIZE ),
55
+ .NUM (NUM )
56
+ )data_pair_map_A2_inst(
57
+ //-->> WRITE
58
+ /* data_inf_c.slaver */ .write_inf (write_inf ), //data -> [ISIZE-1:0][OSIZE-1:0]
59
+ //-->> READ <<----------------
60
+ /* data_inf_c.slaver */ .iread_inf (iread_inf ), //data -> [ISIZE-1:0]
61
+ /* data_inf_c.slaver */ .oread_inf (oread_inf ), //data -> [OSIZE-1:0]
62
+ //-->> DELETE
63
+ /* data_inf_c.slaver */ .idel_inf (idel_inf ), //data -> [ISIZE-1:0]
64
+ /* data_inf_c.slaver */ .odel_inf (odel_inf ), //data -> [OSIZE-1:0]
65
+ //-->> OUT
66
+ /* data_inf_c.master */ .Oiread_inf (Oiread_inf ), //data -> [OSIZE-1:0]
67
+ /* data_inf_c.master */ .Ooread_inf (Ooread_inf ), //data -> [ISIZE-1:0]
68
+ //-->> err
69
+ /* data_inf_c.master */ .ierr_inf (ierr_inf ), //data -> [ISIZE-1:0]
70
+ /* data_inf_c.master */ .oerr_inf (oerr_inf ) //data -> [OSIZE-1:0]
71
+ );
72
+
73
+
74
+ logic [opart_inf.DSIZE-OSIZE-1:0] ipart_slaver_data;
75
+ logic [opart_inf.DSIZE-OSIZE-1:0] opart_slaver_data;
76
+
77
+ simple_data_pipe_slaver #(
78
+ .DSIZE (ipart_inf.DSIZE-ISIZE)
79
+ )simple_data_pipe_slaver_inst_i(
80
+ /* input */ .clock (ipart_inf.clock ),
81
+ /* input */ .rst_n (ipart_inf.rst_n ),
82
+ /* input [DSIZE-1:0] */ .indata (ipart_inf.data[ipart_inf.DSIZE-ISIZE-1:0]),
83
+ /* input */ .invalid (ipart_inf.valid ),
84
+ /* input */ .inready (ipart_inf.ready ),
85
+ /* output logic[DSIZE-1:0] */ .outdata (ipart_slaver_data ),
86
+ /* input */ .outvalid (Oiread_inf.valid ),
87
+ /* input */ .outready (Oiread_inf.ready )
88
+ );
89
+
90
+ simple_data_pipe_slaver #(
91
+ .DSIZE (opart_inf.DSIZE-OSIZE)
92
+ )simple_data_pipe_slaver_inst_o(
93
+ /* input */ .clock (opart_inf.clock ),
94
+ /* input */ .rst_n (opart_inf.rst_n ),
95
+ /* input [DSIZE-1:0] */ .indata (opart_inf.data[opart_inf.DSIZE-OSIZE-1:0]),
96
+ /* input */ .invalid (opart_inf.valid ),
97
+ /* input */ .inready (opart_inf.ready ),
98
+ /* output logic[DSIZE-1:0] */ .outdata (opart_slaver_data ),
99
+ /* input */ .outvalid (Ooread_inf.valid ),
100
+ /* input */ .outready (Ooread_inf.ready )
101
+ );
102
+
103
+ assign Oipart_inf.data = {Oiread_inf.data,ipart_slaver_data};
104
+ assign Oipart_inf.valid = Oiread_inf.valid;
105
+ assign Oiread_inf.ready = Oipart_inf.ready;
106
+
107
+ assign Oopart_inf.data = {Ooread_inf.data,opart_slaver_data};
108
+ assign Oopart_inf.valid = Ooread_inf.valid;
109
+ assign Ooread_inf.ready = Oopart_inf.ready;
110
+
111
+ endmodule
data/lib/axi/interface_define/axi_aux_inf.sv ADDED
@@ -0,0 +1,206 @@
1
+ interface axi_wr_aux_inf();
2
+
3
+ logic[2:0] axi_awsize ;
4
+ logic[1:0] axi_awburst ;
5
+ logic[0:0] axi_awlock ;
6
+ logic[3:0] axi_awcache ;
7
+ logic[2:0] axi_awprot ;
8
+ logic[3:0] axi_awqos ;
9
+
10
+ modport master (
11
+ output axi_awsize ,
12
+ output axi_awburst ,
13
+ output axi_awlock ,
14
+ output axi_awcache ,
15
+ output axi_awprot ,
16
+ output axi_awqos
17
+ );
18
+
19
+ modport slaver (
20
+ input axi_awsize ,
21
+ input axi_awburst ,
22
+ input axi_awlock ,
23
+ input axi_awcache ,
24
+ input axi_awprot ,
25
+ input axi_awqos
26
+ );
27
+
28
+ endinterface : axi_wr_aux_inf
29
+
30
+ interface axi_rd_aux_inf();
31
+
32
+ logic[2:0] axi_arsize ;
33
+ logic[1:0] axi_arburst ;
34
+ logic[0:0] axi_arlock ;
35
+ logic[3:0] axi_arcache ;
36
+ logic[2:0] axi_arprot ;
37
+ logic[3:0] axi_arqos ;
38
+
39
+ modport master (
40
+ output axi_arsize ,
41
+ output axi_arburst ,
42
+ output axi_arlock ,
43
+ output axi_arcache ,
44
+ output axi_arprot ,
45
+ output axi_arqos
46
+ );
47
+
48
+ modport slaver (
49
+ input axi_arsize ,
50
+ input axi_arburst ,
51
+ input axi_arlock ,
52
+ input axi_arcache ,
53
+ input axi_arprot ,
54
+ input axi_arqos
55
+ );
56
+
57
+ endinterface : axi_rd_aux_inf
58
+
59
+ interface axi_aw_inf #(
60
+ parameter IDSIZE = 1,
61
+ parameter ASIZE = 32,
62
+ parameter LSIZE = 1
63
+ )();
64
+
65
+ logic[IDSIZE-1:0] axi_awid ;
66
+ logic[ASIZE-1:0] axi_awaddr ;
67
+ logic[LSIZE-1:0] axi_awlen ;
68
+ logic axi_awvalid ;
69
+ logic axi_awready ;
70
+
71
+ modport master (
72
+ output axi_awid ,
73
+ output axi_awaddr ,
74
+ output axi_awlen ,
75
+ output axi_awvalid,
76
+ input axi_awready
77
+ );
78
+
79
+ modport slaver (
80
+ input axi_awid ,
81
+ input axi_awaddr ,
82
+ input axi_awlen ,
83
+ input axi_awvalid,
84
+ output axi_awready
85
+ );
86
+
87
+ endinterface : axi_aw_inf
88
+
89
+ interface axi_ar_inf #(
90
+ parameter IDSIZE = 1,
91
+ parameter ASIZE = 32,
92
+ parameter LSIZE = 1
93
+ )();
94
+
95
+ logic[IDSIZE-1:0] axi_arid ;
96
+ logic[ASIZE-1:0] axi_araddr ;
97
+ logic[LSIZE-1:0] axi_arlen ;
98
+ logic axi_arvalid ;
99
+ logic axi_arready ;
100
+
101
+ modport master (
102
+ output axi_arid ,
103
+ output axi_araddr ,
104
+ output axi_arlen ,
105
+ output axi_arvalid,
106
+ input axi_arready
107
+ );
108
+
109
+ modport slaver (
110
+ input axi_arid ,
111
+ input axi_araddr ,
112
+ input axi_arlen ,
113
+ input axi_arvalid,
114
+ output axi_arready
115
+ );
116
+
117
+ endinterface : axi_ar_inf
118
+
119
+ interface axi_wdata_inf #(
120
+ parameter DSIZE = 32
121
+ )();
122
+
123
+ localparam STSIZE = DSIZE/8+(DSIZE%8 != 0);
124
+
125
+ logic[DSIZE-1:0] axi_wdata ;
126
+ logic[STSIZE-1:0] axi_wstrb ;
127
+ logic axi_wlast ;
128
+ logic axi_wvalid ;
129
+ logic axi_wready ;
130
+
131
+ modport master (
132
+ output axi_wdata ,
133
+ output axi_wstrb ,
134
+ output axi_wlast ,
135
+ output axi_wvalid ,
136
+ input axi_wready
137
+ );
138
+
139
+ modport slaver (
140
+ input axi_wdata ,
141
+ input axi_wstrb ,
142
+ input axi_wlast ,
143
+ input axi_wvalid ,
144
+ output axi_wready
145
+ );
146
+
147
+ endinterface : axi_wdata_inf
148
+
149
+ interface axi_rdata_inf #(
150
+ parameter DSIZE = 32,
151
+ parameter IDSIZE = 1
152
+ )();
153
+
154
+
155
+ logic[IDSIZE-1:0] axi_rid ;
156
+ logic[DSIZE-1:0] axi_rdata ;
157
+ logic[1:0] axi_rresp ;
158
+ logic axi_rlast ;
159
+ logic axi_rvalid ;
160
+ logic axi_rready ;
161
+
162
+ modport master (
163
+ input axi_rid ,
164
+ input axi_rdata ,
165
+ input axi_rresp ,
166
+ input axi_rlast ,
167
+ input axi_rvalid ,
168
+ output axi_rready
169
+ );
170
+
171
+ modport slaver (
172
+ output axi_rid ,
173
+ output axi_rdata ,
174
+ output axi_rresp ,
175
+ output axi_rlast ,
176
+ output axi_rvalid ,
177
+ input axi_rready
178
+ );
179
+
180
+
181
+ endinterface : axi_rdata_inf
182
+
183
+ interface axi_resp_inf #(
184
+ parameter IDSIZE = 1
185
+ )();
186
+
187
+ logic axi_bready ;
188
+ logic[IDSIZE-1:0] axi_bid ;
189
+ logic[1:0] axi_bresp ;
190
+ logic axi_bvalid ;
191
+
192
+ modport master (
193
+ output axi_bready ,
194
+ input axi_bid ,
195
+ input axi_bresp ,
196
+ input axi_bvalid
197
+ );
198
+
199
+ modport slaver (
200
+ input axi_bready ,
201
+ output axi_bid ,
202
+ output axi_bresp ,
203
+ output axi_bvalid
204
+ );
205
+
206
+ endinterface : axi_resp_inf
data/lib/axi/interface_define/axi_inf.sv ADDED
@@ -0,0 +1,1256 @@
1
+ `timescale 1ns/1ps
2
+ `include "define_macro.sv"
3
+ interface axi_inf #(
4
+ parameter IDSIZE = 1,
5
+ parameter ASIZE = 32,
6
+ parameter LSIZE = 1,
7
+ parameter DSIZE = 32,
8
+ `parameter_string MODE = "BOTH", //BOTH:0,ONLY_WRITE:1,ONLY_READ:2
9
+ parameter ADDR_STEP = 32'hFFFF_FFFF, // 1024 : 0
10
+ parameter real FreqM = 1
11
+ )(
12
+ input bit axi_aclk ,
13
+ input bit axi_aresetn
14
+ );
15
+
16
+ initial begin
17
+ if(MODE == "BOTH" || MODE == "ONLY_READ" || MODE == "ONLY_WRITE")
18
+ #(1ps);
19
+ else begin
20
+ $error("$t,AXI INFTERFACE MODE PARAMETER ERROR >>%s<<",MODE);
21
+ $finish;
22
+ end
23
+ end
24
+
25
+ logic timeout;
26
+
27
+ localparam STSIZE = DSIZE/8+(DSIZE%8 != 0);
28
+ //--->> addr write <<-------
29
+ logic[IDSIZE-1:0] axi_awid ;
30
+ logic[ASIZE-1:0] axi_awaddr ;
31
+ logic[LSIZE-1:0] axi_awlen ;
32
+ logic[2:0] axi_awsize ;
33
+ logic[1:0] axi_awburst ;
34
+ logic[0:0] axi_awlock ;
35
+ logic[3:0] axi_awcache ;
36
+ logic[2:0] axi_awprot ;
37
+ logic[3:0] axi_awqos ;
38
+ logic axi_awvalid ;
39
+ logic axi_awready ;
40
+ //---<< addr write >>-------
41
+ //--->> addr read <<--------
42
+ logic[IDSIZE-1:0] axi_arid ;
43
+ logic[ASIZE-1:0] axi_araddr ;
44
+ logic[LSIZE-1:0] axi_arlen ;
45
+ logic[2:0] axi_arsize ;
46
+ logic[1:0] axi_arburst ;
47
+ logic[0:0] axi_arlock ;
48
+ logic[3:0] axi_arcache ;
49
+ logic[2:0] axi_arprot ;
50
+ logic[3:0] axi_arqos ;
51
+ logic axi_arvalid ;
52
+ logic axi_arready ;
53
+ //---<< addr read >>--------
54
+ //--->> Response <<---------
55
+ logic axi_bready ;
56
+ logic[IDSIZE-1:0] axi_bid ;
57
+ logic[1:0] axi_bresp ;
58
+ logic axi_bvalid ;
59
+ //---<< Response >>---------
60
+ //--->> data write <<-------
61
+ logic[DSIZE-1:0] axi_wdata ;
62
+ logic[STSIZE-1:0] axi_wstrb ;
63
+ logic axi_wlast ;
64
+ logic axi_wvalid ;
65
+ logic axi_wready ;
66
+ //---<< data write >>-------
67
+ //--->> data read >>--------
68
+ logic axi_rready ;
69
+ logic[IDSIZE-1:0] axi_rid ;
70
+ logic[DSIZE-1:0] axi_rdata ;
71
+ logic[1:0] axi_rresp ;
72
+ logic axi_rlast ;
73
+ logic axi_rvalid ;
74
+ //---<< data read >>--------
75
+ //--->> error flag <<-------
76
+ // logic axi_wevld ;
77
+ // logic[3:0] axi_weresp ;
78
+ // logic axi_revld ;
79
+ // logic[3:0] axi_reresp ;
80
+ //---<< error flag >>-------
81
+
82
+ //--->> TIME CTRL <<---------------
83
+ always@(posedge axi_aclk,negedge axi_aresetn)begin:TIME_BLOCK
84
+ logic cen;
85
+ logic crst;
86
+ logic [23:0] tcnt;
87
+ if(~axi_aresetn)begin
88
+ tcnt <= 24'd0;
89
+ cen <= 1'b0;
90
+ crst <= 1'b0;
91
+ end else begin
92
+ //-->> COUNT ENABLE
93
+ if(axi_awready && axi_awvalid)
94
+ cen <= 1'b1;
95
+ else if(axi_arready && axi_arvalid)
96
+ cen <= 1'b1;
97
+ else if(axi_bready && axi_bvalid)
98
+ cen <= 1'b0;
99
+ else if(axi_rvalid && axi_rready)
100
+ cen <= 1'b0;
101
+ else cen <= cen;
102
+ //-->> COUNT RST
103
+ if(axi_awready && axi_awvalid)
104
+ crst <= 1'b1;
105
+ else if(axi_arready && axi_arvalid)
106
+ crst <= 1'b1;
107
+ else if(axi_wready && axi_wvalid)
108
+ crst <= 1'b1;
109
+ else if(axi_rready && axi_rvalid)
110
+ crst <= 1'b1;
111
+ else crst <= 1'b0;
112
+ //-->> COUNT
113
+ if(crst)
114
+ tcnt <= 24'd0;
115
+ else if(cen)
116
+ tcnt <= tcnt + 1'b1;
117
+ else tcnt <= tcnt;
118
+ //-->> RESULT
119
+ timeout <= &tcnt;
120
+ end
121
+ end
122
+ //---<< TIME CTRL >>---------------
123
+ //--->> AW_CNT <<-----------------
124
+ logic [LSIZE-1:0] axi_wcnt;
125
+
126
+ always@(posedge axi_aclk,negedge axi_aresetn)begin:WRITE_CNT
127
+ if(~axi_aresetn) axi_wcnt <= '0;
128
+ else begin
129
+ if(axi_wvalid && axi_wready && axi_wlast)
130
+ axi_wcnt <= '0;
131
+ else if(axi_wvalid && axi_wready)
132
+ axi_wcnt <= axi_wcnt + 1'b1;
133
+ else axi_wcnt <= axi_wcnt;
134
+ end
135
+ end
136
+ //---<< AW_CNT >>-----------------
137
+ //--->> AR_CNT <<-----------------
138
+ logic [LSIZE-1:0] axi_rcnt;
139
+
140
+ always@(posedge axi_aclk,negedge axi_aresetn)begin:READ_CNT
141
+ if(~axi_aresetn) axi_rcnt <= '0;
142
+ else begin
143
+ if(axi_rvalid && axi_rready && axi_rlast)
144
+ axi_rcnt <= '0;
145
+ else if(axi_rvalid && axi_rready)
146
+ axi_rcnt <= axi_rcnt + 1'b1;
147
+ else axi_rcnt <= axi_rcnt;
148
+ end
149
+ end
150
+ //---<< AR_CNT >>-----------------
151
+ //--->> MODE CTRL <<---------------
152
+ `ifdef VIVADO_ENV
153
+ generate
154
+ if(MODE=="ONLY_READ")begin
155
+ assign axi_awid = '0;
156
+ assign axi_awaddr = '0;
157
+ assign axi_awlen = '0;
158
+ assign axi_awsize = '0;
159
+ assign axi_awburst = '0;
160
+ assign axi_awlock = '0;
161
+ assign axi_awcache = '0;
162
+ assign axi_awprot = '0;
163
+ assign axi_awqos = '0;
164
+ assign axi_awvalid = '0;
165
+ assign axi_wdata = '0;
166
+ assign axi_wstrb = '0;
167
+ assign axi_wlast = '0;
168
+ assign axi_wvalid = '0;
169
+ assign axi_bready = '0;
170
+ end
171
+ endgenerate
172
+
173
+ generate
174
+ if(MODE=="ONLY_WRITE")begin
175
+ assign axi_arid = '0;
176
+ assign axi_araddr = '0;
177
+ assign axi_arlen = '0;
178
+ assign axi_arsize = '0;
179
+ assign axi_arburst = '0;
180
+ assign axi_arlock = '0;
181
+ assign axi_arcache = '0;
182
+ assign axi_arprot = '0;
183
+ assign axi_arqos = '0;
184
+ assign axi_arvalid = '0;
185
+ assign axi_rready = '0;
186
+ end
187
+ endgenerate
188
+ `endif
189
+
190
+ //---<< MODE CTRL >>---------------
191
+ modport slaver (
192
+ input axi_aclk ,
193
+ input axi_aresetn ,
194
+ input axi_awid ,
195
+ input axi_awaddr ,
196
+ input axi_awlen ,
197
+ input axi_awsize ,
198
+ input axi_awburst ,
199
+ input axi_awlock ,
200
+ input axi_awcache ,
201
+ input axi_awprot ,
202
+ input axi_awqos ,
203
+ input axi_awvalid ,
204
+ output axi_awready ,
205
+ input axi_wdata ,
206
+ input axi_wstrb ,
207
+ input axi_wlast ,
208
+ input axi_wvalid ,
209
+ output axi_wready ,
210
+ input axi_bready ,
211
+ output axi_bid ,
212
+ output axi_bresp ,
213
+ output axi_bvalid ,
214
+ input axi_arid ,
215
+ input axi_araddr ,
216
+ input axi_arlen ,
217
+ input axi_arsize ,
218
+ input axi_arburst ,
219
+ input axi_arlock ,
220
+ input axi_arcache ,
221
+ input axi_arprot ,
222
+ input axi_arqos ,
223
+ input axi_arvalid ,
224
+ output axi_arready ,
225
+ input axi_rready ,
226
+ output axi_rid ,
227
+ output axi_rdata ,
228
+ output axi_rresp ,
229
+ output axi_rlast ,
230
+ output axi_rvalid ,
231
+
232
+ input axi_wcnt,
233
+ input axi_rcnt,
234
+ // input axi_wevld ,
235
+ // input axi_weresp ,
236
+ // input axi_revld ,
237
+ // input axi_reresp ,
238
+ input timeout
239
+ );
240
+
241
+ modport master (
242
+ input axi_aclk ,
243
+ input axi_aresetn ,
244
+ output axi_awid ,
245
+ output axi_awaddr ,
246
+ output axi_awlen ,
247
+ output axi_awsize ,
248
+ output axi_awburst ,
249
+ output axi_awlock ,
250
+ output axi_awcache ,
251
+ output axi_awprot ,
252
+ output axi_awqos ,
253
+ output axi_awvalid ,
254
+ input axi_awready ,
255
+ output axi_wdata ,
256
+ output axi_wstrb ,
257
+ output axi_wlast ,
258
+ output axi_wvalid ,
259
+ input axi_wready ,
260
+ output axi_bready ,
261
+ input axi_bid ,
262
+ input axi_bresp ,
263
+ input axi_bvalid ,
264
+ output axi_arid ,
265
+ output axi_araddr ,
266
+ output axi_arlen ,
267
+ output axi_arsize ,
268
+ output axi_arburst ,
269
+ output axi_arlock ,
270
+ output axi_arcache ,
271
+ output axi_arprot ,
272
+ output axi_arqos ,
273
+ output axi_arvalid ,
274
+ input axi_arready ,
275
+ output axi_rready ,
276
+ input axi_rid ,
277
+ input axi_rdata ,
278
+ input axi_rresp ,
279
+ input axi_rlast ,
280
+ input axi_rvalid ,
281
+ input axi_wcnt,
282
+ input axi_rcnt,
283
+ // input axi_wevld ,
284
+ // input axi_weresp ,
285
+ // input axi_revld ,
286
+ // input axi_reresp ,
287
+ input timeout
288
+ );
289
+
290
+ modport master_wr (
291
+ input axi_aclk ,
292
+ input axi_aresetn ,
293
+ output axi_awid ,
294
+ output axi_awaddr ,
295
+ output axi_awlen ,
296
+ output axi_awsize ,
297
+ output axi_awburst ,
298
+ output axi_awlock ,
299
+ output axi_awcache ,
300
+ output axi_awprot ,
301
+ output axi_awqos ,
302
+ output axi_awvalid ,
303
+ input axi_awready ,
304
+ output axi_wdata ,
305
+ output axi_wstrb ,
306
+ output axi_wlast ,
307
+ output axi_wvalid ,
308
+ input axi_wready ,
309
+ output axi_bready ,
310
+ input axi_bid ,
311
+ input axi_bresp ,
312
+ input axi_bvalid ,
313
+ input axi_wcnt,
314
+ // input axi_rcnt,
315
+ input timeout
316
+ );
317
+
318
+ modport master_rd (
319
+ input axi_aclk ,
320
+ input axi_aresetn ,
321
+ output axi_arid ,
322
+ output axi_araddr ,
323
+ output axi_arlen ,
324
+ output axi_arsize ,
325
+ output axi_arburst ,
326
+ output axi_arlock ,
327
+ output axi_arcache ,
328
+ output axi_arprot ,
329
+ output axi_arqos ,
330
+ output axi_arvalid ,
331
+ input axi_arready ,
332
+ output axi_rready ,
333
+ input axi_rid ,
334
+ input axi_rdata ,
335
+ input axi_rresp ,
336
+ input axi_rlast ,
337
+ input axi_rvalid ,
338
+ // input axi_wcnt,
339
+ input axi_rcnt,
340
+ input timeout
341
+ );
342
+
343
+ modport slaver_wr (
344
+ input axi_aclk ,
345
+ input axi_aresetn ,
346
+ input axi_awid ,
347
+ input axi_awaddr ,
348
+ input axi_awlen ,
349
+ input axi_awsize ,
350
+ input axi_awburst ,
351
+ input axi_awlock ,
352
+ input axi_awcache ,
353
+ input axi_awprot ,
354
+ input axi_awqos ,
355
+ input axi_awvalid ,
356
+ output axi_awready ,
357
+ input axi_wdata ,
358
+ input axi_wstrb ,
359
+ input axi_wlast ,
360
+ input axi_wvalid ,
361
+ output axi_wready ,
362
+ input axi_bready ,
363
+ output axi_bid ,
364
+ output axi_bresp ,
365
+ output axi_bvalid ,
366
+ input axi_wcnt,
367
+ // input axi_rcnt,
368
+ input timeout
369
+ );
370
+
371
+ modport slaver_rd (
372
+ input axi_aclk ,
373
+ input axi_aresetn ,
374
+ input axi_arid ,
375
+ input axi_araddr ,
376
+ input axi_arlen ,
377
+ input axi_arsize ,
378
+ input axi_arburst ,
379
+ input axi_arlock ,
380
+ input axi_arcache ,
381
+ input axi_arprot ,
382
+ input axi_arqos ,
383
+ input axi_arvalid ,
384
+ output axi_arready ,
385
+ input axi_rready ,
386
+ output axi_rid ,
387
+ output axi_rdata ,
388
+ output axi_rresp ,
389
+ output axi_rlast ,
390
+ output axi_rvalid ,
391
+ // input axi_wcnt,
392
+ input axi_rcnt,
393
+ input timeout
394
+ );
395
+
396
+ modport master_wr_aux (
397
+ input axi_aclk ,
398
+ input axi_aresetn ,
399
+ output axi_awid ,
400
+ output axi_awaddr ,
401
+ output axi_awlen ,
402
+ output axi_awsize ,
403
+ output axi_awburst ,
404
+ output axi_awlock ,
405
+ output axi_awcache ,
406
+ output axi_awprot ,
407
+ output axi_awqos ,
408
+ output axi_awvalid ,
409
+ input axi_awready ,
410
+ // output axi_wdata ,
411
+ // output axi_wstrb ,
412
+ input axi_wlast ,
413
+ input axi_wvalid ,
414
+ input axi_wready ,
415
+ output axi_bready ,
416
+ input axi_bid ,
417
+ input axi_bresp ,
418
+ input axi_bvalid ,
419
+ input axi_wcnt,
420
+ input axi_rcnt,
421
+ input timeout
422
+ );
423
+
424
+ modport master_wr_aux_no_resp (
425
+ input axi_aclk ,
426
+ input axi_aresetn ,
427
+ output axi_awid ,
428
+ output axi_awaddr ,
429
+ output axi_awlen ,
430
+ output axi_awsize ,
431
+ output axi_awburst ,
432
+ output axi_awlock ,
433
+ output axi_awcache ,
434
+ output axi_awprot ,
435
+ output axi_awqos ,
436
+ output axi_awvalid ,
437
+ input axi_awready ,
438
+ // output axi_wdata ,
439
+ // output axi_wstrb ,
440
+ input axi_wlast ,
441
+ input axi_wvalid ,
442
+ input axi_wready ,
443
+ // input axi_bready ,
444
+ // input axi_bid ,
445
+ // input axi_bresp ,
446
+ // input axi_bvalid ,
447
+ input axi_wcnt,
448
+ // input axi_rcnt,
449
+ input timeout
450
+ );
451
+
452
+ modport master_rd_aux (
453
+ input axi_aclk ,
454
+ input axi_aresetn ,
455
+ output axi_arid ,
456
+ output axi_araddr ,
457
+ output axi_arlen ,
458
+ output axi_arsize ,
459
+ output axi_arburst ,
460
+ output axi_arlock ,
461
+ output axi_arcache ,
462
+ output axi_arprot ,
463
+ output axi_arqos ,
464
+ output axi_arvalid ,
465
+ input axi_arready ,
466
+ input axi_rready ,
467
+ input axi_rid ,
468
+ // input axi_rdata ,
469
+ input axi_rresp ,
470
+ input axi_rlast ,
471
+ input axi_rvalid ,
472
+ // input axi_wcnt,
473
+ input axi_rcnt,
474
+ input timeout
475
+ );
476
+
477
+ modport mirror (
478
+ input axi_aclk ,
479
+ input axi_aresetn ,
480
+ input axi_awid ,
481
+ input axi_awaddr ,
482
+ input axi_awlen ,
483
+ input axi_awsize ,
484
+ input axi_awburst ,
485
+ input axi_awlock ,
486
+ input axi_awcache ,
487
+ input axi_awprot ,
488
+ input axi_awqos ,
489
+ input axi_awvalid ,
490
+ input axi_awready ,
491
+ input axi_wdata ,
492
+ input axi_wstrb ,
493
+ input axi_wlast ,
494
+ input axi_wvalid ,
495
+ input axi_wready ,
496
+ input axi_bready ,
497
+ input axi_bid ,
498
+ input axi_bresp ,
499
+ input axi_bvalid ,
500
+ input axi_arid ,
501
+ input axi_araddr ,
502
+ input axi_arlen ,
503
+ input axi_arsize ,
504
+ input axi_arburst ,
505
+ input axi_arlock ,
506
+ input axi_arcache ,
507
+ input axi_arprot ,
508
+ input axi_arqos ,
509
+ input axi_arvalid ,
510
+ input axi_arready ,
511
+ input axi_rready ,
512
+ input axi_rid ,
513
+ input axi_rdata ,
514
+ input axi_rresp ,
515
+ input axi_rlast ,
516
+ input axi_rvalid ,
517
+ input axi_wcnt,
518
+ input axi_rcnt,
519
+ // output axi_wevld ,
520
+ // output axi_weresp ,
521
+ // output axi_revld ,
522
+ // output axi_reresp ,
523
+ input timeout
524
+ );
525
+
526
+ modport mirror_wr (
527
+ input axi_aclk ,
528
+ input axi_aresetn ,
529
+ input axi_awid ,
530
+ input axi_awaddr ,
531
+ input axi_awlen ,
532
+ input axi_awsize ,
533
+ input axi_awburst ,
534
+ input axi_awlock ,
535
+ input axi_awcache ,
536
+ input axi_awprot ,
537
+ input axi_awqos ,
538
+ input axi_awvalid ,
539
+ input axi_awready ,
540
+ input axi_wdata ,
541
+ input axi_wstrb ,
542
+ input axi_wlast ,
543
+ input axi_wvalid ,
544
+ input axi_wready ,
545
+ input axi_bready ,
546
+ input axi_bid ,
547
+ input axi_bresp ,
548
+ input axi_bvalid ,
549
+ input axi_wcnt,
550
+ // output axi_wevld ,
551
+ // output axi_weresp ,
552
+ // output axi_revld ,
553
+ // output axi_reresp ,
554
+ input timeout
555
+ );
556
+
557
+ modport mirror_rd (
558
+ input axi_aclk ,
559
+ input axi_aresetn ,
560
+ input axi_arid ,
561
+ input axi_araddr ,
562
+ input axi_arlen ,
563
+ input axi_arsize ,
564
+ input axi_arburst ,
565
+ input axi_arlock ,
566
+ input axi_arcache ,
567
+ input axi_arprot ,
568
+ input axi_arqos ,
569
+ input axi_arvalid ,
570
+ input axi_arready ,
571
+ input axi_rready ,
572
+ input axi_rid ,
573
+ input axi_rdata ,
574
+ input axi_rresp ,
575
+ input axi_rlast ,
576
+ input axi_rvalid ,
577
+ input axi_rcnt,
578
+ // output axi_wevld ,
579
+ // output axi_weresp ,
580
+ // output axi_revld ,
581
+ // output axi_reresp ,
582
+ input timeout
583
+ );
584
+
585
+ modport lite_master(
586
+ input axi_aclk ,
587
+ input axi_aresetn ,
588
+ output axi_awvalid ,
589
+ input axi_awready ,
590
+ output axi_awaddr ,
591
+ output axi_wvalid ,
592
+ input axi_wready ,
593
+ output axi_wdata ,
594
+ input axi_bresp ,
595
+ input axi_bvalid ,
596
+ output axi_bready ,
597
+ output axi_arvalid ,
598
+ input axi_arready ,
599
+ output axi_araddr ,
600
+ input axi_rvalid ,
601
+ output axi_rready ,
602
+ input axi_rdata ,
603
+ // input axi_rresp ,
604
+ input timeout
605
+ );
606
+
607
+ modport lite_slaver(
608
+ input axi_aclk ,
609
+ input axi_aresetn ,
610
+ input axi_awvalid ,
611
+ output axi_awready ,
612
+ input axi_awaddr ,
613
+ input axi_wvalid ,
614
+ output axi_wready ,
615
+ input axi_wdata ,
616
+ output axi_bresp ,
617
+ output axi_bvalid ,
618
+ input axi_bready ,
619
+ input axi_arvalid ,
620
+ output axi_arready ,
621
+ input axi_araddr ,
622
+ output axi_rvalid ,
623
+ input axi_rready ,
624
+ output axi_rdata ,
625
+ // output axi_rresp
626
+ input timeout
627
+ );
628
+
629
+ endinterface:axi_inf
630
+
631
+ interface axi_inf2 #(
632
+ parameter IDSIZE = 1,
633
+ parameter ASIZE = 32,
634
+ parameter LSIZE = 1,
635
+ parameter DSIZE = 32,
636
+ `parameter_string MODE = "BOTH", //BOTH:0,ONLY_WRITE:1,ONLY_READ:2
637
+ parameter ADDR_STEP = 32'hFFFF_FFFF // 1024 : 0
638
+ )(
639
+ input bit axi_aclk ,
640
+ input bit axi_aresetn
641
+ );
642
+
643
+ initial begin
644
+ if(MODE == "BOTH" || MODE == "ONLY_READ" || MODE == "ONLY_WRITE")
645
+ #(1ps);
646
+ else begin
647
+ $error("$t,AXI INFTERFACE MODE PARAMETER ERROR >>%s<<",MODE);
648
+ $finish;
649
+ end
650
+ end
651
+
652
+ logic timeout;
653
+
654
+ localparam STSIZE = DSIZE/8+(DSIZE%8 != 0);
655
+ //--->> addr write <<-------
656
+ wire[IDSIZE-1:0] axi_awid ;
657
+ wire[ASIZE-1:0] axi_awaddr ;
658
+ wire[LSIZE-1:0] axi_awlen ;
659
+ wire[2:0] axi_awsize ;
660
+ wire[1:0] axi_awburst ;
661
+ wire[0:0] axi_awlock ;
662
+ wire[3:0] axi_awcache ;
663
+ wire[2:0] axi_awprot ;
664
+ wire[3:0] axi_awqos ;
665
+ wire axi_awvalid ;
666
+ wire axi_awready ;
667
+ //---<< addr write >>-------
668
+ //--->> addr read <<--------
669
+ wire[IDSIZE-1:0] axi_arid ;
670
+ wire[ASIZE-1:0] axi_araddr ;
671
+ wire[LSIZE-1:0] axi_arlen ;
672
+ wire[2:0] axi_arsize ;
673
+ wire[1:0] axi_arburst ;
674
+ wire[0:0] axi_arlock ;
675
+ wire[3:0] axi_arcache ;
676
+ wire[2:0] axi_arprot ;
677
+ wire[3:0] axi_arqos ;
678
+ wire axi_arvalid ;
679
+ wire axi_arready ;
680
+ //---<< addr read >>--------
681
+ //--->> Response <<---------
682
+ wire axi_bready ;
683
+ wire[IDSIZE-1:0] axi_bid ;
684
+ wire[1:0] axi_bresp ;
685
+ wire axi_bvalid ;
686
+ //---<< Response >>---------
687
+ //--->> data write <<-------
688
+ wire[DSIZE-1:0] axi_wdata ;
689
+ wire[STSIZE-1:0] axi_wstrb ;
690
+ wire axi_wlast ;
691
+ wire axi_wvalid ;
692
+ wire axi_wready ;
693
+ //---<< data write >>-------
694
+ //--->> data read >>--------
695
+ wire axi_rready ;
696
+ wire[IDSIZE-1:0] axi_rid ;
697
+ wire[DSIZE-1:0] axi_rdata ;
698
+ wire[1:0] axi_rresp ;
699
+ wire axi_rlast ;
700
+ wire axi_rvalid ;
701
+ //---<< data read >>--------
702
+ //--->> error flag <<-------
703
+ // logic axi_wevld ;
704
+ // logic[3:0] axi_weresp ;
705
+ // logic axi_revld ;
706
+ // logic[3:0] axi_reresp ;
707
+ //---<< error flag >>-------
708
+
709
+ //--->> TIME CTRL <<---------------
710
+ always@(posedge axi_aclk,negedge axi_aresetn)begin:TIME_BLOCK
711
+ logic cen;
712
+ logic crst;
713
+ logic [23:0] tcnt;
714
+ if(~axi_aresetn)begin
715
+ tcnt <= 24'd0;
716
+ cen <= 1'b0;
717
+ crst <= 1'b0;
718
+ end else begin
719
+ //-->> COUNT ENABLE
720
+ if(axi_awready && axi_awvalid)
721
+ cen <= 1'b1;
722
+ else if(axi_arready && axi_arvalid)
723
+ cen <= 1'b1;
724
+ else if(axi_bready && axi_bvalid)
725
+ cen <= 1'b0;
726
+ else if(axi_rvalid && axi_rready)
727
+ cen <= 1'b0;
728
+ else cen <= cen;
729
+ //-->> COUNT RST
730
+ if(axi_awready && axi_awvalid)
731
+ crst <= 1'b1;
732
+ else if(axi_arready && axi_arvalid)
733
+ crst <= 1'b1;
734
+ else if(axi_wready && axi_wvalid)
735
+ crst <= 1'b1;
736
+ else if(axi_rready && axi_rvalid)
737
+ crst <= 1'b1;
738
+ else crst <= 1'b0;
739
+ //-->> COUNT
740
+ if(crst)
741
+ tcnt <= 24'd0;
742
+ else if(cen)
743
+ tcnt <= tcnt + 1'b1;
744
+ else tcnt <= tcnt;
745
+ //-->> RESULT
746
+ timeout <= &tcnt;
747
+ end
748
+ end
749
+ //---<< TIME CTRL >>---------------
750
+ //--->> AW_CNT <<-----------------
751
+ logic [LSIZE-1:0] axi_wcnt;
752
+
753
+ always@(posedge axi_aclk,negedge axi_aresetn)begin:WRITE_CNT
754
+ if(~axi_aresetn) axi_wcnt <= '0;
755
+ else begin
756
+ if(axi_wvalid && axi_wready && axi_wlast)
757
+ axi_wcnt <= '0;
758
+ else if(axi_wvalid && axi_wready)
759
+ axi_wcnt <= axi_wcnt + 1'b1;
760
+ else axi_wcnt <= axi_wcnt;
761
+ end
762
+ end
763
+ //---<< AW_CNT >>-----------------
764
+ //--->> AR_CNT <<-----------------
765
+ logic [LSIZE-1:0] axi_rcnt;
766
+
767
+ always@(posedge axi_aclk,negedge axi_aresetn)begin:READ_CNT
768
+ if(~axi_aresetn) axi_rcnt <= '0;
769
+ else begin
770
+ if(axi_rvalid && axi_rready && axi_rlast)
771
+ axi_rcnt <= '0;
772
+ else if(axi_rvalid && axi_rready)
773
+ axi_rcnt <= axi_rcnt + 1'b1;
774
+ else axi_rcnt <= axi_rcnt;
775
+ end
776
+ end
777
+ //---<< AR_CNT >>-----------------
778
+ //--->> MODE CTRL <<---------------
779
+ `ifdef VIVADO_ENV
780
+ generate
781
+ if(MODE=="ONLY_READ")begin
782
+ assign axi_awid = '0;
783
+ assign axi_awaddr = '0;
784
+ assign axi_awlen = '0;
785
+ assign axi_awsize = '0;
786
+ assign axi_awburst = '0;
787
+ assign axi_awlock = '0;
788
+ assign axi_awcache = '0;
789
+ assign axi_awprot = '0;
790
+ assign axi_awqos = '0;
791
+ assign axi_awvalid = '0;
792
+ assign axi_wdata = '0;
793
+ assign axi_wstrb = '0;
794
+ assign axi_wlast = '0;
795
+ assign axi_wvalid = '0;
796
+ assign axi_bready = '0;
797
+ end
798
+ endgenerate
799
+
800
+ generate
801
+ if(MODE=="ONLY_WRITE")begin
802
+ assign axi_arid = '0;
803
+ assign axi_araddr = '0;
804
+ assign axi_arlen = '0;
805
+ assign axi_arsize = '0;
806
+ assign axi_arburst = '0;
807
+ assign axi_arlock = '0;
808
+ assign axi_arcache = '0;
809
+ assign axi_arprot = '0;
810
+ assign axi_arqos = '0;
811
+ assign axi_arvalid = '0;
812
+ assign axi_rready = '0;
813
+ end
814
+ endgenerate
815
+ `endif
816
+
817
+ //---<< MODE CTRL >>---------------
818
+ modport slaver (
819
+ input axi_aclk ,
820
+ input axi_aresetn ,
821
+ input axi_awid ,
822
+ input axi_awaddr ,
823
+ input axi_awlen ,
824
+ input axi_awsize ,
825
+ input axi_awburst ,
826
+ input axi_awlock ,
827
+ input axi_awcache ,
828
+ input axi_awprot ,
829
+ input axi_awqos ,
830
+ input axi_awvalid ,
831
+ output axi_awready ,
832
+ input axi_wdata ,
833
+ input axi_wstrb ,
834
+ input axi_wlast ,
835
+ input axi_wvalid ,
836
+ output axi_wready ,
837
+ input axi_bready ,
838
+ output axi_bid ,
839
+ output axi_bresp ,
840
+ output axi_bvalid ,
841
+ input axi_arid ,
842
+ input axi_araddr ,
843
+ input axi_arlen ,
844
+ input axi_arsize ,
845
+ input axi_arburst ,
846
+ input axi_arlock ,
847
+ input axi_arcache ,
848
+ input axi_arprot ,
849
+ input axi_arqos ,
850
+ input axi_arvalid ,
851
+ output axi_arready ,
852
+ input axi_rready ,
853
+ output axi_rid ,
854
+ output axi_rdata ,
855
+ output axi_rresp ,
856
+ output axi_rlast ,
857
+ output axi_rvalid ,
858
+
859
+ input axi_wcnt,
860
+ input axi_rcnt,
861
+ // input axi_wevld ,
862
+ // input axi_weresp ,
863
+ // input axi_revld ,
864
+ // input axi_reresp ,
865
+ input timeout
866
+ );
867
+
868
+ modport master (
869
+ input axi_aclk ,
870
+ input axi_aresetn ,
871
+ output axi_awid ,
872
+ output axi_awaddr ,
873
+ output axi_awlen ,
874
+ output axi_awsize ,
875
+ output axi_awburst ,
876
+ output axi_awlock ,
877
+ output axi_awcache ,
878
+ output axi_awprot ,
879
+ output axi_awqos ,
880
+ output axi_awvalid ,
881
+ input axi_awready ,
882
+ output axi_wdata ,
883
+ output axi_wstrb ,
884
+ output axi_wlast ,
885
+ output axi_wvalid ,
886
+ input axi_wready ,
887
+ output axi_bready ,
888
+ input axi_bid ,
889
+ input axi_bresp ,
890
+ input axi_bvalid ,
891
+ output axi_arid ,
892
+ output axi_araddr ,
893
+ output axi_arlen ,
894
+ output axi_arsize ,
895
+ output axi_arburst ,
896
+ output axi_arlock ,
897
+ output axi_arcache ,
898
+ output axi_arprot ,
899
+ output axi_arqos ,
900
+ output axi_arvalid ,
901
+ input axi_arready ,
902
+ output axi_rready ,
903
+ input axi_rid ,
904
+ input axi_rdata ,
905
+ input axi_rresp ,
906
+ input axi_rlast ,
907
+ input axi_rvalid ,
908
+ input axi_wcnt,
909
+ input axi_rcnt,
910
+ // input axi_wevld ,
911
+ // input axi_weresp ,
912
+ // input axi_revld ,
913
+ // input axi_reresp ,
914
+ input timeout
915
+ );
916
+
917
+ modport master_wr (
918
+ input axi_aclk ,
919
+ input axi_aresetn ,
920
+ output axi_awid ,
921
+ output axi_awaddr ,
922
+ output axi_awlen ,
923
+ output axi_awsize ,
924
+ output axi_awburst ,
925
+ output axi_awlock ,
926
+ output axi_awcache ,
927
+ output axi_awprot ,
928
+ output axi_awqos ,
929
+ output axi_awvalid ,
930
+ input axi_awready ,
931
+ output axi_wdata ,
932
+ output axi_wstrb ,
933
+ output axi_wlast ,
934
+ output axi_wvalid ,
935
+ input axi_wready ,
936
+ output axi_bready ,
937
+ input axi_bid ,
938
+ input axi_bresp ,
939
+ input axi_bvalid ,
940
+ input axi_wcnt,
941
+ // input axi_rcnt,
942
+ input timeout
943
+ );
944
+
945
+ modport master_rd (
946
+ input axi_aclk ,
947
+ input axi_aresetn ,
948
+ output axi_arid ,
949
+ output axi_araddr ,
950
+ output axi_arlen ,
951
+ output axi_arsize ,
952
+ output axi_arburst ,
953
+ output axi_arlock ,
954
+ output axi_arcache ,
955
+ output axi_arprot ,
956
+ output axi_arqos ,
957
+ output axi_arvalid ,
958
+ input axi_arready ,
959
+ output axi_rready ,
960
+ input axi_rid ,
961
+ input axi_rdata ,
962
+ input axi_rresp ,
963
+ input axi_rlast ,
964
+ input axi_rvalid ,
965
+ // input axi_wcnt,
966
+ input axi_rcnt,
967
+ input timeout
968
+ );
969
+
970
+ modport slaver_wr (
971
+ input axi_aclk ,
972
+ input axi_aresetn ,
973
+ input axi_awid ,
974
+ input axi_awaddr ,
975
+ input axi_awlen ,
976
+ input axi_awsize ,
977
+ input axi_awburst ,
978
+ input axi_awlock ,
979
+ input axi_awcache ,
980
+ input axi_awprot ,
981
+ input axi_awqos ,
982
+ input axi_awvalid ,
983
+ output axi_awready ,
984
+ input axi_wdata ,
985
+ input axi_wstrb ,
986
+ input axi_wlast ,
987
+ input axi_wvalid ,
988
+ output axi_wready ,
989
+ input axi_bready ,
990
+ output axi_bid ,
991
+ output axi_bresp ,
992
+ output axi_bvalid ,
993
+ input axi_wcnt,
994
+ // input axi_rcnt,
995
+ input timeout
996
+ );
997
+
998
+ modport slaver_rd (
999
+ input axi_aclk ,
1000
+ input axi_aresetn ,
1001
+ input axi_arid ,
1002
+ input axi_araddr ,
1003
+ input axi_arlen ,
1004
+ input axi_arsize ,
1005
+ input axi_arburst ,
1006
+ input axi_arlock ,
1007
+ input axi_arcache ,
1008
+ input axi_arprot ,
1009
+ input axi_arqos ,
1010
+ input axi_arvalid ,
1011
+ output axi_arready ,
1012
+ input axi_rready ,
1013
+ output axi_rid ,
1014
+ output axi_rdata ,
1015
+ output axi_rresp ,
1016
+ output axi_rlast ,
1017
+ output axi_rvalid ,
1018
+ // input axi_wcnt,
1019
+ input axi_rcnt,
1020
+ input timeout
1021
+ );
1022
+
1023
+ modport master_wr_aux (
1024
+ input axi_aclk ,
1025
+ input axi_aresetn ,
1026
+ output axi_awid ,
1027
+ output axi_awaddr ,
1028
+ output axi_awlen ,
1029
+ output axi_awsize ,
1030
+ output axi_awburst ,
1031
+ output axi_awlock ,
1032
+ output axi_awcache ,
1033
+ output axi_awprot ,
1034
+ output axi_awqos ,
1035
+ output axi_awvalid ,
1036
+ input axi_awready ,
1037
+ // output axi_wdata ,
1038
+ // output axi_wstrb ,
1039
+ input axi_wlast ,
1040
+ input axi_wvalid ,
1041
+ input axi_wready ,
1042
+ output axi_bready ,
1043
+ input axi_bid ,
1044
+ input axi_bresp ,
1045
+ input axi_bvalid ,
1046
+ input axi_wcnt,
1047
+ input axi_rcnt,
1048
+ input timeout
1049
+ );
1050
+
1051
+ modport master_wr_aux_no_resp (
1052
+ input axi_aclk ,
1053
+ input axi_aresetn ,
1054
+ output axi_awid ,
1055
+ output axi_awaddr ,
1056
+ output axi_awlen ,
1057
+ output axi_awsize ,
1058
+ output axi_awburst ,
1059
+ output axi_awlock ,
1060
+ output axi_awcache ,
1061
+ output axi_awprot ,
1062
+ output axi_awqos ,
1063
+ output axi_awvalid ,
1064
+ input axi_awready ,
1065
+ // output axi_wdata ,
1066
+ // output axi_wstrb ,
1067
+ input axi_wlast ,
1068
+ input axi_wvalid ,
1069
+ input axi_wready ,
1070
+ // input axi_bready ,
1071
+ // input axi_bid ,
1072
+ // input axi_bresp ,
1073
+ // input axi_bvalid ,
1074
+ input axi_wcnt,
1075
+ // input axi_rcnt,
1076
+ input timeout
1077
+ );
1078
+
1079
+ modport master_rd_aux (
1080
+ input axi_aclk ,
1081
+ input axi_aresetn ,
1082
+ output axi_arid ,
1083
+ output axi_araddr ,
1084
+ output axi_arlen ,
1085
+ output axi_arsize ,
1086
+ output axi_arburst ,
1087
+ output axi_arlock ,
1088
+ output axi_arcache ,
1089
+ output axi_arprot ,
1090
+ output axi_arqos ,
1091
+ output axi_arvalid ,
1092
+ input axi_arready ,
1093
+ input axi_rready ,
1094
+ input axi_rid ,
1095
+ // input axi_rdata ,
1096
+ input axi_rresp ,
1097
+ input axi_rlast ,
1098
+ input axi_rvalid ,
1099
+ // input axi_wcnt,
1100
+ input axi_rcnt,
1101
+ input timeout
1102
+ );
1103
+
1104
+ modport mirror (
1105
+ input axi_aclk ,
1106
+ input axi_aresetn ,
1107
+ input axi_awid ,
1108
+ input axi_awaddr ,
1109
+ input axi_awlen ,
1110
+ input axi_awsize ,
1111
+ input axi_awburst ,
1112
+ input axi_awlock ,
1113
+ input axi_awcache ,
1114
+ input axi_awprot ,
1115
+ input axi_awqos ,
1116
+ input axi_awvalid ,
1117
+ input axi_awready ,
1118
+ input axi_wdata ,
1119
+ input axi_wstrb ,
1120
+ input axi_wlast ,
1121
+ input axi_wvalid ,
1122
+ input axi_wready ,
1123
+ input axi_bready ,
1124
+ input axi_bid ,
1125
+ input axi_bresp ,
1126
+ input axi_bvalid ,
1127
+ input axi_arid ,
1128
+ input axi_araddr ,
1129
+ input axi_arlen ,
1130
+ input axi_arsize ,
1131
+ input axi_arburst ,
1132
+ input axi_arlock ,
1133
+ input axi_arcache ,
1134
+ input axi_arprot ,
1135
+ input axi_arqos ,
1136
+ input axi_arvalid ,
1137
+ input axi_arready ,
1138
+ input axi_rready ,
1139
+ input axi_rid ,
1140
+ input axi_rdata ,
1141
+ input axi_rresp ,
1142
+ input axi_rlast ,
1143
+ input axi_rvalid ,
1144
+ input axi_wcnt,
1145
+ input axi_rcnt,
1146
+ // output axi_wevld ,
1147
+ // output axi_weresp ,
1148
+ // output axi_revld ,
1149
+ // output axi_reresp ,
1150
+ input timeout
1151
+ );
1152
+
1153
+ modport mirror_wr (
1154
+ input axi_aclk ,
1155
+ input axi_aresetn ,
1156
+ input axi_awid ,
1157
+ input axi_awaddr ,
1158
+ input axi_awlen ,
1159
+ input axi_awsize ,
1160
+ input axi_awburst ,
1161
+ input axi_awlock ,
1162
+ input axi_awcache ,
1163
+ input axi_awprot ,
1164
+ input axi_awqos ,
1165
+ input axi_awvalid ,
1166
+ input axi_awready ,
1167
+ input axi_wdata ,
1168
+ input axi_wstrb ,
1169
+ input axi_wlast ,
1170
+ input axi_wvalid ,
1171
+ input axi_wready ,
1172
+ input axi_bready ,
1173
+ input axi_bid ,
1174
+ input axi_bresp ,
1175
+ input axi_bvalid ,
1176
+ input axi_wcnt,
1177
+ // output axi_wevld ,
1178
+ // output axi_weresp ,
1179
+ // output axi_revld ,
1180
+ // output axi_reresp ,
1181
+ input timeout
1182
+ );
1183
+
1184
+ modport mirror_rd (
1185
+ input axi_aclk ,
1186
+ input axi_aresetn ,
1187
+ input axi_arid ,
1188
+ input axi_araddr ,
1189
+ input axi_arlen ,
1190
+ input axi_arsize ,
1191
+ input axi_arburst ,
1192
+ input axi_arlock ,
1193
+ input axi_arcache ,
1194
+ input axi_arprot ,
1195
+ input axi_arqos ,
1196
+ input axi_arvalid ,
1197
+ input axi_arready ,
1198
+ input axi_rready ,
1199
+ input axi_rid ,
1200
+ input axi_rdata ,
1201
+ input axi_rresp ,
1202
+ input axi_rlast ,
1203
+ input axi_rvalid ,
1204
+ input axi_rcnt,
1205
+ // output axi_wevld ,
1206
+ // output axi_weresp ,
1207
+ // output axi_revld ,
1208
+ // output axi_reresp ,
1209
+ input timeout
1210
+ );
1211
+
1212
+ modport lite_master(
1213
+ input axi_aclk ,
1214
+ input axi_aresetn ,
1215
+ output axi_awvalid ,
1216
+ input axi_awready ,
1217
+ output axi_awaddr ,
1218
+ output axi_wvalid ,
1219
+ input axi_wready ,
1220
+ output axi_wdata ,
1221
+ input axi_bresp ,
1222
+ input axi_bvalid ,
1223
+ output axi_bready ,
1224
+ output axi_arvalid ,
1225
+ input axi_arready ,
1226
+ output axi_araddr ,
1227
+ input axi_rvalid ,
1228
+ output axi_rready ,
1229
+ input axi_rdata ,
1230
+ // input axi_rresp ,
1231
+ input timeout
1232
+ );
1233
+
1234
+ modport lite_slaver(
1235
+ input axi_aclk ,
1236
+ input axi_aresetn ,
1237
+ input axi_awvalid ,
1238
+ output axi_awready ,
1239
+ input axi_awaddr ,
1240
+ input axi_wvalid ,
1241
+ output axi_wready ,
1242
+ input axi_wdata ,
1243
+ output axi_bresp ,
1244
+ output axi_bvalid ,
1245
+ input axi_bready ,
1246
+ input axi_arvalid ,
1247
+ output axi_arready ,
1248
+ input axi_araddr ,
1249
+ output axi_rvalid ,
1250
+ input axi_rready ,
1251
+ output axi_rdata ,
1252
+ // output axi_rresp
1253
+ input timeout
1254
+ );
1255
+
1256
+ endinterface:axi_inf2