axi_tdl 0.0.2

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Files changed (1189) hide show
  1. checksums.yaml +7 -0
  2. data/.gitignore +8 -0
  3. data/CODE_OF_CONDUCT.md +74 -0
  4. data/Gemfile +6 -0
  5. data/Gemfile.lock +43 -0
  6. data/LICENSE +504 -0
  7. data/README.md +311 -0
  8. data/Rakefile +18 -0
  9. data/axi_tdl.gemspec +43 -0
  10. data/bin/console +14 -0
  11. data/bin/setup +8 -0
  12. data/lib/.rspec +1 -0
  13. data/lib/axi/AXI4/axi4_combin_wr_rd_batch.sv +59 -0
  14. data/lib/axi/AXI4/axi4_direct.sv +137 -0
  15. data/lib/axi/AXI4/axi4_direct_A1.sv +229 -0
  16. data/lib/axi/AXI4/axi4_direct_B1.sv +74 -0
  17. data/lib/axi/AXI4/axi4_direct_verb.sv +79 -0
  18. data/lib/axi/AXI4/axi4_direct_verc.sv +146 -0
  19. data/lib/axi/AXI4/axi4_dpram_cache.rb +106 -0
  20. data/lib/axi/AXI4/axi4_dpram_cache.sv +112 -0
  21. data/lib/axi/AXI4/axi4_long_to_axi4_wide.sv +85 -0
  22. data/lib/axi/AXI4/axi4_long_to_axi4_wide_A1.sv +96 -0
  23. data/lib/axi/AXI4/axi4_long_to_axi4_wide_track.sv +118 -0
  24. data/lib/axi/AXI4/axi4_long_to_axi4_wide_verb.sv +131 -0
  25. data/lib/axi/AXI4/axi4_pipe/axi4_pipe.sv +44 -0
  26. data/lib/axi/AXI4/axi4_pipe/axi4_pipe_verb.sv +45 -0
  27. data/lib/axi/AXI4/axi4_pipe/axi4_rd_pipe.sv +111 -0
  28. data/lib/axi/AXI4/axi4_pipe/axi4_rd_pipe_verb.sv +113 -0
  29. data/lib/axi/AXI4/axi4_pipe/axi4_wr_pipe.sv +142 -0
  30. data/lib/axi/AXI4/axi4_pipe/axi4_wr_pipe_verb.sv +146 -0
  31. data/lib/axi/AXI4/axi4_rd_auxiliary_batch_gen.sv +134 -0
  32. data/lib/axi/AXI4/axi4_rd_auxiliary_gen.sv +89 -0
  33. data/lib/axi/AXI4/axi4_rd_auxiliary_gen_A1.sv +109 -0
  34. data/lib/axi/AXI4/axi4_rd_burst_track.sv +164 -0
  35. data/lib/axi/AXI4/axi4_wr_aux_bind_data.sv +121 -0
  36. data/lib/axi/AXI4/axi4_wr_auxiliary_batch_gen.sv +140 -0
  37. data/lib/axi/AXI4/axi4_wr_auxiliary_gen.sv +102 -0
  38. data/lib/axi/AXI4/axi4_wr_auxiliary_gen_without_resp.sv +91 -0
  39. data/lib/axi/AXI4/axi4_wr_burst_track.sv +146 -0
  40. data/lib/axi/AXI4/axi_stream_add_addr_len.sv +50 -0
  41. data/lib/axi/AXI4/axi_stream_to_axi4_wr.sv +61 -0
  42. data/lib/axi/AXI4/axi_stream_to_axi4_wr_verb.sv.bak +123 -0
  43. data/lib/axi/AXI4/axis_to_axi4_wr.rb +149 -0
  44. data/lib/axi/AXI4/axis_to_axi4_wr.sv +141 -0
  45. data/lib/axi/AXI4/full_axi4_to_axis.sv +188 -0
  46. data/lib/axi/AXI4/full_axi4_to_axis_partition_wr_rd.sv +208 -0
  47. data/lib/axi/AXI4/id_record.sv +55 -0
  48. data/lib/axi/AXI4/idata_pool_axi4.sv +110 -0
  49. data/lib/axi/AXI4/interconnect/AXI4_interconnect_M2S.sv +291 -0
  50. data/lib/axi/AXI4/interconnect/axi4_mix_interconnect_M2S.sv +72 -0
  51. data/lib/axi/AXI4/interconnect/axi4_rd_interconnect_M2S.sv +148 -0
  52. data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S.sv +255 -0
  53. data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S.sv.bak +255 -0
  54. data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S_A1.sv +286 -0
  55. data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S_A2.sv +281 -0
  56. data/lib/axi/AXI4/interconnect/axi4_wr_interconnect_M2S.sv +235 -0
  57. data/lib/axi/AXI4/interconnect/axi4_wr_interconnect_M2S_A1.sv +283 -0
  58. data/lib/axi/AXI4/interconnect/axi4_wr_mix_interconnect_M2S.sv +32 -0
  59. data/lib/axi/AXI4/long_axi4_to_wide_axi4.sv.bak +251 -0
  60. data/lib/axi/AXI4/odata_pool_axi4.sv +134 -0
  61. data/lib/axi/AXI4/odata_pool_axi4_A1.sv +165 -0
  62. data/lib/axi/AXI4/odata_pool_axi4_A2.sv +159 -0
  63. data/lib/axi/AXI4/odata_pool_axi4_A3.sv +183 -0
  64. data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo.sv +61 -0
  65. data/lib/axi/AXI4/packet_fifo/axi4_rd_packet_fifo.sv +282 -0
  66. data/lib/axi/AXI4/packet_fifo/axi4_wr_packet_fifo.sv +181 -0
  67. data/lib/axi/AXI4/packet_merge/axi4_merge.sv +60 -0
  68. data/lib/axi/AXI4/packet_merge/axi4_merge_rd.sv +279 -0
  69. data/lib/axi/AXI4/packet_merge/axi4_merge_wr.sv +267 -0
  70. data/lib/axi/AXI4/packet_partition/axi4_partition.sv +36 -0
  71. data/lib/axi/AXI4/packet_partition/axi4_partition_OD.sv +66 -0
  72. data/lib/axi/AXI4/packet_partition/axi4_partition_rd.sv +211 -0
  73. data/lib/axi/AXI4/packet_partition/axi4_partition_rd_OD.sv +322 -0
  74. data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.rb +80 -0
  75. data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +93 -0
  76. data/lib/axi/AXI4/packet_partition/axi4_partition_wr.sv +239 -0
  77. data/lib/axi/AXI4/packet_partition/axi4_partition_wr_OD.sv +302 -0
  78. data/lib/axi/AXI4/packet_partition/data_inf_partition.rb +293 -0
  79. data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +307 -0
  80. data/lib/axi/AXI4/vcs_axi4_array_comptable.sv +35 -0
  81. data/lib/axi/AXI4/vcs_axi4_comptable.sv +330 -0
  82. data/lib/axi/AXI4/wide_axis_to_axi4_wr.rb +149 -0
  83. data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +140 -0
  84. data/lib/axi/AXI4/width_convert/axi4_data_combin_aflag_pipe.sv +239 -0
  85. data/lib/axi/AXI4/width_convert/axi4_data_combin_aflag_pipe_A1.sv +204 -0
  86. data/lib/axi/AXI4/width_convert/axi4_data_convert.sv +312 -0
  87. data/lib/axi/AXI4/width_convert/axi4_data_convert_A1.sv +217 -0
  88. data/lib/axi/AXI4/width_convert/data_combin.sv +366 -0
  89. data/lib/axi/AXI4/width_convert/data_combin.sv.bak +290 -0
  90. data/lib/axi/AXI4/width_convert/data_destruct.sv +304 -0
  91. data/lib/axi/AXI4/width_convert/feed_check.sv +94 -0
  92. data/lib/axi/AXI4/width_convert/len_convert.sv.bak +61 -0
  93. data/lib/axi/AXI4/width_convert/odd_width_convert.sv +229 -0
  94. data/lib/axi/AXI4/width_convert/odd_width_convert_verb.sv +105 -0
  95. data/lib/axi/AXI4/width_convert/simple_data_pipe.sv +40 -0
  96. data/lib/axi/AXI4/width_convert/simple_data_pipe_slaver.sv +33 -0
  97. data/lib/axi/AXI4/width_convert/width_combin.sv +113 -0
  98. data/lib/axi/AXI4/width_convert/width_convert.sv +87 -0
  99. data/lib/axi/AXI4/width_convert/width_convert_verb.sv +249 -0
  100. data/lib/axi/AXI4/width_convert/width_destruct.sv +206 -0
  101. data/lib/axi/AXI4/width_convert/width_destruct_A1.sv +251 -0
  102. data/lib/axi/AXI_BFM/AXI_BFM_PKG.sv +1039 -0
  103. data/lib/axi/AXI_BFM/Data_C_BFM_PKG.sv +97 -0
  104. data/lib/axi/AXI_BFM/axi4_error_chk.sv +298 -0
  105. data/lib/axi/AXI_BFM/axi4_illegal_bfm_pkg.sv +607 -0
  106. data/lib/axi/AXI_BFM/axi_lite_master.sv +102 -0
  107. data/lib/axi/AXI_BFM/axi_lite_tb.sv +23 -0
  108. data/lib/axi/AXI_BFM/axi_master.sv +185 -0
  109. data/lib/axi/AXI_BFM/axi_mirror.sv +266 -0
  110. data/lib/axi/AXI_BFM/axi_mm_tb.sv +134 -0
  111. data/lib/axi/AXI_BFM/axi_slaver.sv.bak +340 -0
  112. data/lib/axi/AXI_BFM/axistreambfm.sv +117 -0
  113. data/lib/axi/AXI_Lite/axi4_to_lite.sv +36 -0
  114. data/lib/axi/AXI_Lite/axi_lite_configure.sv +356 -0
  115. data/lib/axi/AXI_Lite/axi_lite_configure_inf2.sv +365 -0
  116. data/lib/axi/AXI_Lite/axi_lite_configure_verb.sv.bck +370 -0
  117. data/lib/axi/AXI_Lite/axi_lite_interconnect_M2S.sv +437 -0
  118. data/lib/axi/AXI_Lite/axi_lite_interconnect_S2M.sv +359 -0
  119. data/lib/axi/AXI_Lite/axi_lite_interconnect_S2M.sv.bak +359 -0
  120. data/lib/axi/AXI_Lite/axi_lite_master_empty.sv +30 -0
  121. data/lib/axi/AXI_Lite/axi_lite_slaver_empty.sv +27 -0
  122. data/lib/axi/AXI_Lite/axil_direct.sv +52 -0
  123. data/lib/axi/AXI_Lite/common_configure_reg_interface/common_configure_reg_interface.sv +230 -0
  124. data/lib/axi/AXI_Lite/common_configure_reg_interface/common_configure_reg_interface.sv.bak +109 -0
  125. data/lib/axi/AXI_Lite/common_configure_reg_interface/jtag_to_axilite_wrapper.sv +56 -0
  126. data/lib/axi/AXI_Lite/gen_axi_lite_ctrl.sv +515 -0
  127. data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_C1.sv +369 -0
  128. data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_verb.sv +365 -0
  129. data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_verc.sv +401 -0
  130. data/lib/axi/AXI_Lite/wr_lite_to_axis.sv +141 -0
  131. data/lib/axi/AXI_Lite/wr_lite_to_axis.sv.bak +141 -0
  132. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S.sv +76 -0
  133. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_A1.sv +77 -0
  134. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_A2.sv +71 -0
  135. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_bind_tuser.sv +72 -0
  136. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_noaddr.sv +151 -0
  137. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_with_addr.sv +87 -0
  138. data/lib/axi/AXI_stream/axi_stream_interconnect_S2M.sv +65 -0
  139. data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_auto.sv +50 -0
  140. data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_with_info.sv +64 -0
  141. data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_with_keep.sv.bak +64 -0
  142. data/lib/axi/AXI_stream/axi_stream_packet_fifo_with_info.sv.bak +49 -0
  143. data/lib/axi/AXI_stream/axi_stream_partition.sv +147 -0
  144. data/lib/axi/AXI_stream/axi_stream_partition_A1.sv +63 -0
  145. data/lib/axi/AXI_stream/axi_stream_planer.sv +51 -0
  146. data/lib/axi/AXI_stream/axi_stream_split_channel.rb +56 -0
  147. data/lib/axi/AXI_stream/axi_stream_split_channel.sv +149 -0
  148. data/lib/axi/AXI_stream/axi_streams_combin.sv +151 -0
  149. data/lib/axi/AXI_stream/axi_streams_combin_A1.sv +179 -0
  150. data/lib/axi/AXI_stream/axi_streams_scaler.sv +171 -0
  151. data/lib/axi/AXI_stream/axi_streams_scaler_A1.sv +179 -0
  152. data/lib/axi/AXI_stream/axis_append.sv +79 -0
  153. data/lib/axi/AXI_stream/axis_append_A1.sv +82 -0
  154. data/lib/axi/AXI_stream/axis_base_pipe.sv +184 -0
  155. data/lib/axi/AXI_stream/axis_combin_with_fifo.sv +69 -0
  156. data/lib/axi/AXI_stream/axis_connect_pipe.sv +86 -0
  157. data/lib/axi/AXI_stream/axis_connect_pipe_A1.sv.bak +170 -0
  158. data/lib/axi/AXI_stream/axis_connect_pipe_left_shift.sv +64 -0
  159. data/lib/axi/AXI_stream/axis_connect_pipe_right_shift.sv +64 -0
  160. data/lib/axi/AXI_stream/axis_connect_pipe_right_shift_verb.sv +70 -0
  161. data/lib/axi/AXI_stream/axis_connect_pipe_with_info.sv +93 -0
  162. data/lib/axi/AXI_stream/axis_direct.sv +55 -0
  163. data/lib/axi/AXI_stream/axis_direct_A1.sv +81 -0
  164. data/lib/axi/AXI_stream/axis_filter.sv +38 -0
  165. data/lib/axi/AXI_stream/axis_full_to_data_c.sv +26 -0
  166. data/lib/axi/AXI_stream/axis_head_cut.sv +67 -0
  167. data/lib/axi/AXI_stream/axis_head_cut_verb.sv +60 -0
  168. data/lib/axi/AXI_stream/axis_head_cut_verc.rb +175 -0
  169. data/lib/axi/AXI_stream/axis_head_cut_verc.sv +245 -0
  170. data/lib/axi/AXI_stream/axis_inct_s2m_with_flag.sv +84 -0
  171. data/lib/axi/AXI_stream/axis_insert_copy.rb +59 -0
  172. data/lib/axi/AXI_stream/axis_insert_copy.sv +66 -0
  173. data/lib/axi/AXI_stream/axis_intc_M2S_with_addr_inf.sv +114 -0
  174. data/lib/axi/AXI_stream/axis_intc_S2M_with_addr_inf.sv +85 -0
  175. data/lib/axi/AXI_stream/axis_interconnect_S2M_pipe.sv +75 -0
  176. data/lib/axi/AXI_stream/axis_length_cut.sv +64 -0
  177. data/lib/axi/AXI_stream/axis_length_fill.sv +194 -0
  178. data/lib/axi/AXI_stream/axis_length_split.sv +86 -0
  179. data/lib/axi/AXI_stream/axis_length_split_with_addr.sv +127 -0
  180. data/lib/axi/AXI_stream/axis_length_split_writh_user.sv +87 -0
  181. data/lib/axi/AXI_stream/axis_link_trigger.sv +81 -0
  182. data/lib/axi/AXI_stream/axis_master_empty.sv +26 -0
  183. data/lib/axi/AXI_stream/axis_mirror_to_master.sv +126 -0
  184. data/lib/axi/AXI_stream/axis_mirrors.sv +60 -0
  185. data/lib/axi/AXI_stream/axis_orthogonal.sv +66 -0
  186. data/lib/axi/AXI_stream/axis_ram_buffer.sv +118 -0
  187. data/lib/axi/AXI_stream/axis_rom_contect.rb +97 -0
  188. data/lib/axi/AXI_stream/axis_rom_contect.sv +110 -0
  189. data/lib/axi/AXI_stream/axis_rom_contect_sim.rb +102 -0
  190. data/lib/axi/AXI_stream/axis_rom_contect_sim.sv +113 -0
  191. data/lib/axi/AXI_stream/axis_slaver_empty.sv +22 -0
  192. data/lib/axi/AXI_stream/axis_slaver_pipe.sv +84 -0
  193. data/lib/axi/AXI_stream/axis_slaver_pipe_A1.sv +54 -0
  194. data/lib/axi/AXI_stream/axis_slaver_vector_empty.sv +27 -0
  195. data/lib/axi/AXI_stream/axis_split_channel_verb.rb +42 -0
  196. data/lib/axi/AXI_stream/axis_split_channel_verb.sv +62 -0
  197. data/lib/axi/AXI_stream/axis_to_axi4_or_lite.rb +127 -0
  198. data/lib/axi/AXI_stream/axis_to_axi4_or_lite.sv +153 -0
  199. data/lib/axi/AXI_stream/axis_to_data_inf.sv +34 -0
  200. data/lib/axi/AXI_stream/axis_to_lite_rd.sv +81 -0
  201. data/lib/axi/AXI_stream/axis_to_lite_wr.sv +71 -0
  202. data/lib/axi/AXI_stream/axis_uncompress.sv +147 -0
  203. data/lib/axi/AXI_stream/axis_uncompress_A1.sv +150 -0
  204. data/lib/axi/AXI_stream/axis_uncompress_verb.rb +32 -0
  205. data/lib/axi/AXI_stream/axis_uncompress_verb.sv +54 -0
  206. data/lib/axi/AXI_stream/axis_valve.sv +29 -0
  207. data/lib/axi/AXI_stream/axis_valve_with_pipe.sv +76 -0
  208. data/lib/axi/AXI_stream/axis_vector_master_empty.rb +11 -0
  209. data/lib/axi/AXI_stream/axis_vector_master_empty.sv +35 -0
  210. data/lib/axi/AXI_stream/axis_vector_slaver_empty.rb +11 -0
  211. data/lib/axi/AXI_stream/axis_vector_slaver_empty.sv +35 -0
  212. data/lib/axi/AXI_stream/check_stream_crc.sv +28 -0
  213. data/lib/axi/AXI_stream/data_c_to_axis_full.sv +23 -0
  214. data/lib/axi/AXI_stream/data_to_axis_inf.sv +103 -0
  215. data/lib/axi/AXI_stream/data_to_axis_inf_A1.sv +28 -0
  216. data/lib/axi/AXI_stream/data_width/axis_width_combin.sv +204 -0
  217. data/lib/axi/AXI_stream/data_width/axis_width_combin_A1.sv +220 -0
  218. data/lib/axi/AXI_stream/data_width/axis_width_convert.sv +49 -0
  219. data/lib/axi/AXI_stream/data_width/axis_width_destruct.sv +82 -0
  220. data/lib/axi/AXI_stream/data_width/axis_width_destruct_A1.sv +86 -0
  221. data/lib/axi/AXI_stream/ex_status/axis_ex_status.sv +97 -0
  222. data/lib/axi/AXI_stream/gen_big_field_table.sv +170 -0
  223. data/lib/axi/AXI_stream/gen_common_frame_table.sv +382 -0
  224. data/lib/axi/AXI_stream/gen_common_frame_table_bind_tuser.sv +428 -0
  225. data/lib/axi/AXI_stream/gen_origin_axis.sv +116 -0
  226. data/lib/axi/AXI_stream/gen_origin_axis_A1.sv +129 -0
  227. data/lib/axi/AXI_stream/gen_origin_axis_A2.sv +162 -0
  228. data/lib/axi/AXI_stream/gen_simple_axis.sv +164 -0
  229. data/lib/axi/AXI_stream/packet_fifo/axi_stream_long_fifo.sv +132 -0
  230. data/lib/axi/AXI_stream/packet_fifo/axi_stream_long_fifo_verb.sv +140 -0
  231. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo.sv +125 -0
  232. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1.sv +142 -0
  233. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1E.sv +198 -0
  234. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_verb.sv +120 -0
  235. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_with_info.sv +49 -0
  236. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_long_fifo.sv +197 -0
  237. data/lib/axi/AXI_stream/packet_fifo/axi_stream_wide_fifo.sv +141 -0
  238. data/lib/axi/AXI_stream/packet_fifo/axis_pkt_fifo_filter_keep.sv +164 -0
  239. data/lib/axi/AXI_stream/packet_fifo/axis_pkt_fifo_filter_keep_A1.sv +166 -0
  240. data/lib/axi/AXI_stream/parse_big_field_table.sv +164 -0
  241. data/lib/axi/AXI_stream/parse_big_field_table_A1.sv +162 -0
  242. data/lib/axi/AXI_stream/parse_big_field_table_A2.sv +165 -0
  243. data/lib/axi/AXI_stream/parse_big_field_table_verb.sv +118 -0
  244. data/lib/axi/AXI_stream/parse_common_frame_table.sv +202 -0
  245. data/lib/axi/AXI_stream/parse_common_frame_table_A1.sv +521 -0
  246. data/lib/axi/AXI_stream/parse_common_frame_table_A2.sv +561 -0
  247. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache.sv +46 -0
  248. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_35bit.sv +122 -0
  249. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_36_71bit.sv +71 -0
  250. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_72_95bit.sv +96 -0
  251. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_72_95bit_with_keep.sv +99 -0
  252. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_96_143bit.sv +119 -0
  253. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_A1.sv +49 -0
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  255. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_mirror.sv +44 -0
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  257. data/lib/axi/AXI_stream/stream_cache/axi_stream_long_cache.sv +55 -0
  258. data/lib/axi/AXI_stream/stream_crc.sv +67 -0
  259. data/lib/axi/AXI_stream/vcs_axis_comptable.sv +73 -0
  260. data/lib/axi/LICENSE +504 -0
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  263. data/lib/axi/SIM/tb_axis_bfm_0504.sv +61 -0
  264. data/lib/axi/SIM/tb_axis_partitiom_0929.sv +102 -0
  265. data/lib/axi/SIM/tb_axis_s2m_pipe_1023.sv +163 -0
  266. data/lib/axi/SIM/tb_axis_to_axi4_0925.sv +107 -0
  267. data/lib/axi/SIM/tb_data_c_m2s_inf_20200114.sv +222 -0
  268. data/lib/axi/SIM/tb_data_c_m2s_inf_20201103.sv +245 -0
  269. data/lib/axi/SIM/tb_data_c_pipe_inf_20180417.sv +114 -0
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  275. data/lib/axi/axi4_to_xilinx_ddr_native/ddr3_ip_native_to_axi4.sv +194 -0
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  283. data/lib/axi/cfg.yml +15 -0
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  285. data/lib/axi/common/common_ram_sim_wrapper.rb +66 -0
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  287. data/lib/axi/common/common_ram_wrapper.rb +71 -0
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  289. data/lib/axi/common/data_c_interface_dram.rb +90 -0
  290. data/lib/axi/common/data_c_interface_dram.sv +106 -0
  291. data/lib/axi/common/mem_format.coe +60 -0
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  311. data/lib/axi/data_interface/data_inf_c/data_c_pipe_force_vld_bind_data.sv +81 -0
  312. data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf.sv +130 -0
  313. data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf_A1.sv +135 -0
  314. data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf_left_shift.sv +158 -0
  315. data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf_right_shift.sv +155 -0
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  319. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_best_last.sv +319 -0
  320. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_best_robin.sv +293 -0
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  322. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_robin_with_id.sv +46 -0
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  324. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_verc_with_addr.sv +226 -0
  325. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_verc_with_id.sv +54 -0
  326. data/lib/axi/data_interface/data_inf_c/data_c_pipe_latency.sv +68 -0
  327. data/lib/axi/data_interface/data_inf_c/data_c_scaler.sv +326 -0
  328. data/lib/axi/data_interface/data_inf_c/data_c_scaler_A1.sv +333 -0
  329. data/lib/axi/data_interface/data_inf_c/data_c_tmp_cache.sv +44 -0
  330. data/lib/axi/data_interface/data_inf_c/data_condition_mirror.sv +64 -0
  331. data/lib/axi/data_interface/data_inf_c/data_condition_valve.sv +53 -0
  332. data/lib/axi/data_interface/data_inf_c/data_connect_pipe_inf.sv +73 -0
  333. data/lib/axi/data_interface/data_inf_c/data_inf_c_M2S_with_addr_and_id.sv +66 -0
  334. data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_M2S_with_id.sv +67 -0
  335. data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_S2M.sv +70 -0
  336. data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_S2M_A1.sv +72 -0
  337. data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_S2M_with_lazy.sv +49 -0
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  339. data/lib/axi/data_interface/data_inf_c/data_inf_c_pipe_condition.sv +33 -0
  340. data/lib/axi/data_interface/data_inf_c/data_inf_c_planer.sv +50 -0
  341. data/lib/axi/data_interface/data_inf_c/data_inf_c_planer_A1.sv +53 -0
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  347. data/lib/axi/data_interface/data_inf_c/next_prio.sv +42 -0
  348. data/lib/axi/data_interface/data_inf_c/trigger_data_inf_c.sv +51 -0
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  354. data/lib/axi/data_interface/data_inf_intc_M2S_prio.sv +152 -0
  355. data/lib/axi/data_interface/data_inf_intc_M2S_prio_with_id.sv +55 -0
  356. data/lib/axi/data_interface/data_inf_interconnect_M2S_noaddr.sv +136 -0
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  358. data/lib/axi/data_interface/data_inf_planer.sv +59 -0
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  382. data/lib/axi/data_interface/datainf_slaver_empty.sv +22 -0
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  384. data/lib/axi/interface_define/axi_aux_inf.sv +206 -0
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  423. data/lib/axi/platform_ip/fifo_73_96bit.sv +102 -0
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  468. data/lib/axi/top/tb_data_intc_S2M_0807.sv +168 -0
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  482. data/lib/tdl/Logic/logic_operator.rb.bak +128 -0
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  486. data/lib/tdl/ReadMe.md +295 -0
  487. data/lib/tdl/SDL/axi4/AXI4_interconnect_M2S_sdl.rb +10 -0
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  498. data/lib/tdl/SDL/axi4/axi4_long_to_axi4_wide_A1_sdl.rb +10 -0
  499. data/lib/tdl/SDL/axi4/axi4_long_to_axi4_wide_sdl.rb +9 -0
  500. data/lib/tdl/SDL/axi4/axi4_long_to_axi4_wide_track_sdl.rb +9 -0
  501. data/lib/tdl/SDL/axi4/axi4_long_to_axi4_wide_verb_sdl.rb +11 -0
  502. data/lib/tdl/SDL/axi4/axi4_merge_rd_sdl.rb +10 -0
  503. data/lib/tdl/SDL/axi4/axi4_merge_sdl.rb +10 -0
  504. data/lib/tdl/SDL/axi4/axi4_merge_wr_sdl.rb +10 -0
  505. data/lib/tdl/SDL/axi4/axi4_mix_interconnect_M2S_sdl.rb +10 -0
  506. data/lib/tdl/SDL/axi4/axi4_packet_fifo_sdl.rb +12 -0
  507. data/lib/tdl/SDL/axi4/axi4_partition_OD_sdl.rb +11 -0
  508. data/lib/tdl/SDL/axi4/axi4_partition_rd_OD_sdl.rb +10 -0
  509. data/lib/tdl/SDL/axi4/axi4_partition_rd_sdl.rb +11 -0
  510. data/lib/tdl/SDL/axi4/axi4_partition_sdl.rb +11 -0
  511. data/lib/tdl/SDL/axi4/axi4_partition_wr_OD_sdl.rb +10 -0
  512. data/lib/tdl/SDL/axi4/axi4_partition_wr_sdl.rb +11 -0
  513. data/lib/tdl/SDL/axi4/axi4_pipe_sdl.rb +9 -0
  514. data/lib/tdl/SDL/axi4/axi4_pipe_verb_sdl.rb +9 -0
  515. data/lib/tdl/SDL/axi4/axi4_rd_auxiliary_batch_gen_sdl.rb +11 -0
  516. data/lib/tdl/SDL/axi4/axi4_rd_auxiliary_gen_A1_sdl.rb +9 -0
  517. data/lib/tdl/SDL/axi4/axi4_rd_auxiliary_gen_sdl.rb +9 -0
  518. data/lib/tdl/SDL/axi4/axi4_rd_burst_track_sdl.rb +10 -0
  519. data/lib/tdl/SDL/axi4/axi4_rd_interconnect_M2S_sdl.rb +10 -0
  520. data/lib/tdl/SDL/axi4/axi4_rd_mix_interconnect_M2S_A1_sdl.rb +10 -0
  521. data/lib/tdl/SDL/axi4/axi4_rd_mix_interconnect_M2S_A2_sdl.rb +10 -0
  522. data/lib/tdl/SDL/axi4/axi4_rd_mix_interconnect_M2S_sdl.rb +10 -0
  523. data/lib/tdl/SDL/axi4/axi4_rd_packet_fifo_sdl.rb +11 -0
  524. data/lib/tdl/SDL/axi4/axi4_rd_pipe_sdl.rb +9 -0
  525. data/lib/tdl/SDL/axi4/axi4_rd_pipe_verb_sdl.rb +9 -0
  526. data/lib/tdl/SDL/axi4/axi4_wr_aux_bind_data_sdl.rb +9 -0
  527. data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_batch_gen_sdl.rb +11 -0
  528. data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_gen_sdl.rb +10 -0
  529. data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_gen_without_resp_sdl.rb +10 -0
  530. data/lib/tdl/SDL/axi4/axi4_wr_burst_track_sdl.rb +10 -0
  531. data/lib/tdl/SDL/axi4/axi4_wr_interconnect_M2S_A1_sdl.rb +10 -0
  532. data/lib/tdl/SDL/axi4/axi4_wr_interconnect_M2S_sdl.rb +10 -0
  533. data/lib/tdl/SDL/axi4/axi4_wr_mix_interconnect_M2S_sdl.rb +10 -0
  534. data/lib/tdl/SDL/axi4/axi4_wr_packet_fifo_sdl.rb +11 -0
  535. data/lib/tdl/SDL/axi4/axi4_wr_pipe_sdl.rb +9 -0
  536. data/lib/tdl/SDL/axi4/axi4_wr_pipe_verb_sdl.rb +9 -0
  537. data/lib/tdl/SDL/axi4/axi_stream_add_addr_len_sdl.rb +11 -0
  538. data/lib/tdl/SDL/axi4/axi_stream_to_axi4_wr_sdl.rb +9 -0
  539. data/lib/tdl/SDL/axi4/data_combin_sdl.rb +20 -0
  540. data/lib/tdl/SDL/axi4/data_destruct_sdl.rb +19 -0
  541. data/lib/tdl/SDL/axi4/feed_check_sdl.rb +18 -0
  542. data/lib/tdl/SDL/axi4/full_axi4_to_axis_partition_wr_rd_sdl.rb +11 -0
  543. data/lib/tdl/SDL/axi4/full_axi4_to_axis_sdl.rb +10 -0
  544. data/lib/tdl/SDL/axi4/id_record_sdl.rb +19 -0
  545. data/lib/tdl/SDL/axi4/idata_pool_axi4_sdl.rb +18 -0
  546. data/lib/tdl/SDL/axi4/odata_pool_axi4_A1_sdl.rb +13 -0
  547. data/lib/tdl/SDL/axi4/odata_pool_axi4_A2_sdl.rb +10 -0
  548. data/lib/tdl/SDL/axi4/odata_pool_axi4_sdl.rb +19 -0
  549. data/lib/tdl/SDL/axi4/odd_width_convert_sdl.rb +19 -0
  550. data/lib/tdl/SDL/axi4/odd_width_convert_verb_sdl.rb +19 -0
  551. data/lib/tdl/SDL/axi4/simple_data_pipe_sdl.rb +16 -0
  552. data/lib/tdl/SDL/axi4/simple_data_pipe_slaver_sdl.rb +16 -0
  553. data/lib/tdl/SDL/axi4/vcs_axi4_array_comptable.rb +9 -0
  554. data/lib/tdl/SDL/axi4/vcs_axi4_array_comptable_sdl.rb +10 -0
  555. data/lib/tdl/SDL/axi4/vcs_axi4_comptable.rb +8 -0
  556. data/lib/tdl/SDL/axi4/vcs_axi4_comptable_sdl.rb +9 -0
  557. data/lib/tdl/SDL/axi4/width_combin_sdl.rb +20 -0
  558. data/lib/tdl/SDL/axi4/width_convert_sdl.rb +20 -0
  559. data/lib/tdl/SDL/axi4/width_convert_verb_sdl.rb +20 -0
  560. data/lib/tdl/SDL/axi4/width_destruct_A1_sdl.rb +22 -0
  561. data/lib/tdl/SDL/axi4/width_destruct_sdl.rb +19 -0
  562. data/lib/tdl/SDL/axistream/axi_stream_cache_35bit_sdl.rb +9 -0
  563. data/lib/tdl/SDL/axistream/axi_stream_cache_36_71bit_sdl.rb +9 -0
  564. data/lib/tdl/SDL/axistream/axi_stream_cache_72_95bit_sdl.rb +9 -0
  565. data/lib/tdl/SDL/axistream/axi_stream_cache_72_95bit_with_keep_sdl.rb +9 -0
  566. data/lib/tdl/SDL/axistream/axi_stream_cache_96_143bit_sdl.rb +9 -0
  567. data/lib/tdl/SDL/axistream/axi_stream_cache_B1_sdl.rb +9 -0
  568. data/lib/tdl/SDL/axistream/axi_stream_cache_mirror_sdl.rb +9 -0
  569. data/lib/tdl/SDL/axistream/axi_stream_cache_sdl.rb +9 -0
  570. data/lib/tdl/SDL/axistream/axi_stream_cache_verb_sdl.rb +9 -0
  571. data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_A1_sdl.rb +11 -0
  572. data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_A2_sdl.rb +13 -0
  573. data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_bind_tuser_sdl.rb +11 -0
  574. data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_noaddr_sdl.rb +11 -0
  575. data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_sdl.rb +12 -0
  576. data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_with_addr_sdl.rb +12 -0
  577. data/lib/tdl/SDL/axistream/axi_stream_interconnect_S2M_auto_sdl.rb +11 -0
  578. data/lib/tdl/SDL/axistream/axi_stream_interconnect_S2M_sdl.rb +12 -0
  579. data/lib/tdl/SDL/axistream/axi_stream_long_cache_sdl.rb +10 -0
  580. data/lib/tdl/SDL/axistream/axi_stream_long_fifo_sdl.rb +11 -0
  581. data/lib/tdl/SDL/axistream/axi_stream_long_fifo_verb_sdl.rb +11 -0
  582. data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_B1E_sdl.rb +16 -0
  583. data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_B1_sdl.rb +14 -0
  584. data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_sdl.rb +10 -0
  585. data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_verb_sdl.rb +13 -0
  586. data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_with_info_sdl.rb +13 -0
  587. data/lib/tdl/SDL/axistream/axi_stream_packet_long_fifo_sdl.rb +11 -0
  588. data/lib/tdl/SDL/axistream/axi_stream_partition_A1_sdl.rb +11 -0
  589. data/lib/tdl/SDL/axistream/axi_stream_partition_sdl.rb +12 -0
  590. data/lib/tdl/SDL/axistream/axi_stream_wide_fifo_sdl.rb +10 -0
  591. data/lib/tdl/SDL/axistream/axi_streams_combin_A1_sdl.rb +15 -0
  592. data/lib/tdl/SDL/axistream/axi_streams_combin_sdl.rb +16 -0
  593. data/lib/tdl/SDL/axistream/axi_streams_scaler_A1_sdl.rb +14 -0
  594. data/lib/tdl/SDL/axistream/axi_streams_scaler_sdl.rb +15 -0
  595. data/lib/tdl/SDL/axistream/axis_append_A1_sdl.rb +18 -0
  596. data/lib/tdl/SDL/axistream/axis_append_sdl.rb +17 -0
  597. data/lib/tdl/SDL/axistream/axis_base_pipe_sdl.rb +10 -0
  598. data/lib/tdl/SDL/axistream/axis_combin_with_fifo_sdl.rb +14 -0
  599. data/lib/tdl/SDL/axistream/axis_connect_pipe_right_shift_sdl.rb +10 -0
  600. data/lib/tdl/SDL/axistream/axis_connect_pipe_sdl.rb +9 -0
  601. data/lib/tdl/SDL/axistream/axis_connect_pipe_with_info_sdl.rb +12 -0
  602. data/lib/tdl/SDL/axistream/axis_direct_A1_sdl.rb +11 -0
  603. data/lib/tdl/SDL/axistream/axis_direct_sdl.rb +9 -0
  604. data/lib/tdl/SDL/axistream/axis_ex_status_sdl.rb +12 -0
  605. data/lib/tdl/SDL/axistream/axis_filter_sdl.rb +10 -0
  606. data/lib/tdl/SDL/axistream/axis_full_to_data_c_sdl.rb +9 -0
  607. data/lib/tdl/SDL/axistream/axis_head_cut_sdl.rb +10 -0
  608. data/lib/tdl/SDL/axistream/axis_inct_s2m_with_flag_sdl.rb +11 -0
  609. data/lib/tdl/SDL/axistream/axis_intc_M2S_with_addr_inf_sdl.rb +11 -0
  610. data/lib/tdl/SDL/axistream/axis_intc_S2M_with_addr_inf_sdl.rb +12 -0
  611. data/lib/tdl/SDL/axistream/axis_interconnect_S2M_pipe_sdl.rb +15 -0
  612. data/lib/tdl/SDL/axistream/axis_length_cut_sdl.rb +10 -0
  613. data/lib/tdl/SDL/axistream/axis_length_fill_sdl.rb +10 -0
  614. data/lib/tdl/SDL/axistream/axis_length_split_sdl.rb +10 -0
  615. data/lib/tdl/SDL/axistream/axis_length_split_with_addr_sdl.rb +13 -0
  616. data/lib/tdl/SDL/axistream/axis_length_split_writh_user_sdl.rb +10 -0
  617. data/lib/tdl/SDL/axistream/axis_link_trigger_sdl.rb +12 -0
  618. data/lib/tdl/SDL/axistream/axis_master_empty_sdl.rb +8 -0
  619. data/lib/tdl/SDL/axistream/axis_mirror_to_master_sdl.rb +10 -0
  620. data/lib/tdl/SDL/axistream/axis_mirrors_sdl.rb +14 -0
  621. data/lib/tdl/SDL/axistream/axis_orthogonal_sdl.rb +10 -0
  622. data/lib/tdl/SDL/axistream/axis_pkt_fifo_filter_keep_A1_sdl.rb +10 -0
  623. data/lib/tdl/SDL/axistream/axis_pkt_fifo_filter_keep_sdl.rb +10 -0
  624. data/lib/tdl/SDL/axistream/axis_ram_buffer_sdl.rb +13 -0
  625. data/lib/tdl/SDL/axistream/axis_slaver_empty_sdl.rb +8 -0
  626. data/lib/tdl/SDL/axistream/axis_slaver_pipe_A1_sdl.rb +10 -0
  627. data/lib/tdl/SDL/axistream/axis_slaver_pipe_sdl.rb +9 -0
  628. data/lib/tdl/SDL/axistream/axis_slaver_vector_empty_sdl.rb +9 -0
  629. data/lib/tdl/SDL/axistream/axis_to_data_inf_sdl.rb +10 -0
  630. data/lib/tdl/SDL/axistream/axis_to_lite_rd_sdl.rb +11 -0
  631. data/lib/tdl/SDL/axistream/axis_to_lite_wr_sdl.rb +10 -0
  632. data/lib/tdl/SDL/axistream/axis_uncompress_A1_sdl.rb +12 -0
  633. data/lib/tdl/SDL/axistream/axis_uncompress_sdl.rb +11 -0
  634. data/lib/tdl/SDL/axistream/axis_valve_sdl.rb +10 -0
  635. data/lib/tdl/SDL/axistream/axis_valve_with_pipe_sdl.rb +11 -0
  636. data/lib/tdl/SDL/axistream/axis_width_combin_A1_sdl.rb +9 -0
  637. data/lib/tdl/SDL/axistream/axis_width_combin_sdl.rb +9 -0
  638. data/lib/tdl/SDL/axistream/axis_width_convert_sdl.rb +9 -0
  639. data/lib/tdl/SDL/axistream/axis_width_destruct_A1_sdl.rb +9 -0
  640. data/lib/tdl/SDL/axistream/axis_width_destruct_sdl.rb +9 -0
  641. data/lib/tdl/SDL/axistream/check_stream_crc_sdl.rb +8 -0
  642. data/lib/tdl/SDL/axistream/data_c_to_axis_full_sdl.rb +9 -0
  643. data/lib/tdl/SDL/axistream/data_to_axis_inf_A1_sdl.rb +10 -0
  644. data/lib/tdl/SDL/axistream/data_to_axis_inf_sdl.rb +11 -0
  645. data/lib/tdl/SDL/axistream/gen_big_field_table_sdl.rb +14 -0
  646. data/lib/tdl/SDL/axistream/gen_common_frame_table_sdl.rb +60 -0
  647. data/lib/tdl/SDL/axistream/gen_origin_axis_A1_sdl.rb +13 -0
  648. data/lib/tdl/SDL/axistream/gen_origin_axis_sdl.rb +12 -0
  649. data/lib/tdl/SDL/axistream/gen_simple_axis_sdl.rb +13 -0
  650. data/lib/tdl/SDL/axistream/parse_big_field_table_A1_sdl.rb +17 -0
  651. data/lib/tdl/SDL/axistream/parse_big_field_table_A2_sdl.rb +17 -0
  652. data/lib/tdl/SDL/axistream/parse_big_field_table_sdl.rb +17 -0
  653. data/lib/tdl/SDL/axistream/stream_crc_sdl.rb +9 -0
  654. data/lib/tdl/SDL/axistream/vcs_axis_comptable.rb +16 -0
  655. data/lib/tdl/SDL/axistream/vcs_axis_comptable_sdl.rb +9 -0
  656. data/lib/tdl/SDL/data_inf_c/data_bind_sdl.rb +10 -0
  657. data/lib/tdl/SDL/data_inf_c/data_c_cache_sdl.rb +9 -0
  658. data/lib/tdl/SDL/data_inf_c/data_c_direct_mirror_sdl.rb +9 -0
  659. data/lib/tdl/SDL/data_inf_c/data_c_direct_sdl.rb +9 -0
  660. data/lib/tdl/SDL/data_inf_c/data_c_intc_M2S_force_robin_sdl.rb +10 -0
  661. data/lib/tdl/SDL/data_inf_c/data_c_pipe_force_vld_bind_data_sdl.rb +13 -0
  662. data/lib/tdl/SDL/data_inf_c/data_c_pipe_force_vld_sdl.rb +9 -0
  663. data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_A1_sdl.rb +10 -0
  664. data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_right_shift_sdl.rb +13 -0
  665. data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_sdl.rb +9 -0
  666. data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_C1_sdl.rb +14 -0
  667. data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_C1_with_id_sdl.rb +16 -0
  668. data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_sdl.rb +13 -0
  669. data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_with_addr_sdl.rb +13 -0
  670. data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_with_id_sdl.rb +15 -0
  671. data/lib/tdl/SDL/data_inf_c/data_c_pipe_latency_sdl.rb +10 -0
  672. data/lib/tdl/SDL/data_inf_c/data_c_scaler_A1_sdl.rb +16 -0
  673. data/lib/tdl/SDL/data_inf_c/data_c_scaler_sdl.rb +15 -0
  674. data/lib/tdl/SDL/data_inf_c/data_c_tmp_cache_sdl.rb +9 -0
  675. data/lib/tdl/SDL/data_inf_c/data_condition_mirror_sdl.rb +13 -0
  676. data/lib/tdl/SDL/data_inf_c/data_condition_valve_sdl.rb +13 -0
  677. data/lib/tdl/SDL/data_inf_c/data_connect_pipe_inf_sdl.rb +9 -0
  678. data/lib/tdl/SDL/data_inf_c/data_connect_pipe_sdl.rb +17 -0
  679. data/lib/tdl/SDL/data_inf_c/data_inf_A2B_sdl.rb +9 -0
  680. data/lib/tdl/SDL/data_inf_c/data_inf_B2A_sdl.rb +9 -0
  681. data/lib/tdl/SDL/data_inf_c/data_inf_c_M2S_with_addr_and_id_sdl.rb +17 -0
  682. data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_M2S_with_id_sdl.rb +15 -0
  683. data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_A1_sdl.rb +13 -0
  684. data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_sdl.rb +12 -0
  685. data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_with_lazy_sdl.rb +15 -0
  686. data/lib/tdl/SDL/data_inf_c/data_inf_c_interconnect_M2S_sdl.rb +12 -0
  687. data/lib/tdl/SDL/data_inf_c/data_inf_c_pipe_condition_sdl.rb +10 -0
  688. data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_A1.rb +12 -0
  689. data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_A1_sdl.rb +14 -0
  690. data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_sdl.rb +13 -0
  691. data/lib/tdl/SDL/data_inf_c/data_inf_cross_clk_sdl.rb +9 -0
  692. data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_force_addr_with_id_sdl.rb +19 -0
  693. data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_prio_sdl.rb +14 -0
  694. data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_prio_with_id_sdl.rb +17 -0
  695. data/lib/tdl/SDL/data_inf_c/data_inf_interconnect_M2S_noaddr_sdl.rb +14 -0
  696. data/lib/tdl/SDL/data_inf_c/data_inf_interconnect_M2S_with_id_noaddr_sdl.rb +17 -0
  697. data/lib/tdl/SDL/data_inf_c/data_inf_planer_A1_sdl.rb +15 -0
  698. data/lib/tdl/SDL/data_inf_c/data_inf_planer_sdl.rb +14 -0
  699. data/lib/tdl/SDL/data_inf_c/data_inf_ticktock_sdl.rb +18 -0
  700. data/lib/tdl/SDL/data_inf_c/data_intc_M2S_force_robin_sdl.rb +10 -0
  701. data/lib/tdl/SDL/data_inf_c/data_mirrors_sdl.rb +14 -0
  702. data/lib/tdl/SDL/data_inf_c/data_pair_map_A1_sdl.rb +16 -0
  703. data/lib/tdl/SDL/data_inf_c/data_pair_map_A2_sdl.rb +19 -0
  704. data/lib/tdl/SDL/data_inf_c/data_pair_map_sdl.rb +14 -0
  705. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_A1_sdl.rb +19 -0
  706. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_sdl.rb +17 -0
  707. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_verb_sdl.rb +16 -0
  708. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_A1_sdl.rb +19 -0
  709. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_sdl.rb +16 -0
  710. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_verb_sdl.rb +15 -0
  711. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_sdl.rb +23 -0
  712. data/lib/tdl/SDL/data_inf_c/data_streams_combin_A1_sdl.rb +20 -0
  713. data/lib/tdl/SDL/data_inf_c/data_streams_combin_sdl.rb +20 -0
  714. data/lib/tdl/SDL/data_inf_c/data_streams_scaler_sdl.rb +19 -0
  715. data/lib/tdl/SDL/data_inf_c/data_uncompress_sdl.rb +11 -0
  716. data/lib/tdl/SDL/data_inf_c/data_valve_sdl.rb +10 -0
  717. data/lib/tdl/SDL/data_inf_c/datainf_c_master_empty_sdl.rb +8 -0
  718. data/lib/tdl/SDL/data_inf_c/datainf_c_slaver_empty_sdl.rb +8 -0
  719. data/lib/tdl/SDL/data_inf_c/datainf_master_empty_sdl.rb +8 -0
  720. data/lib/tdl/SDL/data_inf_c/datainf_slaver_empty_sdl.rb +8 -0
  721. data/lib/tdl/SDL/data_inf_c/latency_sdl.rb +8 -0
  722. data/lib/tdl/SDL/data_inf_c/next_prio_sdl.rb +12 -0
  723. data/lib/tdl/SDL/data_inf_c/part_data_pair_map_sdl.rb +19 -0
  724. data/lib/tdl/SDL/data_inf_c/trigger_data_inf_c_A1_sdl.rb +11 -0
  725. data/lib/tdl/SDL/data_inf_c/trigger_data_inf_c_sdl.rb +11 -0
  726. data/lib/tdl/SDL/data_inf_c/trigger_ready_ctrl_sdl.rb +12 -0
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  969. data/lib/tdl/class_hdl/hdl_parameter.rb +73 -0
  970. data/lib/tdl/class_hdl/hdl_random.rb +31 -0
  971. data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +653 -0
  972. data/lib/tdl/class_hdl/hdl_struct.rb +209 -0
  973. data/lib/tdl/class_hdl/hdl_verify.rb +136 -0
  974. data/lib/tdl/data_inf/_data_mirrors.rb +92 -0
  975. data/lib/tdl/data_inf/bak/_data_mirrors.rb +273 -0
  976. data/lib/tdl/data_inf/bak/common_fifo_auto.rb +279 -0
  977. data/lib/tdl/data_inf/bak/data_bind_auto.rb +128 -0
  978. data/lib/tdl/data_inf/bak/data_c_direct_auto.rb +138 -0
  979. data/lib/tdl/data_inf/bak/data_c_direct_mirror_auto.rb +138 -0
  980. data/lib/tdl/data_inf/bak/data_c_tmp_cache_auto.rb +138 -0
  981. data/lib/tdl/data_inf/bak/data_condition_mirror_auto.rb +216 -0
  982. data/lib/tdl/data_inf/bak/data_condition_valve_auto.rb +215 -0
  983. data/lib/tdl/data_inf/bak/data_connect_pipe.rb +80 -0
  984. data/lib/tdl/data_inf/bak/data_connect_pipe_inf_auto.rb +138 -0
  985. data/lib/tdl/data_inf/bak/data_inf_c_interconnect.rb +86 -0
  986. data/lib/tdl/data_inf/bak/data_inf_c_pipe_condition_auto.rb +157 -0
  987. data/lib/tdl/data_inf/bak/data_inf_cross_clk.rb +60 -0
  988. data/lib/tdl/data_inf/bak/data_inf_interconnect.rb +144 -0
  989. data/lib/tdl/data_inf/bak/data_inf_planer.rb +78 -0
  990. data/lib/tdl/data_inf/bak/data_inf_ticktack.rb +80 -0
  991. data/lib/tdl/data_inf/bak/data_inf_ticktock_auto.rb +0 -0
  992. data/lib/tdl/data_inf/bak/data_mirrors_auto.rb +234 -0
  993. data/lib/tdl/data_inf/bak/data_mirrors_verb.sv_auto.rb +234 -0
  994. data/lib/tdl/data_inf/bak/data_uncompress_auto.rb +177 -0
  995. data/lib/tdl/data_inf/bak/data_valve_auto.rb +127 -0
  996. data/lib/tdl/data_inf/bak/datainf_c_master_empty_auto.rb +95 -0
  997. data/lib/tdl/data_inf/bak/datainf_c_slaver_empty_auto.rb +88 -0
  998. data/lib/tdl/data_inf/bak/datainf_master_empty_auto.rb +95 -0
  999. data/lib/tdl/data_inf/bak/datainf_slaver_empty_auto.rb +88 -0
  1000. data/lib/tdl/data_inf/bak/independent_clock_fifo_auto.rb +298 -0
  1001. data/lib/tdl/data_inf/bak/part_data_pair_map_auto.rb +306 -0
  1002. data/lib/tdl/data_inf/common_fifo_auto.rb +141 -0
  1003. data/lib/tdl/data_inf/data_bind_auto.rb +79 -0
  1004. data/lib/tdl/data_inf/data_c_cache_auto.rb +135 -0
  1005. data/lib/tdl/data_inf/data_c_direct_auto.rb +127 -0
  1006. data/lib/tdl/data_inf/data_c_direct_mirror_auto.rb +127 -0
  1007. data/lib/tdl/data_inf/data_c_interconnect.rb +97 -0
  1008. data/lib/tdl/data_inf/data_c_pipe_force_vld_auto.rb +127 -0
  1009. data/lib/tdl/data_inf/data_c_pipe_inf_auto.rb +127 -0
  1010. data/lib/tdl/data_inf/data_c_pipe_intc_M2S_verc_auto.rb +123 -0
  1011. data/lib/tdl/data_inf/data_c_tmp_cache_auto.rb +127 -0
  1012. data/lib/tdl/data_inf/data_condition_mirror_auto.rb +165 -0
  1013. data/lib/tdl/data_inf/data_condition_valve_auto.rb +164 -0
  1014. data/lib/tdl/data_inf/data_connect_pipe_inf_auto.rb +127 -0
  1015. data/lib/tdl/data_inf/data_inf_c_pipe_condition_auto.rb +136 -0
  1016. data/lib/tdl/data_inf/data_mirrors_auto.rb +173 -0
  1017. data/lib/tdl/data_inf/data_mirrors_verb.sv_auto.rb +173 -0
  1018. data/lib/tdl/data_inf/data_uncompress_auto.rb +146 -0
  1019. data/lib/tdl/data_inf/data_valve_auto.rb +104 -0
  1020. data/lib/tdl/data_inf/datainf_c_master_empty_auto.rb +85 -0
  1021. data/lib/tdl/data_inf/datainf_c_slaver_empty_auto.rb +68 -0
  1022. data/lib/tdl/data_inf/datainf_master_empty_auto.rb +85 -0
  1023. data/lib/tdl/data_inf/datainf_slaver_empty_auto.rb +68 -0
  1024. data/lib/tdl/data_inf/independent_clock_fifo_auto.rb +141 -0
  1025. data/lib/tdl/data_inf/part_data_pair_map_auto.rb +149 -0
  1026. data/lib/tdl/data_inf/path_lib.rb +18 -0
  1027. data/lib/tdl/elements/Reset.rb +153 -0
  1028. data/lib/tdl/elements/axi4.rb +642 -0
  1029. data/lib/tdl/elements/axi_lite.rb +246 -0
  1030. data/lib/tdl/elements/axi_stream.rb +674 -0
  1031. data/lib/tdl/elements/clock.rb +193 -0
  1032. data/lib/tdl/elements/common_configure_reg.rb +135 -0
  1033. data/lib/tdl/elements/data_inf.rb +660 -0
  1034. data/lib/tdl/elements/logic.rb +356 -0
  1035. data/lib/tdl/elements/mail_box.rb +64 -0
  1036. data/lib/tdl/elements/originclass.rb +689 -0
  1037. data/lib/tdl/elements/parameter.rb +318 -0
  1038. data/lib/tdl/elements/track_inf.rb +163 -0
  1039. data/lib/tdl/elements/videoinf.rb +224 -0
  1040. data/lib/tdl/examples/10_random/exp_random.rb +13 -0
  1041. data/lib/tdl/examples/10_random/exp_random.sv +36 -0
  1042. data/lib/tdl/examples/11_test_unit/dve.tcl +64 -0
  1043. data/lib/tdl/examples/11_test_unit/exp_test_unit.rb +58 -0
  1044. data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +35 -0
  1045. data/lib/tdl/examples/11_test_unit/exp_test_unit_constraints.xdc +25 -0
  1046. data/lib/tdl/examples/11_test_unit/modules/sub_md0.rb +23 -0
  1047. data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +41 -0
  1048. data/lib/tdl/examples/11_test_unit/modules/sub_md1.rb +25 -0
  1049. data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv +41 -0
  1050. data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +28 -0
  1051. data/lib/tdl/examples/11_test_unit/tu0.sv +38 -0
  1052. data/lib/tdl/examples/11_test_unit/tu1.sv +28 -0
  1053. data/lib/tdl/examples/1_define_module/example1.rb +39 -0
  1054. data/lib/tdl/examples/1_define_module/exmple_md.sv +50 -0
  1055. data/lib/tdl/examples/2_hdl_class/always_comb.rb +99 -0
  1056. data/lib/tdl/examples/2_hdl_class/always_ff.rb +143 -0
  1057. data/lib/tdl/examples/2_hdl_class/case.rb +93 -0
  1058. data/lib/tdl/examples/2_hdl_class/foreach.rb +21 -0
  1059. data/lib/tdl/examples/2_hdl_class/function.rb +34 -0
  1060. data/lib/tdl/examples/2_hdl_class/generate.rb +62 -0
  1061. data/lib/tdl/examples/2_hdl_class/module_def.rb +33 -0
  1062. data/lib/tdl/examples/2_hdl_class/module_head_import_package.rb +36 -0
  1063. data/lib/tdl/examples/2_hdl_class/module_instance_test.rb +13 -0
  1064. data/lib/tdl/examples/2_hdl_class/package.rb +29 -0
  1065. data/lib/tdl/examples/2_hdl_class/package2.rb +21 -0
  1066. data/lib/tdl/examples/2_hdl_class/simple_assign.rb +39 -0
  1067. data/lib/tdl/examples/2_hdl_class/state_case.rb +65 -0
  1068. data/lib/tdl/examples/2_hdl_class/struct.rb +25 -0
  1069. data/lib/tdl/examples/2_hdl_class/struct_function.rb +28 -0
  1070. data/lib/tdl/examples/2_hdl_class/test_axi4_M2S.rb +16 -0
  1071. data/lib/tdl/examples/2_hdl_class/test_initial_assert.rb +11 -0
  1072. data/lib/tdl/examples/2_hdl_class/test_inst_sugar.rb +28 -0
  1073. data/lib/tdl/examples/2_hdl_class/test_module_port.rb +47 -0
  1074. data/lib/tdl/examples/2_hdl_class/test_module_var.rb +18 -0
  1075. data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv +108 -0
  1076. data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +35 -0
  1077. data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv +105 -0
  1078. data/lib/tdl/examples/2_hdl_class/tmp/head_pkg_module.sv +42 -0
  1079. data/lib/tdl/examples/2_hdl_class/tmp/init_module.sv +110 -0
  1080. data/lib/tdl/examples/2_hdl_class/tmp/module_instance_test.sv +31 -0
  1081. data/lib/tdl/examples/2_hdl_class/tmp/port_module.sv +99 -0
  1082. data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv +27 -0
  1083. data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv +78 -0
  1084. data/lib/tdl/examples/2_hdl_class/tmp/test_axi4_M2S.sv +30 -0
  1085. data/lib/tdl/examples/2_hdl_class/tmp/test_foreach.sv +34 -0
  1086. data/lib/tdl/examples/2_hdl_class/tmp/test_function.sv +52 -0
  1087. data/lib/tdl/examples/2_hdl_class/tmp/test_initial_assert.sv +31 -0
  1088. data/lib/tdl/examples/2_hdl_class/tmp/test_inst_sugar.sv +42 -0
  1089. data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +36 -0
  1090. data/lib/tdl/examples/2_hdl_class/tmp/test_module_port.sv +33 -0
  1091. data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +35 -0
  1092. data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +38 -0
  1093. data/lib/tdl/examples/2_hdl_class/tmp/test_package2.sv +36 -0
  1094. data/lib/tdl/examples/2_hdl_class/tmp/test_struct.sv +38 -0
  1095. data/lib/tdl/examples/2_hdl_class/tmp/test_struct_function.sv +44 -0
  1096. data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +27 -0
  1097. data/lib/tdl/examples/2_hdl_class/tmp/text_generate.sv +54 -0
  1098. data/lib/tdl/examples/2_hdl_class/vcs_string.rb +5 -0
  1099. data/lib/tdl/examples/3_hdl_sdl_instance/hdl_test.sv +13 -0
  1100. data/lib/tdl/examples/3_hdl_sdl_instance/main.rb +26 -0
  1101. data/lib/tdl/examples/3_hdl_sdl_instance/main_md.sv +42 -0
  1102. data/lib/tdl/examples/3_hdl_sdl_instance/sdl_md.sv +30 -0
  1103. data/lib/tdl/examples/3_hdl_sdl_instance/sdl_test.rb +9 -0
  1104. data/lib/tdl/examples/4_generate/example.rb +38 -0
  1105. data/lib/tdl/examples/4_generate/test_generate.sv +59 -0
  1106. data/lib/tdl/examples/5_logic_combin/login_combin.rb +22 -0
  1107. data/lib/tdl/examples/5_logic_combin/test_logic_combin.sv +36 -0
  1108. data/lib/tdl/examples/6_module_with_interface/example.rb +48 -0
  1109. data/lib/tdl/examples/6_module_with_interface/example_interface.sv +40 -0
  1110. data/lib/tdl/examples/6_module_with_interface/inf_collect.rb +54 -0
  1111. data/lib/tdl/examples/6_module_with_interface/inf_collect.sv +63 -0
  1112. data/lib/tdl/examples/7_module_with_package/body_package.rb +3 -0
  1113. data/lib/tdl/examples/7_module_with_package/body_package.sv +25 -0
  1114. data/lib/tdl/examples/7_module_with_package/example_pkg.rb +20 -0
  1115. data/lib/tdl/examples/7_module_with_package/example_pkg.sv +35 -0
  1116. data/lib/tdl/examples/7_module_with_package/head_package.rb +8 -0
  1117. data/lib/tdl/examples/7_module_with_package/head_package.sv +29 -0
  1118. data/lib/tdl/examples/8_top_module/dve.tcl +64 -0
  1119. data/lib/tdl/examples/8_top_module/example.rb +8 -0
  1120. data/lib/tdl/examples/8_top_module/pins.yml +7 -0
  1121. data/lib/tdl/examples/8_top_module/tb_test_top.sv +29 -0
  1122. data/lib/tdl/examples/8_top_module/test_top.sv +28 -0
  1123. data/lib/tdl/examples/8_top_module/test_top_constraints.xdc +37 -0
  1124. data/lib/tdl/examples/9_itegration/A_itgt/a_test_md.sv +29 -0
  1125. data/lib/tdl/examples/9_itegration/A_itgt/a_test_module.rb +6 -0
  1126. data/lib/tdl/examples/9_itegration/A_itgt/itgt_module_a_block.rb +34 -0
  1127. data/lib/tdl/examples/9_itegration/clock_manage/itgt_module_clock_manage.rb +33 -0
  1128. data/lib/tdl/examples/9_itegration/clock_manage/simple_clock.rb +7 -0
  1129. data/lib/tdl/examples/9_itegration/clock_manage/simple_clock.sv +29 -0
  1130. data/lib/tdl/examples/9_itegration/dve.tcl +64 -0
  1131. data/lib/tdl/examples/9_itegration/pins.yml +4 -0
  1132. data/lib/tdl/examples/9_itegration/tb_test_top.sv +29 -0
  1133. data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +29 -0
  1134. data/lib/tdl/examples/9_itegration/test_top.sv +40 -0
  1135. data/lib/tdl/examples/9_itegration/test_top_constraints.xdc +29 -0
  1136. data/lib/tdl/examples/9_itegration/test_tttop.sv +40 -0
  1137. data/lib/tdl/examples/9_itegration/test_tttop_constraints.xdc +29 -0
  1138. data/lib/tdl/examples/9_itegration/top.rb +11 -0
  1139. data/lib/tdl/examples/readme.md +31 -0
  1140. data/lib/tdl/exlib/common_cfg_reg_inf.rb +139 -0
  1141. data/lib/tdl/exlib/constraints.rb +286 -0
  1142. data/lib/tdl/exlib/constraints_verb.rb +304 -0
  1143. data/lib/tdl/exlib/dve_tcl.rb +162 -0
  1144. data/lib/tdl/exlib/element_class_vars.rb +106 -0
  1145. data/lib/tdl/exlib/global_param.rb +108 -0
  1146. data/lib/tdl/exlib/integral_test/bak/integral_test.rb +206 -0
  1147. data/lib/tdl/exlib/integral_test/clock_itest.rb +28 -0
  1148. data/lib/tdl/exlib/integral_test/diff_clock_itest.rb +30 -0
  1149. data/lib/tdl/exlib/integral_test/io_itest.rb +41 -0
  1150. data/lib/tdl/exlib/integral_test/reset_itest.rb +31 -0
  1151. data/lib/tdl/exlib/integral_test/simple_logic_itest.rb +19 -0
  1152. data/lib/tdl/exlib/itegration.rb +307 -0
  1153. data/lib/tdl/exlib/itegration_verb.rb +913 -0
  1154. data/lib/tdl/exlib/parse_argv.rb +43 -0
  1155. data/lib/tdl/exlib/sdlmodule_sim.bak.rb +375 -0
  1156. data/lib/tdl/exlib/test_point.rb +287 -0
  1157. data/lib/tdl/global_scan.rb +134 -0
  1158. data/lib/tdl/rebuild_ele/axi4.rb +141 -0
  1159. data/lib/tdl/rebuild_ele/axi_lite.rb +56 -0
  1160. data/lib/tdl/rebuild_ele/axi_stream.rb +121 -0
  1161. data/lib/tdl/rebuild_ele/cm_ram_inf.sv +105 -0
  1162. data/lib/tdl/rebuild_ele/cm_ram_inf_define.rb +44 -0
  1163. data/lib/tdl/rebuild_ele/data_inf.rb +27 -0
  1164. data/lib/tdl/rebuild_ele/data_inf_c.rb +83 -0
  1165. data/lib/tdl/rebuild_ele/ele_base.rb +822 -0
  1166. data/lib/tdl/rebuild_ele/readme.md +1 -0
  1167. data/lib/tdl/sdlimplement/resource.yml +154 -0
  1168. data/lib/tdl/sdlimplement/sdl_impl_module.rb +391 -0
  1169. data/lib/tdl/sdlimplement/sdl_impl_param.rb +26 -0
  1170. data/lib/tdl/sdlimplement/test.rb +64 -0
  1171. data/lib/tdl/sdlmodule/bak/sdlmodule_varible_ex.rb +120 -0
  1172. data/lib/tdl/sdlmodule/generator_block_module.rb +84 -0
  1173. data/lib/tdl/sdlmodule/sdlmodule.rb +407 -0
  1174. data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb +333 -0
  1175. data/lib/tdl/sdlmodule/sdlmodule_draw.rb +272 -0
  1176. data/lib/tdl/sdlmodule/sdlmodule_head_logo.txt +10 -0
  1177. data/lib/tdl/sdlmodule/sdlmodule_instance.rb +623 -0
  1178. data/lib/tdl/sdlmodule/sdlmodule_port_define.rb +374 -0
  1179. data/lib/tdl/sdlmodule/sdlmodule_varible.rb +160 -0
  1180. data/lib/tdl/sdlmodule/sdlmodule_vcs_comptable.rb +140 -0
  1181. data/lib/tdl/sdlmodule/techbench_module.rb +14 -0
  1182. data/lib/tdl/sdlmodule/test_unit_module.rb +138 -0
  1183. data/lib/tdl/sdlmodule/top_module.rb +543 -0
  1184. data/lib/tdl/tdl.rb +265 -0
  1185. data/lib/tdl/tdlerror/tdlerror.rb +8 -0
  1186. data/lib/tdl/testunit/test_all.rb +4 -0
  1187. data/lib/tdl/testunit/test_array_chain.rb +89 -0
  1188. data/lib/tdl/testunit/test_tmp.rb +47 -0
  1189. metadata +1301 -0
data/lib/axi/AXI_Lite/axi_lite_interconnect_M2S.sv ADDED
@@ -0,0 +1,437 @@
1
+ /**********************************************
2
+ _______________________________________
3
+ ___________ Cook Darwin __________
4
+ _______________________________________
5
+ descript:
6
+ author : Cook.Darwin
7
+ Version: VERA.0.0
8
+ creaded: 2017/1/10
9
+ madified:
10
+ ***********************************************/
11
+ `timescale 1ns/1ps
12
+ module axi_lite_interconnect_M2S #(
13
+ parameter NUM = 4
14
+ )(
15
+ axi_lite_inf.slaver s00 [NUM-1:0],
16
+ axi_lite_inf.master m00
17
+ );
18
+
19
+ localparam NSIZE = NUM <= 2? 1 :
20
+ NUM <= 4? 2 :
21
+ NUM <= 8? 3 :
22
+ NUM <= 16?4 : 5;
23
+
24
+ logic[NSIZE-1:0] waddr;
25
+ logic waddr_vld;
26
+ logic[NSIZE-1:0] curr_waddr;
27
+
28
+ logic[NSIZE-1:0] raddr;
29
+ logic raddr_vld;
30
+ logic[NSIZE-1:0] curr_raddr;
31
+
32
+ //--->> STREAM CLOCK AND RESET <<-------------------
33
+ wire clock,rst_n;
34
+ assign clock = m00.axi_aclk;
35
+ assign rst_n = m00.axi_aresetn;
36
+ //---<< STREAM CLOCK AND RESET >>-------------------
37
+ genvar KK;
38
+ //--->> IMPORT EXPORT GET ADDR FUNCTION <<------------
39
+ // generate
40
+ // for(KK=0;KK<NUM;KK++)begin
41
+ // lite_connect_addr lite_connect_addr_inst (s00[KK],m00);
42
+ // end
43
+ // endgenerate
44
+ //---<< IMPORT EXPORT GET ADDR FUNCTION >>------------
45
+ //--->> ADDR STATUS <<---------------------
46
+
47
+ logic wlock_addr;
48
+ logic [NUM-1:0] wstart_s;
49
+ logic [NUM-1:0] wrelex;
50
+
51
+ logic rlock_addr;
52
+ logic [NUM-1:0] rstart_s;
53
+ logic [NUM-1:0] rrelex;
54
+
55
+ logic [NUM-1:0] awlock_relex;
56
+ logic [NUM-1:0] arlock_relex;
57
+
58
+ generate
59
+ for(KK=0;KK<NUM;KK++)begin
60
+ assign wstart_s[KK] = s00[KK].axi_awvalid ;
61
+ assign wrelex[KK] = (s00[KK].axi_bvalid && s00[KK].axi_bready && !s00[KK].axi_awlock) || awlock_relex[KK];
62
+
63
+ assign rstart_s[KK] = s00[KK].axi_arvalid;
64
+ assign rrelex[KK] = (s00[KK].axi_rvalid && s00[KK].axi_rready && !s00[KK].axi_arlock) || arlock_relex[KK];
65
+ end
66
+ endgenerate
67
+
68
+ int II;
69
+
70
+ //--->> LOCK <<-----------------------------
71
+ logic s00_wr_status [NUM-1:0];
72
+ logic s00_rd_status [NUM-1:0];
73
+
74
+ generate
75
+ for(KK=0;KK<NUM;KK++)begin
76
+ //------------------------------------------------------------
77
+ always@(posedge m00.axi_aclk)begin:WR_STATUS_BLOCK
78
+ if(~m00.axi_aresetn)
79
+ s00_wr_status[KK] <= '0;
80
+ else begin
81
+ if(s00[KK].axi_awvalid && s00[KK].axi_awready)
82
+ s00_wr_status[KK] <= 1'b1;
83
+ else if(s00[KK].axi_bvalid && s00[KK].axi_bready)
84
+ s00_wr_status[KK] <= 1'b0;
85
+ else s00_wr_status[KK] <= s00_wr_status[KK];
86
+ end
87
+ end
88
+
89
+ always@(posedge m00.axi_aclk)begin:RD_STATUS_BLOCK
90
+ if(~m00.axi_aresetn)
91
+ s00_rd_status[KK] <= '0;
92
+ else begin
93
+ if(s00[KK].axi_arvalid && s00[KK].axi_arready)
94
+ s00_rd_status[KK] <= 1'b1;
95
+ else if(s00[KK].axi_rvalid && s00[KK].axi_rready)
96
+ s00_rd_status[KK] <= 1'b0;
97
+ else s00_rd_status[KK] <= s00_rd_status[KK];
98
+ end
99
+ end
100
+ end
101
+ //==================================================================
102
+ endgenerate
103
+
104
+ logic[NUM-1:0] awlock_raising;
105
+ logic[NUM-1:0] awlock_falling;
106
+
107
+ logic[NUM-1:0] arlock_raising;
108
+ logic[NUM-1:0] arlock_falling;
109
+
110
+ generate
111
+ for(KK=0;KK<NUM;KK++)begin:GEN_EDGE_BLOCK
112
+ edge_generator aw_edge_generator_inst(
113
+ /* input */ .clk (m00.axi_aclk ),
114
+ /* input */ .rst_n (m00.axi_aresetn ),
115
+ /* input */ .in (s00[KK].axi_awlock ),
116
+ /* output */ .raising (awlock_raising[KK] ),
117
+ /* output */ .falling (awlock_falling[KK] )
118
+ );
119
+
120
+ edge_generator ar_edge_generator_inst(
121
+ /* input */ .clk (m00.axi_aclk ),
122
+ /* input */ .rst_n (m00.axi_aresetn ),
123
+ /* input */ .in (s00[KK].axi_arlock ),
124
+ /* output */ .raising (arlock_raising[KK] ),
125
+ /* output */ .falling (arlock_falling[KK] )
126
+ );
127
+
128
+ always@(posedge m00.axi_aclk)begin
129
+ if(~m00.axi_aresetn) awlock_relex[KK] <= 1'b0;
130
+ else begin
131
+ awlock_relex[KK] <= awlock_falling[KK] && !s00_wr_status[KK];
132
+ end
133
+ end
134
+
135
+ always@(posedge m00.axi_aclk)begin
136
+ if(~m00.axi_aresetn) arlock_relex[KK] <= 1'b0;
137
+ else begin
138
+ arlock_relex[KK] <= arlock_falling[KK] && !s00_rd_status[KK];
139
+ end
140
+ end
141
+ end
142
+ endgenerate
143
+ //---<< LOCK >>-----------------------------
144
+
145
+
146
+ always@(posedge m00.axi_aclk)begin:LOCK_BLOCK
147
+ if(~m00.axi_aresetn) wlock_addr <= 1'b0;
148
+ else begin
149
+ if(|wrelex)
150
+ wlock_addr <= 1'b0;
151
+ else if(|wstart_s)
152
+ wlock_addr <= 1'b1;
153
+ else wlock_addr <= wlock_addr;
154
+ end
155
+ end
156
+
157
+ always@(posedge m00.axi_aclk)begin
158
+ if(~m00.axi_aresetn) rlock_addr <= 1'b0;
159
+ else begin
160
+ if(|rrelex)
161
+ rlock_addr <= 1'b0;
162
+ else if(|rstart_s)
163
+ rlock_addr <= 1'b1;
164
+ else rlock_addr <= rlock_addr;
165
+ end
166
+ end
167
+
168
+ logic [NSIZE-1:0] waddr_t = {NSIZE{1'b0}};
169
+ logic [NSIZE-1:0] raddr_t = {NSIZE{1'b0}};
170
+
171
+ always@(*)begin
172
+ for(II=0;II<NUM;II++)begin
173
+ waddr_t = wstart_s[II]? II : waddr_t;
174
+ raddr_t = rstart_s[II]? II : raddr_t;
175
+ end
176
+ end
177
+
178
+ always@(posedge m00.axi_aclk)begin
179
+ if(~m00.axi_aresetn) waddr <= {NSIZE{1'b0}};
180
+ else begin
181
+ if(!wlock_addr)
182
+ waddr <= waddr_t;
183
+ else waddr <= waddr;
184
+ end
185
+ end
186
+
187
+ always@(posedge m00.axi_aclk)begin
188
+ if(~m00.axi_aresetn) raddr <= {NSIZE{1'b0}};
189
+ else begin
190
+ if(!rlock_addr)
191
+ raddr <= raddr_t;
192
+ else raddr <= raddr;
193
+ end
194
+ end
195
+
196
+ always@(posedge m00.axi_aclk)begin
197
+ if(~m00.axi_aresetn) waddr_vld <= 1'b0;
198
+ else begin
199
+ if(wlock_addr)
200
+ waddr_vld <= waddr == curr_waddr;
201
+ else waddr_vld <= 1'b0;
202
+ end
203
+ end
204
+
205
+ always@(posedge m00.axi_aclk)begin
206
+ if(~m00.axi_aresetn) raddr_vld <= 1'b0;
207
+ else begin
208
+ if(rlock_addr)
209
+ raddr_vld <= raddr == curr_raddr;
210
+ else raddr_vld <= 1'b0;
211
+ end
212
+ end
213
+ //---<< ADDR STATUS >>---------------------
214
+ //--->> WRITE LOCK <<----------------------
215
+ data_inf #(.DSIZE(1) ) s00_wlock_inf [NUM-1:0] ();
216
+ data_inf #(.DSIZE(1) ) m00_wlock_inf ();
217
+
218
+ generate
219
+ for(KK=0;KK<NUM;KK++)begin:WLOCK_GEN
220
+ assign s00_wlock_inf[KK].valid = s00[KK].axi_awlock;
221
+ assign s00_wlock_inf[KK].data = s00[KK].axi_awlock;
222
+ // assign s00[KK].axi_awready = s00_wlock_inf[KK].ready;
223
+ end
224
+ endgenerate
225
+
226
+
227
+
228
+ data_pipe_interconnect_M2S_verb #(
229
+ // data_pipe_interconnect_M2S #(
230
+ .DSIZE (1 ),
231
+ .NUM (NUM )
232
+ )wlock_inst(
233
+ /* input */ .clock (m00.axi_aclk ),
234
+ /* input */ .rst_n (m00.axi_aresetn ),
235
+ /* input */ .clk_en (1'b1 ),
236
+ // /* input */ .vld_sw (waddr_vld ),
237
+ // /* input [NSIZE-1:0] */ .sw (waddr ),
238
+ // /* output logic[NSIZE-1:0]*/ .curr_path (curr_waddr ),
239
+ /* input [NSIZE-1:0] */ .addr (waddr ),
240
+ /* data_inf.slaver */ .s00 (s00_wlock_inf ),
241
+ /* data_inf.master */ .m00 (m00_wlock_inf )
242
+ );
243
+
244
+ assign m00.axi_awlock = m00_wlock_inf.data && m00_wlock_inf.valid;
245
+ // assign m00.axi_awvalid = m00_wlock_inf.valid;
246
+ assign m00_wlock_inf.ready = m00.axi_awready || 1'b1;
247
+ //---<< WRITE LOCK >>----------------------
248
+ //--->> AXIL WADDR <<-----------------------
249
+ data_inf #(.DSIZE(m00.ASIZE) ) s00_waddr_inf [NUM-1:0] ();
250
+ data_inf #(.DSIZE(m00.ASIZE) ) m00_waddr_inf ();
251
+
252
+ generate
253
+ for(KK=0;KK<NUM;KK++)begin
254
+ assign s00_waddr_inf[KK].valid = s00[KK].axi_awvalid;
255
+ assign s00_waddr_inf[KK].data = s00[KK].axi_awaddr;
256
+ assign s00[KK].axi_awready = s00_waddr_inf[KK].ready;
257
+ end
258
+ endgenerate
259
+
260
+ localparam sub_ASIZE = m00.ASIZE;
261
+
262
+ data_pipe_interconnect_M2S_verb #(
263
+ // data_pipe_interconnect_M2S #(
264
+ .DSIZE (sub_ASIZE ),
265
+ .NUM (NUM )
266
+ )waddr_inst(
267
+ /* input */ .clock (m00.axi_aclk ),
268
+ /* input */ .rst_n (m00.axi_aresetn ),
269
+ /* input */ .clk_en (1'b1 ),
270
+ // /* input */ .vld_sw (waddr_vld ),
271
+ // /* input [NSIZE-1:0] */ .sw (waddr ),
272
+ // /* output logic[NSIZE-1:0]*/ .curr_path (curr_waddr ),
273
+ /* input [NSIZE-1:0] */ .addr (waddr ),
274
+ /* data_inf.slaver */ .s00 (s00_waddr_inf ),
275
+ /* data_inf.master */ .m00 (m00_waddr_inf )
276
+ );
277
+
278
+ assign m00.axi_awaddr = m00_waddr_inf.data;
279
+ assign m00.axi_awvalid = m00_waddr_inf.valid;
280
+ assign m00_waddr_inf.ready = m00.axi_awready;
281
+ //---<< AXIL WADDR >>-----------------------
282
+ //--->> READ LOCK <<----------------------
283
+ data_inf #(.DSIZE(1) ) s00_rlock_inf [NUM-1:0] ();
284
+ data_inf #(.DSIZE(1) ) m00_rlock_inf ();
285
+
286
+ generate
287
+ for(KK=0;KK<NUM;KK++)begin:RLOCK_GEN
288
+ assign s00_rlock_inf[KK].valid = s00[KK].axi_arlock;
289
+ assign s00_rlock_inf[KK].data = s00[KK].axi_arlock;
290
+ // assign s00[KK].axi_awready = s00_wlock_inf[KK].ready;
291
+ end
292
+ endgenerate
293
+
294
+
295
+
296
+ data_pipe_interconnect_M2S_verb #(
297
+ .DSIZE (1 ),
298
+ .NUM (NUM )
299
+ )rlock_inst(
300
+ /* input */ .clock (m00.axi_aclk ),
301
+ /* input */ .rst_n (m00.axi_aresetn ),
302
+ /* input */ .clk_en (1'b1 ),
303
+ /* input [NSIZE-1:0] */ .addr (raddr ),
304
+ /* data_inf.slaver */ .s00 (s00_rlock_inf ),
305
+ /* data_inf.master */ .m00 (m00_rlock_inf )
306
+ );
307
+
308
+ assign m00.axi_arlock = m00_rlock_inf.data;
309
+ // assign m00.axi_arvalid = m00_rlock_inf.valid;
310
+ assign m00_rlock_inf.ready = m00.axi_arready || 1'b1;
311
+ //---<< READ LOCK >>----------------------
312
+ //--->> AXIL RADDR <<-----------------------
313
+ data_inf #(.DSIZE(m00.ASIZE) ) s00_raddr_inf [NUM-1:0] ();
314
+ data_inf #(.DSIZE(m00.ASIZE) ) m00_raddr_inf ();
315
+
316
+
317
+ generate
318
+ for(KK=0;KK<NUM;KK++)begin
319
+ assign s00_raddr_inf[KK].valid = s00[KK].axi_arvalid;
320
+ assign s00_raddr_inf[KK].data = s00[KK].axi_araddr;
321
+ assign s00[KK].axi_arready = s00_raddr_inf[KK].ready;
322
+ end
323
+ endgenerate
324
+
325
+
326
+ data_pipe_interconnect_M2S_verb #(
327
+ .DSIZE (sub_ASIZE ),
328
+ .NUM (NUM )
329
+ )raddr_inst(
330
+ /* input */ .clock (m00.axi_aclk ),
331
+ /* input */ .rst_n (m00.axi_aresetn ),
332
+ /* input */ .clk_en (1'b1 ),
333
+ // /* input */ .vld_sw (raddr_vld ),
334
+ // /* input [NSIZE-1:0] */ .sw (raddr ),
335
+ // /* output logic[NSIZE-1:0]*/ .curr_path (curr_raddr ),
336
+ /* input [NSIZE-1:0] */ .addr (raddr ),
337
+ /* data_inf.slaver */ .s00 (s00_raddr_inf ),
338
+ /* data_inf.master */ .m00 (m00_raddr_inf )
339
+ );
340
+
341
+ assign m00.axi_araddr = m00_raddr_inf.data;
342
+ assign m00.axi_arvalid = m00_raddr_inf.valid;
343
+ assign m00_raddr_inf.ready = m00.axi_arready;
344
+ //---<< AXIL RADDR >>-----------------------
345
+ //--->> AXIL WDATA <<-----------------------
346
+ data_inf #(.DSIZE(m00.DSIZE) ) s00_wdata_inf [NUM-1:0] ();
347
+ data_inf #(.DSIZE(m00.DSIZE) ) m00_wdata_inf ();
348
+
349
+
350
+ generate
351
+ for(KK=0;KK<NUM;KK++)begin
352
+ assign s00_wdata_inf[KK].valid = s00[KK].axi_wvalid;
353
+ assign s00_wdata_inf[KK].data = s00[KK].axi_wdata;
354
+ assign s00[KK].axi_wready = s00_wdata_inf[KK].ready;
355
+ end
356
+ endgenerate
357
+
358
+
359
+ data_pipe_interconnect_M2S_verb #(
360
+ .DSIZE (m00.DSIZE ),
361
+ .NUM (NUM )
362
+ )wdata_inst(
363
+ /* input */ .clock (m00.axi_aclk ),
364
+ /* input */ .rst_n (m00.axi_aresetn ),
365
+ /* input */ .clk_en (1'b1 ),
366
+ // /* input */ .vld_sw (waddr_vld ),
367
+ // /* input [NSIZE-1:0] */ .sw (waddr ),
368
+ // /* output logic[NSIZE-1:0]*/ .curr_path ( ),
369
+ /* input [NSIZE-1:0] */ .addr (waddr ),
370
+ /* data_inf.slaver */ .s00 (s00_wdata_inf ),
371
+ /* data_inf.master */ .m00 (m00_wdata_inf )
372
+ );
373
+
374
+ assign m00.axi_wdata = m00_wdata_inf.data;
375
+ assign m00.axi_wvalid = m00_wdata_inf.valid;
376
+ assign m00_wdata_inf.ready = m00.axi_wready;
377
+ //---<< AXIL WDATA >>-----------------------
378
+ //--->> AXIL RDATA <<-----------------------
379
+ data_inf #(.DSIZE(m00.DSIZE) ) s00_rdata_inf ();
380
+ data_inf #(.DSIZE(m00.DSIZE) ) m00_rdata_inf [NUM-1:0] ();
381
+
382
+ assign s00_rdata_inf.valid = m00.axi_rvalid;
383
+ assign s00_rdata_inf.data = m00.axi_rdata;
384
+ assign m00.axi_rready = s00_rdata_inf.ready;
385
+
386
+
387
+ data_pipe_interconnect_S2M_verb #(
388
+ .NUM (NUM )
389
+ )rdata_inst(
390
+ /* input */ .clock (m00.axi_aclk ),
391
+ /* input */ .rst_n (m00.axi_aresetn ),
392
+ /* input */ .clk_en (1'b1 ),
393
+ /* input [NSIZE-1:0] */ .addr (raddr ), // sync to s00.valid
394
+ // output logic[2:0] curr_path,
395
+ /* data_inf.master */ .m00 (m00_rdata_inf ), //[NUM-1:0],
396
+ /* data_inf.slaver */ .s00 (s00_rdata_inf )
397
+ );
398
+
399
+ generate
400
+ for(KK=0;KK<NUM;KK++)begin
401
+ assign s00[KK].axi_rdata = m00_rdata_inf[KK].data;
402
+ assign s00[KK].axi_rvalid = m00_rdata_inf[KK].valid;
403
+ assign m00_rdata_inf[KK].ready = s00[KK].axi_rready;
404
+ end
405
+ endgenerate
406
+ //---<< AXIL RDATA >>-----------------------
407
+ //--->> AXIL BDATA <<-----------------------
408
+ data_inf #(.DSIZE(2) ) s00_bdata_inf ();
409
+ data_inf #(.DSIZE(2) ) m00_bdata_inf [NUM-1:0] ();
410
+
411
+ assign s00_bdata_inf.valid = m00.axi_bvalid;
412
+ assign s00_bdata_inf.data = m00.axi_bresp;
413
+ assign m00.axi_bready = s00_bdata_inf.ready;
414
+
415
+
416
+ data_pipe_interconnect_S2M_verb #(
417
+ .NUM (NUM )
418
+ )bdata_inst(
419
+ /* input */ .clock (m00.axi_aclk ),
420
+ /* input */ .rst_n (m00.axi_aresetn ),
421
+ /* input */ .clk_en (1'b1 ),
422
+ /* input [NSIZE-1:0] */ .addr (waddr ), // sync to s00.valid
423
+ // output logic[2:0] curr_path,
424
+ /* data_inf.master */ .m00 (m00_bdata_inf ), //[NUM-1:0],
425
+ /* data_inf.slaver */ .s00 (s00_bdata_inf )
426
+ );
427
+
428
+ generate
429
+ for(KK=0;KK<NUM;KK++)begin
430
+ assign s00[KK].axi_bresp = m00_bdata_inf[KK].data;
431
+ assign s00[KK].axi_bvalid = m00_bdata_inf[KK].valid;
432
+ assign m00_bdata_inf[KK].ready = s00[KK].axi_bready;
433
+ end
434
+ endgenerate
435
+ //---<< AXIL BDATA >>-----------------------
436
+
437
+ endmodule
data/lib/axi/AXI_Lite/axi_lite_interconnect_S2M.sv ADDED
@@ -0,0 +1,359 @@
1
+ /**********************************************
2
+ _______________________________________
3
+ ___________ Cook Darwin __________
4
+ _______________________________________
5
+ descript:
6
+ author : Cook.Darwin
7
+ Version: VERA.0.0
8
+ creaded: 2016/12/27
9
+ madified:
10
+ ***********************************************/
11
+ `timescale 1ns/1ps
12
+ module axi_lite_interconnect_S2M #(
13
+ parameter NUM = 4
14
+ )(
15
+ axi_lite_inf.slaver s00,
16
+ axi_lite_inf.master m00 [NUM-1:0]
17
+ );
18
+ localparam NSIZE = $clog2(NUM);
19
+ //--->> STREAM CLOCK AND RESET <<-------------------
20
+ wire clock,rst_n;
21
+ assign clock = s00.axi_aclk;
22
+ assign rst_n = s00.axi_aresetn;
23
+ //---<< STREAM CLOCK AND RESET >>-------------------
24
+
25
+ import SystemPkg::*;
26
+
27
+ initial begin
28
+ assert(s00.ASIZE == (m00[0].ASIZE+NSIZE) )
29
+ else begin
30
+ $error("Lite S2M ASIZE ERROR!!!");
31
+ $stop;
32
+ end
33
+ end
34
+ //--->> WR CMD CHANNEL <<--------------------
35
+ // logic [3:0] aw_from_down_ready;
36
+ // logic [3:0] aw_to_down_vld;
37
+ // logic [ASIZE-1:0] awaddr [3:0];
38
+ //
39
+ // assign m00.axi_awvalid = aw_to_down_vld[0];
40
+ // assign m00.axi_awaddr = awaddr[0];
41
+ //
42
+ // assign m01.axi_awvalid = aw_to_down_vld[1];
43
+ // assign m01.axi_awaddr = awaddr[1];
44
+ //
45
+ // assign m02.axi_awvalid = aw_to_down_vld[2];
46
+ // assign m02.axi_awaddr = awaddr[2];
47
+ //
48
+ // assign m03.axi_awvalid = aw_to_down_vld[3];
49
+ // assign m03.axi_awaddr = awaddr[3];
50
+
51
+ // assign aw_from_down_ready[0] = m00.axi_awready;
52
+ // assign aw_from_down_ready[1] = m01.axi_awready;
53
+ // assign aw_from_down_ready[2] = m02.axi_awready;
54
+ // assign aw_from_down_ready[3] = m03.axi_awready;
55
+
56
+
57
+ genvar KK;
58
+ //--->> IMPORT EXPORT GET ADDR FUNCTION <<------------
59
+ // generate
60
+ // for(KK=0;KK<NUM;KK++)begin
61
+ // Mlite_connect_addr #(NUM) Mlite_connect_addr_inst (s00,m00);
62
+ // end
63
+ // endgenerate
64
+ //---<< IMPORT EXPORT GET ADDR FUNCTION >>------------
65
+ // generate
66
+ // for(KK=0;KK<4;KK++)begin:WR_CMD_BLOCK
67
+ // data_connect_pipe #(
68
+ // .DSIZE (ASIZE)
69
+ // )wr_cmd_connect_pipe_inst(
70
+ // /* input */ .clock (clock ),
71
+ // /* input */ .rst_n (rst_n ),
72
+ // /* input */ .clk_en (1'b1 ),
73
+ // /* input */ .from_up_vld (s00.axi_awvalid && s00.axi_awaddr[ASIZE+2-1-:2]==KK ),
74
+ // /* input [DSIZE-1:0] */ .from_up_data (s00.axi_awaddr[ASIZE-1:0] ),
75
+ // /* output */ .to_up_ready (s00.axi_awready ),
76
+ // /* input */ .from_down_ready (aw_from_down_ready[KK] ),
77
+ // /* output */ .to_down_vld (aw_to_down_vld[KK] ),
78
+ // /* output[DSIZE-1:0] */ .to_down_data (awaddr[KK] )
79
+ // );
80
+ // end
81
+ // endgenerate
82
+
83
+ data_inf #(.DSIZE(s00.ASIZE-NSIZE) ) m_wcmd_inf [NUM-1:0] ();
84
+ data_inf #(.DSIZE(s00.ASIZE-NSIZE) ) s_wcmd_inf ();
85
+
86
+ generate
87
+ for(KK=0;KK<NUM;KK++)begin
88
+ assign m00[KK].axi_awvalid = m_wcmd_inf[KK].valid;
89
+ assign m00[KK].axi_awaddr = m_wcmd_inf[KK].data;
90
+ assign m_wcmd_inf[KK].ready = m00[KK].axi_awready;
91
+ end
92
+ endgenerate
93
+
94
+ assign s_wcmd_inf.valid = s00.axi_awvalid;
95
+ assign s_wcmd_inf.data = s00.axi_awaddr;
96
+ assign s00.axi_awready = s_wcmd_inf.ready;
97
+
98
+ data_pipe_interconnect_S2M_verb #(
99
+ .DSIZE (s00.ASIZE-NSIZE ),
100
+ .NUM (NUM )
101
+ )wr_cmd_pipe_interconnect_S2M_inst(
102
+ /* input */ .clock (clock ),
103
+ /* input */ .rst_n (rst_n ),
104
+ /* input */ .clk_en (1'b1 ),
105
+ /* input [2:0] */ .addr (s00.axi_awaddr[s00.ASIZE-1-:NSIZE] ), // sync to s00.valid
106
+ /* data_inf.master */ .m00 (m_wcmd_inf[NUM-1:0] ),//[NUM-1:0]
107
+ /* data_inf.slaver */ .s00 (s_wcmd_inf )
108
+ );
109
+ //---<< WR CMD CHANNEL >>--------------------
110
+ //--->> WR LOCK <<---------------------------
111
+ data_inf #(.DSIZE(1) ) m_wlock_inf [NUM-1:0] ();
112
+ data_inf #(.DSIZE(1) ) s_wlock_inf ();
113
+
114
+ generate
115
+ for(KK=0;KK<NUM;KK++)begin:WLOCK_GEN
116
+ // assign m00[KK].axi_awvalid = m_wlock_inf[KK].valid;
117
+ assign m00[KK].axi_awlock = m_wlock_inf[KK].data && m_wlock_inf[KK].valid;
118
+ assign m_wlock_inf[KK].ready = m00[KK].axi_awready || 1'b1;
119
+ end
120
+ endgenerate
121
+
122
+ assign s_wlock_inf.valid = s00.axi_awlock;
123
+ assign s_wlock_inf.data = s00.axi_awlock;
124
+ // assign s00.axi_awready = s_wlock_inf.ready;
125
+
126
+ data_pipe_interconnect_S2M_verb #(
127
+ .DSIZE (1 ),
128
+ .NUM (NUM )
129
+ )wr_lock_pipe_interconnect_S2M_inst(
130
+ /* input */ .clock (clock ),
131
+ /* input */ .rst_n (rst_n ),
132
+ /* input */ .clk_en (1'b1 ),
133
+ /* input [2:0] */ .addr (s00.axi_awaddr[s00.ASIZE-1-:NSIZE] ), // sync to s00.valid
134
+ /* data_inf.master */ .m00 (m_wlock_inf[NUM-1:0] ),//[NUM-1:0]
135
+ /* data_inf.slaver */ .s00 (s_wlock_inf )
136
+ );
137
+ //---<< WR LOCK >>---------------------------
138
+ //--->> RD CMD CHANNEL <<--------------------
139
+
140
+ data_inf #(.DSIZE(s00.ASIZE-NSIZE) ) m_rcmd_inf [NUM-1:0] ();
141
+ data_inf #(.DSIZE(s00.ASIZE-NSIZE) ) s_rcmd_inf ();
142
+
143
+ generate
144
+ for(KK=0;KK<NUM;KK++)begin
145
+ assign m00[KK].axi_arvalid = m_rcmd_inf[KK].valid;
146
+ assign m00[KK].axi_araddr = m_rcmd_inf[KK].data;
147
+ assign m_rcmd_inf[KK].ready = m00[KK].axi_arready;
148
+ end
149
+ endgenerate
150
+
151
+ assign s_rcmd_inf.valid = s00.axi_arvalid;
152
+ assign s_rcmd_inf.data = s00.axi_araddr;
153
+ assign s00.axi_arready = s_rcmd_inf.ready;
154
+
155
+
156
+ data_pipe_interconnect_S2M_verb #(
157
+ .DSIZE (s00.ASIZE-NSIZE ),
158
+ .NUM (NUM )
159
+ )rd_cmd_pipe_interconnect_S2M_inst(
160
+ /* input */ .clock (clock ),
161
+ /* input */ .rst_n (rst_n ),
162
+ /* input */ .clk_en (1'b1 ),
163
+ /* input [2:0] */ .addr (s00.axi_araddr[s00.ASIZE-1-:NSIZE] ), // sync to s00.valid
164
+ /* data_inf.master */ .m00 (m_rcmd_inf[NUM-1:0] ),//[NUM-1:0]
165
+ /* data_inf.slaver */ .s00 (s_rcmd_inf )
166
+ );
167
+ //---<< RD CMD CHANNEL >>--------------------
168
+ //--->> RD LOCK <<---------------------------
169
+ data_inf #(.DSIZE(1) ) m_rlock_inf [NUM-1:0] ();
170
+ data_inf #(.DSIZE(1) ) s_rlock_inf ();
171
+
172
+ generate
173
+ for(KK=0;KK<NUM;KK++)begin:RLOCK_GEN
174
+ // assign m00[KK].axi_awvalid = m_wlock_inf[KK].valid;
175
+ assign m00[KK].axi_arlock = m_rlock_inf[KK].data && m_rlock_inf[KK].valid;
176
+ assign m_rlock_inf[KK].ready = m00[KK].axi_arready || 1'b1;
177
+ end
178
+ endgenerate
179
+
180
+ assign s_rlock_inf.valid = s00.axi_arlock;
181
+ assign s_rlock_inf.data = s00.axi_arlock;
182
+ // assign s00.axi_awready = s_wlock_inf.ready;
183
+
184
+ data_pipe_interconnect_S2M_verb #(
185
+ .DSIZE (1 ),
186
+ .NUM (NUM )
187
+ )rd_lock_pipe_interconnect_S2M_inst(
188
+ /* input */ .clock (clock ),
189
+ /* input */ .rst_n (rst_n ),
190
+ /* input */ .clk_en (1'b1 ),
191
+ /* input [2:0] */ .addr (s00.axi_araddr[s00.ASIZE-1-:NSIZE] ), // sync to s00.valid
192
+ /* data_inf.master */ .m00 (m_rlock_inf[NUM-1:0] ),//[NUM-1:0]
193
+ /* data_inf.slaver */ .s00 (s_rlock_inf )
194
+ );
195
+ //---<< RD LOCK >>---------------------------
196
+ //--->> LOCK WR DATA CHANNEL <<--------------
197
+ //---<< LOCK WR DATA CHANNEL >>--------------
198
+ //--->> WR DATA CHANNEL <<-------------------
199
+ data_inf #(.DSIZE(s00.DSIZE) ) m_wdata_inf [NUM-1:0] ();
200
+ data_inf #(.DSIZE(s00.DSIZE) ) s_wdata_inf ();
201
+
202
+ generate
203
+ for(KK=0;KK<NUM;KK++)begin
204
+ assign m00[KK].axi_wvalid = m_wdata_inf[KK].valid;
205
+ assign m00[KK].axi_wdata = m_wdata_inf[KK].data;
206
+ assign m_wdata_inf[KK].ready = m00[KK].axi_wready;
207
+ end
208
+ endgenerate
209
+
210
+ assign s_wdata_inf.valid = s00.axi_wvalid;
211
+ assign s_wdata_inf.data = s00.axi_wdata;
212
+ assign s00.axi_wready = s_wdata_inf.ready;
213
+
214
+ data_pipe_interconnect_S2M_verb #(
215
+ .DSIZE (s00.DSIZE ),
216
+ .NUM (NUM )
217
+ )wr_data_pipe_interconnect_S2M_inst(
218
+ /* input */ .clock (clock ),
219
+ /* input */ .rst_n (rst_n ),
220
+ /* input */ .clk_en (1'b1 ),
221
+ /* input [2:0] */ .addr (s00.axi_awaddr[s00.ASIZE-1-:NSIZE] ), // sync to s00.valid
222
+ /* data_inf.master */ .m00 (m_wdata_inf[NUM-1:0] ),//[NUM-1:0]
223
+ /* data_inf.slaver */ .s00 (s_wdata_inf )
224
+ );
225
+ //---<< WR DATA CHANNEL >>-------------------
226
+ //--->> RD DATA CHANNEL <<-------------------
227
+ logic [NSIZE-1:0] sw_path;
228
+ logic sw_vld;
229
+
230
+ always@(posedge clock,negedge rst_n)
231
+ if(~rst_n) sw_path <= {NSIZE{1'b0}};
232
+ else begin
233
+ if(s00.axi_arvalid && s00.axi_arready)
234
+ sw_path <= s00.axi_araddr[s00.ASIZE-1-:NSIZE];
235
+ else sw_path <= sw_path;
236
+ end
237
+
238
+ always@(posedge clock,negedge rst_n)
239
+ if(~rst_n) sw_vld <= 1'd0;
240
+ else begin
241
+ if(s00.axi_arvalid && s00.axi_arready)
242
+ sw_vld <= 1'b1;
243
+ else if(s00.axi_rvalid && s00.axi_rready)
244
+ sw_vld <= 1'b0;
245
+ else sw_vld <= sw_vld;
246
+ end
247
+
248
+ data_inf #(.DSIZE(s00.DSIZE) ) s00_rdata_inf [NUM-1:0]();
249
+ data_inf #(.DSIZE(s00.DSIZE) ) m00_rdata_inf ();
250
+
251
+ generate
252
+ for(KK=0;KK<NUM;KK++)begin
253
+ assign s00_rdata_inf[KK].data = m00[KK].axi_rdata;
254
+ assign s00_rdata_inf[KK].valid = m00[KK].axi_rvalid;
255
+ assign m00[KK].axi_rready = s00_rdata_inf[KK].ready ;
256
+ end
257
+ endgenerate
258
+
259
+ assign s00.axi_rdata = m00_rdata_inf.data;
260
+ assign s00.axi_rvalid = m00_rdata_inf.valid;
261
+ assign m00_rdata_inf.ready = s00.axi_rready;
262
+
263
+ data_pipe_interconnect_M2S #(
264
+ // .DSIZE (s00.DSIZE ),
265
+ .NUM (NUM )
266
+ )rd_data_pipe_interconnect_M2S(
267
+ /* input */ .clock (clock ),
268
+ /* input */ .rst_n (rst_n ),
269
+ /* input */ .clk_en (1'b1 ),
270
+ /* input */ .vld_sw (sw_vld ),
271
+ /* input [2:0] */ .sw (sw_path ),
272
+ /* output logic[2:0] */ .curr_path (),
273
+
274
+ /* data_inf.slaver */ .s00/* [NUM-1:0],*/(s00_rdata_inf[NUM-1:0] ),
275
+ /* data_inf.master */ .m00 (m00_rdata_inf )
276
+ );
277
+
278
+ //---<< RD DATA CHANNEL >>-------------------
279
+ //--->> RESP DATA CHANNEL <<-------------------
280
+ //--->> LOCK <<------------
281
+ logic wstatus;
282
+ logic awlock_raising;
283
+ logic awlock_falling;
284
+
285
+ always@(posedge clock,negedge rst_n)
286
+ if(~rst_n) wstatus <= 1'b0;
287
+ else begin
288
+ if(s00.axi_awvalid && s00.axi_awready)
289
+ wstatus <= 1'b1;
290
+ else if(s00.axi_bvalid && s00.axi_bready)
291
+ wstatus <= 1'b0;
292
+ else wstatus <= wstatus;
293
+ end
294
+
295
+ edge_generator aw_edge_generator_inst(
296
+ /* input */ .clk (s00.axi_aclk ),
297
+ /* input */ .rst_n (s00.axi_aresetn ),
298
+ /* input */ .in (s00.axi_awlock ),
299
+ /* output */ .raising (awlock_raising ),
300
+ /* output */ .falling (awlock_falling )
301
+ );
302
+
303
+ //---<< LOCK >>------------
304
+ logic [NSIZE-1:0] bsw_path;
305
+ logic bsw_vld;
306
+
307
+ always@(posedge clock,negedge rst_n)
308
+ if(~rst_n) bsw_path <= {NSIZE{1'd0}};
309
+ else begin
310
+ if(s00.axi_awvalid && s00.axi_awready)
311
+ bsw_path <= {1'b0,s00.axi_awaddr[s00.ASIZE-1-:NSIZE]};
312
+ else bsw_path <= bsw_path;
313
+ end
314
+
315
+ always@(posedge clock,negedge rst_n)
316
+ if(~rst_n) bsw_vld <= 1'd0;
317
+ else begin
318
+ if(s00.axi_awvalid && s00.axi_awready)
319
+ bsw_vld <= 1'b1;
320
+ else if(s00.axi_bvalid && s00.axi_bready && !s00.axi_awlock)
321
+ bsw_vld <= 1'b0;
322
+ else if(awlock_falling && !wstatus)
323
+ bsw_vld <= 1'b0;
324
+ else bsw_vld <= bsw_vld;
325
+ end
326
+
327
+ data_inf #(.DSIZE(2) ) s00_bdata_inf [NUM-1:0]();
328
+ data_inf #(.DSIZE(2) ) m00_bdata_inf ();
329
+
330
+ generate
331
+ for(KK=0;KK<NUM;KK++)begin
332
+ assign s00_bdata_inf[KK].data = m00[KK].axi_bresp;
333
+ assign s00_bdata_inf[KK].valid = m00[KK].axi_bvalid;
334
+ assign m00[KK].axi_bready = s00_bdata_inf[KK].ready ;
335
+ end
336
+ endgenerate
337
+
338
+ assign s00.axi_bresp = m00_bdata_inf.data;
339
+ assign s00.axi_bvalid = m00_bdata_inf.valid;
340
+ assign m00_bdata_inf.ready = s00.axi_bready;
341
+
342
+ data_pipe_interconnect_M2S #(
343
+ .NUM (NUM )
344
+ // .DSIZE (2 )
345
+ )resp_data_pipe_interconnect_inst(
346
+ /* input */ .clock (clock ),
347
+ /* input */ .rst_n (rst_n ),
348
+ /* input */ .clk_en (1'b1 ),
349
+ /* input */ .vld_sw (bsw_vld ),
350
+ /* input [2:0] */ .sw (bsw_path ),
351
+ /* output logic[2:0] */ .curr_path (),
352
+
353
+ /* data_inf.slaver */ .s00 (s00_bdata_inf[NUM-1:0] ),
354
+ /* data_inf.master */ .m00 (m00_bdata_inf )
355
+ );
356
+
357
+ //---<< RD DATA CHANNEL >>-------------------
358
+
359
+ endmodule