axi_tdl 0.0.2
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- checksums.yaml +7 -0
- data/.gitignore +8 -0
- data/CODE_OF_CONDUCT.md +74 -0
- data/Gemfile +6 -0
- data/Gemfile.lock +43 -0
- data/LICENSE +504 -0
- data/README.md +311 -0
- data/Rakefile +18 -0
- data/axi_tdl.gemspec +43 -0
- data/bin/console +14 -0
- data/bin/setup +8 -0
- data/lib/.rspec +1 -0
- data/lib/axi/AXI4/axi4_combin_wr_rd_batch.sv +59 -0
- data/lib/axi/AXI4/axi4_direct.sv +137 -0
- data/lib/axi/AXI4/axi4_direct_A1.sv +229 -0
- data/lib/axi/AXI4/axi4_direct_B1.sv +74 -0
- data/lib/axi/AXI4/axi4_direct_verb.sv +79 -0
- data/lib/axi/AXI4/axi4_direct_verc.sv +146 -0
- data/lib/axi/AXI4/axi4_dpram_cache.rb +106 -0
- data/lib/axi/AXI4/axi4_dpram_cache.sv +112 -0
- data/lib/axi/AXI4/axi4_long_to_axi4_wide.sv +85 -0
- data/lib/axi/AXI4/axi4_long_to_axi4_wide_A1.sv +96 -0
- data/lib/axi/AXI4/axi4_long_to_axi4_wide_track.sv +118 -0
- data/lib/axi/AXI4/axi4_long_to_axi4_wide_verb.sv +131 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_pipe.sv +44 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_pipe_verb.sv +45 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_rd_pipe.sv +111 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_rd_pipe_verb.sv +113 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_wr_pipe.sv +142 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_wr_pipe_verb.sv +146 -0
- data/lib/axi/AXI4/axi4_rd_auxiliary_batch_gen.sv +134 -0
- data/lib/axi/AXI4/axi4_rd_auxiliary_gen.sv +89 -0
- data/lib/axi/AXI4/axi4_rd_auxiliary_gen_A1.sv +109 -0
- data/lib/axi/AXI4/axi4_rd_burst_track.sv +164 -0
- data/lib/axi/AXI4/axi4_wr_aux_bind_data.sv +121 -0
- data/lib/axi/AXI4/axi4_wr_auxiliary_batch_gen.sv +140 -0
- data/lib/axi/AXI4/axi4_wr_auxiliary_gen.sv +102 -0
- data/lib/axi/AXI4/axi4_wr_auxiliary_gen_without_resp.sv +91 -0
- data/lib/axi/AXI4/axi4_wr_burst_track.sv +146 -0
- data/lib/axi/AXI4/axi_stream_add_addr_len.sv +50 -0
- data/lib/axi/AXI4/axi_stream_to_axi4_wr.sv +61 -0
- data/lib/axi/AXI4/axi_stream_to_axi4_wr_verb.sv.bak +123 -0
- data/lib/axi/AXI4/axis_to_axi4_wr.rb +149 -0
- data/lib/axi/AXI4/axis_to_axi4_wr.sv +141 -0
- data/lib/axi/AXI4/full_axi4_to_axis.sv +188 -0
- data/lib/axi/AXI4/full_axi4_to_axis_partition_wr_rd.sv +208 -0
- data/lib/axi/AXI4/id_record.sv +55 -0
- data/lib/axi/AXI4/idata_pool_axi4.sv +110 -0
- data/lib/axi/AXI4/interconnect/AXI4_interconnect_M2S.sv +291 -0
- data/lib/axi/AXI4/interconnect/axi4_mix_interconnect_M2S.sv +72 -0
- data/lib/axi/AXI4/interconnect/axi4_rd_interconnect_M2S.sv +148 -0
- data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S.sv +255 -0
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- data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S_A2.sv +281 -0
- data/lib/axi/AXI4/interconnect/axi4_wr_interconnect_M2S.sv +235 -0
- data/lib/axi/AXI4/interconnect/axi4_wr_interconnect_M2S_A1.sv +283 -0
- data/lib/axi/AXI4/interconnect/axi4_wr_mix_interconnect_M2S.sv +32 -0
- data/lib/axi/AXI4/long_axi4_to_wide_axi4.sv.bak +251 -0
- data/lib/axi/AXI4/odata_pool_axi4.sv +134 -0
- data/lib/axi/AXI4/odata_pool_axi4_A1.sv +165 -0
- data/lib/axi/AXI4/odata_pool_axi4_A2.sv +159 -0
- data/lib/axi/AXI4/odata_pool_axi4_A3.sv +183 -0
- data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo.sv +61 -0
- data/lib/axi/AXI4/packet_fifo/axi4_rd_packet_fifo.sv +282 -0
- data/lib/axi/AXI4/packet_fifo/axi4_wr_packet_fifo.sv +181 -0
- data/lib/axi/AXI4/packet_merge/axi4_merge.sv +60 -0
- data/lib/axi/AXI4/packet_merge/axi4_merge_rd.sv +279 -0
- data/lib/axi/AXI4/packet_merge/axi4_merge_wr.sv +267 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition.sv +36 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_OD.sv +66 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd.sv +211 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_OD.sv +322 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.rb +80 -0
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- data/lib/axi/AXI4/packet_partition/data_inf_partition.rb +293 -0
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- data/lib/axi/AXI4/width_convert/axi4_data_combin_aflag_pipe.sv +239 -0
- data/lib/axi/AXI4/width_convert/axi4_data_combin_aflag_pipe_A1.sv +204 -0
- data/lib/axi/AXI4/width_convert/axi4_data_convert.sv +312 -0
- data/lib/axi/AXI4/width_convert/axi4_data_convert_A1.sv +217 -0
- data/lib/axi/AXI4/width_convert/data_combin.sv +366 -0
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- data/lib/axi/AXI4/width_convert/data_destruct.sv +304 -0
- data/lib/axi/AXI4/width_convert/feed_check.sv +94 -0
- data/lib/axi/AXI4/width_convert/len_convert.sv.bak +61 -0
- data/lib/axi/AXI4/width_convert/odd_width_convert.sv +229 -0
- data/lib/axi/AXI4/width_convert/odd_width_convert_verb.sv +105 -0
- data/lib/axi/AXI4/width_convert/simple_data_pipe.sv +40 -0
- data/lib/axi/AXI4/width_convert/simple_data_pipe_slaver.sv +33 -0
- data/lib/axi/AXI4/width_convert/width_combin.sv +113 -0
- data/lib/axi/AXI4/width_convert/width_convert.sv +87 -0
- data/lib/axi/AXI4/width_convert/width_convert_verb.sv +249 -0
- data/lib/axi/AXI4/width_convert/width_destruct.sv +206 -0
- data/lib/axi/AXI4/width_convert/width_destruct_A1.sv +251 -0
- data/lib/axi/AXI_BFM/AXI_BFM_PKG.sv +1039 -0
- data/lib/axi/AXI_BFM/Data_C_BFM_PKG.sv +97 -0
- data/lib/axi/AXI_BFM/axi4_error_chk.sv +298 -0
- data/lib/axi/AXI_BFM/axi4_illegal_bfm_pkg.sv +607 -0
- data/lib/axi/AXI_BFM/axi_lite_master.sv +102 -0
- data/lib/axi/AXI_BFM/axi_lite_tb.sv +23 -0
- data/lib/axi/AXI_BFM/axi_master.sv +185 -0
- data/lib/axi/AXI_BFM/axi_mirror.sv +266 -0
- data/lib/axi/AXI_BFM/axi_mm_tb.sv +134 -0
- data/lib/axi/AXI_BFM/axi_slaver.sv.bak +340 -0
- data/lib/axi/AXI_BFM/axistreambfm.sv +117 -0
- data/lib/axi/AXI_Lite/axi4_to_lite.sv +36 -0
- data/lib/axi/AXI_Lite/axi_lite_configure.sv +356 -0
- data/lib/axi/AXI_Lite/axi_lite_configure_inf2.sv +365 -0
- data/lib/axi/AXI_Lite/axi_lite_configure_verb.sv.bck +370 -0
- data/lib/axi/AXI_Lite/axi_lite_interconnect_M2S.sv +437 -0
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- data/lib/axi/AXI_Lite/axi_lite_slaver_empty.sv +27 -0
- data/lib/axi/AXI_Lite/axil_direct.sv +52 -0
- data/lib/axi/AXI_Lite/common_configure_reg_interface/common_configure_reg_interface.sv +230 -0
- data/lib/axi/AXI_Lite/common_configure_reg_interface/common_configure_reg_interface.sv.bak +109 -0
- data/lib/axi/AXI_Lite/common_configure_reg_interface/jtag_to_axilite_wrapper.sv +56 -0
- data/lib/axi/AXI_Lite/gen_axi_lite_ctrl.sv +515 -0
- data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_C1.sv +369 -0
- data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_verb.sv +365 -0
- data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_verc.sv +401 -0
- data/lib/axi/AXI_Lite/wr_lite_to_axis.sv +141 -0
- data/lib/axi/AXI_Lite/wr_lite_to_axis.sv.bak +141 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S.sv +76 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_A1.sv +77 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_A2.sv +71 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_bind_tuser.sv +72 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_noaddr.sv +151 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_with_addr.sv +87 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_S2M.sv +65 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_auto.sv +50 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_with_info.sv +64 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_with_keep.sv.bak +64 -0
- data/lib/axi/AXI_stream/axi_stream_packet_fifo_with_info.sv.bak +49 -0
- data/lib/axi/AXI_stream/axi_stream_partition.sv +147 -0
- data/lib/axi/AXI_stream/axi_stream_partition_A1.sv +63 -0
- data/lib/axi/AXI_stream/axi_stream_planer.sv +51 -0
- data/lib/axi/AXI_stream/axi_stream_split_channel.rb +56 -0
- data/lib/axi/AXI_stream/axi_stream_split_channel.sv +149 -0
- data/lib/axi/AXI_stream/axi_streams_combin.sv +151 -0
- data/lib/axi/AXI_stream/axi_streams_combin_A1.sv +179 -0
- data/lib/axi/AXI_stream/axi_streams_scaler.sv +171 -0
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- data/lib/axi/AXI_stream/axis_append.sv +79 -0
- data/lib/axi/AXI_stream/axis_append_A1.sv +82 -0
- data/lib/axi/AXI_stream/axis_base_pipe.sv +184 -0
- data/lib/axi/AXI_stream/axis_combin_with_fifo.sv +69 -0
- data/lib/axi/AXI_stream/axis_connect_pipe.sv +86 -0
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- data/lib/axi/AXI_stream/axis_connect_pipe_left_shift.sv +64 -0
- data/lib/axi/AXI_stream/axis_connect_pipe_right_shift.sv +64 -0
- data/lib/axi/AXI_stream/axis_connect_pipe_right_shift_verb.sv +70 -0
- data/lib/axi/AXI_stream/axis_connect_pipe_with_info.sv +93 -0
- data/lib/axi/AXI_stream/axis_direct.sv +55 -0
- data/lib/axi/AXI_stream/axis_direct_A1.sv +81 -0
- data/lib/axi/AXI_stream/axis_filter.sv +38 -0
- data/lib/axi/AXI_stream/axis_full_to_data_c.sv +26 -0
- data/lib/axi/AXI_stream/axis_head_cut.sv +67 -0
- data/lib/axi/AXI_stream/axis_head_cut_verb.sv +60 -0
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- data/lib/axi/AXI_stream/axis_head_cut_verc.sv +245 -0
- data/lib/axi/AXI_stream/axis_inct_s2m_with_flag.sv +84 -0
- data/lib/axi/AXI_stream/axis_insert_copy.rb +59 -0
- data/lib/axi/AXI_stream/axis_insert_copy.sv +66 -0
- data/lib/axi/AXI_stream/axis_intc_M2S_with_addr_inf.sv +114 -0
- data/lib/axi/AXI_stream/axis_intc_S2M_with_addr_inf.sv +85 -0
- data/lib/axi/AXI_stream/axis_interconnect_S2M_pipe.sv +75 -0
- data/lib/axi/AXI_stream/axis_length_cut.sv +64 -0
- data/lib/axi/AXI_stream/axis_length_fill.sv +194 -0
- data/lib/axi/AXI_stream/axis_length_split.sv +86 -0
- data/lib/axi/AXI_stream/axis_length_split_with_addr.sv +127 -0
- data/lib/axi/AXI_stream/axis_length_split_writh_user.sv +87 -0
- data/lib/axi/AXI_stream/axis_link_trigger.sv +81 -0
- data/lib/axi/AXI_stream/axis_master_empty.sv +26 -0
- data/lib/axi/AXI_stream/axis_mirror_to_master.sv +126 -0
- data/lib/axi/AXI_stream/axis_mirrors.sv +60 -0
- data/lib/axi/AXI_stream/axis_orthogonal.sv +66 -0
- data/lib/axi/AXI_stream/axis_ram_buffer.sv +118 -0
- data/lib/axi/AXI_stream/axis_rom_contect.rb +97 -0
- data/lib/axi/AXI_stream/axis_rom_contect.sv +110 -0
- data/lib/axi/AXI_stream/axis_rom_contect_sim.rb +102 -0
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- data/lib/axi/AXI_stream/axis_slaver_empty.sv +22 -0
- data/lib/axi/AXI_stream/axis_slaver_pipe.sv +84 -0
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- data/lib/axi/AXI_stream/axis_split_channel_verb.rb +42 -0
- data/lib/axi/AXI_stream/axis_split_channel_verb.sv +62 -0
- data/lib/axi/AXI_stream/axis_to_axi4_or_lite.rb +127 -0
- data/lib/axi/AXI_stream/axis_to_axi4_or_lite.sv +153 -0
- data/lib/axi/AXI_stream/axis_to_data_inf.sv +34 -0
- data/lib/axi/AXI_stream/axis_to_lite_rd.sv +81 -0
- data/lib/axi/AXI_stream/axis_to_lite_wr.sv +71 -0
- data/lib/axi/AXI_stream/axis_uncompress.sv +147 -0
- data/lib/axi/AXI_stream/axis_uncompress_A1.sv +150 -0
- data/lib/axi/AXI_stream/axis_uncompress_verb.rb +32 -0
- data/lib/axi/AXI_stream/axis_uncompress_verb.sv +54 -0
- data/lib/axi/AXI_stream/axis_valve.sv +29 -0
- data/lib/axi/AXI_stream/axis_valve_with_pipe.sv +76 -0
- data/lib/axi/AXI_stream/axis_vector_master_empty.rb +11 -0
- data/lib/axi/AXI_stream/axis_vector_master_empty.sv +35 -0
- data/lib/axi/AXI_stream/axis_vector_slaver_empty.rb +11 -0
- data/lib/axi/AXI_stream/axis_vector_slaver_empty.sv +35 -0
- data/lib/axi/AXI_stream/check_stream_crc.sv +28 -0
- data/lib/axi/AXI_stream/data_c_to_axis_full.sv +23 -0
- data/lib/axi/AXI_stream/data_to_axis_inf.sv +103 -0
- data/lib/axi/AXI_stream/data_to_axis_inf_A1.sv +28 -0
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- data/lib/axi/AXI_stream/data_width/axis_width_combin_A1.sv +220 -0
- data/lib/axi/AXI_stream/data_width/axis_width_convert.sv +49 -0
- data/lib/axi/AXI_stream/data_width/axis_width_destruct.sv +82 -0
- data/lib/axi/AXI_stream/data_width/axis_width_destruct_A1.sv +86 -0
- data/lib/axi/AXI_stream/ex_status/axis_ex_status.sv +97 -0
- data/lib/axi/AXI_stream/gen_big_field_table.sv +170 -0
- data/lib/axi/AXI_stream/gen_common_frame_table.sv +382 -0
- data/lib/axi/AXI_stream/gen_common_frame_table_bind_tuser.sv +428 -0
- data/lib/axi/AXI_stream/gen_origin_axis.sv +116 -0
- data/lib/axi/AXI_stream/gen_origin_axis_A1.sv +129 -0
- data/lib/axi/AXI_stream/gen_origin_axis_A2.sv +162 -0
- data/lib/axi/AXI_stream/gen_simple_axis.sv +164 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_long_fifo.sv +132 -0
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- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo.sv +125 -0
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- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1E.sv +198 -0
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- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_B1.sv +82 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_mirror.sv +44 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_verb.sv +58 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_long_cache.sv +55 -0
- data/lib/axi/AXI_stream/stream_crc.sv +67 -0
- data/lib/axi/AXI_stream/vcs_axis_comptable.sv +73 -0
- data/lib/axi/LICENSE +504 -0
- data/lib/axi/ReadME.md +6 -0
- data/lib/axi/SIM/tb_axi4_partition_20201105.sv +115 -0
- data/lib/axi/SIM/tb_axis_bfm_0504.sv +61 -0
- data/lib/axi/SIM/tb_axis_partitiom_0929.sv +102 -0
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- data/lib/axi/SIM/tb_axis_to_axi4_0925.sv +107 -0
- data/lib/axi/SIM/tb_data_c_m2s_inf_20200114.sv +222 -0
- data/lib/axi/SIM/tb_data_c_m2s_inf_20201103.sv +245 -0
- data/lib/axi/SIM/tb_data_c_pipe_inf_20180417.sv +114 -0
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- data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_gen_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_gen_without_resp_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_wr_burst_track_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_wr_interconnect_M2S_A1_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_wr_interconnect_M2S_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_wr_mix_interconnect_M2S_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_wr_packet_fifo_sdl.rb +11 -0
- data/lib/tdl/SDL/axi4/axi4_wr_pipe_sdl.rb +9 -0
- data/lib/tdl/SDL/axi4/axi4_wr_pipe_verb_sdl.rb +9 -0
- data/lib/tdl/SDL/axi4/axi_stream_add_addr_len_sdl.rb +11 -0
- data/lib/tdl/SDL/axi4/axi_stream_to_axi4_wr_sdl.rb +9 -0
- data/lib/tdl/SDL/axi4/data_combin_sdl.rb +20 -0
- data/lib/tdl/SDL/axi4/data_destruct_sdl.rb +19 -0
- data/lib/tdl/SDL/axi4/feed_check_sdl.rb +18 -0
- data/lib/tdl/SDL/axi4/full_axi4_to_axis_partition_wr_rd_sdl.rb +11 -0
- data/lib/tdl/SDL/axi4/full_axi4_to_axis_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/id_record_sdl.rb +19 -0
- data/lib/tdl/SDL/axi4/idata_pool_axi4_sdl.rb +18 -0
- data/lib/tdl/SDL/axi4/odata_pool_axi4_A1_sdl.rb +13 -0
- data/lib/tdl/SDL/axi4/odata_pool_axi4_A2_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/odata_pool_axi4_sdl.rb +19 -0
- data/lib/tdl/SDL/axi4/odd_width_convert_sdl.rb +19 -0
- data/lib/tdl/SDL/axi4/odd_width_convert_verb_sdl.rb +19 -0
- data/lib/tdl/SDL/axi4/simple_data_pipe_sdl.rb +16 -0
- data/lib/tdl/SDL/axi4/simple_data_pipe_slaver_sdl.rb +16 -0
- data/lib/tdl/SDL/axi4/vcs_axi4_array_comptable.rb +9 -0
- data/lib/tdl/SDL/axi4/vcs_axi4_array_comptable_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/vcs_axi4_comptable.rb +8 -0
- data/lib/tdl/SDL/axi4/vcs_axi4_comptable_sdl.rb +9 -0
- data/lib/tdl/SDL/axi4/width_combin_sdl.rb +20 -0
- data/lib/tdl/SDL/axi4/width_convert_sdl.rb +20 -0
- data/lib/tdl/SDL/axi4/width_convert_verb_sdl.rb +20 -0
- data/lib/tdl/SDL/axi4/width_destruct_A1_sdl.rb +22 -0
- data/lib/tdl/SDL/axi4/width_destruct_sdl.rb +19 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_35bit_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_36_71bit_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_72_95bit_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_72_95bit_with_keep_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_96_143bit_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_B1_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_mirror_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_verb_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_A1_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_A2_sdl.rb +13 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_bind_tuser_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_noaddr_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_with_addr_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_S2M_auto_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_S2M_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axi_stream_long_cache_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axi_stream_long_fifo_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axi_stream_long_fifo_verb_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_B1E_sdl.rb +16 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_B1_sdl.rb +14 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_verb_sdl.rb +13 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_with_info_sdl.rb +13 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_long_fifo_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axi_stream_partition_A1_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axi_stream_partition_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axi_stream_wide_fifo_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axi_streams_combin_A1_sdl.rb +15 -0
- data/lib/tdl/SDL/axistream/axi_streams_combin_sdl.rb +16 -0
- data/lib/tdl/SDL/axistream/axi_streams_scaler_A1_sdl.rb +14 -0
- data/lib/tdl/SDL/axistream/axi_streams_scaler_sdl.rb +15 -0
- data/lib/tdl/SDL/axistream/axis_append_A1_sdl.rb +18 -0
- data/lib/tdl/SDL/axistream/axis_append_sdl.rb +17 -0
- data/lib/tdl/SDL/axistream/axis_base_pipe_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_combin_with_fifo_sdl.rb +14 -0
- data/lib/tdl/SDL/axistream/axis_connect_pipe_right_shift_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_connect_pipe_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_connect_pipe_with_info_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axis_direct_A1_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axis_direct_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_ex_status_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axis_filter_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_full_to_data_c_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_head_cut_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_inct_s2m_with_flag_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axis_intc_M2S_with_addr_inf_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axis_intc_S2M_with_addr_inf_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axis_interconnect_S2M_pipe_sdl.rb +15 -0
- data/lib/tdl/SDL/axistream/axis_length_cut_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_length_fill_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_length_split_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_length_split_with_addr_sdl.rb +13 -0
- data/lib/tdl/SDL/axistream/axis_length_split_writh_user_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_link_trigger_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axis_master_empty_sdl.rb +8 -0
- data/lib/tdl/SDL/axistream/axis_mirror_to_master_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_mirrors_sdl.rb +14 -0
- data/lib/tdl/SDL/axistream/axis_orthogonal_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_pkt_fifo_filter_keep_A1_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_pkt_fifo_filter_keep_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_ram_buffer_sdl.rb +13 -0
- data/lib/tdl/SDL/axistream/axis_slaver_empty_sdl.rb +8 -0
- data/lib/tdl/SDL/axistream/axis_slaver_pipe_A1_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_slaver_pipe_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_slaver_vector_empty_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_to_data_inf_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_to_lite_rd_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axis_to_lite_wr_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_uncompress_A1_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axis_uncompress_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axis_valve_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_valve_with_pipe_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axis_width_combin_A1_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_width_combin_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_width_convert_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_width_destruct_A1_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_width_destruct_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/check_stream_crc_sdl.rb +8 -0
- data/lib/tdl/SDL/axistream/data_c_to_axis_full_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/data_to_axis_inf_A1_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/data_to_axis_inf_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/gen_big_field_table_sdl.rb +14 -0
- data/lib/tdl/SDL/axistream/gen_common_frame_table_sdl.rb +60 -0
- data/lib/tdl/SDL/axistream/gen_origin_axis_A1_sdl.rb +13 -0
- data/lib/tdl/SDL/axistream/gen_origin_axis_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/gen_simple_axis_sdl.rb +13 -0
- data/lib/tdl/SDL/axistream/parse_big_field_table_A1_sdl.rb +17 -0
- data/lib/tdl/SDL/axistream/parse_big_field_table_A2_sdl.rb +17 -0
- data/lib/tdl/SDL/axistream/parse_big_field_table_sdl.rb +17 -0
- data/lib/tdl/SDL/axistream/stream_crc_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/vcs_axis_comptable.rb +16 -0
- data/lib/tdl/SDL/axistream/vcs_axis_comptable_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_bind_sdl.rb +10 -0
- data/lib/tdl/SDL/data_inf_c/data_c_cache_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_c_direct_mirror_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_c_direct_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_c_intc_M2S_force_robin_sdl.rb +10 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_force_vld_bind_data_sdl.rb +13 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_force_vld_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_A1_sdl.rb +10 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_right_shift_sdl.rb +13 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_C1_sdl.rb +14 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_C1_with_id_sdl.rb +16 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_sdl.rb +13 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_with_addr_sdl.rb +13 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_with_id_sdl.rb +15 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_latency_sdl.rb +10 -0
- data/lib/tdl/SDL/data_inf_c/data_c_scaler_A1_sdl.rb +16 -0
- data/lib/tdl/SDL/data_inf_c/data_c_scaler_sdl.rb +15 -0
- data/lib/tdl/SDL/data_inf_c/data_c_tmp_cache_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_condition_mirror_sdl.rb +13 -0
- data/lib/tdl/SDL/data_inf_c/data_condition_valve_sdl.rb +13 -0
- data/lib/tdl/SDL/data_inf_c/data_connect_pipe_inf_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_connect_pipe_sdl.rb +17 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_A2B_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_B2A_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_M2S_with_addr_and_id_sdl.rb +17 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_M2S_with_id_sdl.rb +15 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_A1_sdl.rb +13 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_sdl.rb +12 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_with_lazy_sdl.rb +15 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_interconnect_M2S_sdl.rb +12 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_pipe_condition_sdl.rb +10 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_A1.rb +12 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_A1_sdl.rb +14 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_sdl.rb +13 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_cross_clk_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_force_addr_with_id_sdl.rb +19 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_prio_sdl.rb +14 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_prio_with_id_sdl.rb +17 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_interconnect_M2S_noaddr_sdl.rb +14 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_interconnect_M2S_with_id_noaddr_sdl.rb +17 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_planer_A1_sdl.rb +15 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_planer_sdl.rb +14 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_ticktock_sdl.rb +18 -0
- data/lib/tdl/SDL/data_inf_c/data_intc_M2S_force_robin_sdl.rb +10 -0
- data/lib/tdl/SDL/data_inf_c/data_mirrors_sdl.rb +14 -0
- data/lib/tdl/SDL/data_inf_c/data_pair_map_A1_sdl.rb +16 -0
- data/lib/tdl/SDL/data_inf_c/data_pair_map_A2_sdl.rb +19 -0
- data/lib/tdl/SDL/data_inf_c/data_pair_map_sdl.rb +14 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_A1_sdl.rb +19 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_sdl.rb +17 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_verb_sdl.rb +16 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_A1_sdl.rb +19 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_sdl.rb +16 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_verb_sdl.rb +15 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_sdl.rb +23 -0
- data/lib/tdl/SDL/data_inf_c/data_streams_combin_A1_sdl.rb +20 -0
- data/lib/tdl/SDL/data_inf_c/data_streams_combin_sdl.rb +20 -0
- data/lib/tdl/SDL/data_inf_c/data_streams_scaler_sdl.rb +19 -0
- data/lib/tdl/SDL/data_inf_c/data_uncompress_sdl.rb +11 -0
- data/lib/tdl/SDL/data_inf_c/data_valve_sdl.rb +10 -0
- data/lib/tdl/SDL/data_inf_c/datainf_c_master_empty_sdl.rb +8 -0
- data/lib/tdl/SDL/data_inf_c/datainf_c_slaver_empty_sdl.rb +8 -0
- data/lib/tdl/SDL/data_inf_c/datainf_master_empty_sdl.rb +8 -0
- data/lib/tdl/SDL/data_inf_c/datainf_slaver_empty_sdl.rb +8 -0
- data/lib/tdl/SDL/data_inf_c/latency_sdl.rb +8 -0
- data/lib/tdl/SDL/data_inf_c/next_prio_sdl.rb +12 -0
- data/lib/tdl/SDL/data_inf_c/part_data_pair_map_sdl.rb +19 -0
- data/lib/tdl/SDL/data_inf_c/trigger_data_inf_c_A1_sdl.rb +11 -0
- data/lib/tdl/SDL/data_inf_c/trigger_data_inf_c_sdl.rb +11 -0
- data/lib/tdl/SDL/data_inf_c/trigger_ready_ctrl_sdl.rb +12 -0
- data/lib/tdl/SDL/data_inf_c/vcs_data_c_comptable.rb +8 -0
- data/lib/tdl/SDL/data_inf_c/vcs_data_c_comptable_sdl.rb +9 -0
- data/lib/tdl/SDL/fifo/common_fifo_sdl.rb +20 -0
- data/lib/tdl/SDL/fifo/common_stack_sdl.rb +14 -0
- data/lib/tdl/SDL/fifo/independent_clock_fifo_a1_sdl.rb +21 -0
- data/lib/tdl/SDL/fifo/independent_clock_fifo_sdl.rb +20 -0
- data/lib/tdl/SDL/fifo/independent_stack_sdl.rb +18 -0
- data/lib/tdl/SDL/path_lib.rb +6 -0
- data/lib/tdl/VideoInf/simple_video_gen.rb +46 -0
- data/lib/tdl/VideoInf/video_from_axi4.rb +108 -0
- data/lib/tdl/VideoInf/video_lib.rb +8 -0
- data/lib/tdl/VideoInf/video_stream_2_axi_stream.rb +67 -0
- data/lib/tdl/VideoInf/video_to_axi4.rb +75 -0
- data/lib/tdl/auto_script/auto_gen_tdl.rb +49 -0
- data/lib/tdl/auto_script/autogensdl.rb +289 -0
- data/lib/tdl/auto_script/autogentdl_a2.rb +452 -0
- data/lib/tdl/auto_script/import_hdl.rb +35 -0
- data/lib/tdl/auto_script/import_sdl.rb +26 -0
- data/lib/tdl/auto_script/test_autogensdl.rb +73 -0
- data/lib/tdl/auto_script/tmp.rb +6 -0
- data/lib/tdl/auto_script/tmp/hdl_test_sdl.rb +12 -0
- data/lib/tdl/axi4/axi4_combin_wr_rd_batch_auto.rb +79 -0
- data/lib/tdl/axi4/axi4_direct.rb +36 -0
- data/lib/tdl/axi4/axi4_direct_A1_auto.rb +137 -0
- data/lib/tdl/axi4/axi4_direct_auto.rb +79 -0
- data/lib/tdl/axi4/axi4_direct_verb_auto.rb +71 -0
- data/lib/tdl/axi4/axi4_interconnect_verb.rb +323 -0
- data/lib/tdl/axi4/axi4_lib.rb +9 -0
- data/lib/tdl/axi4/axi4_long_to_axi4_wide_A1_auto.rb +79 -0
- data/lib/tdl/axi4/axi4_long_to_axi4_wide_auto.rb +71 -0
- data/lib/tdl/axi4/axi4_long_to_axi4_wide_verb_auto.rb +86 -0
- data/lib/tdl/axi4/axi4_packet_fifo_auto.rb +155 -0
- data/lib/tdl/axi4/axi4_pipe_auto.rb +127 -0
- data/lib/tdl/axi4/axi4_pipe_verb_auto.rb +127 -0
- data/lib/tdl/axi4/axi4_rd_auxiliary_gen_auto.rb +71 -0
- data/lib/tdl/axi4/axi4_wr_auxiliary_gen_without_resp_auto.rb +78 -0
- data/lib/tdl/axi4/axis_to_axi4_wr_auto.rb +85 -0
- data/lib/tdl/axi4/bak/__axi4_wr_auxiliary_gen_without_resp.rb +175 -0
- data/lib/tdl/axi4/bak/axi4_combin_wr_rd_batch_auto.rb +153 -0
- data/lib/tdl/axi4/bak/axi4_data_convert.rb +74 -0
- data/lib/tdl/axi4/bak/axi4_direct_auto.rb +153 -0
- data/lib/tdl/axi4/bak/axi4_direct_verb_auto.rb +126 -0
- data/lib/tdl/axi4/bak/axi4_interconnect.rb.bak +91 -0
- data/lib/tdl/axi4/bak/axi4_long_to_axi4_wide_A1_auto.rb +153 -0
- data/lib/tdl/axi4/bak/axi4_long_to_axi4_wide_auto.rb +126 -0
- data/lib/tdl/axi4/bak/axi4_long_to_axi4_wide_verb_auto.rb +179 -0
- data/lib/tdl/axi4/bak/axi4_packet_fifo.rb.bak +75 -0
- data/lib/tdl/axi4/bak/axi4_packet_fifo_auto.rb +259 -0
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- data/lib/tdl/examples/11_test_unit/dve.tcl +64 -0
- data/lib/tdl/examples/11_test_unit/exp_test_unit.rb +58 -0
- data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +35 -0
- data/lib/tdl/examples/11_test_unit/exp_test_unit_constraints.xdc +25 -0
- data/lib/tdl/examples/11_test_unit/modules/sub_md0.rb +23 -0
- data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +41 -0
- data/lib/tdl/examples/11_test_unit/modules/sub_md1.rb +25 -0
- data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv +41 -0
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +28 -0
- data/lib/tdl/examples/11_test_unit/tu0.sv +38 -0
- data/lib/tdl/examples/11_test_unit/tu1.sv +28 -0
- data/lib/tdl/examples/1_define_module/example1.rb +39 -0
- data/lib/tdl/examples/1_define_module/exmple_md.sv +50 -0
- data/lib/tdl/examples/2_hdl_class/always_comb.rb +99 -0
- data/lib/tdl/examples/2_hdl_class/always_ff.rb +143 -0
- data/lib/tdl/examples/2_hdl_class/case.rb +93 -0
- data/lib/tdl/examples/2_hdl_class/foreach.rb +21 -0
- data/lib/tdl/examples/2_hdl_class/function.rb +34 -0
- data/lib/tdl/examples/2_hdl_class/generate.rb +62 -0
- data/lib/tdl/examples/2_hdl_class/module_def.rb +33 -0
- data/lib/tdl/examples/2_hdl_class/module_head_import_package.rb +36 -0
- data/lib/tdl/examples/2_hdl_class/module_instance_test.rb +13 -0
- data/lib/tdl/examples/2_hdl_class/package.rb +29 -0
- data/lib/tdl/examples/2_hdl_class/package2.rb +21 -0
- data/lib/tdl/examples/2_hdl_class/simple_assign.rb +39 -0
- data/lib/tdl/examples/2_hdl_class/state_case.rb +65 -0
- data/lib/tdl/examples/2_hdl_class/struct.rb +25 -0
- data/lib/tdl/examples/2_hdl_class/struct_function.rb +28 -0
- data/lib/tdl/examples/2_hdl_class/test_axi4_M2S.rb +16 -0
- data/lib/tdl/examples/2_hdl_class/test_initial_assert.rb +11 -0
- data/lib/tdl/examples/2_hdl_class/test_inst_sugar.rb +28 -0
- data/lib/tdl/examples/2_hdl_class/test_module_port.rb +47 -0
- data/lib/tdl/examples/2_hdl_class/test_module_var.rb +18 -0
- data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv +108 -0
- data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +35 -0
- data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv +105 -0
- data/lib/tdl/examples/2_hdl_class/tmp/head_pkg_module.sv +42 -0
- data/lib/tdl/examples/2_hdl_class/tmp/init_module.sv +110 -0
- data/lib/tdl/examples/2_hdl_class/tmp/module_instance_test.sv +31 -0
- data/lib/tdl/examples/2_hdl_class/tmp/port_module.sv +99 -0
- data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv +27 -0
- data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv +78 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_axi4_M2S.sv +30 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_foreach.sv +34 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_function.sv +52 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_initial_assert.sv +31 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_inst_sugar.sv +42 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +36 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_port.sv +33 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +35 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +38 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_package2.sv +36 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_struct.sv +38 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_struct_function.sv +44 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +27 -0
- data/lib/tdl/examples/2_hdl_class/tmp/text_generate.sv +54 -0
- data/lib/tdl/examples/2_hdl_class/vcs_string.rb +5 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/hdl_test.sv +13 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/main.rb +26 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/main_md.sv +42 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/sdl_md.sv +30 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/sdl_test.rb +9 -0
- data/lib/tdl/examples/4_generate/example.rb +38 -0
- data/lib/tdl/examples/4_generate/test_generate.sv +59 -0
- data/lib/tdl/examples/5_logic_combin/login_combin.rb +22 -0
- data/lib/tdl/examples/5_logic_combin/test_logic_combin.sv +36 -0
- data/lib/tdl/examples/6_module_with_interface/example.rb +48 -0
- data/lib/tdl/examples/6_module_with_interface/example_interface.sv +40 -0
- data/lib/tdl/examples/6_module_with_interface/inf_collect.rb +54 -0
- data/lib/tdl/examples/6_module_with_interface/inf_collect.sv +63 -0
- data/lib/tdl/examples/7_module_with_package/body_package.rb +3 -0
- data/lib/tdl/examples/7_module_with_package/body_package.sv +25 -0
- data/lib/tdl/examples/7_module_with_package/example_pkg.rb +20 -0
- data/lib/tdl/examples/7_module_with_package/example_pkg.sv +35 -0
- data/lib/tdl/examples/7_module_with_package/head_package.rb +8 -0
- data/lib/tdl/examples/7_module_with_package/head_package.sv +29 -0
- data/lib/tdl/examples/8_top_module/dve.tcl +64 -0
- data/lib/tdl/examples/8_top_module/example.rb +8 -0
- data/lib/tdl/examples/8_top_module/pins.yml +7 -0
- data/lib/tdl/examples/8_top_module/tb_test_top.sv +29 -0
- data/lib/tdl/examples/8_top_module/test_top.sv +28 -0
- data/lib/tdl/examples/8_top_module/test_top_constraints.xdc +37 -0
- data/lib/tdl/examples/9_itegration/A_itgt/a_test_md.sv +29 -0
- data/lib/tdl/examples/9_itegration/A_itgt/a_test_module.rb +6 -0
- data/lib/tdl/examples/9_itegration/A_itgt/itgt_module_a_block.rb +34 -0
- data/lib/tdl/examples/9_itegration/clock_manage/itgt_module_clock_manage.rb +33 -0
- data/lib/tdl/examples/9_itegration/clock_manage/simple_clock.rb +7 -0
- data/lib/tdl/examples/9_itegration/clock_manage/simple_clock.sv +29 -0
- data/lib/tdl/examples/9_itegration/dve.tcl +64 -0
- data/lib/tdl/examples/9_itegration/pins.yml +4 -0
- data/lib/tdl/examples/9_itegration/tb_test_top.sv +29 -0
- data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +29 -0
- data/lib/tdl/examples/9_itegration/test_top.sv +40 -0
- data/lib/tdl/examples/9_itegration/test_top_constraints.xdc +29 -0
- data/lib/tdl/examples/9_itegration/test_tttop.sv +40 -0
- data/lib/tdl/examples/9_itegration/test_tttop_constraints.xdc +29 -0
- data/lib/tdl/examples/9_itegration/top.rb +11 -0
- data/lib/tdl/examples/readme.md +31 -0
- data/lib/tdl/exlib/common_cfg_reg_inf.rb +139 -0
- data/lib/tdl/exlib/constraints.rb +286 -0
- data/lib/tdl/exlib/constraints_verb.rb +304 -0
- data/lib/tdl/exlib/dve_tcl.rb +162 -0
- data/lib/tdl/exlib/element_class_vars.rb +106 -0
- data/lib/tdl/exlib/global_param.rb +108 -0
- data/lib/tdl/exlib/integral_test/bak/integral_test.rb +206 -0
- data/lib/tdl/exlib/integral_test/clock_itest.rb +28 -0
- data/lib/tdl/exlib/integral_test/diff_clock_itest.rb +30 -0
- data/lib/tdl/exlib/integral_test/io_itest.rb +41 -0
- data/lib/tdl/exlib/integral_test/reset_itest.rb +31 -0
- data/lib/tdl/exlib/integral_test/simple_logic_itest.rb +19 -0
- data/lib/tdl/exlib/itegration.rb +307 -0
- data/lib/tdl/exlib/itegration_verb.rb +913 -0
- data/lib/tdl/exlib/parse_argv.rb +43 -0
- data/lib/tdl/exlib/sdlmodule_sim.bak.rb +375 -0
- data/lib/tdl/exlib/test_point.rb +287 -0
- data/lib/tdl/global_scan.rb +134 -0
- data/lib/tdl/rebuild_ele/axi4.rb +141 -0
- data/lib/tdl/rebuild_ele/axi_lite.rb +56 -0
- data/lib/tdl/rebuild_ele/axi_stream.rb +121 -0
- data/lib/tdl/rebuild_ele/cm_ram_inf.sv +105 -0
- data/lib/tdl/rebuild_ele/cm_ram_inf_define.rb +44 -0
- data/lib/tdl/rebuild_ele/data_inf.rb +27 -0
- data/lib/tdl/rebuild_ele/data_inf_c.rb +83 -0
- data/lib/tdl/rebuild_ele/ele_base.rb +822 -0
- data/lib/tdl/rebuild_ele/readme.md +1 -0
- data/lib/tdl/sdlimplement/resource.yml +154 -0
- data/lib/tdl/sdlimplement/sdl_impl_module.rb +391 -0
- data/lib/tdl/sdlimplement/sdl_impl_param.rb +26 -0
- data/lib/tdl/sdlimplement/test.rb +64 -0
- data/lib/tdl/sdlmodule/bak/sdlmodule_varible_ex.rb +120 -0
- data/lib/tdl/sdlmodule/generator_block_module.rb +84 -0
- data/lib/tdl/sdlmodule/sdlmodule.rb +407 -0
- data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb +333 -0
- data/lib/tdl/sdlmodule/sdlmodule_draw.rb +272 -0
- data/lib/tdl/sdlmodule/sdlmodule_head_logo.txt +10 -0
- data/lib/tdl/sdlmodule/sdlmodule_instance.rb +623 -0
- data/lib/tdl/sdlmodule/sdlmodule_port_define.rb +374 -0
- data/lib/tdl/sdlmodule/sdlmodule_varible.rb +160 -0
- data/lib/tdl/sdlmodule/sdlmodule_vcs_comptable.rb +140 -0
- data/lib/tdl/sdlmodule/techbench_module.rb +14 -0
- data/lib/tdl/sdlmodule/test_unit_module.rb +138 -0
- data/lib/tdl/sdlmodule/top_module.rb +543 -0
- data/lib/tdl/tdl.rb +265 -0
- data/lib/tdl/tdlerror/tdlerror.rb +8 -0
- data/lib/tdl/testunit/test_all.rb +4 -0
- data/lib/tdl/testunit/test_array_chain.rb +89 -0
- data/lib/tdl/testunit/test_tmp.rb +47 -0
- metadata +1301 -0
@@ -0,0 +1,333 @@
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"""
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DefArrayChain:
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- DefAxi4_ArrayChain
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"""
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module TdlSpace
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class DefArrayChain
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attr_accessor :chain,:belong_to_module
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def initialize(belong_to_module)
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@chain = []
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@belong_to_module = belong_to_module
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end
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def [](*a)
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if a.empty?
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raise TdlError.new("参数不能为空")
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end
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new_dla = self.class.new(@belong_to_module)
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new_dla.chain = @chain + a
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new_dla
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end
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def -(name)
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# raise TDLError.new("简化定义模式不允许传入 StringBandItegration 类型")
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# end
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end
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def check_name(name)
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check_topmodule_method(name)
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raise TdlError.new("简化定义模式不允许传入 StringBandItegration 类型")
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end
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end
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def to_inp(name)
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check_name(name)
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else
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end
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return yname
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end
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ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
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super
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self - name
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def check_topmodule_method(name)
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if $_implicit_curr_itgt_.slast.respond_to?('top_module') && $_implicit_curr_itgt_.slast.top_module.respond_to?(name)
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raise TdlError.new("TopModule[#{$_implicit_curr_itgt_.slast.top_module.module_name}] 已经定义了方法 [#{name}],Itgt 不能定义新方法#{name},以免发生混淆")
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end
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class DefLogicArrayChain < DefArrayChain
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def -(name)
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dimension = []
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end
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name = to_inp(name)
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belong_to_module.Def.logic(name: name,dsize: @chain.last || 1,dimension: dimension,type: @type || 'logic')
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end
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def wire
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def tri0
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def integer
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def string
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class DefDebugLogicArrayChain < DefArrayChain
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def -(name)
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dimension = []
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end
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name = to_inp(name)
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belong_to_module.Def.debuglogic(name: name,dsize: @chain.last || 1,dimension: dimension,type: @type || 'logic')
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end
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def wire
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end
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end
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class DefGenVar < DefArrayChain
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def -(name)
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if @chain.length > 1
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dimension = @chain[0,@chain.length-1]
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else
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dimension = []
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end
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name = to_inp(name)
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belong_to_module.Def.logic(name: name,dsize: @chain.last || 1,dimension: dimension,type: 'genvar')
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end
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end
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class DefDataInf_ArrayChain < DefArrayChain
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attr_accessor :dsize
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def initialize(belong_to_module: nil,dsize: 8)
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super(belong_to_module)
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@dsize = dsize
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end
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def [](*a)
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if a.empty?
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raise TdlError.new("参数不能为空")
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end
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new_dla = self.class.new(belong_to_module: @belong_to_module,dsize: @dsize)
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new_dla.chain = @chain + a
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new_dla
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end
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def -(name,dsize: nil )
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name = to_inp(name)
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belong_to_module.Def.datainf_c(name: name ,dsize: dsize||@dsize,dimension: @chain)
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end
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end
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class DefDataInf_C_ArrayChain < DefArrayChain
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attr_accessor :dsize,:freqM,:clock,:reset
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def initialize(belong_to_module: nil,dsize: nil,freqM: nil,clock: nil,reset: nil)
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super(belong_to_module)
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@dsize = dsize
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@freqM = freqM
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@clock = clock
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@reset = reset
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end
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def [](*a)
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if a.empty?
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raise TdlError.new("参数不能为空")
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end
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new_dla = self.class.new(belong_to_module: @belong_to_module,clock: @clock,reset:@reset,freqM: @freqM,dsize: @dsize)
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new_dla.chain = @chain + a
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new_dla
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end
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def -(name,clock: nil,reset: nil,freqM: nil,dsize: nil )
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name = to_inp(name)
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belong_to_module.Def.datainf_c(name: name ,clock: clock||@clock,reset: reset||@reset ,dsize: dsize||@dsize ,dimension: @chain,freqM:freqM||@freqM)
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end
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end
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+
|
199
|
+
class DefAxiStream_ArrayChain < DefDataInf_C_ArrayChain
|
200
|
+
def -(name,clock: nil,reset: nil,freqM: nil,dsize: nil )
|
201
|
+
name = to_inp(name)
|
202
|
+
|
203
|
+
belong_to_module.Def.axi_stream(name: name ,clock: clock||@clock,reset: reset||@reset ,dsize: dsize||@dsize ,dimension: @chain,freqM:freqM||@freqM)
|
204
|
+
end
|
205
|
+
end
|
206
|
+
|
207
|
+
class DefAxiLite_ArrayChain < DefArrayChain
|
208
|
+
attr_accessor :dsize,:freqM,:clock,:reset,:asize,:mode
|
209
|
+
def initialize(belong_to_module: nil,clock: nil,reset: nil,dsize: 8,asize: 8,mode: AxiLite::BOTH,freqM: nil)
|
210
|
+
super(belong_to_module)
|
211
|
+
@dsize = dsize
|
212
|
+
@freqM = freqM
|
213
|
+
@clock = clock
|
214
|
+
@reset = reset
|
215
|
+
@asize = asize
|
216
|
+
@mode = mode
|
217
|
+
end
|
218
|
+
|
219
|
+
def [](*a)
|
220
|
+
if a.empty?
|
221
|
+
raise TdlError.new("参数不能为空")
|
222
|
+
end
|
223
|
+
new_dla = self.class.new(belong_to_module: @belong_to_module,clock: @clock,reset:@reset,freqM: @freqM,dsize: @dsize,asize: @asize,mode: @mode)
|
224
|
+
new_dla.chain = @chain + a
|
225
|
+
new_dla
|
226
|
+
end
|
227
|
+
|
228
|
+
def -(name,clock: nil,reset: nil,freqM: nil,dsize: nil,asize: nil,mode: nil)
|
229
|
+
name = to_inp(name)
|
230
|
+
|
231
|
+
belong_to_module.Def.axilite(
|
232
|
+
name: name ,
|
233
|
+
clock: clock||@clock,
|
234
|
+
reset: reset||@reset ,
|
235
|
+
dsize: dsize||@dsize ,
|
236
|
+
# dimension: @chain,
|
237
|
+
asize: asize || @asize,
|
238
|
+
mode: mode || @mode,
|
239
|
+
freqM:freqM||@freqM)
|
240
|
+
end
|
241
|
+
|
242
|
+
end
|
243
|
+
|
244
|
+
class DefAxi4_ArrayChain < DefArrayChain
|
245
|
+
attr_accessor :dsize,:freqM,:clock,:reset,:idsize,:asize,:lsize,:mode,:addr_step
|
246
|
+
def initialize(belong_to_module: nil,clock: nil,reset: nil,dsize: 8,asize: 8,lsize:8,idsize:1,addr_step: 1.0,mode: Axi4::BOTH,freqM: nil)
|
247
|
+
super(belong_to_module)
|
248
|
+
@dsize = dsize
|
249
|
+
@freqM = freqM
|
250
|
+
@clock = clock
|
251
|
+
@reset = reset
|
252
|
+
@asize = asize
|
253
|
+
@mode = mode
|
254
|
+
@lsize = lsize
|
255
|
+
@idsize = idsize
|
256
|
+
@addr_step = addr_step
|
257
|
+
end
|
258
|
+
|
259
|
+
def [](*a)
|
260
|
+
if a.empty?
|
261
|
+
raise TdlError.new("参数不能为空")
|
262
|
+
end
|
263
|
+
new_dla = self.class.new(
|
264
|
+
belong_to_module: @belong_to_module,
|
265
|
+
clock: @clock,
|
266
|
+
reset:@reset,
|
267
|
+
freqM: @freqM,
|
268
|
+
dsize: @dsize,
|
269
|
+
idsize: @idsize,
|
270
|
+
lsize: @lsize,
|
271
|
+
addr_step: @addr_step,
|
272
|
+
asize: @asize,
|
273
|
+
mode: @mode)
|
274
|
+
new_dla.chain = @chain + a
|
275
|
+
new_dla
|
276
|
+
end
|
277
|
+
|
278
|
+
def -(name,clock: nil,reset: nil,freqM: nil,dsize: nil,asize: nil,mode: nil,lsize: nil,idsize: nil,addr_step: nil)
|
279
|
+
name = to_inp(name)
|
280
|
+
|
281
|
+
belong_to_module.Def.axi4(
|
282
|
+
name: name ,
|
283
|
+
clock: clock||@clock,
|
284
|
+
reset: reset||@reset ,
|
285
|
+
dsize: dsize||@dsize ,
|
286
|
+
dimension: @chain,
|
287
|
+
asize: asize || @asize,
|
288
|
+
mode: mode || @mode,
|
289
|
+
lsize: lsize || @lsize,
|
290
|
+
idsize: idsize || @idsize,
|
291
|
+
addr_step: addr_step || @addr_step,
|
292
|
+
freqM:freqM||@freqM)
|
293
|
+
end
|
294
|
+
|
295
|
+
end
|
296
|
+
|
297
|
+
end
|
298
|
+
|
299
|
+
class SdlModule
|
300
|
+
|
301
|
+
def logic
|
302
|
+
TdlSpace::DefLogicArrayChain.new(self)
|
303
|
+
end
|
304
|
+
|
305
|
+
def debugLogic
|
306
|
+
TdlSpace::DefDebugLogicArrayChain.new(self)
|
307
|
+
end
|
308
|
+
|
309
|
+
def genvar
|
310
|
+
TdlSpace::DefGenVar.new(self)
|
311
|
+
end
|
312
|
+
|
313
|
+
# def data_inf_c(dsize: 8,freqM: nil,clock: nil,reset: nil)
|
314
|
+
# TdlSpace::DefDataInf_C_ArrayChain.new(belong_to_module: self,clock: clock,reset: reset,freqM: freqM,dsize: dsize)
|
315
|
+
# end
|
316
|
+
|
317
|
+
# def data_inf(dsize:8)
|
318
|
+
# TdlSpace::DefDataInf_ArrayChain.new(belong_to_module: self,dsize: dsize)
|
319
|
+
# end
|
320
|
+
|
321
|
+
# def axi_stream_inf(dsize: 8,freqM: nil,clock: nil,reset: nil)
|
322
|
+
# TdlSpace::DefAxiStream_ArrayChain.new(belong_to_module: self,clock: clock,reset: reset,freqM: freqM,dsize: dsize)
|
323
|
+
# end
|
324
|
+
|
325
|
+
# def axi_lite_inf(clock: nil,reset: nil,dsize: 8,asize: 8,mode: AxiLite::BOTH,freqM: nil)
|
326
|
+
# TdlSpace::DefAxiLite_ArrayChain.new(belong_to_module: self,clock: clock,reset: reset,freqM: freqM,dsize: dsize,asize: asize,mode: mode)
|
327
|
+
# end
|
328
|
+
|
329
|
+
# def axi_inf(clock: nil,reset: nil,dsize: 8,asize: 8,mode: AxiLite::BOTH,freqM: nil,lsize: 8,idsize:1,addr_step: 1.0)
|
330
|
+
# TdlSpace::DefAxi4_ArrayChain.new(belong_to_module: self,clock: clock,reset: reset,freqM: freqM,dsize: dsize,asize: asize,mode: mode,lsize: lsize,idsize: idsize,addr_step: addr_step)
|
331
|
+
# end
|
332
|
+
|
333
|
+
end
|
@@ -0,0 +1,272 @@
|
|
1
|
+
## read sdlmodule head
|
2
|
+
$__sdlmodule_head_logo__ = File.open(File.join(__dir__,"sdlmodule_head_logo.txt")).read
|
3
|
+
class SdlModule
|
4
|
+
attr_accessor :origin_sv
|
5
|
+
|
6
|
+
def self.gen_sv_module
|
7
|
+
@@allmodule.each do |e|
|
8
|
+
e.gen_sv_module
|
9
|
+
end
|
10
|
+
end
|
11
|
+
|
12
|
+
private
|
13
|
+
|
14
|
+
def pre_inst_stack_call
|
15
|
+
@@ele_array.each do |e|
|
16
|
+
head_str = "#{e.to_s}"
|
17
|
+
method("#{head_str}_pre_inst_stack").call.each do |proc|
|
18
|
+
proc.call
|
19
|
+
end
|
20
|
+
end
|
21
|
+
end
|
22
|
+
|
23
|
+
def post_inst_stack_call
|
24
|
+
str = ''
|
25
|
+
@@ele_array.each do |e|
|
26
|
+
head_str = "#{e.to_s}"
|
27
|
+
method("#{head_str}_post_inst_stack").call.each do |proc|
|
28
|
+
str += proc.call
|
29
|
+
end
|
30
|
+
end
|
31
|
+
str
|
32
|
+
end
|
33
|
+
|
34
|
+
public
|
35
|
+
|
36
|
+
def gen_sv_module
|
37
|
+
# @out_sv_path ||= File.dirname(File.expand_path(__FILE__))
|
38
|
+
return if (@origin_sv || @dont_gen_sv)
|
39
|
+
pre_inst_stack_call
|
40
|
+
@out_sv_path ||= '..\..\tdl\test_sdlmodule'
|
41
|
+
# unless GlobalParam.sim
|
42
|
+
File.open(File.join(@out_sv_path,"#{module_name}.sv"),"w") do |f|
|
43
|
+
f.puts build_module(ex_param:ex_param,ex_port:ex_port,ex_up_code:ex_up_code,ex_down_code:ex_down_code)
|
44
|
+
end
|
45
|
+
# else
|
46
|
+
# Tdl.Puts "+INFO+ It generate SIM top File"
|
47
|
+
# File.open(File.join(out_sv_path,"#{module_name}_sim.sv"),"w") do |f|
|
48
|
+
# f.puts build_module(ex_param:ex_param,ex_port:ex_port,ex_up_code:ex_up_code,ex_down_code:ex_down_code)
|
49
|
+
# end
|
50
|
+
# end
|
51
|
+
end
|
52
|
+
|
53
|
+
def gen_sv_module_text
|
54
|
+
# @out_sv_path ||= File.dirname(File.expand_path(__FILE__))
|
55
|
+
return if (@origin_sv || @dont_gen_sv)
|
56
|
+
pre_inst_stack_call
|
57
|
+
@out_sv_path ||= '..\..\tdl\test_sdlmodule'
|
58
|
+
# unless GlobalParam.sim
|
59
|
+
|
60
|
+
return build_module(ex_param:ex_param,ex_port:ex_port,ex_up_code:ex_up_code,ex_down_code:ex_down_code)
|
61
|
+
|
62
|
+
end
|
63
|
+
|
64
|
+
def build_module(ex_param:"",ex_port:"",ex_up_code:"",ex_down_code:"")
|
65
|
+
# Tdl.Puts pagination(module_name)
|
66
|
+
Tdl.Build_SdlModule_Puts(module_name)
|
67
|
+
|
68
|
+
ex_param = ex_param.to_s unless ex_param
|
69
|
+
ex_port = ex_port.to_s unless ex_port
|
70
|
+
ex_up_code = ex_up_code.to_s unless ex_up_code
|
71
|
+
ex_down_code = ex_down_code.to_s unless ex_down_code
|
72
|
+
|
73
|
+
# gen_auto_method # auto generate class method for interface
|
74
|
+
# draw = Tdl.inst + Tdl.draw
|
75
|
+
|
76
|
+
instance_draw_str = instance_draw # It must run before vars_define_inst,because some signals define when inst
|
77
|
+
vars_exec_inst_str = vars_exec_inst # It must run before vars_define_inst,because some signals define when vars exec
|
78
|
+
|
79
|
+
post_str = post_inst_stack_call()
|
80
|
+
|
81
|
+
unless post_str.strip.empty?
|
82
|
+
post_str = pagination("ROOT REF") + post_str
|
83
|
+
end
|
84
|
+
|
85
|
+
draw = pagination("define") + vars_define_inst + pagination("instance") + instance_draw_str + pagination("expression") + vars_exec_inst_str + post_str
|
86
|
+
|
87
|
+
unless ex_up_code.empty?
|
88
|
+
ex_up_code = "\n//------>> EX CODE <<-------------------\n" + ex_up_code + "//------<< EX CODE >>-------------------\n"
|
89
|
+
end
|
90
|
+
|
91
|
+
unless ex_down_code.empty?
|
92
|
+
ex_down_code = "//------>> EX CODE <<-------------------\n" + ex_down_code + "//------<< EX CODE >>-------------------\n"
|
93
|
+
end
|
94
|
+
|
95
|
+
# str = module_head+"module #{@module_name}" + build_params(ex_param) + build_ports(ex_port) + ex_up_code + gen_lite_str() + draw + ex_down_code + "\nendmodule\n"
|
96
|
+
# unless GlobalParam.sim
|
97
|
+
module_name_str = @module_name
|
98
|
+
# else
|
99
|
+
# module_name_str = @module_name+"_sim"
|
100
|
+
# end
|
101
|
+
unless head_import_packages
|
102
|
+
str = module_head+"module #{module_name_str}" + build_params(ex_param) + build_ports(ex_port) + ex_up_code + draw + ex_down_code + "\nendmodule\n" + add_sub_module_file_paths
|
103
|
+
else
|
104
|
+
head_import_pkgs_str = head_import_packages.map{|e| "import #{e}::*;" }.join('')
|
105
|
+
str = module_head+"module #{module_name_str} #{head_import_pkgs_str}" + build_params(ex_param) + build_ports(ex_port) + ex_up_code + draw + ex_down_code + "\nendmodule\n" + add_sub_module_file_paths
|
106
|
+
end
|
107
|
+
|
108
|
+
create_vivado_tcl if @create_tcl
|
109
|
+
create_constraints_file if @create_sdc
|
110
|
+
|
111
|
+
return str
|
112
|
+
end
|
113
|
+
|
114
|
+
private
|
115
|
+
|
116
|
+
def old_module_head
|
117
|
+
%Q{/**********************************************
|
118
|
+
_______________________________________
|
119
|
+
___________ Cook Darwin __________
|
120
|
+
_______________________________________
|
121
|
+
descript:
|
122
|
+
author : Cook.Darwin
|
123
|
+
Version: VERA.0.0
|
124
|
+
created: #{Time.now()}
|
125
|
+
madified:
|
126
|
+
***********************************************/
|
127
|
+
#{macro_def}
|
128
|
+
#{head_class}
|
129
|
+
}
|
130
|
+
end
|
131
|
+
|
132
|
+
def module_head
|
133
|
+
%Q{#{$__sdlmodule_head_logo__}
|
134
|
+
#{macro_def}
|
135
|
+
#{head_class}
|
136
|
+
}
|
137
|
+
end
|
138
|
+
|
139
|
+
def head_class
|
140
|
+
case(@target_class.to_s)
|
141
|
+
when "AxiStream"
|
142
|
+
'(* axi_stream = "true" *)'
|
143
|
+
when "Axi4"
|
144
|
+
'(* axi4 = "true" *)'
|
145
|
+
when "AxiLite"
|
146
|
+
'(* axi_lite = "true" *)'
|
147
|
+
when "VideoInf"
|
148
|
+
'(* videoinf = "true" *)'
|
149
|
+
when "DataInf"
|
150
|
+
'(* data_inf = "true" *)'
|
151
|
+
when "DataInf_C"
|
152
|
+
'(* data_inf_c = "true" *)'
|
153
|
+
else
|
154
|
+
@target_class.to_s
|
155
|
+
end
|
156
|
+
end
|
157
|
+
|
158
|
+
def build_params(ex_str="")
|
159
|
+
"Draw Parameters of sv module"
|
160
|
+
str = []
|
161
|
+
max_len = 0
|
162
|
+
@port_params.each do |k,v|
|
163
|
+
if v.port_length > max_len
|
164
|
+
max_len = v.port_length;
|
165
|
+
end
|
166
|
+
end
|
167
|
+
|
168
|
+
@port_params.each do |k,v|
|
169
|
+
str << " " + v.inst_port(max_len-v.port_length)
|
170
|
+
end
|
171
|
+
|
172
|
+
unless ex_str.empty?
|
173
|
+
head_tap = '//------>> EX PARAMETER <<-------------------'+"\n"
|
174
|
+
end_tap = "\n//------<< EX PARAMETER >>-------------------"+"\n"
|
175
|
+
else
|
176
|
+
head_tap = ""
|
177
|
+
end_tap = ""
|
178
|
+
end
|
179
|
+
|
180
|
+
if str.empty?
|
181
|
+
if ex_str.empty?
|
182
|
+
return ""
|
183
|
+
else
|
184
|
+
# ex_str.gsub!(/,\s*$/m,"")
|
185
|
+
return "#(\n" + head_tap + ex_str + end_tap + "\n)"
|
186
|
+
end
|
187
|
+
else
|
188
|
+
# if (ex_str !~ /,\s*$/m)
|
189
|
+
# ex_str = ex_str + ",\n" unless ex_str.empty?
|
190
|
+
# end
|
191
|
+
"#(\n" + head_tap + ex_str + end_tap + str.join(",\n")+"\n)"
|
192
|
+
end
|
193
|
+
|
194
|
+
end
|
195
|
+
|
196
|
+
def align_tt(max_len,tt,tap=1)
|
197
|
+
tt+" "*(max_len+tap-tt.length)
|
198
|
+
end
|
199
|
+
|
200
|
+
def build_ports(ex_str="")
|
201
|
+
"Draw Ports of sv module"
|
202
|
+
"<T0> type.[.]... <T1>name <T2> Array"
|
203
|
+
str = []
|
204
|
+
# ports = (@port_clocks + @port_resets + @port_logics + @port_datainfs + @port_datainf_c_s + @port_videoinfs + @port_axisinfs + @port_axi4infs + @port_axilinfs)
|
205
|
+
|
206
|
+
t0 = []
|
207
|
+
t1 = []
|
208
|
+
t2 = []
|
209
|
+
@ports ||= Hash.new
|
210
|
+
@ports.each do |k,v|
|
211
|
+
tmp = v.inst_port
|
212
|
+
t0 << tmp[0]
|
213
|
+
t1 << tmp[1]
|
214
|
+
t2 << tmp[2]
|
215
|
+
end
|
216
|
+
|
217
|
+
max_len_t0 = t0.map { |e| e.length }.max
|
218
|
+
max_len_t1 = t1.map { |e| e.length }.max
|
219
|
+
max_len_t2 = t2.map { |e| e.length }.max
|
220
|
+
|
221
|
+
t0.each_index do |index|
|
222
|
+
str << " "+align_tt(max_len_t0,t0[index])+align_tt(max_len_t1,t1[index])+align_tt(max_len_t2,t2[index])
|
223
|
+
end
|
224
|
+
|
225
|
+
str = str.map { |e| e.rstrip }.join(",\n")
|
226
|
+
|
227
|
+
unless ex_str.empty?
|
228
|
+
head_tap = '//------>> EX PORT <<-------------------'+"\n"
|
229
|
+
end_tap = "\n//------<< EX PORT >>-------------------"+"\n"
|
230
|
+
else
|
231
|
+
head_tap = ""
|
232
|
+
end_tap = ""
|
233
|
+
end
|
234
|
+
|
235
|
+
if str.empty?
|
236
|
+
if ex_str.empty?
|
237
|
+
return "();"
|
238
|
+
else
|
239
|
+
# ex_str.gsub!(/,\s*$/m,"")
|
240
|
+
return "(\n" + head_tap + ex_str + end_tap + "\n);\n"
|
241
|
+
end
|
242
|
+
else
|
243
|
+
ex_str = ex_str.rstrip
|
244
|
+
if ex_str[ex_str.length] != "," && !ex_str.empty?
|
245
|
+
ex_str = ex_str + ",\n"
|
246
|
+
end
|
247
|
+
"(\n" + head_tap + ex_str + end_tap + str+"\n);\n"
|
248
|
+
end
|
249
|
+
|
250
|
+
end
|
251
|
+
|
252
|
+
def add_sub_module_file_paths
|
253
|
+
""
|
254
|
+
end
|
255
|
+
|
256
|
+
end
|
257
|
+
|
258
|
+
|
259
|
+
class SdlModule
|
260
|
+
|
261
|
+
def macro_def
|
262
|
+
@_head_macro_ ||=[]
|
263
|
+
@_head_macro_ << "`timescale 1ns/1ps"
|
264
|
+
@_head_macro_.reverse.join("\n")
|
265
|
+
end
|
266
|
+
|
267
|
+
def macro_add_vcs
|
268
|
+
@_head_macro_ ||=[]
|
269
|
+
|
270
|
+
@_head_macro_ << "`include \"define_macro.sv\" "
|
271
|
+
end
|
272
|
+
end
|