axi_tdl 0.0.2
Sign up to get free protection for your applications and to get access to all the features.
- checksums.yaml +7 -0
- data/.gitignore +8 -0
- data/CODE_OF_CONDUCT.md +74 -0
- data/Gemfile +6 -0
- data/Gemfile.lock +43 -0
- data/LICENSE +504 -0
- data/README.md +311 -0
- data/Rakefile +18 -0
- data/axi_tdl.gemspec +43 -0
- data/bin/console +14 -0
- data/bin/setup +8 -0
- data/lib/.rspec +1 -0
- data/lib/axi/AXI4/axi4_combin_wr_rd_batch.sv +59 -0
- data/lib/axi/AXI4/axi4_direct.sv +137 -0
- data/lib/axi/AXI4/axi4_direct_A1.sv +229 -0
- data/lib/axi/AXI4/axi4_direct_B1.sv +74 -0
- data/lib/axi/AXI4/axi4_direct_verb.sv +79 -0
- data/lib/axi/AXI4/axi4_direct_verc.sv +146 -0
- data/lib/axi/AXI4/axi4_dpram_cache.rb +106 -0
- data/lib/axi/AXI4/axi4_dpram_cache.sv +112 -0
- data/lib/axi/AXI4/axi4_long_to_axi4_wide.sv +85 -0
- data/lib/axi/AXI4/axi4_long_to_axi4_wide_A1.sv +96 -0
- data/lib/axi/AXI4/axi4_long_to_axi4_wide_track.sv +118 -0
- data/lib/axi/AXI4/axi4_long_to_axi4_wide_verb.sv +131 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_pipe.sv +44 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_pipe_verb.sv +45 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_rd_pipe.sv +111 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_rd_pipe_verb.sv +113 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_wr_pipe.sv +142 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_wr_pipe_verb.sv +146 -0
- data/lib/axi/AXI4/axi4_rd_auxiliary_batch_gen.sv +134 -0
- data/lib/axi/AXI4/axi4_rd_auxiliary_gen.sv +89 -0
- data/lib/axi/AXI4/axi4_rd_auxiliary_gen_A1.sv +109 -0
- data/lib/axi/AXI4/axi4_rd_burst_track.sv +164 -0
- data/lib/axi/AXI4/axi4_wr_aux_bind_data.sv +121 -0
- data/lib/axi/AXI4/axi4_wr_auxiliary_batch_gen.sv +140 -0
- data/lib/axi/AXI4/axi4_wr_auxiliary_gen.sv +102 -0
- data/lib/axi/AXI4/axi4_wr_auxiliary_gen_without_resp.sv +91 -0
- data/lib/axi/AXI4/axi4_wr_burst_track.sv +146 -0
- data/lib/axi/AXI4/axi_stream_add_addr_len.sv +50 -0
- data/lib/axi/AXI4/axi_stream_to_axi4_wr.sv +61 -0
- data/lib/axi/AXI4/axi_stream_to_axi4_wr_verb.sv.bak +123 -0
- data/lib/axi/AXI4/axis_to_axi4_wr.rb +149 -0
- data/lib/axi/AXI4/axis_to_axi4_wr.sv +141 -0
- data/lib/axi/AXI4/full_axi4_to_axis.sv +188 -0
- data/lib/axi/AXI4/full_axi4_to_axis_partition_wr_rd.sv +208 -0
- data/lib/axi/AXI4/id_record.sv +55 -0
- data/lib/axi/AXI4/idata_pool_axi4.sv +110 -0
- data/lib/axi/AXI4/interconnect/AXI4_interconnect_M2S.sv +291 -0
- data/lib/axi/AXI4/interconnect/axi4_mix_interconnect_M2S.sv +72 -0
- data/lib/axi/AXI4/interconnect/axi4_rd_interconnect_M2S.sv +148 -0
- data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S.sv +255 -0
- data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S.sv.bak +255 -0
- data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S_A1.sv +286 -0
- data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S_A2.sv +281 -0
- data/lib/axi/AXI4/interconnect/axi4_wr_interconnect_M2S.sv +235 -0
- data/lib/axi/AXI4/interconnect/axi4_wr_interconnect_M2S_A1.sv +283 -0
- data/lib/axi/AXI4/interconnect/axi4_wr_mix_interconnect_M2S.sv +32 -0
- data/lib/axi/AXI4/long_axi4_to_wide_axi4.sv.bak +251 -0
- data/lib/axi/AXI4/odata_pool_axi4.sv +134 -0
- data/lib/axi/AXI4/odata_pool_axi4_A1.sv +165 -0
- data/lib/axi/AXI4/odata_pool_axi4_A2.sv +159 -0
- data/lib/axi/AXI4/odata_pool_axi4_A3.sv +183 -0
- data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo.sv +61 -0
- data/lib/axi/AXI4/packet_fifo/axi4_rd_packet_fifo.sv +282 -0
- data/lib/axi/AXI4/packet_fifo/axi4_wr_packet_fifo.sv +181 -0
- data/lib/axi/AXI4/packet_merge/axi4_merge.sv +60 -0
- data/lib/axi/AXI4/packet_merge/axi4_merge_rd.sv +279 -0
- data/lib/axi/AXI4/packet_merge/axi4_merge_wr.sv +267 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition.sv +36 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_OD.sv +66 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd.sv +211 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_OD.sv +322 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.rb +80 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +93 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_wr.sv +239 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_wr_OD.sv +302 -0
- data/lib/axi/AXI4/packet_partition/data_inf_partition.rb +293 -0
- data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +307 -0
- data/lib/axi/AXI4/vcs_axi4_array_comptable.sv +35 -0
- data/lib/axi/AXI4/vcs_axi4_comptable.sv +330 -0
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.rb +149 -0
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +140 -0
- data/lib/axi/AXI4/width_convert/axi4_data_combin_aflag_pipe.sv +239 -0
- data/lib/axi/AXI4/width_convert/axi4_data_combin_aflag_pipe_A1.sv +204 -0
- data/lib/axi/AXI4/width_convert/axi4_data_convert.sv +312 -0
- data/lib/axi/AXI4/width_convert/axi4_data_convert_A1.sv +217 -0
- data/lib/axi/AXI4/width_convert/data_combin.sv +366 -0
- data/lib/axi/AXI4/width_convert/data_combin.sv.bak +290 -0
- data/lib/axi/AXI4/width_convert/data_destruct.sv +304 -0
- data/lib/axi/AXI4/width_convert/feed_check.sv +94 -0
- data/lib/axi/AXI4/width_convert/len_convert.sv.bak +61 -0
- data/lib/axi/AXI4/width_convert/odd_width_convert.sv +229 -0
- data/lib/axi/AXI4/width_convert/odd_width_convert_verb.sv +105 -0
- data/lib/axi/AXI4/width_convert/simple_data_pipe.sv +40 -0
- data/lib/axi/AXI4/width_convert/simple_data_pipe_slaver.sv +33 -0
- data/lib/axi/AXI4/width_convert/width_combin.sv +113 -0
- data/lib/axi/AXI4/width_convert/width_convert.sv +87 -0
- data/lib/axi/AXI4/width_convert/width_convert_verb.sv +249 -0
- data/lib/axi/AXI4/width_convert/width_destruct.sv +206 -0
- data/lib/axi/AXI4/width_convert/width_destruct_A1.sv +251 -0
- data/lib/axi/AXI_BFM/AXI_BFM_PKG.sv +1039 -0
- data/lib/axi/AXI_BFM/Data_C_BFM_PKG.sv +97 -0
- data/lib/axi/AXI_BFM/axi4_error_chk.sv +298 -0
- data/lib/axi/AXI_BFM/axi4_illegal_bfm_pkg.sv +607 -0
- data/lib/axi/AXI_BFM/axi_lite_master.sv +102 -0
- data/lib/axi/AXI_BFM/axi_lite_tb.sv +23 -0
- data/lib/axi/AXI_BFM/axi_master.sv +185 -0
- data/lib/axi/AXI_BFM/axi_mirror.sv +266 -0
- data/lib/axi/AXI_BFM/axi_mm_tb.sv +134 -0
- data/lib/axi/AXI_BFM/axi_slaver.sv.bak +340 -0
- data/lib/axi/AXI_BFM/axistreambfm.sv +117 -0
- data/lib/axi/AXI_Lite/axi4_to_lite.sv +36 -0
- data/lib/axi/AXI_Lite/axi_lite_configure.sv +356 -0
- data/lib/axi/AXI_Lite/axi_lite_configure_inf2.sv +365 -0
- data/lib/axi/AXI_Lite/axi_lite_configure_verb.sv.bck +370 -0
- data/lib/axi/AXI_Lite/axi_lite_interconnect_M2S.sv +437 -0
- data/lib/axi/AXI_Lite/axi_lite_interconnect_S2M.sv +359 -0
- data/lib/axi/AXI_Lite/axi_lite_interconnect_S2M.sv.bak +359 -0
- data/lib/axi/AXI_Lite/axi_lite_master_empty.sv +30 -0
- data/lib/axi/AXI_Lite/axi_lite_slaver_empty.sv +27 -0
- data/lib/axi/AXI_Lite/axil_direct.sv +52 -0
- data/lib/axi/AXI_Lite/common_configure_reg_interface/common_configure_reg_interface.sv +230 -0
- data/lib/axi/AXI_Lite/common_configure_reg_interface/common_configure_reg_interface.sv.bak +109 -0
- data/lib/axi/AXI_Lite/common_configure_reg_interface/jtag_to_axilite_wrapper.sv +56 -0
- data/lib/axi/AXI_Lite/gen_axi_lite_ctrl.sv +515 -0
- data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_C1.sv +369 -0
- data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_verb.sv +365 -0
- data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_verc.sv +401 -0
- data/lib/axi/AXI_Lite/wr_lite_to_axis.sv +141 -0
- data/lib/axi/AXI_Lite/wr_lite_to_axis.sv.bak +141 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S.sv +76 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_A1.sv +77 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_A2.sv +71 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_bind_tuser.sv +72 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_noaddr.sv +151 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_with_addr.sv +87 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_S2M.sv +65 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_auto.sv +50 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_with_info.sv +64 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_with_keep.sv.bak +64 -0
- data/lib/axi/AXI_stream/axi_stream_packet_fifo_with_info.sv.bak +49 -0
- data/lib/axi/AXI_stream/axi_stream_partition.sv +147 -0
- data/lib/axi/AXI_stream/axi_stream_partition_A1.sv +63 -0
- data/lib/axi/AXI_stream/axi_stream_planer.sv +51 -0
- data/lib/axi/AXI_stream/axi_stream_split_channel.rb +56 -0
- data/lib/axi/AXI_stream/axi_stream_split_channel.sv +149 -0
- data/lib/axi/AXI_stream/axi_streams_combin.sv +151 -0
- data/lib/axi/AXI_stream/axi_streams_combin_A1.sv +179 -0
- data/lib/axi/AXI_stream/axi_streams_scaler.sv +171 -0
- data/lib/axi/AXI_stream/axi_streams_scaler_A1.sv +179 -0
- data/lib/axi/AXI_stream/axis_append.sv +79 -0
- data/lib/axi/AXI_stream/axis_append_A1.sv +82 -0
- data/lib/axi/AXI_stream/axis_base_pipe.sv +184 -0
- data/lib/axi/AXI_stream/axis_combin_with_fifo.sv +69 -0
- data/lib/axi/AXI_stream/axis_connect_pipe.sv +86 -0
- data/lib/axi/AXI_stream/axis_connect_pipe_A1.sv.bak +170 -0
- data/lib/axi/AXI_stream/axis_connect_pipe_left_shift.sv +64 -0
- data/lib/axi/AXI_stream/axis_connect_pipe_right_shift.sv +64 -0
- data/lib/axi/AXI_stream/axis_connect_pipe_right_shift_verb.sv +70 -0
- data/lib/axi/AXI_stream/axis_connect_pipe_with_info.sv +93 -0
- data/lib/axi/AXI_stream/axis_direct.sv +55 -0
- data/lib/axi/AXI_stream/axis_direct_A1.sv +81 -0
- data/lib/axi/AXI_stream/axis_filter.sv +38 -0
- data/lib/axi/AXI_stream/axis_full_to_data_c.sv +26 -0
- data/lib/axi/AXI_stream/axis_head_cut.sv +67 -0
- data/lib/axi/AXI_stream/axis_head_cut_verb.sv +60 -0
- data/lib/axi/AXI_stream/axis_head_cut_verc.rb +175 -0
- data/lib/axi/AXI_stream/axis_head_cut_verc.sv +245 -0
- data/lib/axi/AXI_stream/axis_inct_s2m_with_flag.sv +84 -0
- data/lib/axi/AXI_stream/axis_insert_copy.rb +59 -0
- data/lib/axi/AXI_stream/axis_insert_copy.sv +66 -0
- data/lib/axi/AXI_stream/axis_intc_M2S_with_addr_inf.sv +114 -0
- data/lib/axi/AXI_stream/axis_intc_S2M_with_addr_inf.sv +85 -0
- data/lib/axi/AXI_stream/axis_interconnect_S2M_pipe.sv +75 -0
- data/lib/axi/AXI_stream/axis_length_cut.sv +64 -0
- data/lib/axi/AXI_stream/axis_length_fill.sv +194 -0
- data/lib/axi/AXI_stream/axis_length_split.sv +86 -0
- data/lib/axi/AXI_stream/axis_length_split_with_addr.sv +127 -0
- data/lib/axi/AXI_stream/axis_length_split_writh_user.sv +87 -0
- data/lib/axi/AXI_stream/axis_link_trigger.sv +81 -0
- data/lib/axi/AXI_stream/axis_master_empty.sv +26 -0
- data/lib/axi/AXI_stream/axis_mirror_to_master.sv +126 -0
- data/lib/axi/AXI_stream/axis_mirrors.sv +60 -0
- data/lib/axi/AXI_stream/axis_orthogonal.sv +66 -0
- data/lib/axi/AXI_stream/axis_ram_buffer.sv +118 -0
- data/lib/axi/AXI_stream/axis_rom_contect.rb +97 -0
- data/lib/axi/AXI_stream/axis_rom_contect.sv +110 -0
- data/lib/axi/AXI_stream/axis_rom_contect_sim.rb +102 -0
- data/lib/axi/AXI_stream/axis_rom_contect_sim.sv +113 -0
- data/lib/axi/AXI_stream/axis_slaver_empty.sv +22 -0
- data/lib/axi/AXI_stream/axis_slaver_pipe.sv +84 -0
- data/lib/axi/AXI_stream/axis_slaver_pipe_A1.sv +54 -0
- data/lib/axi/AXI_stream/axis_slaver_vector_empty.sv +27 -0
- data/lib/axi/AXI_stream/axis_split_channel_verb.rb +42 -0
- data/lib/axi/AXI_stream/axis_split_channel_verb.sv +62 -0
- data/lib/axi/AXI_stream/axis_to_axi4_or_lite.rb +127 -0
- data/lib/axi/AXI_stream/axis_to_axi4_or_lite.sv +153 -0
- data/lib/axi/AXI_stream/axis_to_data_inf.sv +34 -0
- data/lib/axi/AXI_stream/axis_to_lite_rd.sv +81 -0
- data/lib/axi/AXI_stream/axis_to_lite_wr.sv +71 -0
- data/lib/axi/AXI_stream/axis_uncompress.sv +147 -0
- data/lib/axi/AXI_stream/axis_uncompress_A1.sv +150 -0
- data/lib/axi/AXI_stream/axis_uncompress_verb.rb +32 -0
- data/lib/axi/AXI_stream/axis_uncompress_verb.sv +54 -0
- data/lib/axi/AXI_stream/axis_valve.sv +29 -0
- data/lib/axi/AXI_stream/axis_valve_with_pipe.sv +76 -0
- data/lib/axi/AXI_stream/axis_vector_master_empty.rb +11 -0
- data/lib/axi/AXI_stream/axis_vector_master_empty.sv +35 -0
- data/lib/axi/AXI_stream/axis_vector_slaver_empty.rb +11 -0
- data/lib/axi/AXI_stream/axis_vector_slaver_empty.sv +35 -0
- data/lib/axi/AXI_stream/check_stream_crc.sv +28 -0
- data/lib/axi/AXI_stream/data_c_to_axis_full.sv +23 -0
- data/lib/axi/AXI_stream/data_to_axis_inf.sv +103 -0
- data/lib/axi/AXI_stream/data_to_axis_inf_A1.sv +28 -0
- data/lib/axi/AXI_stream/data_width/axis_width_combin.sv +204 -0
- data/lib/axi/AXI_stream/data_width/axis_width_combin_A1.sv +220 -0
- data/lib/axi/AXI_stream/data_width/axis_width_convert.sv +49 -0
- data/lib/axi/AXI_stream/data_width/axis_width_destruct.sv +82 -0
- data/lib/axi/AXI_stream/data_width/axis_width_destruct_A1.sv +86 -0
- data/lib/axi/AXI_stream/ex_status/axis_ex_status.sv +97 -0
- data/lib/axi/AXI_stream/gen_big_field_table.sv +170 -0
- data/lib/axi/AXI_stream/gen_common_frame_table.sv +382 -0
- data/lib/axi/AXI_stream/gen_common_frame_table_bind_tuser.sv +428 -0
- data/lib/axi/AXI_stream/gen_origin_axis.sv +116 -0
- data/lib/axi/AXI_stream/gen_origin_axis_A1.sv +129 -0
- data/lib/axi/AXI_stream/gen_origin_axis_A2.sv +162 -0
- data/lib/axi/AXI_stream/gen_simple_axis.sv +164 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_long_fifo.sv +132 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_long_fifo_verb.sv +140 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo.sv +125 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1.sv +142 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1E.sv +198 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_verb.sv +120 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_with_info.sv +49 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_long_fifo.sv +197 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_wide_fifo.sv +141 -0
- data/lib/axi/AXI_stream/packet_fifo/axis_pkt_fifo_filter_keep.sv +164 -0
- data/lib/axi/AXI_stream/packet_fifo/axis_pkt_fifo_filter_keep_A1.sv +166 -0
- data/lib/axi/AXI_stream/parse_big_field_table.sv +164 -0
- data/lib/axi/AXI_stream/parse_big_field_table_A1.sv +162 -0
- data/lib/axi/AXI_stream/parse_big_field_table_A2.sv +165 -0
- data/lib/axi/AXI_stream/parse_big_field_table_verb.sv +118 -0
- data/lib/axi/AXI_stream/parse_common_frame_table.sv +202 -0
- data/lib/axi/AXI_stream/parse_common_frame_table_A1.sv +521 -0
- data/lib/axi/AXI_stream/parse_common_frame_table_A2.sv +561 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache.sv +46 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_35bit.sv +122 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_36_71bit.sv +71 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_72_95bit.sv +96 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_72_95bit_with_keep.sv +99 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_96_143bit.sv +119 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_A1.sv +49 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_B1.sv +82 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_mirror.sv +44 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_verb.sv +58 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_long_cache.sv +55 -0
- data/lib/axi/AXI_stream/stream_crc.sv +67 -0
- data/lib/axi/AXI_stream/vcs_axis_comptable.sv +73 -0
- data/lib/axi/LICENSE +504 -0
- data/lib/axi/ReadME.md +6 -0
- data/lib/axi/SIM/tb_axi4_partition_20201105.sv +115 -0
- data/lib/axi/SIM/tb_axis_bfm_0504.sv +61 -0
- data/lib/axi/SIM/tb_axis_partitiom_0929.sv +102 -0
- data/lib/axi/SIM/tb_axis_s2m_pipe_1023.sv +163 -0
- data/lib/axi/SIM/tb_axis_to_axi4_0925.sv +107 -0
- data/lib/axi/SIM/tb_data_c_m2s_inf_20200114.sv +222 -0
- data/lib/axi/SIM/tb_data_c_m2s_inf_20201103.sv +245 -0
- data/lib/axi/SIM/tb_data_c_pipe_inf_20180417.sv +114 -0
- data/lib/axi/SIM/tb_wide_axis_to_axi4_wr.sv +81 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip.sv +589 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip_C1.sv +69 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip_verb.sv +388 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip_verc.sv +70 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/ddr3_ip_native_to_axi4.sv +194 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/ddr3_ip_wrapper_sim.sv +99 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/ddr_axi4_to_axis.sv +188 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo.sv +156 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo_A1.sv +180 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo_verb.sv +269 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/model_ddr_ip_app.sv +303 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/tb_ddr3_ip_wrapper_sim.sv +154 -0
- data/lib/axi/cfg.yml +15 -0
- data/lib/axi/common/ClockSameDomain.sv +128 -0
- data/lib/axi/common/common_ram_sim_wrapper.rb +66 -0
- data/lib/axi/common/common_ram_sim_wrapper.sv +75 -0
- data/lib/axi/common/common_ram_wrapper.rb +71 -0
- data/lib/axi/common/common_ram_wrapper.sv +82 -0
- data/lib/axi/common/data_c_interface_dram.rb +90 -0
- data/lib/axi/common/data_c_interface_dram.sv +106 -0
- data/lib/axi/common/mem_format.coe +60 -0
- data/lib/axi/common/pipe_vld.sv +45 -0
- data/lib/axi/common/test_write_mem.sv +22 -0
- data/lib/axi/common/xilinx_hdl_dpram.sv +142 -0
- data/lib/axi/common/xilinx_hdl_dpram_sim.sv +176 -0
- data/lib/axi/common_fifo/common_fifo.sv +165 -0
- data/lib/axi/common_fifo/common_stack.sv +56 -0
- data/lib/axi/common_fifo/independent_clock_fifo.sv +200 -0
- data/lib/axi/common_fifo/independent_clock_fifo_a1.sv +202 -0
- data/lib/axi/common_fifo/independent_stack.sv +85 -0
- data/lib/axi/data_interface/data_connect_pipe.sv +228 -0
- data/lib/axi/data_interface/data_inf_A2B.sv +21 -0
- data/lib/axi/data_interface/data_inf_B2A.sv +21 -0
- data/lib/axi/data_interface/data_inf_c/data_bind.sv +74 -0
- data/lib/axi/data_interface/data_inf_c/data_c_cache.sv +49 -0
- data/lib/axi/data_interface/data_inf_c/data_c_direct.sv +51 -0
- data/lib/axi/data_interface/data_inf_c/data_c_direct_mirror.sv +28 -0
- data/lib/axi/data_interface/data_inf_c/data_c_intc_M2S_force_robin.rb.bak +268 -0
- data/lib/axi/data_interface/data_inf_c/data_c_intc_M2S_force_robin.sv +301 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_force_vld.sv +57 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_force_vld_bind_data.sv +81 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf.sv +130 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf_A1.sv +135 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf_left_shift.sv +158 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf_right_shift.sv +155 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf_right_shift_verb.sv +174 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_C1.sv +296 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_C1_with_id.sv +58 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_best_last.sv +319 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_best_robin.sv +293 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_robin.sv +296 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_robin_with_id.sv +46 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_verc.sv +405 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_verc_with_addr.sv +226 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_verc_with_id.sv +54 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_latency.sv +68 -0
- data/lib/axi/data_interface/data_inf_c/data_c_scaler.sv +326 -0
- data/lib/axi/data_interface/data_inf_c/data_c_scaler_A1.sv +333 -0
- data/lib/axi/data_interface/data_inf_c/data_c_tmp_cache.sv +44 -0
- data/lib/axi/data_interface/data_inf_c/data_condition_mirror.sv +64 -0
- data/lib/axi/data_interface/data_inf_c/data_condition_valve.sv +53 -0
- data/lib/axi/data_interface/data_inf_c/data_connect_pipe_inf.sv +73 -0
- data/lib/axi/data_interface/data_inf_c/data_inf_c_M2S_with_addr_and_id.sv +66 -0
- data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_M2S_with_id.sv +67 -0
- data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_S2M.sv +70 -0
- data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_S2M_A1.sv +72 -0
- data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_S2M_with_lazy.sv +49 -0
- data/lib/axi/data_interface/data_inf_c/data_inf_c_interconnect_M2S.sv +50 -0
- data/lib/axi/data_interface/data_inf_c/data_inf_c_pipe_condition.sv +33 -0
- data/lib/axi/data_interface/data_inf_c/data_inf_c_planer.sv +50 -0
- data/lib/axi/data_interface/data_inf_c/data_inf_c_planer_A1.sv +53 -0
- data/lib/axi/data_interface/data_inf_c/data_intc_M2S_force_robin.sv +31 -0
- data/lib/axi/data_interface/data_inf_c/data_mirrors.sv +108 -0
- data/lib/axi/data_interface/data_inf_c/data_mirrors_verb.sv.bak +101 -0
- data/lib/axi/data_interface/data_inf_c/data_uncompress.sv +150 -0
- data/lib/axi/data_interface/data_inf_c/data_valve.sv +26 -0
- data/lib/axi/data_interface/data_inf_c/next_prio.sv +42 -0
- data/lib/axi/data_interface/data_inf_c/trigger_data_inf_c.sv +51 -0
- data/lib/axi/data_interface/data_inf_c/trigger_data_inf_c_A1.sv +54 -0
- data/lib/axi/data_interface/data_inf_c/trigger_ready_ctrl.sv +33 -0
- data/lib/axi/data_interface/data_inf_c/vcs_data_c_comptable.sv +40 -0
- data/lib/axi/data_interface/data_inf_cross_clk.sv +40 -0
- data/lib/axi/data_interface/data_inf_intc_M2S_force_addr_with_id.sv +62 -0
- data/lib/axi/data_interface/data_inf_intc_M2S_prio.sv +152 -0
- data/lib/axi/data_interface/data_inf_intc_M2S_prio_with_id.sv +55 -0
- data/lib/axi/data_interface/data_inf_interconnect_M2S_noaddr.sv +136 -0
- data/lib/axi/data_interface/data_inf_interconnect_M2S_with_id_noaddr.sv +55 -0
- data/lib/axi/data_interface/data_inf_planer.sv +59 -0
- data/lib/axi/data_interface/data_inf_planer_A1.sv +66 -0
- data/lib/axi/data_interface/data_inf_ticktock.sv +154 -0
- data/lib/axi/data_interface/data_interface.sv +91 -0
- data/lib/axi/data_interface/data_interface_pkg.sv +79 -0
- data/lib/axi/data_interface/data_pair_map.sv +152 -0
- data/lib/axi/data_interface/data_pair_map_A1.sv +159 -0
- data/lib/axi/data_interface/data_pair_map_A2.sv +212 -0
- data/lib/axi/data_interface/data_pipe_intc_M2S_addr.sv.bak +231 -0
- data/lib/axi/data_interface/data_pipe_interconnect.sv +290 -0
- data/lib/axi/data_interface/data_pipe_interconnect_M2S.sv +236 -0
- data/lib/axi/data_interface/data_pipe_interconnect_M2S.sv.bak1012 +237 -0
- data/lib/axi/data_interface/data_pipe_interconnect_M2S_A1.sv +241 -0
- data/lib/axi/data_interface/data_pipe_interconnect_M2S_verb.sv +302 -0
- data/lib/axi/data_interface/data_pipe_interconnect_M2S_verb.sv.bad_work +280 -0
- data/lib/axi/data_interface/data_pipe_interconnect_S2M.sv +332 -0
- data/lib/axi/data_interface/data_pipe_interconnect_S2M_A1.sv +376 -0
- data/lib/axi/data_interface/data_pipe_interconnect_S2M_verb.sv +265 -0
- data/lib/axi/data_interface/data_streams_combin.sv +592 -0
- data/lib/axi/data_interface/data_streams_combin_A1.sv +621 -0
- data/lib/axi/data_interface/data_streams_scaler.sv +593 -0
- data/lib/axi/data_interface/datainf_c_master_empty.sv +22 -0
- data/lib/axi/data_interface/datainf_c_slaver_empty.sv +22 -0
- data/lib/axi/data_interface/datainf_master_empty.sv +22 -0
- data/lib/axi/data_interface/datainf_slaver_empty.sv +22 -0
- data/lib/axi/data_interface/part_data_pair_map.sv +111 -0
- data/lib/axi/interface_define/axi_aux_inf.sv +206 -0
- data/lib/axi/interface_define/axi_inf.sv +1256 -0
- data/lib/axi/interface_define/axi_inf_verb.sv +42 -0
- data/lib/axi/interface_define/axi_interface_instance.svo +13 -0
- data/lib/axi/interface_define/axi_lite_inf.sv +345 -0
- data/lib/axi/interface_define/axi_stream_inf.sv +108 -0
- data/lib/axi/interface_define/bak/axi_aux_inf.sv +206 -0
- data/lib/axi/interface_define/bak/axi_inf_verb.sv +42 -0
- data/lib/axi/interface_define/bak/axi_interface_instance.svo +13 -0
- data/lib/axi/interface_define/bak/microblaze_inf.sv +136 -0
- data/lib/axi/interface_define/bak/xilinx_axi4_to_axi4.sv +87 -0
- data/lib/axi/interface_define/bak/xilinx_lite_to_lite.sv +128 -0
- data/lib/axi/interface_define/lite_inf2_to_inf.sv +38 -0
- data/lib/axi/interface_define/xilinx_axi4_to_axi4.sv +87 -0
- data/lib/axi/interface_define/xilinx_lite_to_lite.sv +128 -0
- data/lib/axi/macro/axil_macro.sv +132 -0
- data/lib/axi/macro/bak/axi4_base_files_add_to_vivado.tcl +28 -0
- data/lib/axi/macro/bak/axi_macro.sv +15 -0
- data/lib/axi/macro/bak/axis_base_files_add_to_vivado.tcl +26 -0
- data/lib/axi/macro/bak/base_files_add_to_vivado.tcl +24 -0
- data/lib/axi/macro/bak/data_inf_base_files_add_to_vivado.tcl +22 -0
- data/lib/axi/macro/bak/lite_inf_base_files_add_to_vivado.tcl +4 -0
- data/lib/axi/macro/bak/standard_tcl.rb +28 -0
- data/lib/axi/macro/bak/system_macro.sv +19 -0
- data/lib/axi/macro/bak/tcl_axi4_base_files_add_to_vivado.tcl +28 -0
- data/lib/axi/macro/bak/tcl_axis_base_files_add_to_vivado.tcl +26 -0
- data/lib/axi/macro/bak/tcl_base_files_add_to_vivado.tcl +24 -0
- data/lib/axi/macro/bak/tcl_data_inf_base_files_add_to_vivado.tcl +22 -0
- data/lib/axi/macro/bak/tcl_lite_inf_base_files_add_to_vivado.tcl +4 -0
- data/lib/axi/macro/bak/tcl_tmp.tcl +12 -0
- data/lib/axi/macro/bak/tmp.tcl +13 -0
- data/lib/axi/platform_ip/fifo_10_18bit_long.sv +125 -0
- data/lib/axi/platform_ip/fifo_145_216bit_A1.sv +167 -0
- data/lib/axi/platform_ip/fifo_217_288bit_A1.sv +191 -0
- data/lib/axi/platform_ip/fifo_36bit.sv +77 -0
- data/lib/axi/platform_ip/fifo_36bit_A1.sv +113 -0
- data/lib/axi/platform_ip/fifo_36kb_long.sv +145 -0
- data/lib/axi/platform_ip/fifo_37_72bit.sv +77 -0
- data/lib/axi/platform_ip/fifo_505_576bit_A1.sv +141 -0
- data/lib/axi/platform_ip/fifo_73_96bit.sv +102 -0
- data/lib/axi/platform_ip/fifo_97_144bit.sv +102 -0
- data/lib/axi/platform_ip/fifo_97_144bit_A1.sv +133 -0
- data/lib/axi/platform_ip/fifo_ku.sv +212 -0
- data/lib/axi/platform_ip/fifo_ku.sv.bak +488 -0
- data/lib/axi/platform_ip/fifo_ku_18bit.sv +138 -0
- data/lib/axi/platform_ip/fifo_ku_36bit.sv +148 -0
- data/lib/axi/platform_ip/fifo_ku_36kb_long.sv +135 -0
- data/lib/axi/platform_ip/fifo_ku_xbit_8192.sv.bak +107 -0
- data/lib/axi/platform_ip/fifo_wr_rd_mark.sv +94 -0
- data/lib/axi/platform_ip/ku_long_fifo_4bit.sv +189 -0
- data/lib/axi/platform_ip/long_fifo.sv +72 -0
- data/lib/axi/platform_ip/long_fifo_4bit.sv +156 -0
- data/lib/axi/platform_ip/long_fifo_4bit_8192.sv +133 -0
- data/lib/axi/platform_ip/long_fifo_4bit_SL8192.sv +133 -0
- data/lib/axi/platform_ip/long_fifo_verb.sv +110 -0
- data/lib/axi/platform_ip/wide_fifo.sv +66 -0
- data/lib/axi/platform_ip/wide_fifo_7series.sv +136 -0
- data/lib/axi/platform_ip/xilinx_fifo.sv +174 -0
- data/lib/axi/platform_ip/xilinx_fifo_A1.sv +223 -0
- data/lib/axi/platform_ip/xilinx_fifo_verb.sv +87 -0
- data/lib/axi/platform_ip/xilinx_fifo_verc.sv +87 -0
- data/lib/axi/platform_ip/xilinx_stream_packet_fifo_ip.sv +40 -0
- data/lib/axi/top/axi4_data_convert_2_20_tb.sv +126 -0
- data/lib/axi/top/axi4_data_convert_5_24_tb.sv +156 -0
- data/lib/axi/top/axi4_interconnnect_2_24_tb.sv +143 -0
- data/lib/axi/top/axi4_interconnnect_5_23_tb.sv +155 -0
- data/lib/axi/top/axi4_merge_tb_0331.sv +120 -0
- data/lib/axi/top/axi4_packet_fifo_2_28_tb.sv +107 -0
- data/lib/axi/top/axi4_partition_2_23_tb.sv +93 -0
- data/lib/axi/top/axi_stream_packet_fifo_2_28_tb.sv +78 -0
- data/lib/axi/top/axis_length_cut_2_28_tb.sv +79 -0
- data/lib/axi/top/axis_length_fill_8_18_tb.sv +81 -0
- data/lib/axi/top/common_fifo_2_27_tb.sv +77 -0
- data/lib/axi/top/data_convert_2_16_tb.sv +162 -0
- data/lib/axi/top/independent_fifo_2_27_tb.sv +90 -0
- data/lib/axi/top/long_to_wide_3_1_tb.sv +142 -0
- data/lib/axi/top/odd_width_convert_tb_420.sv +83 -0
- data/lib/axi/top/tb_axis_m2s_A1_0115.sv +158 -0
- data/lib/axi/top/tb_axis_width_combin_0913.sv +57 -0
- data/lib/axi/top/tb_axis_width_test_0914.sv +115 -0
- data/lib/axi/top/tb_data_c_inf_M2S_0823.sv +154 -0
- data/lib/axi/top/tb_data_c_inf_M2S_addr_0824.sv +252 -0
- data/lib/axi/top/tb_data_c_pipe_force_vld_1228.sv +96 -0
- data/lib/axi/top/tb_data_c_scaler_20180413.sv +187 -0
- data/lib/axi/top/tb_data_intc_S2M_0807.sv +168 -0
- data/lib/axi/top/tb_test_ku_fifo_0919.sv +98 -0
- data/lib/axi/top/width_convert_verb_tb_523.sv +68 -0
- data/lib/axi/video/video_stream_2_axi_stream.sv +90 -0
- data/lib/axi/video_interface/video_interface.sv +173 -0
- data/lib/axi_tdl.rb +6 -0
- data/lib/axi_tdl/version.rb +3 -0
- data/lib/spec/spec_helper.rb +100 -0
- data/lib/tdl/LICENSE +504 -0
- data/lib/tdl/Logic/Logic.tar.gz +0 -0
- data/lib/tdl/Logic/clock_rst_verb_auto.rb +99 -0
- data/lib/tdl/Logic/logic_edge.rb +194 -0
- data/lib/tdl/Logic/logic_latency.rb +197 -0
- data/lib/tdl/Logic/logic_main.rb +188 -0
- data/lib/tdl/Logic/logic_operator.rb.bak +128 -0
- data/lib/tdl/Logic/mdio_model_auto.rb +77 -0
- data/lib/tdl/Logic/path_lib.rb +7 -0
- data/lib/tdl/Logic/redefine_operator.rb +28 -0
- data/lib/tdl/ReadMe.md +295 -0
- data/lib/tdl/SDL/axi4/AXI4_interconnect_M2S_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_combin_wr_rd_batch_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_data_combin_aflag_pipe_A1_sdl.rb +38 -0
- data/lib/tdl/SDL/axi4/axi4_data_combin_aflag_pipe_sdl.rb +37 -0
- data/lib/tdl/SDL/axi4/axi4_data_convert_A1_sdl.rb +9 -0
- data/lib/tdl/SDL/axi4/axi4_data_convert_sdl.rb +9 -0
- data/lib/tdl/SDL/axi4/axi4_direct_A1_sdl.rb +14 -0
- data/lib/tdl/SDL/axi4/axi4_direct_B1_sdl.rb +9 -0
- data/lib/tdl/SDL/axi4/axi4_direct_sdl.rb +14 -0
- data/lib/tdl/SDL/axi4/axi4_direct_verb_sdl.rb +9 -0
- data/lib/tdl/SDL/axi4/axi4_direct_verc_sdl.rb +16 -0
- data/lib/tdl/SDL/axi4/axi4_long_to_axi4_wide_A1_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_long_to_axi4_wide_sdl.rb +9 -0
- data/lib/tdl/SDL/axi4/axi4_long_to_axi4_wide_track_sdl.rb +9 -0
- data/lib/tdl/SDL/axi4/axi4_long_to_axi4_wide_verb_sdl.rb +11 -0
- data/lib/tdl/SDL/axi4/axi4_merge_rd_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_merge_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_merge_wr_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_mix_interconnect_M2S_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_packet_fifo_sdl.rb +12 -0
- data/lib/tdl/SDL/axi4/axi4_partition_OD_sdl.rb +11 -0
- data/lib/tdl/SDL/axi4/axi4_partition_rd_OD_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_partition_rd_sdl.rb +11 -0
- data/lib/tdl/SDL/axi4/axi4_partition_sdl.rb +11 -0
- data/lib/tdl/SDL/axi4/axi4_partition_wr_OD_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_partition_wr_sdl.rb +11 -0
- data/lib/tdl/SDL/axi4/axi4_pipe_sdl.rb +9 -0
- data/lib/tdl/SDL/axi4/axi4_pipe_verb_sdl.rb +9 -0
- data/lib/tdl/SDL/axi4/axi4_rd_auxiliary_batch_gen_sdl.rb +11 -0
- data/lib/tdl/SDL/axi4/axi4_rd_auxiliary_gen_A1_sdl.rb +9 -0
- data/lib/tdl/SDL/axi4/axi4_rd_auxiliary_gen_sdl.rb +9 -0
- data/lib/tdl/SDL/axi4/axi4_rd_burst_track_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_rd_interconnect_M2S_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_rd_mix_interconnect_M2S_A1_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_rd_mix_interconnect_M2S_A2_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_rd_mix_interconnect_M2S_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_rd_packet_fifo_sdl.rb +11 -0
- data/lib/tdl/SDL/axi4/axi4_rd_pipe_sdl.rb +9 -0
- data/lib/tdl/SDL/axi4/axi4_rd_pipe_verb_sdl.rb +9 -0
- data/lib/tdl/SDL/axi4/axi4_wr_aux_bind_data_sdl.rb +9 -0
- data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_batch_gen_sdl.rb +11 -0
- data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_gen_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_gen_without_resp_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_wr_burst_track_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_wr_interconnect_M2S_A1_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_wr_interconnect_M2S_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_wr_mix_interconnect_M2S_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_wr_packet_fifo_sdl.rb +11 -0
- data/lib/tdl/SDL/axi4/axi4_wr_pipe_sdl.rb +9 -0
- data/lib/tdl/SDL/axi4/axi4_wr_pipe_verb_sdl.rb +9 -0
- data/lib/tdl/SDL/axi4/axi_stream_add_addr_len_sdl.rb +11 -0
- data/lib/tdl/SDL/axi4/axi_stream_to_axi4_wr_sdl.rb +9 -0
- data/lib/tdl/SDL/axi4/data_combin_sdl.rb +20 -0
- data/lib/tdl/SDL/axi4/data_destruct_sdl.rb +19 -0
- data/lib/tdl/SDL/axi4/feed_check_sdl.rb +18 -0
- data/lib/tdl/SDL/axi4/full_axi4_to_axis_partition_wr_rd_sdl.rb +11 -0
- data/lib/tdl/SDL/axi4/full_axi4_to_axis_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/id_record_sdl.rb +19 -0
- data/lib/tdl/SDL/axi4/idata_pool_axi4_sdl.rb +18 -0
- data/lib/tdl/SDL/axi4/odata_pool_axi4_A1_sdl.rb +13 -0
- data/lib/tdl/SDL/axi4/odata_pool_axi4_A2_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/odata_pool_axi4_sdl.rb +19 -0
- data/lib/tdl/SDL/axi4/odd_width_convert_sdl.rb +19 -0
- data/lib/tdl/SDL/axi4/odd_width_convert_verb_sdl.rb +19 -0
- data/lib/tdl/SDL/axi4/simple_data_pipe_sdl.rb +16 -0
- data/lib/tdl/SDL/axi4/simple_data_pipe_slaver_sdl.rb +16 -0
- data/lib/tdl/SDL/axi4/vcs_axi4_array_comptable.rb +9 -0
- data/lib/tdl/SDL/axi4/vcs_axi4_array_comptable_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/vcs_axi4_comptable.rb +8 -0
- data/lib/tdl/SDL/axi4/vcs_axi4_comptable_sdl.rb +9 -0
- data/lib/tdl/SDL/axi4/width_combin_sdl.rb +20 -0
- data/lib/tdl/SDL/axi4/width_convert_sdl.rb +20 -0
- data/lib/tdl/SDL/axi4/width_convert_verb_sdl.rb +20 -0
- data/lib/tdl/SDL/axi4/width_destruct_A1_sdl.rb +22 -0
- data/lib/tdl/SDL/axi4/width_destruct_sdl.rb +19 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_35bit_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_36_71bit_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_72_95bit_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_72_95bit_with_keep_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_96_143bit_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_B1_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_mirror_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_verb_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_A1_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_A2_sdl.rb +13 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_bind_tuser_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_noaddr_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_with_addr_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_S2M_auto_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_S2M_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axi_stream_long_cache_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axi_stream_long_fifo_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axi_stream_long_fifo_verb_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_B1E_sdl.rb +16 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_B1_sdl.rb +14 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_verb_sdl.rb +13 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_with_info_sdl.rb +13 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_long_fifo_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axi_stream_partition_A1_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axi_stream_partition_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axi_stream_wide_fifo_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axi_streams_combin_A1_sdl.rb +15 -0
- data/lib/tdl/SDL/axistream/axi_streams_combin_sdl.rb +16 -0
- data/lib/tdl/SDL/axistream/axi_streams_scaler_A1_sdl.rb +14 -0
- data/lib/tdl/SDL/axistream/axi_streams_scaler_sdl.rb +15 -0
- data/lib/tdl/SDL/axistream/axis_append_A1_sdl.rb +18 -0
- data/lib/tdl/SDL/axistream/axis_append_sdl.rb +17 -0
- data/lib/tdl/SDL/axistream/axis_base_pipe_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_combin_with_fifo_sdl.rb +14 -0
- data/lib/tdl/SDL/axistream/axis_connect_pipe_right_shift_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_connect_pipe_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_connect_pipe_with_info_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axis_direct_A1_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axis_direct_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_ex_status_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axis_filter_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_full_to_data_c_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_head_cut_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_inct_s2m_with_flag_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axis_intc_M2S_with_addr_inf_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axis_intc_S2M_with_addr_inf_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axis_interconnect_S2M_pipe_sdl.rb +15 -0
- data/lib/tdl/SDL/axistream/axis_length_cut_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_length_fill_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_length_split_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_length_split_with_addr_sdl.rb +13 -0
- data/lib/tdl/SDL/axistream/axis_length_split_writh_user_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_link_trigger_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axis_master_empty_sdl.rb +8 -0
- data/lib/tdl/SDL/axistream/axis_mirror_to_master_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_mirrors_sdl.rb +14 -0
- data/lib/tdl/SDL/axistream/axis_orthogonal_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_pkt_fifo_filter_keep_A1_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_pkt_fifo_filter_keep_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_ram_buffer_sdl.rb +13 -0
- data/lib/tdl/SDL/axistream/axis_slaver_empty_sdl.rb +8 -0
- data/lib/tdl/SDL/axistream/axis_slaver_pipe_A1_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_slaver_pipe_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_slaver_vector_empty_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_to_data_inf_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_to_lite_rd_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axis_to_lite_wr_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_uncompress_A1_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axis_uncompress_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axis_valve_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_valve_with_pipe_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axis_width_combin_A1_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_width_combin_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_width_convert_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_width_destruct_A1_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_width_destruct_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/check_stream_crc_sdl.rb +8 -0
- data/lib/tdl/SDL/axistream/data_c_to_axis_full_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/data_to_axis_inf_A1_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/data_to_axis_inf_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/gen_big_field_table_sdl.rb +14 -0
- data/lib/tdl/SDL/axistream/gen_common_frame_table_sdl.rb +60 -0
- data/lib/tdl/SDL/axistream/gen_origin_axis_A1_sdl.rb +13 -0
- data/lib/tdl/SDL/axistream/gen_origin_axis_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/gen_simple_axis_sdl.rb +13 -0
- data/lib/tdl/SDL/axistream/parse_big_field_table_A1_sdl.rb +17 -0
- data/lib/tdl/SDL/axistream/parse_big_field_table_A2_sdl.rb +17 -0
- data/lib/tdl/SDL/axistream/parse_big_field_table_sdl.rb +17 -0
- data/lib/tdl/SDL/axistream/stream_crc_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/vcs_axis_comptable.rb +16 -0
- data/lib/tdl/SDL/axistream/vcs_axis_comptable_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_bind_sdl.rb +10 -0
- data/lib/tdl/SDL/data_inf_c/data_c_cache_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_c_direct_mirror_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_c_direct_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_c_intc_M2S_force_robin_sdl.rb +10 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_force_vld_bind_data_sdl.rb +13 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_force_vld_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_A1_sdl.rb +10 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_right_shift_sdl.rb +13 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_C1_sdl.rb +14 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_C1_with_id_sdl.rb +16 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_sdl.rb +13 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_with_addr_sdl.rb +13 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_with_id_sdl.rb +15 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_latency_sdl.rb +10 -0
- data/lib/tdl/SDL/data_inf_c/data_c_scaler_A1_sdl.rb +16 -0
- data/lib/tdl/SDL/data_inf_c/data_c_scaler_sdl.rb +15 -0
- data/lib/tdl/SDL/data_inf_c/data_c_tmp_cache_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_condition_mirror_sdl.rb +13 -0
- data/lib/tdl/SDL/data_inf_c/data_condition_valve_sdl.rb +13 -0
- data/lib/tdl/SDL/data_inf_c/data_connect_pipe_inf_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_connect_pipe_sdl.rb +17 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_A2B_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_B2A_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_M2S_with_addr_and_id_sdl.rb +17 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_M2S_with_id_sdl.rb +15 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_A1_sdl.rb +13 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_sdl.rb +12 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_with_lazy_sdl.rb +15 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_interconnect_M2S_sdl.rb +12 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_pipe_condition_sdl.rb +10 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_A1.rb +12 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_A1_sdl.rb +14 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_sdl.rb +13 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_cross_clk_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_force_addr_with_id_sdl.rb +19 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_prio_sdl.rb +14 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_prio_with_id_sdl.rb +17 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_interconnect_M2S_noaddr_sdl.rb +14 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_interconnect_M2S_with_id_noaddr_sdl.rb +17 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_planer_A1_sdl.rb +15 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_planer_sdl.rb +14 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_ticktock_sdl.rb +18 -0
- data/lib/tdl/SDL/data_inf_c/data_intc_M2S_force_robin_sdl.rb +10 -0
- data/lib/tdl/SDL/data_inf_c/data_mirrors_sdl.rb +14 -0
- data/lib/tdl/SDL/data_inf_c/data_pair_map_A1_sdl.rb +16 -0
- data/lib/tdl/SDL/data_inf_c/data_pair_map_A2_sdl.rb +19 -0
- data/lib/tdl/SDL/data_inf_c/data_pair_map_sdl.rb +14 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_A1_sdl.rb +19 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_sdl.rb +17 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_verb_sdl.rb +16 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_A1_sdl.rb +19 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_sdl.rb +16 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_verb_sdl.rb +15 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_sdl.rb +23 -0
- data/lib/tdl/SDL/data_inf_c/data_streams_combin_A1_sdl.rb +20 -0
- data/lib/tdl/SDL/data_inf_c/data_streams_combin_sdl.rb +20 -0
- data/lib/tdl/SDL/data_inf_c/data_streams_scaler_sdl.rb +19 -0
- data/lib/tdl/SDL/data_inf_c/data_uncompress_sdl.rb +11 -0
- data/lib/tdl/SDL/data_inf_c/data_valve_sdl.rb +10 -0
- data/lib/tdl/SDL/data_inf_c/datainf_c_master_empty_sdl.rb +8 -0
- data/lib/tdl/SDL/data_inf_c/datainf_c_slaver_empty_sdl.rb +8 -0
- data/lib/tdl/SDL/data_inf_c/datainf_master_empty_sdl.rb +8 -0
- data/lib/tdl/SDL/data_inf_c/datainf_slaver_empty_sdl.rb +8 -0
- data/lib/tdl/SDL/data_inf_c/latency_sdl.rb +8 -0
- data/lib/tdl/SDL/data_inf_c/next_prio_sdl.rb +12 -0
- data/lib/tdl/SDL/data_inf_c/part_data_pair_map_sdl.rb +19 -0
- data/lib/tdl/SDL/data_inf_c/trigger_data_inf_c_A1_sdl.rb +11 -0
- data/lib/tdl/SDL/data_inf_c/trigger_data_inf_c_sdl.rb +11 -0
- data/lib/tdl/SDL/data_inf_c/trigger_ready_ctrl_sdl.rb +12 -0
- data/lib/tdl/SDL/data_inf_c/vcs_data_c_comptable.rb +8 -0
- data/lib/tdl/SDL/data_inf_c/vcs_data_c_comptable_sdl.rb +9 -0
- data/lib/tdl/SDL/fifo/common_fifo_sdl.rb +20 -0
- data/lib/tdl/SDL/fifo/common_stack_sdl.rb +14 -0
- data/lib/tdl/SDL/fifo/independent_clock_fifo_a1_sdl.rb +21 -0
- data/lib/tdl/SDL/fifo/independent_clock_fifo_sdl.rb +20 -0
- data/lib/tdl/SDL/fifo/independent_stack_sdl.rb +18 -0
- data/lib/tdl/SDL/path_lib.rb +6 -0
- data/lib/tdl/VideoInf/simple_video_gen.rb +46 -0
- data/lib/tdl/VideoInf/video_from_axi4.rb +108 -0
- data/lib/tdl/VideoInf/video_lib.rb +8 -0
- data/lib/tdl/VideoInf/video_stream_2_axi_stream.rb +67 -0
- data/lib/tdl/VideoInf/video_to_axi4.rb +75 -0
- data/lib/tdl/auto_script/auto_gen_tdl.rb +49 -0
- data/lib/tdl/auto_script/autogensdl.rb +289 -0
- data/lib/tdl/auto_script/autogentdl_a2.rb +452 -0
- data/lib/tdl/auto_script/import_hdl.rb +35 -0
- data/lib/tdl/auto_script/import_sdl.rb +26 -0
- data/lib/tdl/auto_script/test_autogensdl.rb +73 -0
- data/lib/tdl/auto_script/tmp.rb +6 -0
- data/lib/tdl/auto_script/tmp/hdl_test_sdl.rb +12 -0
- data/lib/tdl/axi4/axi4_combin_wr_rd_batch_auto.rb +79 -0
- data/lib/tdl/axi4/axi4_direct.rb +36 -0
- data/lib/tdl/axi4/axi4_direct_A1_auto.rb +137 -0
- data/lib/tdl/axi4/axi4_direct_auto.rb +79 -0
- data/lib/tdl/axi4/axi4_direct_verb_auto.rb +71 -0
- data/lib/tdl/axi4/axi4_interconnect_verb.rb +323 -0
- data/lib/tdl/axi4/axi4_lib.rb +9 -0
- data/lib/tdl/axi4/axi4_long_to_axi4_wide_A1_auto.rb +79 -0
- data/lib/tdl/axi4/axi4_long_to_axi4_wide_auto.rb +71 -0
- data/lib/tdl/axi4/axi4_long_to_axi4_wide_verb_auto.rb +86 -0
- data/lib/tdl/axi4/axi4_packet_fifo_auto.rb +155 -0
- data/lib/tdl/axi4/axi4_pipe_auto.rb +127 -0
- data/lib/tdl/axi4/axi4_pipe_verb_auto.rb +127 -0
- data/lib/tdl/axi4/axi4_rd_auxiliary_gen_auto.rb +71 -0
- data/lib/tdl/axi4/axi4_wr_auxiliary_gen_without_resp_auto.rb +78 -0
- data/lib/tdl/axi4/axis_to_axi4_wr_auto.rb +85 -0
- data/lib/tdl/axi4/bak/__axi4_wr_auxiliary_gen_without_resp.rb +175 -0
- data/lib/tdl/axi4/bak/axi4_combin_wr_rd_batch_auto.rb +153 -0
- data/lib/tdl/axi4/bak/axi4_data_convert.rb +74 -0
- data/lib/tdl/axi4/bak/axi4_direct_auto.rb +153 -0
- data/lib/tdl/axi4/bak/axi4_direct_verb_auto.rb +126 -0
- data/lib/tdl/axi4/bak/axi4_interconnect.rb.bak +91 -0
- data/lib/tdl/axi4/bak/axi4_long_to_axi4_wide_A1_auto.rb +153 -0
- data/lib/tdl/axi4/bak/axi4_long_to_axi4_wide_auto.rb +126 -0
- data/lib/tdl/axi4/bak/axi4_long_to_axi4_wide_verb_auto.rb +179 -0
- data/lib/tdl/axi4/bak/axi4_packet_fifo.rb.bak +75 -0
- data/lib/tdl/axi4/bak/axi4_packet_fifo_auto.rb +259 -0
- data/lib/tdl/axi4/bak/axi4_partition_od.rb +84 -0
- data/lib/tdl/axi4/bak/axi4_pipe_auto.rb +174 -0
- data/lib/tdl/axi4/bak/axi4_wr_auxiliary_gen_without_resp_auto.rb +152 -0
- data/lib/tdl/axi4/bak/axis_to_axi4_wr_auto.rb +178 -0
- data/lib/tdl/axi4/bak/ddr3.rb +40 -0
- data/lib/tdl/axi4/bak/idata_pool_axi4_auto.rb +396 -0
- data/lib/tdl/axi4/bak/odata_pool_axi4_A1_auto.rb +230 -0
- data/lib/tdl/axi4/bak/odata_pool_axi4_auto.rb +386 -0
- data/lib/tdl/axi4/idata_pool_axi4_auto.rb +176 -0
- data/lib/tdl/axi4/odata_pool_axi4_A1_auto.rb +99 -0
- data/lib/tdl/axi4/odata_pool_axi4_auto.rb +141 -0
- data/lib/tdl/axi4/wide_axis_to_axi4_wr.rb +84 -0
- data/lib/tdl/axi4/wide_axis_to_axi4_wr_auto.rb +84 -0
- data/lib/tdl/axi_lite/axi_lite_master_empty_auto.rb +85 -0
- data/lib/tdl/axi_lite/axi_lite_slaver_empty_auto.rb +68 -0
- data/lib/tdl/axi_lite/bak/axi_lite_master_empty_auto.rb +95 -0
- data/lib/tdl/axi_lite/bak/axi_lite_slaver_empty_auto.rb +88 -0
- data/lib/tdl/axi_lite/bak/jtag_to_axilite_wrapper_auto.rb +112 -0
- data/lib/tdl/axi_lite/jtag_to_axilite_wrapper_auto.rb +63 -0
- data/lib/tdl/axi_lite/lite_cmd.rb +154 -0
- data/lib/tdl/axi_lite/prj_lib.rb +6 -0
- data/lib/tdl/axi_stream/axi_stream_cache_35bit_auto.rb +127 -0
- data/lib/tdl/axi_stream/axi_stream_cache_72_95bit_with_keep_auto.rb +127 -0
- data/lib/tdl/axi_stream/axi_stream_cache_B1_auto.rb +127 -0
- data/lib/tdl/axi_stream/axi_stream_cache_auto.rb +134 -0
- data/lib/tdl/axi_stream/axi_stream_cache_mirror_auto.rb +127 -0
- data/lib/tdl/axi_stream/axi_stream_cache_verb_auto.rb +127 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect.rb +214 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_M2S.rb +85 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_M2S_A1.rb +129 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_M2S_A1_auto.rb +137 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_M2S_auto.rb +93 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_M2S_bind_tuser_auto.rb +137 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_S2M.rb +86 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_S2M_auto.rb +86 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_S2M_auto_auto.rb +91 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_S2M_with_keep.sv_auto.rb +93 -0
- data/lib/tdl/axi_stream/axi_stream_lib.rb +18 -0
- data/lib/tdl/axi_stream/axi_stream_long_cache_auto.rb +137 -0
- data/lib/tdl/axi_stream/axi_stream_long_fifo_auto.rb +146 -0
- data/lib/tdl/axi_stream/axi_stream_long_fifo_verb_auto.rb +146 -0
- data/lib/tdl/axi_stream/axi_stream_packet_fifo_auto.rb +137 -0
- data/lib/tdl/axi_stream/axi_stream_packet_fifo_with_info_auto.rb +164 -0
- data/lib/tdl/axi_stream/axi_stream_partition_A1_auto.rb +145 -0
- data/lib/tdl/axi_stream/axi_stream_partition_auto.rb +154 -0
- data/lib/tdl/axi_stream/axi_stream_wide_fifo_auto.rb +137 -0
- data/lib/tdl/axi_stream/axi_streams_combin_A1_auto.rb +184 -0
- data/lib/tdl/axi_stream/axi_streams_combin_auto.rb +193 -0
- data/lib/tdl/axi_stream/axi_streams_scaler_A1_auto.rb +175 -0
- data/lib/tdl/axi_stream/axi_streams_scaler_auto.rb +184 -0
- data/lib/tdl/axi_stream/axis_append_A1_auto.rb +209 -0
- data/lib/tdl/axi_stream/axis_append_auto.rb +200 -0
- data/lib/tdl/axi_stream/axis_combin_with_fifo_auto.rb +175 -0
- data/lib/tdl/axi_stream/axis_connect_pipe_A1.sv_auto.rb +127 -0
- data/lib/tdl/axi_stream/axis_connect_pipe_auto.rb +127 -0
- data/lib/tdl/axi_stream/axis_connect_pipe_with_info_auto.rb +155 -0
- data/lib/tdl/axi_stream/axis_direct_auto.rb +127 -0
- data/lib/tdl/axi_stream/axis_filter_auto.rb +136 -0
- data/lib/tdl/axi_stream/axis_full_to_data_c_auto.rb +71 -0
- data/lib/tdl/axi_stream/axis_head_cut_auto.rb +137 -0
- data/lib/tdl/axi_stream/axis_length_fill_auto.rb +136 -0
- data/lib/tdl/axi_stream/axis_length_split_auto.rb +136 -0
- data/lib/tdl/axi_stream/axis_length_split_with_addr_auto.rb +164 -0
- data/lib/tdl/axi_stream/axis_length_split_writh_user_auto.rb +136 -0
- data/lib/tdl/axi_stream/axis_link_trigger_auto.rb +93 -0
- data/lib/tdl/axi_stream/axis_master_empty_auto.rb +85 -0
- data/lib/tdl/axi_stream/axis_mirror_to_master_auto.rb +137 -0
- data/lib/tdl/axi_stream/axis_mirrors_auto.rb +173 -0
- data/lib/tdl/axi_stream/axis_pkt_fifo_filter_keep_A1_auto.rb +137 -0
- data/lib/tdl/axi_stream/axis_pkt_fifo_filter_keep_auto.rb +137 -0
- data/lib/tdl/axi_stream/axis_ram_buffer_auto.rb +164 -0
- data/lib/tdl/axi_stream/axis_slaver_empty_auto.rb +68 -0
- data/lib/tdl/axi_stream/axis_slaver_pipe_A1_auto.rb +137 -0
- data/lib/tdl/axi_stream/axis_slaver_pipe_auto.rb +127 -0
- data/lib/tdl/axi_stream/axis_to_axi4_or_lite_auto.rb +87 -0
- data/lib/tdl/axi_stream/axis_to_data_inf_auto.rb +79 -0
- data/lib/tdl/axi_stream/axis_to_lite_rd_auto.rb +87 -0
- data/lib/tdl/axi_stream/axis_to_lite_wr_auto.rb +79 -0
- data/lib/tdl/axi_stream/axis_uncompress_auto.rb +86 -0
- data/lib/tdl/axi_stream/axis_valve_auto.rb +136 -0
- data/lib/tdl/axi_stream/axis_valve_with_pipe_auto.rb +153 -0
- data/lib/tdl/axi_stream/axis_width_combin_A1_auto.rb +127 -0
- data/lib/tdl/axi_stream/axis_width_combin_auto.rb +127 -0
- data/lib/tdl/axi_stream/axis_width_convert_auto.rb +127 -0
- data/lib/tdl/axi_stream/axis_width_destruct_A1.sv_auto.rb +127 -0
- data/lib/tdl/axi_stream/axis_width_destruct_auto.rb +127 -0
- data/lib/tdl/axi_stream/bak/__axi_stream_interconnect_S2M.rb +186 -0
- data/lib/tdl/axi_stream/bak/_axis_mirrors.rb +270 -0
- data/lib/tdl/axi_stream/bak/axi4_to_native_for_ddr_ip_verb_auto.rb +343 -0
- data/lib/tdl/axi_stream/bak/axi_stream_S2M.rb +63 -0
- data/lib/tdl/axi_stream/bak/axi_stream_cache_35bit_auto.rb +138 -0
- data/lib/tdl/axi_stream/bak/axi_stream_cache_72_95bit_with_keep_auto.rb +138 -0
- data/lib/tdl/axi_stream/bak/axi_stream_cache_B1_auto.rb +138 -0
- data/lib/tdl/axi_stream/bak/axi_stream_cache_auto.rb +138 -0
- data/lib/tdl/axi_stream/bak/axi_stream_cache_mirror_auto.rb +138 -0
- data/lib/tdl/axi_stream/bak/axi_stream_cache_verb_auto.rb +138 -0
- data/lib/tdl/axi_stream/bak/axi_stream_interconnect_S2M_auto.rb +147 -0
- data/lib/tdl/axi_stream/bak/axi_stream_interconnect_S2M_with_keep.sv_auto.rb +166 -0
- data/lib/tdl/axi_stream/bak/axi_stream_long_fifo_auto.rb +177 -0
- data/lib/tdl/axi_stream/bak/axi_stream_packet_fifo_auto.rb +158 -0
- data/lib/tdl/axi_stream/bak/axi_stream_packet_fifo_with_info_auto.rb +215 -0
- data/lib/tdl/axi_stream/bak/axi_stream_partition_A1_auto.rb +176 -0
- data/lib/tdl/axi_stream/bak/axi_stream_partition_auto.rb +195 -0
- data/lib/tdl/axi_stream/bak/axi_streams_combin_auto.rb +274 -0
- data/lib/tdl/axi_stream/bak/axi_streams_scaler.rb +300 -0
- data/lib/tdl/axi_stream/bak/axi_streams_scaler_auto.rb +255 -0
- data/lib/tdl/axi_stream/bak/axis_append_A1.rb +265 -0
- data/lib/tdl/axi_stream/bak/axis_append_A1_auto.rb +310 -0
- data/lib/tdl/axi_stream/bak/axis_append_auto.rb +291 -0
- data/lib/tdl/axi_stream/bak/axis_combin_with_fifo_auto.rb +236 -0
- data/lib/tdl/axi_stream/bak/axis_connect_pipe.rb.bak +207 -0
- data/lib/tdl/axi_stream/bak/axis_connect_pipe_A1.sv_auto.rb +138 -0
- data/lib/tdl/axi_stream/bak/axis_connect_pipe_auto.rb +138 -0
- data/lib/tdl/axi_stream/bak/axis_connect_pipe_with_info_auto.rb +196 -0
- data/lib/tdl/axi_stream/bak/axis_direct_auto.rb +138 -0
- data/lib/tdl/axi_stream/bak/axis_filter_auto.rb +157 -0
- data/lib/tdl/axi_stream/bak/axis_length_fill_auto.rb +157 -0
- data/lib/tdl/axi_stream/bak/axis_length_split_auto.rb +157 -0
- data/lib/tdl/axi_stream/bak/axis_length_split_with_addr_auto.rb +215 -0
- data/lib/tdl/axi_stream/bak/axis_master_empty_auto.rb +95 -0
- data/lib/tdl/axi_stream/bak/axis_mirrors_auto.rb +234 -0
- data/lib/tdl/axi_stream/bak/axis_pkt_fifo_filter_keep_auto.rb +158 -0
- data/lib/tdl/axi_stream/bak/axis_ram_buffer_auto.rb +215 -0
- data/lib/tdl/axi_stream/bak/axis_slaver_empty_auto.rb +88 -0
- data/lib/tdl/axi_stream/bak/axis_slaver_pipe_A1_auto.rb +158 -0
- data/lib/tdl/axi_stream/bak/axis_slaver_pipe_auto.rb +138 -0
- data/lib/tdl/axi_stream/bak/axis_to_axi4_wr_auto.rb +205 -0
- data/lib/tdl/axi_stream/bak/axis_to_data_inf_auto.rb +108 -0
- data/lib/tdl/axi_stream/bak/axis_uncompress_auto.rb +147 -0
- data/lib/tdl/axi_stream/bak/axis_valve_auto.rb +157 -0
- data/lib/tdl/axi_stream/bak/axis_valve_with_pipe_auto.rb +157 -0
- data/lib/tdl/axi_stream/bak/axis_width_combin_auto.rb +138 -0
- data/lib/tdl/axi_stream/bak/axis_width_convert_auto.rb +138 -0
- data/lib/tdl/axi_stream/bak/axis_width_destruct_auto.rb +138 -0
- data/lib/tdl/axi_stream/bak/axis_wrapper_oled_auto.rb +230 -0
- data/lib/tdl/axi_stream/bak/check_stream_crc_auto.rb +88 -0
- data/lib/tdl/axi_stream/bak/data_to_axis_inf_A1.rb +129 -0
- data/lib/tdl/axi_stream/bak/data_to_axis_inf_A1_auto.rb +127 -0
- data/lib/tdl/axi_stream/bak/data_to_axis_inf_auto.rb +146 -0
- data/lib/tdl/axi_stream/bak/datainf_c_master_empty_auto.rb +115 -0
- data/lib/tdl/axi_stream/bak/datainf_c_slaver_empty_auto.rb +108 -0
- data/lib/tdl/axi_stream/bak/datainf_master_empty_auto.rb +115 -0
- data/lib/tdl/axi_stream/bak/datainf_slaver_empty_auto.rb +108 -0
- data/lib/tdl/axi_stream/bak/dynamic_port_cfg_auto.rb +246 -0
- data/lib/tdl/axi_stream/bak/dynnamic_addr_cfg_auto.rb +200 -0
- data/lib/tdl/axi_stream/bak/gen_big_field_table_auto.rb +210 -0
- data/lib/tdl/axi_stream/bak/gen_origin_axis_auto.rb +172 -0
- data/lib/tdl/axi_stream/bak/gen_simple_axis_auto.rb +191 -0
- data/lib/tdl/axi_stream/bak/idata_pool_axi4_auto.rb +346 -0
- data/lib/tdl/axi_stream/bak/parse_big_field_table_A1_auto.rb +292 -0
- data/lib/tdl/axi_stream/bak/parse_big_field_table_A2_auto.rb +292 -0
- data/lib/tdl/axi_stream/bak/parse_big_field_table_auto.rb +292 -0
- data/lib/tdl/axi_stream/bak/part_data_pair_map_auto.rb +362 -0
- data/lib/tdl/axi_stream/bak/simple_video_gen_A2.rb +146 -0
- data/lib/tdl/axi_stream/bak/simple_video_gen_A2_auto.rb +151 -0
- data/lib/tdl/axi_stream/bak/stream_crc_auto.rb +107 -0
- data/lib/tdl/axi_stream/bak/udp_server_bfm_auto.rb +131 -0
- data/lib/tdl/axi_stream/bak/udp_server_ctrl_bfm_auto.rb +131 -0
- data/lib/tdl/axi_stream/bak/video_to_VDMA.rb +153 -0
- data/lib/tdl/axi_stream/bak/video_to_VDMA_auto.rb +158 -0
- data/lib/tdl/axi_stream/check_stream_crc_auto.rb +63 -0
- data/lib/tdl/axi_stream/data_c_to_axis_full_auto.rb +71 -0
- data/lib/tdl/axi_stream/data_to_axis_inf_A1_auto.rb +78 -0
- data/lib/tdl/axi_stream/data_to_axis_inf_auto.rb +85 -0
- data/lib/tdl/axi_stream/gen_big_field_table_auto.rb +140 -0
- data/lib/tdl/axi_stream/gen_origin_axis_A1_auto.rb +131 -0
- data/lib/tdl/axi_stream/gen_origin_axis_auto.rb +122 -0
- data/lib/tdl/axi_stream/gen_simple_axis_auto.rb +131 -0
- data/lib/tdl/axi_stream/parse_big_field_table_A1_auto.rb +201 -0
- data/lib/tdl/axi_stream/parse_big_field_table_A2_auto.rb +201 -0
- data/lib/tdl/axi_stream/parse_big_field_table_auto.rb +201 -0
- data/lib/tdl/axi_stream/stream_crc_auto.rb +70 -0
- data/lib/tdl/basefunc.rb +338 -0
- data/lib/tdl/bfm/axi4_illegal_bfm.rb +203 -0
- data/lib/tdl/bfm/axi_stream/axi_stream_bfm.rb +351 -0
- data/lib/tdl/bfm/axi_stream/axis_bfm_exp.yml +38 -0
- data/lib/tdl/bfm/axi_stream/axis_bfm_module_build.rb +120 -0
- data/lib/tdl/bfm/axi_stream/axis_bfm_parse.rb +10 -0
- data/lib/tdl/bfm/axi_stream/axis_slice_to_logic.rb +71 -0
- data/lib/tdl/bfm/bfm_lib.rb +7 -0
- data/lib/tdl/bfm/logic_initial_block.rb +52 -0
- data/lib/tdl/cfg.yml +4 -0
- data/lib/tdl/class_hdl/hdl_always_comb.rb +54 -0
- data/lib/tdl/class_hdl/hdl_always_ff.rb +175 -0
- data/lib/tdl/class_hdl/hdl_assign.rb +49 -0
- data/lib/tdl/class_hdl/hdl_block_ifelse.rb +349 -0
- data/lib/tdl/class_hdl/hdl_data.rb +24 -0
- data/lib/tdl/class_hdl/hdl_ex_defarraychain.rb +231 -0
- data/lib/tdl/class_hdl/hdl_foreach.rb +114 -0
- data/lib/tdl/class_hdl/hdl_function.rb +277 -0
- data/lib/tdl/class_hdl/hdl_generate.rb +218 -0
- data/lib/tdl/class_hdl/hdl_initial.rb +147 -0
- data/lib/tdl/class_hdl/hdl_module_def.rb +447 -0
- data/lib/tdl/class_hdl/hdl_package.rb +150 -0
- data/lib/tdl/class_hdl/hdl_parameter.rb +73 -0
- data/lib/tdl/class_hdl/hdl_random.rb +31 -0
- data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +653 -0
- data/lib/tdl/class_hdl/hdl_struct.rb +209 -0
- data/lib/tdl/class_hdl/hdl_verify.rb +136 -0
- data/lib/tdl/data_inf/_data_mirrors.rb +92 -0
- data/lib/tdl/data_inf/bak/_data_mirrors.rb +273 -0
- data/lib/tdl/data_inf/bak/common_fifo_auto.rb +279 -0
- data/lib/tdl/data_inf/bak/data_bind_auto.rb +128 -0
- data/lib/tdl/data_inf/bak/data_c_direct_auto.rb +138 -0
- data/lib/tdl/data_inf/bak/data_c_direct_mirror_auto.rb +138 -0
- data/lib/tdl/data_inf/bak/data_c_tmp_cache_auto.rb +138 -0
- data/lib/tdl/data_inf/bak/data_condition_mirror_auto.rb +216 -0
- data/lib/tdl/data_inf/bak/data_condition_valve_auto.rb +215 -0
- data/lib/tdl/data_inf/bak/data_connect_pipe.rb +80 -0
- data/lib/tdl/data_inf/bak/data_connect_pipe_inf_auto.rb +138 -0
- data/lib/tdl/data_inf/bak/data_inf_c_interconnect.rb +86 -0
- data/lib/tdl/data_inf/bak/data_inf_c_pipe_condition_auto.rb +157 -0
- data/lib/tdl/data_inf/bak/data_inf_cross_clk.rb +60 -0
- data/lib/tdl/data_inf/bak/data_inf_interconnect.rb +144 -0
- data/lib/tdl/data_inf/bak/data_inf_planer.rb +78 -0
- data/lib/tdl/data_inf/bak/data_inf_ticktack.rb +80 -0
- data/lib/tdl/data_inf/bak/data_inf_ticktock_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_mirrors_auto.rb +234 -0
- data/lib/tdl/data_inf/bak/data_mirrors_verb.sv_auto.rb +234 -0
- data/lib/tdl/data_inf/bak/data_uncompress_auto.rb +177 -0
- data/lib/tdl/data_inf/bak/data_valve_auto.rb +127 -0
- data/lib/tdl/data_inf/bak/datainf_c_master_empty_auto.rb +95 -0
- data/lib/tdl/data_inf/bak/datainf_c_slaver_empty_auto.rb +88 -0
- data/lib/tdl/data_inf/bak/datainf_master_empty_auto.rb +95 -0
- data/lib/tdl/data_inf/bak/datainf_slaver_empty_auto.rb +88 -0
- data/lib/tdl/data_inf/bak/independent_clock_fifo_auto.rb +298 -0
- data/lib/tdl/data_inf/bak/part_data_pair_map_auto.rb +306 -0
- data/lib/tdl/data_inf/common_fifo_auto.rb +141 -0
- data/lib/tdl/data_inf/data_bind_auto.rb +79 -0
- data/lib/tdl/data_inf/data_c_cache_auto.rb +135 -0
- data/lib/tdl/data_inf/data_c_direct_auto.rb +127 -0
- data/lib/tdl/data_inf/data_c_direct_mirror_auto.rb +127 -0
- data/lib/tdl/data_inf/data_c_interconnect.rb +97 -0
- data/lib/tdl/data_inf/data_c_pipe_force_vld_auto.rb +127 -0
- data/lib/tdl/data_inf/data_c_pipe_inf_auto.rb +127 -0
- data/lib/tdl/data_inf/data_c_pipe_intc_M2S_verc_auto.rb +123 -0
- data/lib/tdl/data_inf/data_c_tmp_cache_auto.rb +127 -0
- data/lib/tdl/data_inf/data_condition_mirror_auto.rb +165 -0
- data/lib/tdl/data_inf/data_condition_valve_auto.rb +164 -0
- data/lib/tdl/data_inf/data_connect_pipe_inf_auto.rb +127 -0
- data/lib/tdl/data_inf/data_inf_c_pipe_condition_auto.rb +136 -0
- data/lib/tdl/data_inf/data_mirrors_auto.rb +173 -0
- data/lib/tdl/data_inf/data_mirrors_verb.sv_auto.rb +173 -0
- data/lib/tdl/data_inf/data_uncompress_auto.rb +146 -0
- data/lib/tdl/data_inf/data_valve_auto.rb +104 -0
- data/lib/tdl/data_inf/datainf_c_master_empty_auto.rb +85 -0
- data/lib/tdl/data_inf/datainf_c_slaver_empty_auto.rb +68 -0
- data/lib/tdl/data_inf/datainf_master_empty_auto.rb +85 -0
- data/lib/tdl/data_inf/datainf_slaver_empty_auto.rb +68 -0
- data/lib/tdl/data_inf/independent_clock_fifo_auto.rb +141 -0
- data/lib/tdl/data_inf/part_data_pair_map_auto.rb +149 -0
- data/lib/tdl/data_inf/path_lib.rb +18 -0
- data/lib/tdl/elements/Reset.rb +153 -0
- data/lib/tdl/elements/axi4.rb +642 -0
- data/lib/tdl/elements/axi_lite.rb +246 -0
- data/lib/tdl/elements/axi_stream.rb +674 -0
- data/lib/tdl/elements/clock.rb +193 -0
- data/lib/tdl/elements/common_configure_reg.rb +135 -0
- data/lib/tdl/elements/data_inf.rb +660 -0
- data/lib/tdl/elements/logic.rb +356 -0
- data/lib/tdl/elements/mail_box.rb +64 -0
- data/lib/tdl/elements/originclass.rb +689 -0
- data/lib/tdl/elements/parameter.rb +318 -0
- data/lib/tdl/elements/track_inf.rb +163 -0
- data/lib/tdl/elements/videoinf.rb +224 -0
- data/lib/tdl/examples/10_random/exp_random.rb +13 -0
- data/lib/tdl/examples/10_random/exp_random.sv +36 -0
- data/lib/tdl/examples/11_test_unit/dve.tcl +64 -0
- data/lib/tdl/examples/11_test_unit/exp_test_unit.rb +58 -0
- data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +35 -0
- data/lib/tdl/examples/11_test_unit/exp_test_unit_constraints.xdc +25 -0
- data/lib/tdl/examples/11_test_unit/modules/sub_md0.rb +23 -0
- data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +41 -0
- data/lib/tdl/examples/11_test_unit/modules/sub_md1.rb +25 -0
- data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv +41 -0
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +28 -0
- data/lib/tdl/examples/11_test_unit/tu0.sv +38 -0
- data/lib/tdl/examples/11_test_unit/tu1.sv +28 -0
- data/lib/tdl/examples/1_define_module/example1.rb +39 -0
- data/lib/tdl/examples/1_define_module/exmple_md.sv +50 -0
- data/lib/tdl/examples/2_hdl_class/always_comb.rb +99 -0
- data/lib/tdl/examples/2_hdl_class/always_ff.rb +143 -0
- data/lib/tdl/examples/2_hdl_class/case.rb +93 -0
- data/lib/tdl/examples/2_hdl_class/foreach.rb +21 -0
- data/lib/tdl/examples/2_hdl_class/function.rb +34 -0
- data/lib/tdl/examples/2_hdl_class/generate.rb +62 -0
- data/lib/tdl/examples/2_hdl_class/module_def.rb +33 -0
- data/lib/tdl/examples/2_hdl_class/module_head_import_package.rb +36 -0
- data/lib/tdl/examples/2_hdl_class/module_instance_test.rb +13 -0
- data/lib/tdl/examples/2_hdl_class/package.rb +29 -0
- data/lib/tdl/examples/2_hdl_class/package2.rb +21 -0
- data/lib/tdl/examples/2_hdl_class/simple_assign.rb +39 -0
- data/lib/tdl/examples/2_hdl_class/state_case.rb +65 -0
- data/lib/tdl/examples/2_hdl_class/struct.rb +25 -0
- data/lib/tdl/examples/2_hdl_class/struct_function.rb +28 -0
- data/lib/tdl/examples/2_hdl_class/test_axi4_M2S.rb +16 -0
- data/lib/tdl/examples/2_hdl_class/test_initial_assert.rb +11 -0
- data/lib/tdl/examples/2_hdl_class/test_inst_sugar.rb +28 -0
- data/lib/tdl/examples/2_hdl_class/test_module_port.rb +47 -0
- data/lib/tdl/examples/2_hdl_class/test_module_var.rb +18 -0
- data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv +108 -0
- data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +35 -0
- data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv +105 -0
- data/lib/tdl/examples/2_hdl_class/tmp/head_pkg_module.sv +42 -0
- data/lib/tdl/examples/2_hdl_class/tmp/init_module.sv +110 -0
- data/lib/tdl/examples/2_hdl_class/tmp/module_instance_test.sv +31 -0
- data/lib/tdl/examples/2_hdl_class/tmp/port_module.sv +99 -0
- data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv +27 -0
- data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv +78 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_axi4_M2S.sv +30 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_foreach.sv +34 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_function.sv +52 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_initial_assert.sv +31 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_inst_sugar.sv +42 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +36 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_port.sv +33 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +35 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +38 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_package2.sv +36 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_struct.sv +38 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_struct_function.sv +44 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +27 -0
- data/lib/tdl/examples/2_hdl_class/tmp/text_generate.sv +54 -0
- data/lib/tdl/examples/2_hdl_class/vcs_string.rb +5 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/hdl_test.sv +13 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/main.rb +26 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/main_md.sv +42 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/sdl_md.sv +30 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/sdl_test.rb +9 -0
- data/lib/tdl/examples/4_generate/example.rb +38 -0
- data/lib/tdl/examples/4_generate/test_generate.sv +59 -0
- data/lib/tdl/examples/5_logic_combin/login_combin.rb +22 -0
- data/lib/tdl/examples/5_logic_combin/test_logic_combin.sv +36 -0
- data/lib/tdl/examples/6_module_with_interface/example.rb +48 -0
- data/lib/tdl/examples/6_module_with_interface/example_interface.sv +40 -0
- data/lib/tdl/examples/6_module_with_interface/inf_collect.rb +54 -0
- data/lib/tdl/examples/6_module_with_interface/inf_collect.sv +63 -0
- data/lib/tdl/examples/7_module_with_package/body_package.rb +3 -0
- data/lib/tdl/examples/7_module_with_package/body_package.sv +25 -0
- data/lib/tdl/examples/7_module_with_package/example_pkg.rb +20 -0
- data/lib/tdl/examples/7_module_with_package/example_pkg.sv +35 -0
- data/lib/tdl/examples/7_module_with_package/head_package.rb +8 -0
- data/lib/tdl/examples/7_module_with_package/head_package.sv +29 -0
- data/lib/tdl/examples/8_top_module/dve.tcl +64 -0
- data/lib/tdl/examples/8_top_module/example.rb +8 -0
- data/lib/tdl/examples/8_top_module/pins.yml +7 -0
- data/lib/tdl/examples/8_top_module/tb_test_top.sv +29 -0
- data/lib/tdl/examples/8_top_module/test_top.sv +28 -0
- data/lib/tdl/examples/8_top_module/test_top_constraints.xdc +37 -0
- data/lib/tdl/examples/9_itegration/A_itgt/a_test_md.sv +29 -0
- data/lib/tdl/examples/9_itegration/A_itgt/a_test_module.rb +6 -0
- data/lib/tdl/examples/9_itegration/A_itgt/itgt_module_a_block.rb +34 -0
- data/lib/tdl/examples/9_itegration/clock_manage/itgt_module_clock_manage.rb +33 -0
- data/lib/tdl/examples/9_itegration/clock_manage/simple_clock.rb +7 -0
- data/lib/tdl/examples/9_itegration/clock_manage/simple_clock.sv +29 -0
- data/lib/tdl/examples/9_itegration/dve.tcl +64 -0
- data/lib/tdl/examples/9_itegration/pins.yml +4 -0
- data/lib/tdl/examples/9_itegration/tb_test_top.sv +29 -0
- data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +29 -0
- data/lib/tdl/examples/9_itegration/test_top.sv +40 -0
- data/lib/tdl/examples/9_itegration/test_top_constraints.xdc +29 -0
- data/lib/tdl/examples/9_itegration/test_tttop.sv +40 -0
- data/lib/tdl/examples/9_itegration/test_tttop_constraints.xdc +29 -0
- data/lib/tdl/examples/9_itegration/top.rb +11 -0
- data/lib/tdl/examples/readme.md +31 -0
- data/lib/tdl/exlib/common_cfg_reg_inf.rb +139 -0
- data/lib/tdl/exlib/constraints.rb +286 -0
- data/lib/tdl/exlib/constraints_verb.rb +304 -0
- data/lib/tdl/exlib/dve_tcl.rb +162 -0
- data/lib/tdl/exlib/element_class_vars.rb +106 -0
- data/lib/tdl/exlib/global_param.rb +108 -0
- data/lib/tdl/exlib/integral_test/bak/integral_test.rb +206 -0
- data/lib/tdl/exlib/integral_test/clock_itest.rb +28 -0
- data/lib/tdl/exlib/integral_test/diff_clock_itest.rb +30 -0
- data/lib/tdl/exlib/integral_test/io_itest.rb +41 -0
- data/lib/tdl/exlib/integral_test/reset_itest.rb +31 -0
- data/lib/tdl/exlib/integral_test/simple_logic_itest.rb +19 -0
- data/lib/tdl/exlib/itegration.rb +307 -0
- data/lib/tdl/exlib/itegration_verb.rb +913 -0
- data/lib/tdl/exlib/parse_argv.rb +43 -0
- data/lib/tdl/exlib/sdlmodule_sim.bak.rb +375 -0
- data/lib/tdl/exlib/test_point.rb +287 -0
- data/lib/tdl/global_scan.rb +134 -0
- data/lib/tdl/rebuild_ele/axi4.rb +141 -0
- data/lib/tdl/rebuild_ele/axi_lite.rb +56 -0
- data/lib/tdl/rebuild_ele/axi_stream.rb +121 -0
- data/lib/tdl/rebuild_ele/cm_ram_inf.sv +105 -0
- data/lib/tdl/rebuild_ele/cm_ram_inf_define.rb +44 -0
- data/lib/tdl/rebuild_ele/data_inf.rb +27 -0
- data/lib/tdl/rebuild_ele/data_inf_c.rb +83 -0
- data/lib/tdl/rebuild_ele/ele_base.rb +822 -0
- data/lib/tdl/rebuild_ele/readme.md +1 -0
- data/lib/tdl/sdlimplement/resource.yml +154 -0
- data/lib/tdl/sdlimplement/sdl_impl_module.rb +391 -0
- data/lib/tdl/sdlimplement/sdl_impl_param.rb +26 -0
- data/lib/tdl/sdlimplement/test.rb +64 -0
- data/lib/tdl/sdlmodule/bak/sdlmodule_varible_ex.rb +120 -0
- data/lib/tdl/sdlmodule/generator_block_module.rb +84 -0
- data/lib/tdl/sdlmodule/sdlmodule.rb +407 -0
- data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb +333 -0
- data/lib/tdl/sdlmodule/sdlmodule_draw.rb +272 -0
- data/lib/tdl/sdlmodule/sdlmodule_head_logo.txt +10 -0
- data/lib/tdl/sdlmodule/sdlmodule_instance.rb +623 -0
- data/lib/tdl/sdlmodule/sdlmodule_port_define.rb +374 -0
- data/lib/tdl/sdlmodule/sdlmodule_varible.rb +160 -0
- data/lib/tdl/sdlmodule/sdlmodule_vcs_comptable.rb +140 -0
- data/lib/tdl/sdlmodule/techbench_module.rb +14 -0
- data/lib/tdl/sdlmodule/test_unit_module.rb +138 -0
- data/lib/tdl/sdlmodule/top_module.rb +543 -0
- data/lib/tdl/tdl.rb +265 -0
- data/lib/tdl/tdlerror/tdlerror.rb +8 -0
- data/lib/tdl/testunit/test_all.rb +4 -0
- data/lib/tdl/testunit/test_array_chain.rb +89 -0
- data/lib/tdl/testunit/test_tmp.rb +47 -0
- metadata +1301 -0
@@ -0,0 +1,64 @@
|
|
1
|
+
|
2
|
+
## 设置时间精度 1ps
|
3
|
+
gui_set_time_units 1ps
|
4
|
+
|
5
|
+
## 创建一个 group 名字为 test_gg
|
6
|
+
# set _wave_session_group Group1
|
7
|
+
# set _wave_session_group [gui_sg_generate_new_name -seed test_gg]
|
8
|
+
|
9
|
+
# set Group2 "$_wave_session_group"
|
10
|
+
|
11
|
+
## 添加信号到 group
|
12
|
+
## gui_sg_addsignal -group "$_wave_session_group" { {Sim:tb_Mammo_TCP_sim.g1_test_mac_1g_inst.test_fpga_version_inst.ctrl_udp_rd_version} {Sim:tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.to_ctrl_tap_in_inf} {Sim:tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.ctrl_tap_inf} {Sim:tb_Mammo_TCP_sim.g1_test_mac_1g_inst.tcp_udp_proto_workshop_1G_inst.genblk1[0].tcp_data_stack_top_inst.client_port} }
|
13
|
+
## ==== [add_signal] ===== ##
|
14
|
+
|
15
|
+
|
16
|
+
## 创建波形窗口
|
17
|
+
if {![info exists useOldWindow]} {
|
18
|
+
set useOldWindow true
|
19
|
+
}
|
20
|
+
|
21
|
+
if {$useOldWindow && [string first "Wave" [gui_get_current_window -view]]==0} {
|
22
|
+
set Wave.3 [gui_get_current_window -view]
|
23
|
+
} else {
|
24
|
+
set Wave.3 [lindex [gui_get_window_ids -type Wave] 0]
|
25
|
+
if {[string first "Wave" ${Wave.3}]!=0} {
|
26
|
+
gui_open_window Wave
|
27
|
+
set Wave.3 [ gui_get_current_window -view ]
|
28
|
+
}
|
29
|
+
}
|
30
|
+
|
31
|
+
set groupExD [gui_get_pref_value -category Wave -key exclusiveSG]
|
32
|
+
gui_set_pref_value -category Wave -key exclusiveSG -value {false}
|
33
|
+
set origWaveHeight [gui_get_pref_value -category Wave -key waveRowHeight]
|
34
|
+
gui_list_set_height -id Wave -height 25
|
35
|
+
set origGroupCreationState [gui_list_create_group_when_add -wave]
|
36
|
+
gui_list_create_group_when_add -wave -disable
|
37
|
+
gui_marker_set_ref -id ${Wave.3} C1
|
38
|
+
gui_wv_zoom_timerange -id ${Wave.3} 0 1000000000
|
39
|
+
## gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2}]
|
40
|
+
## gui_list_add_group -id ${Wave.3} -after ${Group2} [list ${Group2|tx_inf}]
|
41
|
+
## gui_list_expand -id ${Wave.3} tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.ctrl_tap_inf
|
42
|
+
## === [add_signal_wave] === ##
|
43
|
+
|
44
|
+
|
45
|
+
gui_seek_criteria -id ${Wave.3} {Any Edge}
|
46
|
+
|
47
|
+
|
48
|
+
gui_set_pref_value -category Wave -key exclusiveSG -value $groupExD
|
49
|
+
gui_list_set_height -id Wave -height $origWaveHeight
|
50
|
+
if {$origGroupCreationState} {
|
51
|
+
gui_list_create_group_when_add -wave -enable
|
52
|
+
}
|
53
|
+
if { $groupExD } {
|
54
|
+
gui_msg_report -code DVWW028
|
55
|
+
}
|
56
|
+
gui_list_set_filter -id ${Wave.3} -list { {Buffer 1} {Input 1} {Others 1} {Linkage 1} {Output 1} {Parameter 1} {All 1} {Aggregate 1} {LibBaseMember 1} {Event 1} {Assertion 1} {Constant 1} {Interface 1} {BaseMembers 1} {Signal 1} {$unit 1} {Inout 1} {Variable 1} }
|
57
|
+
gui_list_set_filter -id ${Wave.3} -text {*}
|
58
|
+
##gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2} -position in
|
59
|
+
## === [add_bar] === ##
|
60
|
+
|
61
|
+
|
62
|
+
gui_marker_move -id ${Wave.3} {C1} 560248001
|
63
|
+
gui_view_scroll -id ${Wave.3} -vertical -set 35
|
64
|
+
gui_show_grid -id ${Wave.3} -enable false
|
@@ -0,0 +1,29 @@
|
|
1
|
+
/**********************************************
|
2
|
+
_______________________________________
|
3
|
+
___________ Cook Darwin __________
|
4
|
+
_______________________________________
|
5
|
+
descript:
|
6
|
+
author : Cook.Darwin
|
7
|
+
Version: VERA.0.0
|
8
|
+
created: xxxx.xx.xx
|
9
|
+
madified:
|
10
|
+
***********************************************/
|
11
|
+
`timescale 1ns/1ps
|
12
|
+
|
13
|
+
module tb_test_top();
|
14
|
+
//==========================================================================
|
15
|
+
//-------- define ----------------------------------------------------------
|
16
|
+
logic gl_clk;
|
17
|
+
|
18
|
+
//==========================================================================
|
19
|
+
//-------- instance --------------------------------------------------------
|
20
|
+
test_top rtl_top(
|
21
|
+
/* input clock */.global_sys_clk (gl_clk )
|
22
|
+
);
|
23
|
+
//==========================================================================
|
24
|
+
//-------- expression ------------------------------------------------------
|
25
|
+
initial begin
|
26
|
+
forever begin #(33ns);gl_clk = ~gl_clk;end;
|
27
|
+
end
|
28
|
+
|
29
|
+
endmodule
|
@@ -0,0 +1,29 @@
|
|
1
|
+
/**********************************************
|
2
|
+
_______________________________________
|
3
|
+
___________ Cook Darwin __________
|
4
|
+
_______________________________________
|
5
|
+
descript:
|
6
|
+
author : Cook.Darwin
|
7
|
+
Version: VERA.0.0
|
8
|
+
created: xxxx.xx.xx
|
9
|
+
madified:
|
10
|
+
***********************************************/
|
11
|
+
`timescale 1ns/1ps
|
12
|
+
|
13
|
+
module tb_test_tttop();
|
14
|
+
//==========================================================================
|
15
|
+
//-------- define ----------------------------------------------------------
|
16
|
+
logic gl_clk;
|
17
|
+
|
18
|
+
//==========================================================================
|
19
|
+
//-------- instance --------------------------------------------------------
|
20
|
+
test_tttop rtl_top(
|
21
|
+
/* input clock */.global_sys_clk (gl_clk )
|
22
|
+
);
|
23
|
+
//==========================================================================
|
24
|
+
//-------- expression ------------------------------------------------------
|
25
|
+
initial begin
|
26
|
+
forever begin #(33ns);gl_clk = ~gl_clk;end;
|
27
|
+
end
|
28
|
+
|
29
|
+
endmodule
|
@@ -0,0 +1,40 @@
|
|
1
|
+
/**********************************************
|
2
|
+
_______________________________________
|
3
|
+
___________ Cook Darwin __________
|
4
|
+
_______________________________________
|
5
|
+
descript:
|
6
|
+
author : Cook.Darwin
|
7
|
+
Version: VERA.0.0
|
8
|
+
created: xxxx.xx.xx
|
9
|
+
madified:
|
10
|
+
***********************************************/
|
11
|
+
`timescale 1ns/1ps
|
12
|
+
|
13
|
+
module test_top (
|
14
|
+
input global_sys_clk
|
15
|
+
);
|
16
|
+
|
17
|
+
//==========================================================================
|
18
|
+
//-------- define ----------------------------------------------------------
|
19
|
+
logic clock_100M;
|
20
|
+
logic rstn_100M;
|
21
|
+
axi_stream_inf #(.DSIZE(16),.USIZE(1)) x_origin_inf (.aclk(clock_100M),.aresetn(rstn_100M),.aclken(1'b1)) ;
|
22
|
+
//==========================================================================
|
23
|
+
//-------- instance --------------------------------------------------------
|
24
|
+
simple_clock simple_clock_inst(
|
25
|
+
/* input clock */.sys_clk (global_sys_clk ),
|
26
|
+
/* output clock */.clock (clock_100M ),
|
27
|
+
/* output reset */.rst_n (rstn_100M )
|
28
|
+
);
|
29
|
+
a_test_md a_test_md_inst(
|
30
|
+
/* input clock */.clock (clock_100M ),
|
31
|
+
/* input reset */.rst (~rstn_100M ),
|
32
|
+
/* axi_stream_inf.master */.origin_inf (x_origin_inf )
|
33
|
+
);
|
34
|
+
//==========================================================================
|
35
|
+
//-------- expression ------------------------------------------------------
|
36
|
+
assign x_origin_inf.axis_tvalid = 1'b0;
|
37
|
+
assign x_origin_inf.axis_tdata = '0;
|
38
|
+
assign x_origin_inf.axis_tlast = 1'b0;
|
39
|
+
|
40
|
+
endmodule
|
@@ -0,0 +1,29 @@
|
|
1
|
+
##-------------------------- CLOCK SET ---------------------------------- ##
|
2
|
+
set_system_jitter 0.1
|
3
|
+
create_clock -period 33.058 -name global_sys_clk -waveform {0.000 16.529} [get_ports global_sys_clk]
|
4
|
+
# set_input_jitter [get_clocks -of_objects [get_ports global_sys_clk]] 0.01
|
5
|
+
##========================== CLOCK SET ================================== ##
|
6
|
+
##-------------------------- PIN SET ---------------------------------- ##
|
7
|
+
set_property PACKAGE_PIN C7 [get_ports global_sys_clk]
|
8
|
+
set_property IOSTANDARD LVCMOS18 [get_ports global_sys_clk]
|
9
|
+
##========================== PIN SET ================================== ##
|
10
|
+
|
11
|
+
## -------------------------- FALSE PATH SET ---------------------------------- ##
|
12
|
+
# set_false_path -from [get_pins -hier -regexp .*cross_clk.*ltc.*] -to [all_registers]
|
13
|
+
set_max_delay -from [get_pins -hier -regexp .*cross_clk.*ltc.*] -to [all_registers] 20.00
|
14
|
+
## set_false_path -from [get_pins -hierarchical "*cross_clk*"] -to [all_registers]
|
15
|
+
# set_false_path -from [all_registers] -to [get_pins -hier -regexp .*cross_clk.*ltc.*]
|
16
|
+
set_max_delay -from [all_registers] -to [get_pins -hier -regexp .*cross_clk.*ltc.*] 20.00
|
17
|
+
## set_false_path -from [all_registers] -to [get_pins -hierarchical "*cross_clk*"]
|
18
|
+
|
19
|
+
# set_false_path -from [get_pins -hier -regexp .*xilinx_reset_sync.*reset_sync.*] -to [all_registers]
|
20
|
+
set_max_delay -from [get_pins -hier -regexp .*xilinx_reset_sync.*reset_sync.*] -to [all_registers] 40.000
|
21
|
+
## set_false_path -from [get_pins -hierarchical "*xilinx_reset_sync*reset_sync*"] -to [all_registers]
|
22
|
+
|
23
|
+
## ========================== FALSE PATH SET =================================== ##
|
24
|
+
## -------------------------- EX SET ---------------------------------- ##
|
25
|
+
|
26
|
+
## ========================== EX SET =================================== ##
|
27
|
+
## -------------------------- BITSTREAM SET ---------------------------------- ##
|
28
|
+
|
29
|
+
## ========================== BITSTREAM SET =================================== ##
|
@@ -0,0 +1,40 @@
|
|
1
|
+
/**********************************************
|
2
|
+
_______________________________________
|
3
|
+
___________ Cook Darwin __________
|
4
|
+
_______________________________________
|
5
|
+
descript:
|
6
|
+
author : Cook.Darwin
|
7
|
+
Version: VERA.0.0
|
8
|
+
created: xxxx.xx.xx
|
9
|
+
madified:
|
10
|
+
***********************************************/
|
11
|
+
`timescale 1ns/1ps
|
12
|
+
|
13
|
+
module test_tttop (
|
14
|
+
input global_sys_clk
|
15
|
+
);
|
16
|
+
|
17
|
+
//==========================================================================
|
18
|
+
//-------- define ----------------------------------------------------------
|
19
|
+
logic clock_100M;
|
20
|
+
logic rstn_100M;
|
21
|
+
axi_stream_inf #(.DSIZE(16),.USIZE(1)) x_origin_inf (.aclk(clock_100M),.aresetn(rstn_100M),.aclken(1'b1)) ;
|
22
|
+
//==========================================================================
|
23
|
+
//-------- instance --------------------------------------------------------
|
24
|
+
simple_clock simple_clock_inst(
|
25
|
+
/* input clock */.sys_clk (global_sys_clk ),
|
26
|
+
/* output clock */.clock (clock_100M ),
|
27
|
+
/* output reset */.rst_n (rstn_100M )
|
28
|
+
);
|
29
|
+
a_test_md a_test_md_inst(
|
30
|
+
/* input clock */.clock (clock_100M ),
|
31
|
+
/* input reset */.rst (~rstn_100M ),
|
32
|
+
/* axi_stream_inf.master */.origin_inf (x_origin_inf )
|
33
|
+
);
|
34
|
+
//==========================================================================
|
35
|
+
//-------- expression ------------------------------------------------------
|
36
|
+
assign x_origin_inf.axis_tvalid = 1'b0;
|
37
|
+
assign x_origin_inf.axis_tdata = '0;
|
38
|
+
assign x_origin_inf.axis_tlast = 1'b0;
|
39
|
+
|
40
|
+
endmodule
|
@@ -0,0 +1,29 @@
|
|
1
|
+
##-------------------------- CLOCK SET ---------------------------------- ##
|
2
|
+
set_system_jitter 0.1
|
3
|
+
create_clock -period 33.058 -name global_sys_clk -waveform {0.000 16.529} [get_ports global_sys_clk]
|
4
|
+
# set_input_jitter [get_clocks -of_objects [get_ports global_sys_clk]] 0.01
|
5
|
+
##========================== CLOCK SET ================================== ##
|
6
|
+
##-------------------------- PIN SET ---------------------------------- ##
|
7
|
+
set_property PACKAGE_PIN C7 [get_ports global_sys_clk]
|
8
|
+
set_property IOSTANDARD LVCMOS18 [get_ports global_sys_clk]
|
9
|
+
##========================== PIN SET ================================== ##
|
10
|
+
|
11
|
+
## -------------------------- FALSE PATH SET ---------------------------------- ##
|
12
|
+
# set_false_path -from [get_pins -hier -regexp .*cross_clk.*ltc.*] -to [all_registers]
|
13
|
+
set_max_delay -from [get_pins -hier -regexp .*cross_clk.*ltc.*] -to [all_registers] 20.00
|
14
|
+
## set_false_path -from [get_pins -hierarchical "*cross_clk*"] -to [all_registers]
|
15
|
+
# set_false_path -from [all_registers] -to [get_pins -hier -regexp .*cross_clk.*ltc.*]
|
16
|
+
set_max_delay -from [all_registers] -to [get_pins -hier -regexp .*cross_clk.*ltc.*] 20.00
|
17
|
+
## set_false_path -from [all_registers] -to [get_pins -hierarchical "*cross_clk*"]
|
18
|
+
|
19
|
+
# set_false_path -from [get_pins -hier -regexp .*xilinx_reset_sync.*reset_sync.*] -to [all_registers]
|
20
|
+
set_max_delay -from [get_pins -hier -regexp .*xilinx_reset_sync.*reset_sync.*] -to [all_registers] 40.000
|
21
|
+
## set_false_path -from [get_pins -hierarchical "*xilinx_reset_sync*reset_sync*"] -to [all_registers]
|
22
|
+
|
23
|
+
## ========================== FALSE PATH SET =================================== ##
|
24
|
+
## -------------------------- EX SET ---------------------------------- ##
|
25
|
+
|
26
|
+
## ========================== EX SET =================================== ##
|
27
|
+
## -------------------------- BITSTREAM SET ---------------------------------- ##
|
28
|
+
|
29
|
+
## ========================== BITSTREAM SET =================================== ##
|
@@ -0,0 +1,11 @@
|
|
1
|
+
require_relative "../../tdl.rb"
|
2
|
+
require_relative "./A_itgt/itgt_module_a_block.rb"
|
3
|
+
require_relative "./clock_manage/itgt_module_clock_manage.rb"
|
4
|
+
|
5
|
+
TopModule.test_tttop(__dir__) do
|
6
|
+
load_pins File.join(__dir__, 'pins.yml')
|
7
|
+
|
8
|
+
add_itegration('ClockManage',pins_map: :CM)
|
9
|
+
add_itegration('ABlock')
|
10
|
+
|
11
|
+
end
|
@@ -0,0 +1,31 @@
|
|
1
|
+
|
2
|
+
## 1. define_module
|
3
|
+
define module like systemverilog, include port, parameter
|
4
|
+
|
5
|
+
## 2. hdl_class
|
6
|
+
syntax look like hdl
|
7
|
+
|
8
|
+
## 3. hdl_sdl_instance
|
9
|
+
instance of hdl and sdl
|
10
|
+
|
11
|
+
## 4. generate
|
12
|
+
examples for generate
|
13
|
+
|
14
|
+
## 5. logic_combin
|
15
|
+
combin logic by (>>, <<)
|
16
|
+
|
17
|
+
## 6. module_with_interface
|
18
|
+
define interface in module
|
19
|
+
|
20
|
+
## 7. module_with_package
|
21
|
+
define module with package
|
22
|
+
|
23
|
+
## 8. top_module
|
24
|
+
define hdl top module with xdc
|
25
|
+
|
26
|
+
## 9. itegration
|
27
|
+
powerful!!! Itegrative design
|
28
|
+
|
29
|
+
## 10. random
|
30
|
+
|
31
|
+
## 11. test_unit
|
@@ -0,0 +1,139 @@
|
|
1
|
+
|
2
|
+
class CommCfgReg < BaseElm
|
3
|
+
GENERAL = :general
|
4
|
+
ONLY_READ = :only_read
|
5
|
+
INCLUDE_RESET = :include_reset
|
6
|
+
|
7
|
+
# ONLY_JTAG = :only_jtag
|
8
|
+
# PORT_AND_JTAG = :port_and_jtag
|
9
|
+
# ONLY_PORT = :only_port
|
10
|
+
@@id = 0
|
11
|
+
@@inst_stack = []
|
12
|
+
|
13
|
+
def self.clear
|
14
|
+
@@id = 0
|
15
|
+
@@inst_stack = []
|
16
|
+
end
|
17
|
+
|
18
|
+
def initialize(axil=nil)
|
19
|
+
raise TdlError.new("\nCOMMON CFG REG AXI LITE Can't be nil \n") unless axil
|
20
|
+
@axil = axil
|
21
|
+
@id = @@id
|
22
|
+
@@id += 1
|
23
|
+
@addr_list = []
|
24
|
+
@proc_params = []
|
25
|
+
@reg_inst_stack = []
|
26
|
+
@index = 0
|
27
|
+
|
28
|
+
@@inst_stack << method(:inst)
|
29
|
+
|
30
|
+
end
|
31
|
+
|
32
|
+
|
33
|
+
# attr_reader :addr,:default,:reset,:type
|
34
|
+
def Reg(addr:0,default:0,reset:nil,type: GENERAL,signal:nil,name:nil)
|
35
|
+
raise TdlError.new("\n COMMON CFG REG ADDR[#{@addr_list.to_s}] already has ADD[#{addr}]\n") if @addr_list.include? addr
|
36
|
+
|
37
|
+
@addr_list << addr
|
38
|
+
|
39
|
+
|
40
|
+
unless signal
|
41
|
+
unless name
|
42
|
+
ccr = Logic.new(name:"commCfgReg",dsize:32)
|
43
|
+
else
|
44
|
+
ccr = Logic.new(name:name,dsize:32)
|
45
|
+
end
|
46
|
+
else
|
47
|
+
ccr = signal
|
48
|
+
end
|
49
|
+
|
50
|
+
@proc_params << {index:@index,addr:addr,default:default,reset:reset,type: type,signal:ccr}
|
51
|
+
@index += 1
|
52
|
+
return ccr
|
53
|
+
end
|
54
|
+
|
55
|
+
def WideReg(addr:0,default:0,reset:nil,type: GENERAL,signal:nil,name:nil,dsize:64)
|
56
|
+
if dsize <= 32
|
57
|
+
Reg(addr:addr,default:default,reset:reset,type: type,signal:signal,name:name)
|
58
|
+
else
|
59
|
+
wide = Logic.new(name:"commCfgReg_wide",dsize:dsize)
|
60
|
+
default_logic = Logic.new(name:"commCfgReg_default",dsize:dsize)
|
61
|
+
|
62
|
+
if signal
|
63
|
+
signal_logic = Logic.new(name:"commCfgReg_signal",dsize:dsize)
|
64
|
+
end
|
65
|
+
|
66
|
+
Assign do
|
67
|
+
default_logic <= default
|
68
|
+
if signal
|
69
|
+
signal_logic <= signal
|
70
|
+
end
|
71
|
+
end
|
72
|
+
|
73
|
+
aa = []
|
74
|
+
|
75
|
+
((dsize)/32.0).ceil.times do |i|
|
76
|
+
if signal
|
77
|
+
sstr = signal_logic.signal(h:i*32+32-1,l:i*32)
|
78
|
+
else
|
79
|
+
sstr = nil
|
80
|
+
end
|
81
|
+
aa << Reg(addr:addr+i,default:default_logic.signal(h:i*32+32-1,l:i*32),reset:reset,type: type,signal:sstr,name:name)
|
82
|
+
end
|
83
|
+
|
84
|
+
Assign do
|
85
|
+
wide <= "{#{aa.reverse.map{|e| e.signal }.join(',')}}"
|
86
|
+
end
|
87
|
+
return wide
|
88
|
+
end
|
89
|
+
end
|
90
|
+
|
91
|
+
undef :signal
|
92
|
+
|
93
|
+
|
94
|
+
def inst
|
95
|
+
page(tag:"common_configure_reg_interface",body:head_inst + reg_inst)
|
96
|
+
end
|
97
|
+
|
98
|
+
def self.inst
|
99
|
+
@@inst_stack.map{|e| e.call }.join("")
|
100
|
+
end
|
101
|
+
|
102
|
+
Tdl.after_dynamict_inst_stack << method(:inst)
|
103
|
+
|
104
|
+
def head_inst
|
105
|
+
with_new_align(0) do
|
106
|
+
"
|
107
|
+
common_configure_reg_interface #(
|
108
|
+
.ASIZE (#{align_signal(@axil,q_mark=false)}.ASIZE ),
|
109
|
+
.DSIZE (#{align_signal(@axil,q_mark=false)}.DSIZE )
|
110
|
+
)cfg_inf_#{@id} [#{@addr_list.size}-1:0] ();
|
111
|
+
|
112
|
+
axi_lite_configure #(
|
113
|
+
.TOTAL_NUM (#{@addr_list.size})
|
114
|
+
)axi_lite_configure_inst_#{@id}(
|
115
|
+
/* axi_lite_inf.slaver */ .axil (#{align_signal(@axil,q_mark=false)}),
|
116
|
+
/* common_configure_reg_interface.master */ .cfg_inf (cfg_inf_#{@id})//[TOTAL_NUM-1:0]
|
117
|
+
);
|
118
|
+
" end
|
119
|
+
end
|
120
|
+
|
121
|
+
def reg_inst
|
122
|
+
with_new_align(0) do
|
123
|
+
@proc_params.map do |pp|
|
124
|
+
case pp[:type]
|
125
|
+
when GENERAL
|
126
|
+
"general_reg REG_cfg_inf_#{@id}_#{pp[:index]} (cfg_inf_#{@id}[#{pp[:index]}],#{align_signal(pp[:addr],q_mark=false)},#{align_signal(pp[:signal],q_mark=false)},#{align_signal(pp[:default],q_mark=false)});"
|
127
|
+
when ONLY_READ
|
128
|
+
"general_only_read_reg REG_cfg_inf_#{@id}_#{pp[:index]} (cfg_inf_#{@id}[#{pp[:index]}],#{align_signal(pp[:addr],q_mark=false)},#{align_signal(pp[:signal],q_mark=false)});"
|
129
|
+
when INCLUDE_RESET
|
130
|
+
"CFG_REG REG_cfg_inf_#{@id}_#{pp[:index]} (cfg_inf_#{@id}[#{pp[:index]}],#{align_signal(pp[:addr],q_mark=false)},#{align_signal(pp[:signal],q_mark=false)},#{align_signal(pp[:default],q_mark=false)},#{align_signal(pp[:signal],q_mark=false)},#{align_signal(pp[:reset],q_mark=false)});"
|
131
|
+
else
|
132
|
+
"general_reg REG_cfg_inf_#{@id}_#{pp[:index]} (cfg_inf_#{@id}[#{pp[:index]}],#{align_signal(pp[:addr],q_mark=false)},#{align_signal(pp[:signal],q_mark=false)},#{align_signal(pp[:default],q_mark=false)});"
|
133
|
+
end
|
134
|
+
end.join("\n")
|
135
|
+
end
|
136
|
+
end
|
137
|
+
|
138
|
+
|
139
|
+
end
|