axi_tdl 0.0.2

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Files changed (1189) hide show
  1. checksums.yaml +7 -0
  2. data/.gitignore +8 -0
  3. data/CODE_OF_CONDUCT.md +74 -0
  4. data/Gemfile +6 -0
  5. data/Gemfile.lock +43 -0
  6. data/LICENSE +504 -0
  7. data/README.md +311 -0
  8. data/Rakefile +18 -0
  9. data/axi_tdl.gemspec +43 -0
  10. data/bin/console +14 -0
  11. data/bin/setup +8 -0
  12. data/lib/.rspec +1 -0
  13. data/lib/axi/AXI4/axi4_combin_wr_rd_batch.sv +59 -0
  14. data/lib/axi/AXI4/axi4_direct.sv +137 -0
  15. data/lib/axi/AXI4/axi4_direct_A1.sv +229 -0
  16. data/lib/axi/AXI4/axi4_direct_B1.sv +74 -0
  17. data/lib/axi/AXI4/axi4_direct_verb.sv +79 -0
  18. data/lib/axi/AXI4/axi4_direct_verc.sv +146 -0
  19. data/lib/axi/AXI4/axi4_dpram_cache.rb +106 -0
  20. data/lib/axi/AXI4/axi4_dpram_cache.sv +112 -0
  21. data/lib/axi/AXI4/axi4_long_to_axi4_wide.sv +85 -0
  22. data/lib/axi/AXI4/axi4_long_to_axi4_wide_A1.sv +96 -0
  23. data/lib/axi/AXI4/axi4_long_to_axi4_wide_track.sv +118 -0
  24. data/lib/axi/AXI4/axi4_long_to_axi4_wide_verb.sv +131 -0
  25. data/lib/axi/AXI4/axi4_pipe/axi4_pipe.sv +44 -0
  26. data/lib/axi/AXI4/axi4_pipe/axi4_pipe_verb.sv +45 -0
  27. data/lib/axi/AXI4/axi4_pipe/axi4_rd_pipe.sv +111 -0
  28. data/lib/axi/AXI4/axi4_pipe/axi4_rd_pipe_verb.sv +113 -0
  29. data/lib/axi/AXI4/axi4_pipe/axi4_wr_pipe.sv +142 -0
  30. data/lib/axi/AXI4/axi4_pipe/axi4_wr_pipe_verb.sv +146 -0
  31. data/lib/axi/AXI4/axi4_rd_auxiliary_batch_gen.sv +134 -0
  32. data/lib/axi/AXI4/axi4_rd_auxiliary_gen.sv +89 -0
  33. data/lib/axi/AXI4/axi4_rd_auxiliary_gen_A1.sv +109 -0
  34. data/lib/axi/AXI4/axi4_rd_burst_track.sv +164 -0
  35. data/lib/axi/AXI4/axi4_wr_aux_bind_data.sv +121 -0
  36. data/lib/axi/AXI4/axi4_wr_auxiliary_batch_gen.sv +140 -0
  37. data/lib/axi/AXI4/axi4_wr_auxiliary_gen.sv +102 -0
  38. data/lib/axi/AXI4/axi4_wr_auxiliary_gen_without_resp.sv +91 -0
  39. data/lib/axi/AXI4/axi4_wr_burst_track.sv +146 -0
  40. data/lib/axi/AXI4/axi_stream_add_addr_len.sv +50 -0
  41. data/lib/axi/AXI4/axi_stream_to_axi4_wr.sv +61 -0
  42. data/lib/axi/AXI4/axi_stream_to_axi4_wr_verb.sv.bak +123 -0
  43. data/lib/axi/AXI4/axis_to_axi4_wr.rb +149 -0
  44. data/lib/axi/AXI4/axis_to_axi4_wr.sv +141 -0
  45. data/lib/axi/AXI4/full_axi4_to_axis.sv +188 -0
  46. data/lib/axi/AXI4/full_axi4_to_axis_partition_wr_rd.sv +208 -0
  47. data/lib/axi/AXI4/id_record.sv +55 -0
  48. data/lib/axi/AXI4/idata_pool_axi4.sv +110 -0
  49. data/lib/axi/AXI4/interconnect/AXI4_interconnect_M2S.sv +291 -0
  50. data/lib/axi/AXI4/interconnect/axi4_mix_interconnect_M2S.sv +72 -0
  51. data/lib/axi/AXI4/interconnect/axi4_rd_interconnect_M2S.sv +148 -0
  52. data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S.sv +255 -0
  53. data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S.sv.bak +255 -0
  54. data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S_A1.sv +286 -0
  55. data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S_A2.sv +281 -0
  56. data/lib/axi/AXI4/interconnect/axi4_wr_interconnect_M2S.sv +235 -0
  57. data/lib/axi/AXI4/interconnect/axi4_wr_interconnect_M2S_A1.sv +283 -0
  58. data/lib/axi/AXI4/interconnect/axi4_wr_mix_interconnect_M2S.sv +32 -0
  59. data/lib/axi/AXI4/long_axi4_to_wide_axi4.sv.bak +251 -0
  60. data/lib/axi/AXI4/odata_pool_axi4.sv +134 -0
  61. data/lib/axi/AXI4/odata_pool_axi4_A1.sv +165 -0
  62. data/lib/axi/AXI4/odata_pool_axi4_A2.sv +159 -0
  63. data/lib/axi/AXI4/odata_pool_axi4_A3.sv +183 -0
  64. data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo.sv +61 -0
  65. data/lib/axi/AXI4/packet_fifo/axi4_rd_packet_fifo.sv +282 -0
  66. data/lib/axi/AXI4/packet_fifo/axi4_wr_packet_fifo.sv +181 -0
  67. data/lib/axi/AXI4/packet_merge/axi4_merge.sv +60 -0
  68. data/lib/axi/AXI4/packet_merge/axi4_merge_rd.sv +279 -0
  69. data/lib/axi/AXI4/packet_merge/axi4_merge_wr.sv +267 -0
  70. data/lib/axi/AXI4/packet_partition/axi4_partition.sv +36 -0
  71. data/lib/axi/AXI4/packet_partition/axi4_partition_OD.sv +66 -0
  72. data/lib/axi/AXI4/packet_partition/axi4_partition_rd.sv +211 -0
  73. data/lib/axi/AXI4/packet_partition/axi4_partition_rd_OD.sv +322 -0
  74. data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.rb +80 -0
  75. data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +93 -0
  76. data/lib/axi/AXI4/packet_partition/axi4_partition_wr.sv +239 -0
  77. data/lib/axi/AXI4/packet_partition/axi4_partition_wr_OD.sv +302 -0
  78. data/lib/axi/AXI4/packet_partition/data_inf_partition.rb +293 -0
  79. data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +307 -0
  80. data/lib/axi/AXI4/vcs_axi4_array_comptable.sv +35 -0
  81. data/lib/axi/AXI4/vcs_axi4_comptable.sv +330 -0
  82. data/lib/axi/AXI4/wide_axis_to_axi4_wr.rb +149 -0
  83. data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +140 -0
  84. data/lib/axi/AXI4/width_convert/axi4_data_combin_aflag_pipe.sv +239 -0
  85. data/lib/axi/AXI4/width_convert/axi4_data_combin_aflag_pipe_A1.sv +204 -0
  86. data/lib/axi/AXI4/width_convert/axi4_data_convert.sv +312 -0
  87. data/lib/axi/AXI4/width_convert/axi4_data_convert_A1.sv +217 -0
  88. data/lib/axi/AXI4/width_convert/data_combin.sv +366 -0
  89. data/lib/axi/AXI4/width_convert/data_combin.sv.bak +290 -0
  90. data/lib/axi/AXI4/width_convert/data_destruct.sv +304 -0
  91. data/lib/axi/AXI4/width_convert/feed_check.sv +94 -0
  92. data/lib/axi/AXI4/width_convert/len_convert.sv.bak +61 -0
  93. data/lib/axi/AXI4/width_convert/odd_width_convert.sv +229 -0
  94. data/lib/axi/AXI4/width_convert/odd_width_convert_verb.sv +105 -0
  95. data/lib/axi/AXI4/width_convert/simple_data_pipe.sv +40 -0
  96. data/lib/axi/AXI4/width_convert/simple_data_pipe_slaver.sv +33 -0
  97. data/lib/axi/AXI4/width_convert/width_combin.sv +113 -0
  98. data/lib/axi/AXI4/width_convert/width_convert.sv +87 -0
  99. data/lib/axi/AXI4/width_convert/width_convert_verb.sv +249 -0
  100. data/lib/axi/AXI4/width_convert/width_destruct.sv +206 -0
  101. data/lib/axi/AXI4/width_convert/width_destruct_A1.sv +251 -0
  102. data/lib/axi/AXI_BFM/AXI_BFM_PKG.sv +1039 -0
  103. data/lib/axi/AXI_BFM/Data_C_BFM_PKG.sv +97 -0
  104. data/lib/axi/AXI_BFM/axi4_error_chk.sv +298 -0
  105. data/lib/axi/AXI_BFM/axi4_illegal_bfm_pkg.sv +607 -0
  106. data/lib/axi/AXI_BFM/axi_lite_master.sv +102 -0
  107. data/lib/axi/AXI_BFM/axi_lite_tb.sv +23 -0
  108. data/lib/axi/AXI_BFM/axi_master.sv +185 -0
  109. data/lib/axi/AXI_BFM/axi_mirror.sv +266 -0
  110. data/lib/axi/AXI_BFM/axi_mm_tb.sv +134 -0
  111. data/lib/axi/AXI_BFM/axi_slaver.sv.bak +340 -0
  112. data/lib/axi/AXI_BFM/axistreambfm.sv +117 -0
  113. data/lib/axi/AXI_Lite/axi4_to_lite.sv +36 -0
  114. data/lib/axi/AXI_Lite/axi_lite_configure.sv +356 -0
  115. data/lib/axi/AXI_Lite/axi_lite_configure_inf2.sv +365 -0
  116. data/lib/axi/AXI_Lite/axi_lite_configure_verb.sv.bck +370 -0
  117. data/lib/axi/AXI_Lite/axi_lite_interconnect_M2S.sv +437 -0
  118. data/lib/axi/AXI_Lite/axi_lite_interconnect_S2M.sv +359 -0
  119. data/lib/axi/AXI_Lite/axi_lite_interconnect_S2M.sv.bak +359 -0
  120. data/lib/axi/AXI_Lite/axi_lite_master_empty.sv +30 -0
  121. data/lib/axi/AXI_Lite/axi_lite_slaver_empty.sv +27 -0
  122. data/lib/axi/AXI_Lite/axil_direct.sv +52 -0
  123. data/lib/axi/AXI_Lite/common_configure_reg_interface/common_configure_reg_interface.sv +230 -0
  124. data/lib/axi/AXI_Lite/common_configure_reg_interface/common_configure_reg_interface.sv.bak +109 -0
  125. data/lib/axi/AXI_Lite/common_configure_reg_interface/jtag_to_axilite_wrapper.sv +56 -0
  126. data/lib/axi/AXI_Lite/gen_axi_lite_ctrl.sv +515 -0
  127. data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_C1.sv +369 -0
  128. data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_verb.sv +365 -0
  129. data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_verc.sv +401 -0
  130. data/lib/axi/AXI_Lite/wr_lite_to_axis.sv +141 -0
  131. data/lib/axi/AXI_Lite/wr_lite_to_axis.sv.bak +141 -0
  132. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S.sv +76 -0
  133. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_A1.sv +77 -0
  134. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_A2.sv +71 -0
  135. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_bind_tuser.sv +72 -0
  136. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_noaddr.sv +151 -0
  137. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_with_addr.sv +87 -0
  138. data/lib/axi/AXI_stream/axi_stream_interconnect_S2M.sv +65 -0
  139. data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_auto.sv +50 -0
  140. data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_with_info.sv +64 -0
  141. data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_with_keep.sv.bak +64 -0
  142. data/lib/axi/AXI_stream/axi_stream_packet_fifo_with_info.sv.bak +49 -0
  143. data/lib/axi/AXI_stream/axi_stream_partition.sv +147 -0
  144. data/lib/axi/AXI_stream/axi_stream_partition_A1.sv +63 -0
  145. data/lib/axi/AXI_stream/axi_stream_planer.sv +51 -0
  146. data/lib/axi/AXI_stream/axi_stream_split_channel.rb +56 -0
  147. data/lib/axi/AXI_stream/axi_stream_split_channel.sv +149 -0
  148. data/lib/axi/AXI_stream/axi_streams_combin.sv +151 -0
  149. data/lib/axi/AXI_stream/axi_streams_combin_A1.sv +179 -0
  150. data/lib/axi/AXI_stream/axi_streams_scaler.sv +171 -0
  151. data/lib/axi/AXI_stream/axi_streams_scaler_A1.sv +179 -0
  152. data/lib/axi/AXI_stream/axis_append.sv +79 -0
  153. data/lib/axi/AXI_stream/axis_append_A1.sv +82 -0
  154. data/lib/axi/AXI_stream/axis_base_pipe.sv +184 -0
  155. data/lib/axi/AXI_stream/axis_combin_with_fifo.sv +69 -0
  156. data/lib/axi/AXI_stream/axis_connect_pipe.sv +86 -0
  157. data/lib/axi/AXI_stream/axis_connect_pipe_A1.sv.bak +170 -0
  158. data/lib/axi/AXI_stream/axis_connect_pipe_left_shift.sv +64 -0
  159. data/lib/axi/AXI_stream/axis_connect_pipe_right_shift.sv +64 -0
  160. data/lib/axi/AXI_stream/axis_connect_pipe_right_shift_verb.sv +70 -0
  161. data/lib/axi/AXI_stream/axis_connect_pipe_with_info.sv +93 -0
  162. data/lib/axi/AXI_stream/axis_direct.sv +55 -0
  163. data/lib/axi/AXI_stream/axis_direct_A1.sv +81 -0
  164. data/lib/axi/AXI_stream/axis_filter.sv +38 -0
  165. data/lib/axi/AXI_stream/axis_full_to_data_c.sv +26 -0
  166. data/lib/axi/AXI_stream/axis_head_cut.sv +67 -0
  167. data/lib/axi/AXI_stream/axis_head_cut_verb.sv +60 -0
  168. data/lib/axi/AXI_stream/axis_head_cut_verc.rb +175 -0
  169. data/lib/axi/AXI_stream/axis_head_cut_verc.sv +245 -0
  170. data/lib/axi/AXI_stream/axis_inct_s2m_with_flag.sv +84 -0
  171. data/lib/axi/AXI_stream/axis_insert_copy.rb +59 -0
  172. data/lib/axi/AXI_stream/axis_insert_copy.sv +66 -0
  173. data/lib/axi/AXI_stream/axis_intc_M2S_with_addr_inf.sv +114 -0
  174. data/lib/axi/AXI_stream/axis_intc_S2M_with_addr_inf.sv +85 -0
  175. data/lib/axi/AXI_stream/axis_interconnect_S2M_pipe.sv +75 -0
  176. data/lib/axi/AXI_stream/axis_length_cut.sv +64 -0
  177. data/lib/axi/AXI_stream/axis_length_fill.sv +194 -0
  178. data/lib/axi/AXI_stream/axis_length_split.sv +86 -0
  179. data/lib/axi/AXI_stream/axis_length_split_with_addr.sv +127 -0
  180. data/lib/axi/AXI_stream/axis_length_split_writh_user.sv +87 -0
  181. data/lib/axi/AXI_stream/axis_link_trigger.sv +81 -0
  182. data/lib/axi/AXI_stream/axis_master_empty.sv +26 -0
  183. data/lib/axi/AXI_stream/axis_mirror_to_master.sv +126 -0
  184. data/lib/axi/AXI_stream/axis_mirrors.sv +60 -0
  185. data/lib/axi/AXI_stream/axis_orthogonal.sv +66 -0
  186. data/lib/axi/AXI_stream/axis_ram_buffer.sv +118 -0
  187. data/lib/axi/AXI_stream/axis_rom_contect.rb +97 -0
  188. data/lib/axi/AXI_stream/axis_rom_contect.sv +110 -0
  189. data/lib/axi/AXI_stream/axis_rom_contect_sim.rb +102 -0
  190. data/lib/axi/AXI_stream/axis_rom_contect_sim.sv +113 -0
  191. data/lib/axi/AXI_stream/axis_slaver_empty.sv +22 -0
  192. data/lib/axi/AXI_stream/axis_slaver_pipe.sv +84 -0
  193. data/lib/axi/AXI_stream/axis_slaver_pipe_A1.sv +54 -0
  194. data/lib/axi/AXI_stream/axis_slaver_vector_empty.sv +27 -0
  195. data/lib/axi/AXI_stream/axis_split_channel_verb.rb +42 -0
  196. data/lib/axi/AXI_stream/axis_split_channel_verb.sv +62 -0
  197. data/lib/axi/AXI_stream/axis_to_axi4_or_lite.rb +127 -0
  198. data/lib/axi/AXI_stream/axis_to_axi4_or_lite.sv +153 -0
  199. data/lib/axi/AXI_stream/axis_to_data_inf.sv +34 -0
  200. data/lib/axi/AXI_stream/axis_to_lite_rd.sv +81 -0
  201. data/lib/axi/AXI_stream/axis_to_lite_wr.sv +71 -0
  202. data/lib/axi/AXI_stream/axis_uncompress.sv +147 -0
  203. data/lib/axi/AXI_stream/axis_uncompress_A1.sv +150 -0
  204. data/lib/axi/AXI_stream/axis_uncompress_verb.rb +32 -0
  205. data/lib/axi/AXI_stream/axis_uncompress_verb.sv +54 -0
  206. data/lib/axi/AXI_stream/axis_valve.sv +29 -0
  207. data/lib/axi/AXI_stream/axis_valve_with_pipe.sv +76 -0
  208. data/lib/axi/AXI_stream/axis_vector_master_empty.rb +11 -0
  209. data/lib/axi/AXI_stream/axis_vector_master_empty.sv +35 -0
  210. data/lib/axi/AXI_stream/axis_vector_slaver_empty.rb +11 -0
  211. data/lib/axi/AXI_stream/axis_vector_slaver_empty.sv +35 -0
  212. data/lib/axi/AXI_stream/check_stream_crc.sv +28 -0
  213. data/lib/axi/AXI_stream/data_c_to_axis_full.sv +23 -0
  214. data/lib/axi/AXI_stream/data_to_axis_inf.sv +103 -0
  215. data/lib/axi/AXI_stream/data_to_axis_inf_A1.sv +28 -0
  216. data/lib/axi/AXI_stream/data_width/axis_width_combin.sv +204 -0
  217. data/lib/axi/AXI_stream/data_width/axis_width_combin_A1.sv +220 -0
  218. data/lib/axi/AXI_stream/data_width/axis_width_convert.sv +49 -0
  219. data/lib/axi/AXI_stream/data_width/axis_width_destruct.sv +82 -0
  220. data/lib/axi/AXI_stream/data_width/axis_width_destruct_A1.sv +86 -0
  221. data/lib/axi/AXI_stream/ex_status/axis_ex_status.sv +97 -0
  222. data/lib/axi/AXI_stream/gen_big_field_table.sv +170 -0
  223. data/lib/axi/AXI_stream/gen_common_frame_table.sv +382 -0
  224. data/lib/axi/AXI_stream/gen_common_frame_table_bind_tuser.sv +428 -0
  225. data/lib/axi/AXI_stream/gen_origin_axis.sv +116 -0
  226. data/lib/axi/AXI_stream/gen_origin_axis_A1.sv +129 -0
  227. data/lib/axi/AXI_stream/gen_origin_axis_A2.sv +162 -0
  228. data/lib/axi/AXI_stream/gen_simple_axis.sv +164 -0
  229. data/lib/axi/AXI_stream/packet_fifo/axi_stream_long_fifo.sv +132 -0
  230. data/lib/axi/AXI_stream/packet_fifo/axi_stream_long_fifo_verb.sv +140 -0
  231. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo.sv +125 -0
  232. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1.sv +142 -0
  233. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1E.sv +198 -0
  234. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_verb.sv +120 -0
  235. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_with_info.sv +49 -0
  236. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_long_fifo.sv +197 -0
  237. data/lib/axi/AXI_stream/packet_fifo/axi_stream_wide_fifo.sv +141 -0
  238. data/lib/axi/AXI_stream/packet_fifo/axis_pkt_fifo_filter_keep.sv +164 -0
  239. data/lib/axi/AXI_stream/packet_fifo/axis_pkt_fifo_filter_keep_A1.sv +166 -0
  240. data/lib/axi/AXI_stream/parse_big_field_table.sv +164 -0
  241. data/lib/axi/AXI_stream/parse_big_field_table_A1.sv +162 -0
  242. data/lib/axi/AXI_stream/parse_big_field_table_A2.sv +165 -0
  243. data/lib/axi/AXI_stream/parse_big_field_table_verb.sv +118 -0
  244. data/lib/axi/AXI_stream/parse_common_frame_table.sv +202 -0
  245. data/lib/axi/AXI_stream/parse_common_frame_table_A1.sv +521 -0
  246. data/lib/axi/AXI_stream/parse_common_frame_table_A2.sv +561 -0
  247. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache.sv +46 -0
  248. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_35bit.sv +122 -0
  249. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_36_71bit.sv +71 -0
  250. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_72_95bit.sv +96 -0
  251. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_72_95bit_with_keep.sv +99 -0
  252. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_96_143bit.sv +119 -0
  253. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_A1.sv +49 -0
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  255. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_mirror.sv +44 -0
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  257. data/lib/axi/AXI_stream/stream_cache/axi_stream_long_cache.sv +55 -0
  258. data/lib/axi/AXI_stream/stream_crc.sv +67 -0
  259. data/lib/axi/AXI_stream/vcs_axis_comptable.sv +73 -0
  260. data/lib/axi/LICENSE +504 -0
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  263. data/lib/axi/SIM/tb_axis_bfm_0504.sv +61 -0
  264. data/lib/axi/SIM/tb_axis_partitiom_0929.sv +102 -0
  265. data/lib/axi/SIM/tb_axis_s2m_pipe_1023.sv +163 -0
  266. data/lib/axi/SIM/tb_axis_to_axi4_0925.sv +107 -0
  267. data/lib/axi/SIM/tb_data_c_m2s_inf_20200114.sv +222 -0
  268. data/lib/axi/SIM/tb_data_c_m2s_inf_20201103.sv +245 -0
  269. data/lib/axi/SIM/tb_data_c_pipe_inf_20180417.sv +114 -0
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  275. data/lib/axi/axi4_to_xilinx_ddr_native/ddr3_ip_native_to_axi4.sv +194 -0
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  283. data/lib/axi/cfg.yml +15 -0
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  285. data/lib/axi/common/common_ram_sim_wrapper.rb +66 -0
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  287. data/lib/axi/common/common_ram_wrapper.rb +71 -0
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  289. data/lib/axi/common/data_c_interface_dram.rb +90 -0
  290. data/lib/axi/common/data_c_interface_dram.sv +106 -0
  291. data/lib/axi/common/mem_format.coe +60 -0
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  311. data/lib/axi/data_interface/data_inf_c/data_c_pipe_force_vld_bind_data.sv +81 -0
  312. data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf.sv +130 -0
  313. data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf_A1.sv +135 -0
  314. data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf_left_shift.sv +158 -0
  315. data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf_right_shift.sv +155 -0
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  319. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_best_last.sv +319 -0
  320. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_best_robin.sv +293 -0
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  322. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_robin_with_id.sv +46 -0
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  324. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_verc_with_addr.sv +226 -0
  325. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_verc_with_id.sv +54 -0
  326. data/lib/axi/data_interface/data_inf_c/data_c_pipe_latency.sv +68 -0
  327. data/lib/axi/data_interface/data_inf_c/data_c_scaler.sv +326 -0
  328. data/lib/axi/data_interface/data_inf_c/data_c_scaler_A1.sv +333 -0
  329. data/lib/axi/data_interface/data_inf_c/data_c_tmp_cache.sv +44 -0
  330. data/lib/axi/data_interface/data_inf_c/data_condition_mirror.sv +64 -0
  331. data/lib/axi/data_interface/data_inf_c/data_condition_valve.sv +53 -0
  332. data/lib/axi/data_interface/data_inf_c/data_connect_pipe_inf.sv +73 -0
  333. data/lib/axi/data_interface/data_inf_c/data_inf_c_M2S_with_addr_and_id.sv +66 -0
  334. data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_M2S_with_id.sv +67 -0
  335. data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_S2M.sv +70 -0
  336. data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_S2M_A1.sv +72 -0
  337. data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_S2M_with_lazy.sv +49 -0
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  339. data/lib/axi/data_interface/data_inf_c/data_inf_c_pipe_condition.sv +33 -0
  340. data/lib/axi/data_interface/data_inf_c/data_inf_c_planer.sv +50 -0
  341. data/lib/axi/data_interface/data_inf_c/data_inf_c_planer_A1.sv +53 -0
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  347. data/lib/axi/data_interface/data_inf_c/next_prio.sv +42 -0
  348. data/lib/axi/data_interface/data_inf_c/trigger_data_inf_c.sv +51 -0
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  354. data/lib/axi/data_interface/data_inf_intc_M2S_prio.sv +152 -0
  355. data/lib/axi/data_interface/data_inf_intc_M2S_prio_with_id.sv +55 -0
  356. data/lib/axi/data_interface/data_inf_interconnect_M2S_noaddr.sv +136 -0
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  358. data/lib/axi/data_interface/data_inf_planer.sv +59 -0
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  382. data/lib/axi/data_interface/datainf_slaver_empty.sv +22 -0
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  384. data/lib/axi/interface_define/axi_aux_inf.sv +206 -0
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  423. data/lib/axi/platform_ip/fifo_73_96bit.sv +102 -0
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  468. data/lib/axi/top/tb_data_intc_S2M_0807.sv +168 -0
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  482. data/lib/tdl/Logic/logic_operator.rb.bak +128 -0
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  486. data/lib/tdl/ReadMe.md +295 -0
  487. data/lib/tdl/SDL/axi4/AXI4_interconnect_M2S_sdl.rb +10 -0
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  498. data/lib/tdl/SDL/axi4/axi4_long_to_axi4_wide_A1_sdl.rb +10 -0
  499. data/lib/tdl/SDL/axi4/axi4_long_to_axi4_wide_sdl.rb +9 -0
  500. data/lib/tdl/SDL/axi4/axi4_long_to_axi4_wide_track_sdl.rb +9 -0
  501. data/lib/tdl/SDL/axi4/axi4_long_to_axi4_wide_verb_sdl.rb +11 -0
  502. data/lib/tdl/SDL/axi4/axi4_merge_rd_sdl.rb +10 -0
  503. data/lib/tdl/SDL/axi4/axi4_merge_sdl.rb +10 -0
  504. data/lib/tdl/SDL/axi4/axi4_merge_wr_sdl.rb +10 -0
  505. data/lib/tdl/SDL/axi4/axi4_mix_interconnect_M2S_sdl.rb +10 -0
  506. data/lib/tdl/SDL/axi4/axi4_packet_fifo_sdl.rb +12 -0
  507. data/lib/tdl/SDL/axi4/axi4_partition_OD_sdl.rb +11 -0
  508. data/lib/tdl/SDL/axi4/axi4_partition_rd_OD_sdl.rb +10 -0
  509. data/lib/tdl/SDL/axi4/axi4_partition_rd_sdl.rb +11 -0
  510. data/lib/tdl/SDL/axi4/axi4_partition_sdl.rb +11 -0
  511. data/lib/tdl/SDL/axi4/axi4_partition_wr_OD_sdl.rb +10 -0
  512. data/lib/tdl/SDL/axi4/axi4_partition_wr_sdl.rb +11 -0
  513. data/lib/tdl/SDL/axi4/axi4_pipe_sdl.rb +9 -0
  514. data/lib/tdl/SDL/axi4/axi4_pipe_verb_sdl.rb +9 -0
  515. data/lib/tdl/SDL/axi4/axi4_rd_auxiliary_batch_gen_sdl.rb +11 -0
  516. data/lib/tdl/SDL/axi4/axi4_rd_auxiliary_gen_A1_sdl.rb +9 -0
  517. data/lib/tdl/SDL/axi4/axi4_rd_auxiliary_gen_sdl.rb +9 -0
  518. data/lib/tdl/SDL/axi4/axi4_rd_burst_track_sdl.rb +10 -0
  519. data/lib/tdl/SDL/axi4/axi4_rd_interconnect_M2S_sdl.rb +10 -0
  520. data/lib/tdl/SDL/axi4/axi4_rd_mix_interconnect_M2S_A1_sdl.rb +10 -0
  521. data/lib/tdl/SDL/axi4/axi4_rd_mix_interconnect_M2S_A2_sdl.rb +10 -0
  522. data/lib/tdl/SDL/axi4/axi4_rd_mix_interconnect_M2S_sdl.rb +10 -0
  523. data/lib/tdl/SDL/axi4/axi4_rd_packet_fifo_sdl.rb +11 -0
  524. data/lib/tdl/SDL/axi4/axi4_rd_pipe_sdl.rb +9 -0
  525. data/lib/tdl/SDL/axi4/axi4_rd_pipe_verb_sdl.rb +9 -0
  526. data/lib/tdl/SDL/axi4/axi4_wr_aux_bind_data_sdl.rb +9 -0
  527. data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_batch_gen_sdl.rb +11 -0
  528. data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_gen_sdl.rb +10 -0
  529. data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_gen_without_resp_sdl.rb +10 -0
  530. data/lib/tdl/SDL/axi4/axi4_wr_burst_track_sdl.rb +10 -0
  531. data/lib/tdl/SDL/axi4/axi4_wr_interconnect_M2S_A1_sdl.rb +10 -0
  532. data/lib/tdl/SDL/axi4/axi4_wr_interconnect_M2S_sdl.rb +10 -0
  533. data/lib/tdl/SDL/axi4/axi4_wr_mix_interconnect_M2S_sdl.rb +10 -0
  534. data/lib/tdl/SDL/axi4/axi4_wr_packet_fifo_sdl.rb +11 -0
  535. data/lib/tdl/SDL/axi4/axi4_wr_pipe_sdl.rb +9 -0
  536. data/lib/tdl/SDL/axi4/axi4_wr_pipe_verb_sdl.rb +9 -0
  537. data/lib/tdl/SDL/axi4/axi_stream_add_addr_len_sdl.rb +11 -0
  538. data/lib/tdl/SDL/axi4/axi_stream_to_axi4_wr_sdl.rb +9 -0
  539. data/lib/tdl/SDL/axi4/data_combin_sdl.rb +20 -0
  540. data/lib/tdl/SDL/axi4/data_destruct_sdl.rb +19 -0
  541. data/lib/tdl/SDL/axi4/feed_check_sdl.rb +18 -0
  542. data/lib/tdl/SDL/axi4/full_axi4_to_axis_partition_wr_rd_sdl.rb +11 -0
  543. data/lib/tdl/SDL/axi4/full_axi4_to_axis_sdl.rb +10 -0
  544. data/lib/tdl/SDL/axi4/id_record_sdl.rb +19 -0
  545. data/lib/tdl/SDL/axi4/idata_pool_axi4_sdl.rb +18 -0
  546. data/lib/tdl/SDL/axi4/odata_pool_axi4_A1_sdl.rb +13 -0
  547. data/lib/tdl/SDL/axi4/odata_pool_axi4_A2_sdl.rb +10 -0
  548. data/lib/tdl/SDL/axi4/odata_pool_axi4_sdl.rb +19 -0
  549. data/lib/tdl/SDL/axi4/odd_width_convert_sdl.rb +19 -0
  550. data/lib/tdl/SDL/axi4/odd_width_convert_verb_sdl.rb +19 -0
  551. data/lib/tdl/SDL/axi4/simple_data_pipe_sdl.rb +16 -0
  552. data/lib/tdl/SDL/axi4/simple_data_pipe_slaver_sdl.rb +16 -0
  553. data/lib/tdl/SDL/axi4/vcs_axi4_array_comptable.rb +9 -0
  554. data/lib/tdl/SDL/axi4/vcs_axi4_array_comptable_sdl.rb +10 -0
  555. data/lib/tdl/SDL/axi4/vcs_axi4_comptable.rb +8 -0
  556. data/lib/tdl/SDL/axi4/vcs_axi4_comptable_sdl.rb +9 -0
  557. data/lib/tdl/SDL/axi4/width_combin_sdl.rb +20 -0
  558. data/lib/tdl/SDL/axi4/width_convert_sdl.rb +20 -0
  559. data/lib/tdl/SDL/axi4/width_convert_verb_sdl.rb +20 -0
  560. data/lib/tdl/SDL/axi4/width_destruct_A1_sdl.rb +22 -0
  561. data/lib/tdl/SDL/axi4/width_destruct_sdl.rb +19 -0
  562. data/lib/tdl/SDL/axistream/axi_stream_cache_35bit_sdl.rb +9 -0
  563. data/lib/tdl/SDL/axistream/axi_stream_cache_36_71bit_sdl.rb +9 -0
  564. data/lib/tdl/SDL/axistream/axi_stream_cache_72_95bit_sdl.rb +9 -0
  565. data/lib/tdl/SDL/axistream/axi_stream_cache_72_95bit_with_keep_sdl.rb +9 -0
  566. data/lib/tdl/SDL/axistream/axi_stream_cache_96_143bit_sdl.rb +9 -0
  567. data/lib/tdl/SDL/axistream/axi_stream_cache_B1_sdl.rb +9 -0
  568. data/lib/tdl/SDL/axistream/axi_stream_cache_mirror_sdl.rb +9 -0
  569. data/lib/tdl/SDL/axistream/axi_stream_cache_sdl.rb +9 -0
  570. data/lib/tdl/SDL/axistream/axi_stream_cache_verb_sdl.rb +9 -0
  571. data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_A1_sdl.rb +11 -0
  572. data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_A2_sdl.rb +13 -0
  573. data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_bind_tuser_sdl.rb +11 -0
  574. data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_noaddr_sdl.rb +11 -0
  575. data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_sdl.rb +12 -0
  576. data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_with_addr_sdl.rb +12 -0
  577. data/lib/tdl/SDL/axistream/axi_stream_interconnect_S2M_auto_sdl.rb +11 -0
  578. data/lib/tdl/SDL/axistream/axi_stream_interconnect_S2M_sdl.rb +12 -0
  579. data/lib/tdl/SDL/axistream/axi_stream_long_cache_sdl.rb +10 -0
  580. data/lib/tdl/SDL/axistream/axi_stream_long_fifo_sdl.rb +11 -0
  581. data/lib/tdl/SDL/axistream/axi_stream_long_fifo_verb_sdl.rb +11 -0
  582. data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_B1E_sdl.rb +16 -0
  583. data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_B1_sdl.rb +14 -0
  584. data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_sdl.rb +10 -0
  585. data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_verb_sdl.rb +13 -0
  586. data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_with_info_sdl.rb +13 -0
  587. data/lib/tdl/SDL/axistream/axi_stream_packet_long_fifo_sdl.rb +11 -0
  588. data/lib/tdl/SDL/axistream/axi_stream_partition_A1_sdl.rb +11 -0
  589. data/lib/tdl/SDL/axistream/axi_stream_partition_sdl.rb +12 -0
  590. data/lib/tdl/SDL/axistream/axi_stream_wide_fifo_sdl.rb +10 -0
  591. data/lib/tdl/SDL/axistream/axi_streams_combin_A1_sdl.rb +15 -0
  592. data/lib/tdl/SDL/axistream/axi_streams_combin_sdl.rb +16 -0
  593. data/lib/tdl/SDL/axistream/axi_streams_scaler_A1_sdl.rb +14 -0
  594. data/lib/tdl/SDL/axistream/axi_streams_scaler_sdl.rb +15 -0
  595. data/lib/tdl/SDL/axistream/axis_append_A1_sdl.rb +18 -0
  596. data/lib/tdl/SDL/axistream/axis_append_sdl.rb +17 -0
  597. data/lib/tdl/SDL/axistream/axis_base_pipe_sdl.rb +10 -0
  598. data/lib/tdl/SDL/axistream/axis_combin_with_fifo_sdl.rb +14 -0
  599. data/lib/tdl/SDL/axistream/axis_connect_pipe_right_shift_sdl.rb +10 -0
  600. data/lib/tdl/SDL/axistream/axis_connect_pipe_sdl.rb +9 -0
  601. data/lib/tdl/SDL/axistream/axis_connect_pipe_with_info_sdl.rb +12 -0
  602. data/lib/tdl/SDL/axistream/axis_direct_A1_sdl.rb +11 -0
  603. data/lib/tdl/SDL/axistream/axis_direct_sdl.rb +9 -0
  604. data/lib/tdl/SDL/axistream/axis_ex_status_sdl.rb +12 -0
  605. data/lib/tdl/SDL/axistream/axis_filter_sdl.rb +10 -0
  606. data/lib/tdl/SDL/axistream/axis_full_to_data_c_sdl.rb +9 -0
  607. data/lib/tdl/SDL/axistream/axis_head_cut_sdl.rb +10 -0
  608. data/lib/tdl/SDL/axistream/axis_inct_s2m_with_flag_sdl.rb +11 -0
  609. data/lib/tdl/SDL/axistream/axis_intc_M2S_with_addr_inf_sdl.rb +11 -0
  610. data/lib/tdl/SDL/axistream/axis_intc_S2M_with_addr_inf_sdl.rb +12 -0
  611. data/lib/tdl/SDL/axistream/axis_interconnect_S2M_pipe_sdl.rb +15 -0
  612. data/lib/tdl/SDL/axistream/axis_length_cut_sdl.rb +10 -0
  613. data/lib/tdl/SDL/axistream/axis_length_fill_sdl.rb +10 -0
  614. data/lib/tdl/SDL/axistream/axis_length_split_sdl.rb +10 -0
  615. data/lib/tdl/SDL/axistream/axis_length_split_with_addr_sdl.rb +13 -0
  616. data/lib/tdl/SDL/axistream/axis_length_split_writh_user_sdl.rb +10 -0
  617. data/lib/tdl/SDL/axistream/axis_link_trigger_sdl.rb +12 -0
  618. data/lib/tdl/SDL/axistream/axis_master_empty_sdl.rb +8 -0
  619. data/lib/tdl/SDL/axistream/axis_mirror_to_master_sdl.rb +10 -0
  620. data/lib/tdl/SDL/axistream/axis_mirrors_sdl.rb +14 -0
  621. data/lib/tdl/SDL/axistream/axis_orthogonal_sdl.rb +10 -0
  622. data/lib/tdl/SDL/axistream/axis_pkt_fifo_filter_keep_A1_sdl.rb +10 -0
  623. data/lib/tdl/SDL/axistream/axis_pkt_fifo_filter_keep_sdl.rb +10 -0
  624. data/lib/tdl/SDL/axistream/axis_ram_buffer_sdl.rb +13 -0
  625. data/lib/tdl/SDL/axistream/axis_slaver_empty_sdl.rb +8 -0
  626. data/lib/tdl/SDL/axistream/axis_slaver_pipe_A1_sdl.rb +10 -0
  627. data/lib/tdl/SDL/axistream/axis_slaver_pipe_sdl.rb +9 -0
  628. data/lib/tdl/SDL/axistream/axis_slaver_vector_empty_sdl.rb +9 -0
  629. data/lib/tdl/SDL/axistream/axis_to_data_inf_sdl.rb +10 -0
  630. data/lib/tdl/SDL/axistream/axis_to_lite_rd_sdl.rb +11 -0
  631. data/lib/tdl/SDL/axistream/axis_to_lite_wr_sdl.rb +10 -0
  632. data/lib/tdl/SDL/axistream/axis_uncompress_A1_sdl.rb +12 -0
  633. data/lib/tdl/SDL/axistream/axis_uncompress_sdl.rb +11 -0
  634. data/lib/tdl/SDL/axistream/axis_valve_sdl.rb +10 -0
  635. data/lib/tdl/SDL/axistream/axis_valve_with_pipe_sdl.rb +11 -0
  636. data/lib/tdl/SDL/axistream/axis_width_combin_A1_sdl.rb +9 -0
  637. data/lib/tdl/SDL/axistream/axis_width_combin_sdl.rb +9 -0
  638. data/lib/tdl/SDL/axistream/axis_width_convert_sdl.rb +9 -0
  639. data/lib/tdl/SDL/axistream/axis_width_destruct_A1_sdl.rb +9 -0
  640. data/lib/tdl/SDL/axistream/axis_width_destruct_sdl.rb +9 -0
  641. data/lib/tdl/SDL/axistream/check_stream_crc_sdl.rb +8 -0
  642. data/lib/tdl/SDL/axistream/data_c_to_axis_full_sdl.rb +9 -0
  643. data/lib/tdl/SDL/axistream/data_to_axis_inf_A1_sdl.rb +10 -0
  644. data/lib/tdl/SDL/axistream/data_to_axis_inf_sdl.rb +11 -0
  645. data/lib/tdl/SDL/axistream/gen_big_field_table_sdl.rb +14 -0
  646. data/lib/tdl/SDL/axistream/gen_common_frame_table_sdl.rb +60 -0
  647. data/lib/tdl/SDL/axistream/gen_origin_axis_A1_sdl.rb +13 -0
  648. data/lib/tdl/SDL/axistream/gen_origin_axis_sdl.rb +12 -0
  649. data/lib/tdl/SDL/axistream/gen_simple_axis_sdl.rb +13 -0
  650. data/lib/tdl/SDL/axistream/parse_big_field_table_A1_sdl.rb +17 -0
  651. data/lib/tdl/SDL/axistream/parse_big_field_table_A2_sdl.rb +17 -0
  652. data/lib/tdl/SDL/axistream/parse_big_field_table_sdl.rb +17 -0
  653. data/lib/tdl/SDL/axistream/stream_crc_sdl.rb +9 -0
  654. data/lib/tdl/SDL/axistream/vcs_axis_comptable.rb +16 -0
  655. data/lib/tdl/SDL/axistream/vcs_axis_comptable_sdl.rb +9 -0
  656. data/lib/tdl/SDL/data_inf_c/data_bind_sdl.rb +10 -0
  657. data/lib/tdl/SDL/data_inf_c/data_c_cache_sdl.rb +9 -0
  658. data/lib/tdl/SDL/data_inf_c/data_c_direct_mirror_sdl.rb +9 -0
  659. data/lib/tdl/SDL/data_inf_c/data_c_direct_sdl.rb +9 -0
  660. data/lib/tdl/SDL/data_inf_c/data_c_intc_M2S_force_robin_sdl.rb +10 -0
  661. data/lib/tdl/SDL/data_inf_c/data_c_pipe_force_vld_bind_data_sdl.rb +13 -0
  662. data/lib/tdl/SDL/data_inf_c/data_c_pipe_force_vld_sdl.rb +9 -0
  663. data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_A1_sdl.rb +10 -0
  664. data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_right_shift_sdl.rb +13 -0
  665. data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_sdl.rb +9 -0
  666. data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_C1_sdl.rb +14 -0
  667. data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_C1_with_id_sdl.rb +16 -0
  668. data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_sdl.rb +13 -0
  669. data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_with_addr_sdl.rb +13 -0
  670. data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_with_id_sdl.rb +15 -0
  671. data/lib/tdl/SDL/data_inf_c/data_c_pipe_latency_sdl.rb +10 -0
  672. data/lib/tdl/SDL/data_inf_c/data_c_scaler_A1_sdl.rb +16 -0
  673. data/lib/tdl/SDL/data_inf_c/data_c_scaler_sdl.rb +15 -0
  674. data/lib/tdl/SDL/data_inf_c/data_c_tmp_cache_sdl.rb +9 -0
  675. data/lib/tdl/SDL/data_inf_c/data_condition_mirror_sdl.rb +13 -0
  676. data/lib/tdl/SDL/data_inf_c/data_condition_valve_sdl.rb +13 -0
  677. data/lib/tdl/SDL/data_inf_c/data_connect_pipe_inf_sdl.rb +9 -0
  678. data/lib/tdl/SDL/data_inf_c/data_connect_pipe_sdl.rb +17 -0
  679. data/lib/tdl/SDL/data_inf_c/data_inf_A2B_sdl.rb +9 -0
  680. data/lib/tdl/SDL/data_inf_c/data_inf_B2A_sdl.rb +9 -0
  681. data/lib/tdl/SDL/data_inf_c/data_inf_c_M2S_with_addr_and_id_sdl.rb +17 -0
  682. data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_M2S_with_id_sdl.rb +15 -0
  683. data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_A1_sdl.rb +13 -0
  684. data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_sdl.rb +12 -0
  685. data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_with_lazy_sdl.rb +15 -0
  686. data/lib/tdl/SDL/data_inf_c/data_inf_c_interconnect_M2S_sdl.rb +12 -0
  687. data/lib/tdl/SDL/data_inf_c/data_inf_c_pipe_condition_sdl.rb +10 -0
  688. data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_A1.rb +12 -0
  689. data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_A1_sdl.rb +14 -0
  690. data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_sdl.rb +13 -0
  691. data/lib/tdl/SDL/data_inf_c/data_inf_cross_clk_sdl.rb +9 -0
  692. data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_force_addr_with_id_sdl.rb +19 -0
  693. data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_prio_sdl.rb +14 -0
  694. data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_prio_with_id_sdl.rb +17 -0
  695. data/lib/tdl/SDL/data_inf_c/data_inf_interconnect_M2S_noaddr_sdl.rb +14 -0
  696. data/lib/tdl/SDL/data_inf_c/data_inf_interconnect_M2S_with_id_noaddr_sdl.rb +17 -0
  697. data/lib/tdl/SDL/data_inf_c/data_inf_planer_A1_sdl.rb +15 -0
  698. data/lib/tdl/SDL/data_inf_c/data_inf_planer_sdl.rb +14 -0
  699. data/lib/tdl/SDL/data_inf_c/data_inf_ticktock_sdl.rb +18 -0
  700. data/lib/tdl/SDL/data_inf_c/data_intc_M2S_force_robin_sdl.rb +10 -0
  701. data/lib/tdl/SDL/data_inf_c/data_mirrors_sdl.rb +14 -0
  702. data/lib/tdl/SDL/data_inf_c/data_pair_map_A1_sdl.rb +16 -0
  703. data/lib/tdl/SDL/data_inf_c/data_pair_map_A2_sdl.rb +19 -0
  704. data/lib/tdl/SDL/data_inf_c/data_pair_map_sdl.rb +14 -0
  705. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_A1_sdl.rb +19 -0
  706. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_sdl.rb +17 -0
  707. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_verb_sdl.rb +16 -0
  708. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_A1_sdl.rb +19 -0
  709. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_sdl.rb +16 -0
  710. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_verb_sdl.rb +15 -0
  711. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_sdl.rb +23 -0
  712. data/lib/tdl/SDL/data_inf_c/data_streams_combin_A1_sdl.rb +20 -0
  713. data/lib/tdl/SDL/data_inf_c/data_streams_combin_sdl.rb +20 -0
  714. data/lib/tdl/SDL/data_inf_c/data_streams_scaler_sdl.rb +19 -0
  715. data/lib/tdl/SDL/data_inf_c/data_uncompress_sdl.rb +11 -0
  716. data/lib/tdl/SDL/data_inf_c/data_valve_sdl.rb +10 -0
  717. data/lib/tdl/SDL/data_inf_c/datainf_c_master_empty_sdl.rb +8 -0
  718. data/lib/tdl/SDL/data_inf_c/datainf_c_slaver_empty_sdl.rb +8 -0
  719. data/lib/tdl/SDL/data_inf_c/datainf_master_empty_sdl.rb +8 -0
  720. data/lib/tdl/SDL/data_inf_c/datainf_slaver_empty_sdl.rb +8 -0
  721. data/lib/tdl/SDL/data_inf_c/latency_sdl.rb +8 -0
  722. data/lib/tdl/SDL/data_inf_c/next_prio_sdl.rb +12 -0
  723. data/lib/tdl/SDL/data_inf_c/part_data_pair_map_sdl.rb +19 -0
  724. data/lib/tdl/SDL/data_inf_c/trigger_data_inf_c_A1_sdl.rb +11 -0
  725. data/lib/tdl/SDL/data_inf_c/trigger_data_inf_c_sdl.rb +11 -0
  726. data/lib/tdl/SDL/data_inf_c/trigger_ready_ctrl_sdl.rb +12 -0
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  969. data/lib/tdl/class_hdl/hdl_parameter.rb +73 -0
  970. data/lib/tdl/class_hdl/hdl_random.rb +31 -0
  971. data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +653 -0
  972. data/lib/tdl/class_hdl/hdl_struct.rb +209 -0
  973. data/lib/tdl/class_hdl/hdl_verify.rb +136 -0
  974. data/lib/tdl/data_inf/_data_mirrors.rb +92 -0
  975. data/lib/tdl/data_inf/bak/_data_mirrors.rb +273 -0
  976. data/lib/tdl/data_inf/bak/common_fifo_auto.rb +279 -0
  977. data/lib/tdl/data_inf/bak/data_bind_auto.rb +128 -0
  978. data/lib/tdl/data_inf/bak/data_c_direct_auto.rb +138 -0
  979. data/lib/tdl/data_inf/bak/data_c_direct_mirror_auto.rb +138 -0
  980. data/lib/tdl/data_inf/bak/data_c_tmp_cache_auto.rb +138 -0
  981. data/lib/tdl/data_inf/bak/data_condition_mirror_auto.rb +216 -0
  982. data/lib/tdl/data_inf/bak/data_condition_valve_auto.rb +215 -0
  983. data/lib/tdl/data_inf/bak/data_connect_pipe.rb +80 -0
  984. data/lib/tdl/data_inf/bak/data_connect_pipe_inf_auto.rb +138 -0
  985. data/lib/tdl/data_inf/bak/data_inf_c_interconnect.rb +86 -0
  986. data/lib/tdl/data_inf/bak/data_inf_c_pipe_condition_auto.rb +157 -0
  987. data/lib/tdl/data_inf/bak/data_inf_cross_clk.rb +60 -0
  988. data/lib/tdl/data_inf/bak/data_inf_interconnect.rb +144 -0
  989. data/lib/tdl/data_inf/bak/data_inf_planer.rb +78 -0
  990. data/lib/tdl/data_inf/bak/data_inf_ticktack.rb +80 -0
  991. data/lib/tdl/data_inf/bak/data_inf_ticktock_auto.rb +0 -0
  992. data/lib/tdl/data_inf/bak/data_mirrors_auto.rb +234 -0
  993. data/lib/tdl/data_inf/bak/data_mirrors_verb.sv_auto.rb +234 -0
  994. data/lib/tdl/data_inf/bak/data_uncompress_auto.rb +177 -0
  995. data/lib/tdl/data_inf/bak/data_valve_auto.rb +127 -0
  996. data/lib/tdl/data_inf/bak/datainf_c_master_empty_auto.rb +95 -0
  997. data/lib/tdl/data_inf/bak/datainf_c_slaver_empty_auto.rb +88 -0
  998. data/lib/tdl/data_inf/bak/datainf_master_empty_auto.rb +95 -0
  999. data/lib/tdl/data_inf/bak/datainf_slaver_empty_auto.rb +88 -0
  1000. data/lib/tdl/data_inf/bak/independent_clock_fifo_auto.rb +298 -0
  1001. data/lib/tdl/data_inf/bak/part_data_pair_map_auto.rb +306 -0
  1002. data/lib/tdl/data_inf/common_fifo_auto.rb +141 -0
  1003. data/lib/tdl/data_inf/data_bind_auto.rb +79 -0
  1004. data/lib/tdl/data_inf/data_c_cache_auto.rb +135 -0
  1005. data/lib/tdl/data_inf/data_c_direct_auto.rb +127 -0
  1006. data/lib/tdl/data_inf/data_c_direct_mirror_auto.rb +127 -0
  1007. data/lib/tdl/data_inf/data_c_interconnect.rb +97 -0
  1008. data/lib/tdl/data_inf/data_c_pipe_force_vld_auto.rb +127 -0
  1009. data/lib/tdl/data_inf/data_c_pipe_inf_auto.rb +127 -0
  1010. data/lib/tdl/data_inf/data_c_pipe_intc_M2S_verc_auto.rb +123 -0
  1011. data/lib/tdl/data_inf/data_c_tmp_cache_auto.rb +127 -0
  1012. data/lib/tdl/data_inf/data_condition_mirror_auto.rb +165 -0
  1013. data/lib/tdl/data_inf/data_condition_valve_auto.rb +164 -0
  1014. data/lib/tdl/data_inf/data_connect_pipe_inf_auto.rb +127 -0
  1015. data/lib/tdl/data_inf/data_inf_c_pipe_condition_auto.rb +136 -0
  1016. data/lib/tdl/data_inf/data_mirrors_auto.rb +173 -0
  1017. data/lib/tdl/data_inf/data_mirrors_verb.sv_auto.rb +173 -0
  1018. data/lib/tdl/data_inf/data_uncompress_auto.rb +146 -0
  1019. data/lib/tdl/data_inf/data_valve_auto.rb +104 -0
  1020. data/lib/tdl/data_inf/datainf_c_master_empty_auto.rb +85 -0
  1021. data/lib/tdl/data_inf/datainf_c_slaver_empty_auto.rb +68 -0
  1022. data/lib/tdl/data_inf/datainf_master_empty_auto.rb +85 -0
  1023. data/lib/tdl/data_inf/datainf_slaver_empty_auto.rb +68 -0
  1024. data/lib/tdl/data_inf/independent_clock_fifo_auto.rb +141 -0
  1025. data/lib/tdl/data_inf/part_data_pair_map_auto.rb +149 -0
  1026. data/lib/tdl/data_inf/path_lib.rb +18 -0
  1027. data/lib/tdl/elements/Reset.rb +153 -0
  1028. data/lib/tdl/elements/axi4.rb +642 -0
  1029. data/lib/tdl/elements/axi_lite.rb +246 -0
  1030. data/lib/tdl/elements/axi_stream.rb +674 -0
  1031. data/lib/tdl/elements/clock.rb +193 -0
  1032. data/lib/tdl/elements/common_configure_reg.rb +135 -0
  1033. data/lib/tdl/elements/data_inf.rb +660 -0
  1034. data/lib/tdl/elements/logic.rb +356 -0
  1035. data/lib/tdl/elements/mail_box.rb +64 -0
  1036. data/lib/tdl/elements/originclass.rb +689 -0
  1037. data/lib/tdl/elements/parameter.rb +318 -0
  1038. data/lib/tdl/elements/track_inf.rb +163 -0
  1039. data/lib/tdl/elements/videoinf.rb +224 -0
  1040. data/lib/tdl/examples/10_random/exp_random.rb +13 -0
  1041. data/lib/tdl/examples/10_random/exp_random.sv +36 -0
  1042. data/lib/tdl/examples/11_test_unit/dve.tcl +64 -0
  1043. data/lib/tdl/examples/11_test_unit/exp_test_unit.rb +58 -0
  1044. data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +35 -0
  1045. data/lib/tdl/examples/11_test_unit/exp_test_unit_constraints.xdc +25 -0
  1046. data/lib/tdl/examples/11_test_unit/modules/sub_md0.rb +23 -0
  1047. data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +41 -0
  1048. data/lib/tdl/examples/11_test_unit/modules/sub_md1.rb +25 -0
  1049. data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv +41 -0
  1050. data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +28 -0
  1051. data/lib/tdl/examples/11_test_unit/tu0.sv +38 -0
  1052. data/lib/tdl/examples/11_test_unit/tu1.sv +28 -0
  1053. data/lib/tdl/examples/1_define_module/example1.rb +39 -0
  1054. data/lib/tdl/examples/1_define_module/exmple_md.sv +50 -0
  1055. data/lib/tdl/examples/2_hdl_class/always_comb.rb +99 -0
  1056. data/lib/tdl/examples/2_hdl_class/always_ff.rb +143 -0
  1057. data/lib/tdl/examples/2_hdl_class/case.rb +93 -0
  1058. data/lib/tdl/examples/2_hdl_class/foreach.rb +21 -0
  1059. data/lib/tdl/examples/2_hdl_class/function.rb +34 -0
  1060. data/lib/tdl/examples/2_hdl_class/generate.rb +62 -0
  1061. data/lib/tdl/examples/2_hdl_class/module_def.rb +33 -0
  1062. data/lib/tdl/examples/2_hdl_class/module_head_import_package.rb +36 -0
  1063. data/lib/tdl/examples/2_hdl_class/module_instance_test.rb +13 -0
  1064. data/lib/tdl/examples/2_hdl_class/package.rb +29 -0
  1065. data/lib/tdl/examples/2_hdl_class/package2.rb +21 -0
  1066. data/lib/tdl/examples/2_hdl_class/simple_assign.rb +39 -0
  1067. data/lib/tdl/examples/2_hdl_class/state_case.rb +65 -0
  1068. data/lib/tdl/examples/2_hdl_class/struct.rb +25 -0
  1069. data/lib/tdl/examples/2_hdl_class/struct_function.rb +28 -0
  1070. data/lib/tdl/examples/2_hdl_class/test_axi4_M2S.rb +16 -0
  1071. data/lib/tdl/examples/2_hdl_class/test_initial_assert.rb +11 -0
  1072. data/lib/tdl/examples/2_hdl_class/test_inst_sugar.rb +28 -0
  1073. data/lib/tdl/examples/2_hdl_class/test_module_port.rb +47 -0
  1074. data/lib/tdl/examples/2_hdl_class/test_module_var.rb +18 -0
  1075. data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv +108 -0
  1076. data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +35 -0
  1077. data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv +105 -0
  1078. data/lib/tdl/examples/2_hdl_class/tmp/head_pkg_module.sv +42 -0
  1079. data/lib/tdl/examples/2_hdl_class/tmp/init_module.sv +110 -0
  1080. data/lib/tdl/examples/2_hdl_class/tmp/module_instance_test.sv +31 -0
  1081. data/lib/tdl/examples/2_hdl_class/tmp/port_module.sv +99 -0
  1082. data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv +27 -0
  1083. data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv +78 -0
  1084. data/lib/tdl/examples/2_hdl_class/tmp/test_axi4_M2S.sv +30 -0
  1085. data/lib/tdl/examples/2_hdl_class/tmp/test_foreach.sv +34 -0
  1086. data/lib/tdl/examples/2_hdl_class/tmp/test_function.sv +52 -0
  1087. data/lib/tdl/examples/2_hdl_class/tmp/test_initial_assert.sv +31 -0
  1088. data/lib/tdl/examples/2_hdl_class/tmp/test_inst_sugar.sv +42 -0
  1089. data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +36 -0
  1090. data/lib/tdl/examples/2_hdl_class/tmp/test_module_port.sv +33 -0
  1091. data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +35 -0
  1092. data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +38 -0
  1093. data/lib/tdl/examples/2_hdl_class/tmp/test_package2.sv +36 -0
  1094. data/lib/tdl/examples/2_hdl_class/tmp/test_struct.sv +38 -0
  1095. data/lib/tdl/examples/2_hdl_class/tmp/test_struct_function.sv +44 -0
  1096. data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +27 -0
  1097. data/lib/tdl/examples/2_hdl_class/tmp/text_generate.sv +54 -0
  1098. data/lib/tdl/examples/2_hdl_class/vcs_string.rb +5 -0
  1099. data/lib/tdl/examples/3_hdl_sdl_instance/hdl_test.sv +13 -0
  1100. data/lib/tdl/examples/3_hdl_sdl_instance/main.rb +26 -0
  1101. data/lib/tdl/examples/3_hdl_sdl_instance/main_md.sv +42 -0
  1102. data/lib/tdl/examples/3_hdl_sdl_instance/sdl_md.sv +30 -0
  1103. data/lib/tdl/examples/3_hdl_sdl_instance/sdl_test.rb +9 -0
  1104. data/lib/tdl/examples/4_generate/example.rb +38 -0
  1105. data/lib/tdl/examples/4_generate/test_generate.sv +59 -0
  1106. data/lib/tdl/examples/5_logic_combin/login_combin.rb +22 -0
  1107. data/lib/tdl/examples/5_logic_combin/test_logic_combin.sv +36 -0
  1108. data/lib/tdl/examples/6_module_with_interface/example.rb +48 -0
  1109. data/lib/tdl/examples/6_module_with_interface/example_interface.sv +40 -0
  1110. data/lib/tdl/examples/6_module_with_interface/inf_collect.rb +54 -0
  1111. data/lib/tdl/examples/6_module_with_interface/inf_collect.sv +63 -0
  1112. data/lib/tdl/examples/7_module_with_package/body_package.rb +3 -0
  1113. data/lib/tdl/examples/7_module_with_package/body_package.sv +25 -0
  1114. data/lib/tdl/examples/7_module_with_package/example_pkg.rb +20 -0
  1115. data/lib/tdl/examples/7_module_with_package/example_pkg.sv +35 -0
  1116. data/lib/tdl/examples/7_module_with_package/head_package.rb +8 -0
  1117. data/lib/tdl/examples/7_module_with_package/head_package.sv +29 -0
  1118. data/lib/tdl/examples/8_top_module/dve.tcl +64 -0
  1119. data/lib/tdl/examples/8_top_module/example.rb +8 -0
  1120. data/lib/tdl/examples/8_top_module/pins.yml +7 -0
  1121. data/lib/tdl/examples/8_top_module/tb_test_top.sv +29 -0
  1122. data/lib/tdl/examples/8_top_module/test_top.sv +28 -0
  1123. data/lib/tdl/examples/8_top_module/test_top_constraints.xdc +37 -0
  1124. data/lib/tdl/examples/9_itegration/A_itgt/a_test_md.sv +29 -0
  1125. data/lib/tdl/examples/9_itegration/A_itgt/a_test_module.rb +6 -0
  1126. data/lib/tdl/examples/9_itegration/A_itgt/itgt_module_a_block.rb +34 -0
  1127. data/lib/tdl/examples/9_itegration/clock_manage/itgt_module_clock_manage.rb +33 -0
  1128. data/lib/tdl/examples/9_itegration/clock_manage/simple_clock.rb +7 -0
  1129. data/lib/tdl/examples/9_itegration/clock_manage/simple_clock.sv +29 -0
  1130. data/lib/tdl/examples/9_itegration/dve.tcl +64 -0
  1131. data/lib/tdl/examples/9_itegration/pins.yml +4 -0
  1132. data/lib/tdl/examples/9_itegration/tb_test_top.sv +29 -0
  1133. data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +29 -0
  1134. data/lib/tdl/examples/9_itegration/test_top.sv +40 -0
  1135. data/lib/tdl/examples/9_itegration/test_top_constraints.xdc +29 -0
  1136. data/lib/tdl/examples/9_itegration/test_tttop.sv +40 -0
  1137. data/lib/tdl/examples/9_itegration/test_tttop_constraints.xdc +29 -0
  1138. data/lib/tdl/examples/9_itegration/top.rb +11 -0
  1139. data/lib/tdl/examples/readme.md +31 -0
  1140. data/lib/tdl/exlib/common_cfg_reg_inf.rb +139 -0
  1141. data/lib/tdl/exlib/constraints.rb +286 -0
  1142. data/lib/tdl/exlib/constraints_verb.rb +304 -0
  1143. data/lib/tdl/exlib/dve_tcl.rb +162 -0
  1144. data/lib/tdl/exlib/element_class_vars.rb +106 -0
  1145. data/lib/tdl/exlib/global_param.rb +108 -0
  1146. data/lib/tdl/exlib/integral_test/bak/integral_test.rb +206 -0
  1147. data/lib/tdl/exlib/integral_test/clock_itest.rb +28 -0
  1148. data/lib/tdl/exlib/integral_test/diff_clock_itest.rb +30 -0
  1149. data/lib/tdl/exlib/integral_test/io_itest.rb +41 -0
  1150. data/lib/tdl/exlib/integral_test/reset_itest.rb +31 -0
  1151. data/lib/tdl/exlib/integral_test/simple_logic_itest.rb +19 -0
  1152. data/lib/tdl/exlib/itegration.rb +307 -0
  1153. data/lib/tdl/exlib/itegration_verb.rb +913 -0
  1154. data/lib/tdl/exlib/parse_argv.rb +43 -0
  1155. data/lib/tdl/exlib/sdlmodule_sim.bak.rb +375 -0
  1156. data/lib/tdl/exlib/test_point.rb +287 -0
  1157. data/lib/tdl/global_scan.rb +134 -0
  1158. data/lib/tdl/rebuild_ele/axi4.rb +141 -0
  1159. data/lib/tdl/rebuild_ele/axi_lite.rb +56 -0
  1160. data/lib/tdl/rebuild_ele/axi_stream.rb +121 -0
  1161. data/lib/tdl/rebuild_ele/cm_ram_inf.sv +105 -0
  1162. data/lib/tdl/rebuild_ele/cm_ram_inf_define.rb +44 -0
  1163. data/lib/tdl/rebuild_ele/data_inf.rb +27 -0
  1164. data/lib/tdl/rebuild_ele/data_inf_c.rb +83 -0
  1165. data/lib/tdl/rebuild_ele/ele_base.rb +822 -0
  1166. data/lib/tdl/rebuild_ele/readme.md +1 -0
  1167. data/lib/tdl/sdlimplement/resource.yml +154 -0
  1168. data/lib/tdl/sdlimplement/sdl_impl_module.rb +391 -0
  1169. data/lib/tdl/sdlimplement/sdl_impl_param.rb +26 -0
  1170. data/lib/tdl/sdlimplement/test.rb +64 -0
  1171. data/lib/tdl/sdlmodule/bak/sdlmodule_varible_ex.rb +120 -0
  1172. data/lib/tdl/sdlmodule/generator_block_module.rb +84 -0
  1173. data/lib/tdl/sdlmodule/sdlmodule.rb +407 -0
  1174. data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb +333 -0
  1175. data/lib/tdl/sdlmodule/sdlmodule_draw.rb +272 -0
  1176. data/lib/tdl/sdlmodule/sdlmodule_head_logo.txt +10 -0
  1177. data/lib/tdl/sdlmodule/sdlmodule_instance.rb +623 -0
  1178. data/lib/tdl/sdlmodule/sdlmodule_port_define.rb +374 -0
  1179. data/lib/tdl/sdlmodule/sdlmodule_varible.rb +160 -0
  1180. data/lib/tdl/sdlmodule/sdlmodule_vcs_comptable.rb +140 -0
  1181. data/lib/tdl/sdlmodule/techbench_module.rb +14 -0
  1182. data/lib/tdl/sdlmodule/test_unit_module.rb +138 -0
  1183. data/lib/tdl/sdlmodule/top_module.rb +543 -0
  1184. data/lib/tdl/tdl.rb +265 -0
  1185. data/lib/tdl/tdlerror/tdlerror.rb +8 -0
  1186. data/lib/tdl/testunit/test_all.rb +4 -0
  1187. data/lib/tdl/testunit/test_array_chain.rb +89 -0
  1188. data/lib/tdl/testunit/test_tmp.rb +47 -0
  1189. metadata +1301 -0
data/lib/axi/SIM/tb_data_c_pipe_inf_20180417.sv ADDED
@@ -0,0 +1,114 @@
1
+ /**********************************************
2
+ _______________________________________
3
+ ___________ Cook Darwin __________
4
+ _______________________________________
5
+ descript:
6
+ author : Cook.Darwin
7
+ Version: VERA.0.0
8
+ creaded: 2018-4-17 10:24:55
9
+ madified:
10
+ ***********************************************/
11
+ `timescale 1ns/1ps
12
+
13
+ module tb_data_c_pipe_inf_20180417;
14
+
15
+ import AxiBfmPkg::*;
16
+ localparam DSIZE = 8;
17
+ logic clock;
18
+ logic rst_n;
19
+
20
+ clock_rst_verb #(
21
+ .ACTIVE (0 ),
22
+ .PERIOD_CNT (0 ),
23
+ .RST_HOLD (5 ),
24
+ .FreqM (100 )
25
+ )clock_rst_pixel(
26
+ .clock (clock ),
27
+ .rst_x (rst_n )
28
+ );
29
+
30
+ axi_stream_inf #(DSIZE) axis_slaver_inf (clock,rst_n,1'b1);
31
+ axi_stream_inf #(DSIZE) axis_master_inf (clock,rst_n,1'b1);
32
+
33
+ data_inf_c #(DSIZE+1) slaver_inf (clock,rst_n);
34
+ data_inf_c #(DSIZE+1) master_inf (clock,rst_n);
35
+
36
+ axis_to_data_inf #(
37
+ .CONTAIN_LAST ("ON")
38
+ )axis_to_data_inf_head_inst(
39
+ /* axi_stream_inf.slaver */ .axis_in (axis_slaver_inf ),
40
+ /* data_inf_c.master */ .data_out_inf (slaver_inf )
41
+ );
42
+
43
+ data_c_pipe_inf data_c_pipe_inf_inst(
44
+ /* data_inf_c.slaver */ .slaver (slaver_inf ),
45
+ /* data_inf_c.master */ .master (master_inf )
46
+ );
47
+
48
+ data_to_axis_inf_A1 data_to_axis_inf_A1_inst(
49
+ /* input */ .last_flag (1'b0 ),
50
+ /* data_inf_c.slaver */ .data_slaver (master_inf ),
51
+ /* axi_stream_inf.master */ .axis_master (axis_master_inf )
52
+ );
53
+
54
+ AxiStreamMasterBfm_c #(DSIZE) master_bfm = new(axis_slaver_inf);
55
+ AxiStreamSlaverBfm_c #(DSIZE) slaver_bfm = new(axis_master_inf);
56
+
57
+ initial begin
58
+ repeat(1000)
59
+ slaver_bfm.get_data($urandom_range(10,100));
60
+ end
61
+
62
+ initial begin
63
+ repeat(1000)
64
+ rand_stream_tk($urandom_range(10,100),1+$urandom_range(1,10)*$urandom_range(0,4));
65
+ end
66
+
67
+ task automatic rand_stream_tk(int send_rate,int len);
68
+ logic [7:0] s00_data [$];
69
+ // #(10us);
70
+ for(int CC=0;CC<len;CC++)
71
+ s00_data[CC] = $urandom_range(0,255);
72
+ master_bfm.gen_axi_stream(0,send_rate,s00_data);
73
+ endtask:rand_stream_tk
74
+
75
+ //--->> TRACK <<------------------------
76
+ typedef struct {
77
+ logic [7:0] data;
78
+ logic last;
79
+ } DataS;
80
+
81
+ mailbox PreM = new(100);
82
+ mailbox PostM = new(100);
83
+
84
+ DataS Pre_s;
85
+ DataS Post_s;
86
+ DataS Cmp_s;
87
+
88
+ always@(negedge clock)begin
89
+ if(axis_slaver_inf.axis_tvalid && axis_slaver_inf.axis_tready)begin
90
+ Pre_s.data = axis_slaver_inf.axis_tdata;
91
+ Pre_s.last = axis_slaver_inf.axis_tlast;
92
+ PreM.put(Pre_s);
93
+ end
94
+ end
95
+
96
+
97
+ always@(negedge clock)begin
98
+ if(axis_master_inf.axis_tvalid && axis_master_inf.axis_tready)begin
99
+ Post_s.data = axis_master_inf.axis_tdata;
100
+ Post_s.last = axis_master_inf.axis_tlast;
101
+
102
+ PreM.try_get(Cmp_s);
103
+
104
+ if((Cmp_s.data != Post_s.data) || (Cmp_s.last != Post_s.last))begin
105
+ $error("\n## ERROR IN STREAM ##\n");
106
+ repeat(3)
107
+ @(posedge clock);
108
+ $stop;
109
+ end
110
+
111
+ end
112
+ end
113
+ //---<< TRACK >>------------------------
114
+ endmodule
data/lib/axi/SIM/tb_wide_axis_to_axi4_wr.sv ADDED
@@ -0,0 +1,81 @@
1
+ /**********************************************
2
+ _______________________________________
3
+ ___________ Cook Darwin __________
4
+ _______________________________________
5
+ descript:
6
+ author : Cook.Darwin
7
+ Version: VERA.0.0
8
+ creaded: ###### Wed May 6 13:44:14 CST 2020
9
+ madified:
10
+ ***********************************************/
11
+ `timescale 1ns/1ps
12
+ module tb_wide_axis_to_axi4_wr;
13
+
14
+ import AxiBfmPkg::*;
15
+ localparam DSIZE = 64;
16
+ logic clock;
17
+ logic rst_n;
18
+
19
+ int stcnt,mtcnt;
20
+
21
+ clock_rst_verb #(
22
+ .ACTIVE (0 ),
23
+ .PERIOD_CNT (0 ),
24
+ .RST_HOLD (5 ),
25
+ .FreqM (100 )
26
+ )clock_rst_pixel(
27
+ .clock (clock ),
28
+ .rst_x (rst_n )
29
+ );
30
+
31
+ axi_stream_inf #(DSIZE) axis_in_inf (clock,rst_n,1'b1);
32
+
33
+ axi_inf #(
34
+ .IDSIZE (1 ),
35
+ .ASIZE (8 ),
36
+ .LSIZE (8 ),
37
+ .DSIZE (DSIZE ),
38
+ .MODE ("BOTH" )
39
+ )axi4_out(
40
+ .axi_aclk (clock),
41
+ .axi_aresetn (rst_n)
42
+ );
43
+
44
+ wide_axis_to_axi4_wr wide_axis_to_axi4_wr_inst(
45
+ /* input logic[31:0] */ .addr (0 ),
46
+ /* input logic[31:0] */ .max_length (128 ),
47
+ /* axi_stream_inf.slaver */ .axis_in (axis_in_inf ),
48
+ /* axi_inf.master_wr */ .axi_wr (axi4_out )
49
+ );
50
+
51
+ AxiStreamMasterBfm_c #(DSIZE) AxisMasterBfm = new(axis_in_inf);
52
+
53
+ Axi4SlaverBfm_c #(
54
+ .IDSIZE (axi4_out.IDSIZE ),
55
+ .ASIZE (axi4_out.ASIZE ),
56
+ .DSIZE (axi4_out.DSIZE ),
57
+ .LSIZE (axi4_out.LSIZE ),
58
+ .MSG ("ON" )
59
+ ) Axi4SlaverBfm;
60
+
61
+ logic [DSIZE-1:0] wdata_queue [$];
62
+
63
+ initial begin
64
+ wait(rst_n);
65
+ wdata_queue = {1,2,3,4,5,6,7,8,9,10};
66
+ // wdata_queue = {>>{64'd1,64'd2,64'd3,64'd4}};
67
+ #(100us);
68
+ repeat(100) begin
69
+ AxisMasterBfm.gen_axi_stream(523,100,wdata_queue);
70
+ end
71
+ end
72
+
73
+ initial begin
74
+ wait(rst_n);
75
+ Axi4SlaverBfm = new(axi4_out);
76
+ repeat(100) begin
77
+ Axi4SlaverBfm.run(50,50);
78
+ end
79
+ end
80
+
81
+ endmodule
data/lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip.sv ADDED
@@ -0,0 +1,589 @@
1
+ /**********************************************
2
+ _______________________________________
3
+ ___________ Cook Darwin __________
4
+ _______________________________________
5
+ descript:
6
+ author : Cook.Darwin
7
+ Version: VERA.0.0
8
+ creaded: 2016/10/12
9
+ madified:
10
+ ***********************************************/
11
+ `timescale 1ns / 1ps
12
+ module axi4_to_native_for_ddr_ip #(
13
+ parameter ADDR_WIDTH = 27,
14
+ parameter DATA_WIDTH = 256
15
+ )(
16
+ axi_inf.slaver axi_inf,
17
+ output logic[ADDR_WIDTH-1:0] app_addr,
18
+ output logic[2:0] app_cmd,
19
+ output logic app_en,
20
+ output logic[DATA_WIDTH-1:0] app_wdf_data,
21
+ output logic app_wdf_end,
22
+ output logic[DATA_WIDTH/8-1:0] app_wdf_mask,
23
+ output logic app_wdf_wren,
24
+ input [DATA_WIDTH-1:0] app_rd_data,
25
+ input app_rd_data_end,
26
+ input app_rd_data_valid,
27
+ input app_rdy,
28
+ input app_wdf_rdy,
29
+ input init_calib_complete
30
+ );
31
+
32
+ logic clock,rst;
33
+
34
+ assign clock = axi_inf.axi_aclk;
35
+ assign rst = !axi_inf.axi_aresetn;
36
+ //assign rst = !axi_inf.axi_aresetn || axi_inf.axi_wevld || axi_inf.axi_revld;
37
+ typedef enum {
38
+ NOP=0,
39
+ WIDLE=1,
40
+ RIDLE=2,
41
+ EXEC_WR=3,
42
+ WR_CMD_E=4,
43
+ WR_FIFO_E=5,
44
+ WR_END=6,
45
+ EXEC_RD=7,
46
+ RD_FIFO_E=8,
47
+ RD_END=9,
48
+ RD_AXI_E=10,
49
+ APP_CMD_E=11,
50
+ CLEAR_WR_FIFO=12
51
+ } MASTER_STATE;
52
+
53
+ MASTER_STATE mnstate,mcstate;
54
+
55
+ always@(posedge clock,posedge rst)begin
56
+ if(rst) mcstate <= NOP;
57
+ // else if(axi_inf.axi_wevld ||��?axi_inf.axi_revld)
58
+ // mcstate <= NOP;
59
+ else mcstate <= mnstate;
60
+ end
61
+
62
+ logic wr_fifo_empty;
63
+ // (* dont_touch = "true" *)
64
+ // logic app_en_last;
65
+ (* dont_touch = "true" *)
66
+ logic app_en_wr_last;
67
+ (* dont_touch = "true" *)
68
+ logic app_en_rd_last;
69
+ logic [8:0] app_len;
70
+ logic [8:0] app_wr_len;
71
+ logic [8:0] app_rd_len;
72
+ logic [9:0] wdf_cnt;
73
+ (* dont_touch = "true" *)
74
+ logic wdf_last;
75
+
76
+ always@(*)
77
+ case(mcstate)
78
+ NOP:
79
+ if(init_calib_complete && app_rdy)
80
+ mnstate = WIDLE;
81
+ else mnstate = NOP;
82
+ WIDLE:
83
+ if(axi_inf.axi_awvalid && axi_inf.axi_awready)
84
+ mnstate = EXEC_WR;
85
+ else mnstate = RIDLE;
86
+ RIDLE:
87
+ if(axi_inf.axi_arvalid && axi_inf.axi_arready)
88
+ mnstate = EXEC_RD;
89
+ else mnstate = WIDLE;
90
+ EXEC_WR:
91
+ // if(axi_inf.axi_wlast && axi_inf.axi_wvalid && axi_inf.axi_wready)
92
+ // if(!wr_fifo_empty && axi_inf.axi_wvalid && axi_inf.axi_wready)
93
+ if(!wr_fifo_empty)
94
+ // mnstate = WR_FIFO_E;
95
+ mnstate = WR_CMD_E;
96
+ else mnstate = EXEC_WR;
97
+ WR_CMD_E:
98
+ if(app_en_wr_last && app_rdy && app_en && wdf_last && app_wdf_wren && app_wdf_rdy)
99
+ mnstate = WR_END;
100
+ else if(app_en_wr_last && app_rdy && app_en)
101
+ // if(app_en_last)
102
+ mnstate = WR_FIFO_E;
103
+ else if(wdf_last && app_wdf_wren && app_wdf_rdy) //data burst first
104
+ mnstate = APP_CMD_E;
105
+ else mnstate = WR_CMD_E;
106
+ APP_CMD_E:
107
+ if(app_en_wr_last && app_rdy && app_en)
108
+ mnstate = WR_END;
109
+ else mnstate = APP_CMD_E;
110
+ WR_FIFO_E:
111
+ // if(wr_fifo_empty)
112
+ if(wdf_last && app_wdf_wren && app_wdf_rdy)
113
+ // if(app_en_last && wr_fifo_empty)
114
+ mnstate = WR_END;
115
+ else mnstate = WR_FIFO_E;
116
+ WR_END:
117
+ if(axi_inf.axi_bready)begin
118
+ if(wr_fifo_empty)
119
+ mnstate = RIDLE;
120
+ else mnstate = CLEAR_WR_FIFO;
121
+ end else mnstate = WR_END;
122
+ EXEC_RD:
123
+ if(app_en_rd_last && app_rdy && app_en)
124
+ mnstate = RD_AXI_E;
125
+ else mnstate = EXEC_RD;
126
+ RD_AXI_E:
127
+ if(axi_inf.axi_rvalid && axi_inf.axi_rlast && axi_inf.axi_rready)
128
+ mnstate = WIDLE;
129
+ else mnstate = RD_AXI_E;
130
+ // EXEC_RD:
131
+ // // if(axi_inf.axi_rvalid && axi_inf.axi_rlast && axi_inf.axi_rready)
132
+ // if(app_en_last && app_rdy)
133
+ // mnstate = RD_FIFO_E;
134
+ // else mnstate = EXEC_RD;
135
+ // RD_FIFO_E:
136
+ // if(axi_inf.axi_rvalid && axi_inf.axi_rlast && axi_inf.axi_rready)
137
+ // mnstate = IDLE;
138
+ // else mnstate = RD_FIFO_E;
139
+ CLEAR_WR_FIFO:
140
+ if(wr_fifo_empty)
141
+ mnstate = RIDLE;
142
+ else mnstate = CLEAR_WR_FIFO;
143
+ default: mnstate = NOP;
144
+ endcase
145
+
146
+ //--->> FORCE CLEAR FIFO <<------------------
147
+ logic clear_wr_fifo_en;
148
+ always@(posedge clock,posedge rst)
149
+ if(rst) clear_wr_fifo_en <= 1'b0;
150
+ else begin
151
+ case(mnstate)
152
+ CLEAR_WR_FIFO:
153
+ clear_wr_fifo_en <= 1'b1;
154
+ default:
155
+ clear_wr_fifo_en <= 1'b0;
156
+ endcase
157
+ end
158
+ //---<< FORCE CLEAR FIFO >>------------------
159
+ logic wr_enable,rd_enable;
160
+ logic rd_app_enable;
161
+
162
+ always@(posedge clock,posedge rst)
163
+ if(rst) wr_enable <= 1'b0;
164
+ else
165
+ case(mnstate)
166
+ // EXEC_WR,WR_CMD_E,WR_FIFO_E:
167
+ WR_CMD_E,APP_CMD_E:
168
+ wr_enable <= 1'b1;
169
+ default: wr_enable <= 1'b0;
170
+ endcase
171
+
172
+ always@(posedge clock,posedge rst)
173
+ if(rst) rd_app_enable <= 1'b0;
174
+ else
175
+ case(mnstate)
176
+ EXEC_RD,RD_AXI_E:
177
+ rd_app_enable <= 1'b1;
178
+ default: rd_app_enable <= 1'b0;
179
+ endcase
180
+
181
+ always@(posedge clock,posedge rst)
182
+ if(rst) rd_enable <= 1'b0;
183
+ else
184
+ case(mnstate)
185
+ EXEC_RD:
186
+ rd_enable <= 1'b1;
187
+ default: rd_enable <= 1'b0;
188
+ endcase
189
+ //--->> WR DDR DATA <<-------------------
190
+ logic rd_fifo_full;
191
+ logic rd_fifo_empty;
192
+ (* dont_touch = "true" *)
193
+ logic rd_fifo_en;
194
+ // assign rd_fifo_en = (rd_enable && axi_inf.axi_rready) || wr_enable;
195
+ assign rd_fifo_en = (rd_app_enable && axi_inf.axi_rready && !rd_fifo_empty) ;
196
+ // assign rd_fifo_en = (rd_app_enable && axi_inf.axi_rready && !rd_fifo_empty) || wr_enable;
197
+ generate
198
+ if(DATA_WIDTH!=512)begin
199
+ FIFO_DDR_IP_BRG FIFO_DDR_IP_BRG_rd (
200
+ /* input */ .clk (clock ),
201
+ /* input */ .rst (rst ),
202
+ /* input [255:0] */ .din (app_rd_data ),
203
+ // /* input */ .wr_en (app_rd_data_valid && !rd_fifo_full ),
204
+ /* input */ .wr_en (app_rd_data_valid ),
205
+ /* input */ .rd_en (/*rd_enable && axi_inf.axi_rready*/rd_fifo_en ),
206
+ /* output [255:0] */ .dout (axi_inf.axi_rdata ),
207
+ /* output */ .full (rd_fifo_full ),
208
+ /* output */ .empty (rd_fifo_empty )
209
+ );
210
+ end else begin
211
+ FIFO_DDR_IP_BRG_512 FIFO_DDR_IP_BRG_rd (
212
+ /* input */ .clk (clock ),
213
+ /* input */ .srst (rst ),
214
+ /* input [511:0] */ .din (app_rd_data ),
215
+ // /* input */ .wr_en (app_rd_data_valid && !rd_fifo_full ),
216
+ /* input */ .wr_en (app_rd_data_valid ),
217
+ /* input */ .rd_en (/*rd_enable && axi_inf.axi_rready */rd_fifo_en ),
218
+ /* output [511:0] */ .dout (axi_inf.axi_rdata ),
219
+ /* output */ .full (rd_fifo_full ),
220
+ /* output */ .empty (rd_fifo_empty )
221
+ );
222
+ end
223
+ endgenerate
224
+
225
+ assign axi_inf.axi_rvalid = !rd_fifo_empty && rd_app_enable;
226
+ //---<< WR DDR DATA >>-------------------
227
+ //--->> RD DDR DATA <<-------------------
228
+ (* dont_touch = "true" *)
229
+ wire wr_fifo_wen;
230
+ // assign wr_fifo_wen = wr_enable && axi_inf.axi_wvalid && axi_inf.axi_wready;
231
+ assign wr_fifo_wen = axi_inf.axi_wvalid && axi_inf.axi_wready;
232
+ (* dont_touch = "true" *)
233
+ wire wr_fifo_ren;
234
+ // assign wr_fifo_ren = (wr_enable && app_wdf_rdy) || rd_enable;
235
+ assign wr_fifo_ren = (app_wdf_wren && app_wdf_rdy) || clear_wr_fifo_en;
236
+ // assign wr_fifo_ren = (app_wdf_wren && app_wdf_rdy);
237
+ logic wr_fifo_full;
238
+ generate
239
+ if(DATA_WIDTH!=512)begin
240
+ FIFO_DDR_IP_BRG FIFO_DDR_IP_BRG_wr (
241
+ /* input */ .clk (clock ),
242
+ /* input */ .rst (rst ),
243
+ /* input [255:0] */ .din (axi_inf.axi_wdata ),
244
+ /* input */ .wr_en (/*wr_enable && axi_inf.axi_wvalid && axi_inf.axi_wready*/wr_fifo_wen ),
245
+ /* input */ .rd_en (/*wr_enable && app_wdf_rdy*/ wr_fifo_ren ),
246
+ /* output [255:0] */ .dout (app_wdf_data ),
247
+ /* output */ .full (wr_fifo_full ),
248
+ /* output */ .empty (wr_fifo_empty )
249
+ );
250
+ end else begin
251
+ FIFO_DDR_IP_BRG_512 FIFO_DDR_IP_BRG_wr (
252
+ /* input */ .clk (clock ),
253
+ /* input */ .srst (rst ),
254
+ /* input [511:0] */ .din (axi_inf.axi_wdata ),
255
+ /* input */ .wr_en (/*wr_enable && axi_inf.axi_wvalid && axi_inf.axi_wready*/ wr_fifo_wen ),
256
+ /* input */ .rd_en (/*wr_enable && app_wdf_rdy*/ wr_fifo_ren ),
257
+ /* output [511:0] */ .dout (app_wdf_data ),
258
+ /* output */ .full (wr_fifo_full ),
259
+ /* output */ .empty (wr_fifo_empty )
260
+ );
261
+ end
262
+ endgenerate
263
+
264
+ // assign axi_inf.axi_wready = !wr_fifo_full && wr_enable;
265
+ // assign axi_inf.axi_wready = wr_enable;
266
+ assign axi_inf.axi_wready = !wr_fifo_full;
267
+ // assign app_wdf_wren = !wr_fifo_empty;
268
+ assign app_wdf_mask = {(DATA_WIDTH/8){1'b0}};
269
+ assign app_wdf_end = 1'b1;
270
+
271
+ //---->> APP WRITE <<--------------------
272
+ always@(posedge clock,posedge rst)
273
+ if(rst) wdf_cnt <= '0;
274
+ else begin
275
+ if(axi_inf.axi_awready)
276
+ wdf_cnt <= '0;
277
+ else if(wdf_last && app_wdf_wren && app_wdf_rdy)
278
+ wdf_cnt <= '0;
279
+ else if(app_wdf_wren && app_wdf_rdy)
280
+ wdf_cnt <= wdf_cnt + 1'b1;
281
+ else wdf_cnt <= wdf_cnt;
282
+ end
283
+
284
+ always@(posedge clock,posedge rst)
285
+ if(rst) wdf_last <= 1'b0;
286
+ else begin
287
+ if(axi_inf.axi_awvalid && axi_inf.axi_awready && axi_inf.axi_awlen==0)
288
+ wdf_last <= 1'b1;
289
+ else if(wdf_last && app_wdf_wren && app_wdf_rdy)
290
+ wdf_last <= 1'b0;
291
+ else if(app_wdf_wren && app_wdf_rdy && (wdf_cnt == app_wr_len-2))
292
+ wdf_last <= 1'b1;
293
+ else wdf_last <= wdf_last;
294
+ end
295
+
296
+
297
+ always@(posedge clock,posedge rst)
298
+ if(rst) app_wdf_wren <= 1'b0;
299
+ else
300
+ case(mnstate)
301
+ WR_CMD_E,WR_FIFO_E:
302
+ app_wdf_wren <= 1'b1;
303
+ default: app_wdf_wren <= 1'b0;
304
+ endcase
305
+ //----<< APP WRITE >>--------------------
306
+ //--->> RD DDR DATA <<-------------------
307
+ //--->> WR AXI CMD <<--------------------
308
+ // typedef enum {AWIDLE,AWRDY,AWEND} AWSTATE;
309
+ // AWSTATE awcstate,awnstate;
310
+ //
311
+ // always@(posedge clock,posedge rst)
312
+ // if(rst) awcstate <= AWIDLE;
313
+ // else awcstate <= awnstate;
314
+ //
315
+ // always@(*)
316
+ // case(awcstate)
317
+ // AWIDLE:
318
+ // if(wr_enable)
319
+ // awnstate = AWRDY;
320
+ // else awnstate = AWIDLE;
321
+ // AWRDY:
322
+ // if(axi_inf.axi_awvalid)
323
+ // awnstate = AWEND;
324
+ // else awnstate = AWIDLE;
325
+ // AWEND:
326
+ // if(!wr_enable)
327
+ // awnstate = AWIDLE;
328
+ // else awnstate = AWEND;
329
+ // default: awnstate = AWIDLE;
330
+ // endcase
331
+
332
+ always@(posedge clock,posedge rst)
333
+ if(rst) axi_inf.axi_awready <= 1'b0;
334
+ else
335
+ case(mnstate)
336
+ WIDLE: axi_inf.axi_awready <= 1'b1;
337
+ default:axi_inf.axi_awready <= 1'b0;
338
+ endcase
339
+
340
+ always@(posedge clock,posedge rst)
341
+ if(rst) axi_inf.axi_arready <= 1'b0;
342
+ else
343
+ case(mnstate)
344
+ RIDLE: axi_inf.axi_arready <= 1'b1;
345
+ default:axi_inf.axi_arready <= 1'b0;
346
+ endcase
347
+ //---<< WR AXI CMD >>--------------------
348
+ //--->> AXI BURST <<------------------
349
+ // always@(posedge clock,posedge rst)
350
+ // if(rst) app_len <= 9'd0;
351
+ // else begin
352
+ // if(axi_inf.axi_awvalid && axi_inf.axi_awready)
353
+ // app_len <= axi_inf.axi_awlen+1'b1;
354
+ // else if(axi_inf.axi_arvalid && axi_inf.axi_arready)
355
+ // app_len <= axi_inf.axi_arlen+1'b1;
356
+ // else app_len <= app_len;
357
+ // end
358
+
359
+ always@(posedge clock,posedge rst)
360
+ if(rst) app_wr_len <= 9'd0;
361
+ else begin
362
+ if(axi_inf.axi_awvalid && axi_inf.axi_awready)
363
+ app_wr_len <= axi_inf.axi_awlen+1'b1;
364
+ else app_wr_len <= app_wr_len;
365
+ end
366
+
367
+
368
+ always@(posedge clock,posedge rst)
369
+ if(rst) app_rd_len <= 9'd0;
370
+ else begin
371
+ if(axi_inf.axi_arvalid && axi_inf.axi_arready)
372
+ app_rd_len <= axi_inf.axi_arlen+1'b1;
373
+ else app_rd_len <= app_rd_len;
374
+ end
375
+
376
+ logic [8:0] len_cnt;
377
+ always@(posedge clock,posedge rst)
378
+ if(rst) len_cnt <= 9'd0;
379
+ else begin
380
+ if(wr_enable || rd_enable)begin
381
+ if(app_rdy && app_en)
382
+ len_cnt <= len_cnt + 1'b1;
383
+ else len_cnt <= len_cnt;
384
+ end else len_cnt <= 9'd0;
385
+ end
386
+ //---<< AXI BURST >>------------------
387
+ // (* dont_touch = "true" *)
388
+ // logic app_en_last;
389
+ // always@(posedge clock,posedge rst)
390
+ // if(rst) app_en_last <= 1'b0;
391
+ // else begin
392
+ // // if(wr_enable || rd_enable)
393
+ // // // app_en_last <= (len_cnt==(app_len-1 ) && app_en && app_rdy) || app_en_last;
394
+ // // app_en_last <= len_cnt==(app_len-1 ) || (len_cnt==(app_len-2 ) && app_en && app_rdy);
395
+ // // // else if(app_en_last && app_rdy && app_en)
396
+ // // // app_en_last <= 1'b0;
397
+ // // // else app_en_last <= app_en_last;
398
+ // // else app_en_last <= 1'b0;
399
+ // if(wr_enable)
400
+ // app_en_last <= len_cnt==(app_wr_len-1 ) || (len_cnt==(app_wr_len-2 ) && app_en && app_rdy);
401
+ // else if(rd_enable)
402
+ // app_en_last <= len_cnt==(app_rd_len-1 ) || (len_cnt==(app_rd_len-2 ) && app_en && app_rdy);
403
+ // else app_en_last <= 1'b0;
404
+ // end
405
+
406
+ //
407
+ always@(posedge clock,posedge rst)
408
+ if(rst) app_en_wr_last <= 1'b0;
409
+ else begin
410
+ if(axi_inf.axi_awvalid && axi_inf.axi_awready && axi_inf.axi_awlen==0)
411
+ app_en_wr_last <= 1'b1;
412
+ else if(app_en && app_rdy && app_en_wr_last)
413
+ app_en_wr_last <= 1'b0;
414
+ else if(len_cnt==(app_wr_len-2 ) && app_en && app_rdy)
415
+ app_en_wr_last <= 1'b1;
416
+ else app_en_wr_last <= app_en_wr_last;
417
+ end
418
+
419
+ always@(posedge clock,posedge rst)
420
+ if(rst) app_en_rd_last <= 1'b0;
421
+ else begin
422
+ if(axi_inf.axi_arvalid && axi_inf.axi_arready && axi_inf.axi_arlen==0)
423
+ app_en_rd_last <= 1'b1;
424
+ else if(rd_enable)
425
+ app_en_rd_last <= len_cnt==(app_rd_len-1 ) || (len_cnt==(app_rd_len-2 ) && app_en && app_rdy);
426
+ else app_en_rd_last <= 1'b0;
427
+ end
428
+
429
+ always@(posedge clock,posedge rst)
430
+ if(rst) axi_inf.axi_bvalid <= 1'b0;
431
+ else
432
+ case(mnstate)
433
+ WR_END: axi_inf.axi_bvalid <= 1'b1;
434
+ default: axi_inf.axi_bvalid <= 1'b0;
435
+ endcase
436
+
437
+ assign axi_inf.axi_bresp = 2'b00;
438
+ // assign axi_inf.axi_bid = 0;
439
+ // assign app_en_last = app_en_last;
440
+ //---<< AXI WR BURST >>------------------
441
+ //--->> DDR ADDR <<-------------------
442
+ logic [26:0] base_wr_addr;
443
+
444
+ always@(posedge clock,posedge rst)
445
+ if(rst) base_wr_addr <= 27'd0;
446
+ else begin
447
+ if(axi_inf.axi_awvalid && axi_inf.axi_awready)
448
+ base_wr_addr <= axi_inf.axi_awaddr;
449
+ else base_wr_addr <= base_wr_addr;
450
+ end
451
+
452
+ always@(posedge clock,posedge rst)begin
453
+ if(rst) app_addr <= 27'd0;
454
+ else begin
455
+ if(app_rdy && app_en)
456
+ app_addr <= app_addr + 8;
457
+ else if(axi_inf.axi_awvalid && axi_inf.axi_awready)
458
+ app_addr <= axi_inf.axi_awaddr;
459
+ else if(axi_inf.axi_arvalid && axi_inf.axi_arready)
460
+ app_addr <= axi_inf.axi_araddr;
461
+ else app_addr <= app_addr;
462
+ end
463
+ end
464
+
465
+ // always@(posedge clock,posedge rst)
466
+ // if(rst) app_en <= 1'b0;
467
+ // else begin
468
+ // // // if(wr_enable || rd_enable)begin
469
+ // // // app_en <= 1'b1;
470
+ // // if(wr_enable || rd_enable)begin
471
+ // // if(app_en_last)begin
472
+ // // // app_en <= 1'b0;
473
+ // // // app_en <= !app_rdy;
474
+ // // if(app_en)begin
475
+ // // if(app_rdy)
476
+ // // app_en <= 1'b0;
477
+ // // else app_en <= app_en;
478
+ // // end else app_en <= 1'b0;
479
+ // // end else app_en <= 1'b1;
480
+ // //
481
+ // // // if(app_en_last && app_en && app_rdy)
482
+ // // // app_en <= 1'b0;
483
+ // // // else app_en <= app_en;
484
+ // //
485
+ // // end else app_en <= 1'b0;
486
+ //
487
+ //
488
+ // end
489
+
490
+ assign app_en = wr_enable || rd_enable;
491
+ assign app_cmd = wr_enable ? 3'b000 : (rd_enable? 3'b001 : 3'b111);
492
+ // reg [2:0] app_cmd_reg;
493
+ // always@(posedge clock,posedge rst)
494
+ // if(rst) app_cmd_reg <= 3'b111;
495
+ // else begin
496
+ // if(wr_enable)
497
+ // app_cmd_reg <= 3'b000;
498
+ // else if(rd_enable)
499
+ // app_cmd_reg <= 3'b001;
500
+ // else app_cmd_reg <= app_cmd_reg;
501
+ // end
502
+ //
503
+ // assign app_cmd = app_cmd_reg;
504
+
505
+ //--->> axi read data last <<-------------
506
+ logic [8:0] axi_rd_cnt;
507
+
508
+ always@(posedge clock,posedge rst)
509
+ if(rst) axi_rd_cnt <= 9'd0;
510
+ else begin
511
+ // if(rd_enable)begin
512
+ if(rd_app_enable)begin
513
+ if(axi_inf.axi_rready && axi_inf.axi_rvalid)
514
+ axi_rd_cnt <= axi_rd_cnt + 1'b1;
515
+ else axi_rd_cnt <= axi_rd_cnt;
516
+ end else axi_rd_cnt <= 9'd0;
517
+ end
518
+ always@(posedge clock,posedge rst)
519
+ if(rst) axi_inf.axi_rlast <= 1'b0;
520
+ else begin
521
+ // if(!rd_enable)
522
+ if(!rd_app_enable)
523
+ axi_inf.axi_rlast <= 1'b0;
524
+ else if(app_rd_len==1)
525
+ axi_inf.axi_rlast <= 1'b1;
526
+ else if(axi_inf.axi_rready && axi_inf.axi_rvalid && axi_inf.axi_rlast)
527
+ axi_inf.axi_rlast <= 1'b0;
528
+ else if(axi_inf.axi_rready && axi_inf.axi_rvalid && axi_rd_cnt == (app_rd_len-2))
529
+ axi_inf.axi_rlast <= 1'b1;
530
+ else axi_inf.axi_rlast <= axi_inf.axi_rlast;
531
+ end
532
+ //---<< axi read data last >>-------------
533
+ // assign axi_inf.axi_rid = 0;
534
+ assign axi_inf.axi_rresp = 2'b00;
535
+ //--->> WR ID <<--------------------------
536
+ always@(posedge clock,posedge rst)
537
+ if(rst) axi_inf.axi_bid <= 0;
538
+ else begin
539
+ if(axi_inf.axi_awvalid && axi_inf.axi_awready)
540
+ axi_inf.axi_bid <= axi_inf.axi_awid;
541
+ else axi_inf.axi_bid <= axi_inf.axi_bid;
542
+ end
543
+ //---<< WR ID >>--------------------------
544
+ //--->> RD ID <<--------------------------
545
+ always@(posedge clock,posedge rst)
546
+ if(rst) axi_inf.axi_rid <= 0;
547
+ else begin
548
+ if(axi_inf.axi_arvalid && axi_inf.axi_arready)
549
+ axi_inf.axi_rid <= axi_inf.axi_arid;
550
+ else axi_inf.axi_rid <= axi_inf.axi_rid;
551
+ end
552
+ //---<< RD ID >>--------------------------
553
+ //--->> APP WRITE CNT <<------------------
554
+ (* dont_touch="true" *)
555
+ logic [5:0] app_wr_cmd_cnt;
556
+ (* dont_touch="true" *)
557
+ logic [5:0] app_wr_data_cnt;
558
+ (* dont_touch="true" *)
559
+ logic [5:0] app_cnt_delta;
560
+
561
+ always@(posedge clock,posedge rst)
562
+ if(rst) app_wr_cmd_cnt <= '0;
563
+ else begin
564
+ if(app_en && app_rdy && app_cmd == 2'b00)
565
+ app_wr_cmd_cnt <= app_wr_cmd_cnt + 1'b1;
566
+ else app_wr_cmd_cnt <= app_wr_cmd_cnt;
567
+ end
568
+
569
+ always@(posedge clock,posedge rst)
570
+ if(rst) app_wr_data_cnt <= '0;
571
+ else begin
572
+ if(app_wdf_wren && app_wdf_rdy)
573
+ // if(app_rd_data_valid)
574
+ app_wr_data_cnt <= app_wr_data_cnt + 1'b1;
575
+ else app_wr_data_cnt <= app_wr_data_cnt;
576
+ end
577
+
578
+ always@(posedge clock,posedge rst)
579
+ if(rst) app_cnt_delta <= '0;
580
+ else begin
581
+ if(!app_wdf_wren && !app_en)
582
+ // if(!app_rd_data_valid && !app_en)
583
+ app_cnt_delta <= app_wr_cmd_cnt-app_wr_data_cnt;
584
+ else app_cnt_delta <= app_cnt_delta;
585
+ end
586
+ //---<< APP WRITE CNT >>------------------
587
+
588
+
589
+ endmodule