axi_tdl 0.0.2

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Files changed (1189) hide show
  1. checksums.yaml +7 -0
  2. data/.gitignore +8 -0
  3. data/CODE_OF_CONDUCT.md +74 -0
  4. data/Gemfile +6 -0
  5. data/Gemfile.lock +43 -0
  6. data/LICENSE +504 -0
  7. data/README.md +311 -0
  8. data/Rakefile +18 -0
  9. data/axi_tdl.gemspec +43 -0
  10. data/bin/console +14 -0
  11. data/bin/setup +8 -0
  12. data/lib/.rspec +1 -0
  13. data/lib/axi/AXI4/axi4_combin_wr_rd_batch.sv +59 -0
  14. data/lib/axi/AXI4/axi4_direct.sv +137 -0
  15. data/lib/axi/AXI4/axi4_direct_A1.sv +229 -0
  16. data/lib/axi/AXI4/axi4_direct_B1.sv +74 -0
  17. data/lib/axi/AXI4/axi4_direct_verb.sv +79 -0
  18. data/lib/axi/AXI4/axi4_direct_verc.sv +146 -0
  19. data/lib/axi/AXI4/axi4_dpram_cache.rb +106 -0
  20. data/lib/axi/AXI4/axi4_dpram_cache.sv +112 -0
  21. data/lib/axi/AXI4/axi4_long_to_axi4_wide.sv +85 -0
  22. data/lib/axi/AXI4/axi4_long_to_axi4_wide_A1.sv +96 -0
  23. data/lib/axi/AXI4/axi4_long_to_axi4_wide_track.sv +118 -0
  24. data/lib/axi/AXI4/axi4_long_to_axi4_wide_verb.sv +131 -0
  25. data/lib/axi/AXI4/axi4_pipe/axi4_pipe.sv +44 -0
  26. data/lib/axi/AXI4/axi4_pipe/axi4_pipe_verb.sv +45 -0
  27. data/lib/axi/AXI4/axi4_pipe/axi4_rd_pipe.sv +111 -0
  28. data/lib/axi/AXI4/axi4_pipe/axi4_rd_pipe_verb.sv +113 -0
  29. data/lib/axi/AXI4/axi4_pipe/axi4_wr_pipe.sv +142 -0
  30. data/lib/axi/AXI4/axi4_pipe/axi4_wr_pipe_verb.sv +146 -0
  31. data/lib/axi/AXI4/axi4_rd_auxiliary_batch_gen.sv +134 -0
  32. data/lib/axi/AXI4/axi4_rd_auxiliary_gen.sv +89 -0
  33. data/lib/axi/AXI4/axi4_rd_auxiliary_gen_A1.sv +109 -0
  34. data/lib/axi/AXI4/axi4_rd_burst_track.sv +164 -0
  35. data/lib/axi/AXI4/axi4_wr_aux_bind_data.sv +121 -0
  36. data/lib/axi/AXI4/axi4_wr_auxiliary_batch_gen.sv +140 -0
  37. data/lib/axi/AXI4/axi4_wr_auxiliary_gen.sv +102 -0
  38. data/lib/axi/AXI4/axi4_wr_auxiliary_gen_without_resp.sv +91 -0
  39. data/lib/axi/AXI4/axi4_wr_burst_track.sv +146 -0
  40. data/lib/axi/AXI4/axi_stream_add_addr_len.sv +50 -0
  41. data/lib/axi/AXI4/axi_stream_to_axi4_wr.sv +61 -0
  42. data/lib/axi/AXI4/axi_stream_to_axi4_wr_verb.sv.bak +123 -0
  43. data/lib/axi/AXI4/axis_to_axi4_wr.rb +149 -0
  44. data/lib/axi/AXI4/axis_to_axi4_wr.sv +141 -0
  45. data/lib/axi/AXI4/full_axi4_to_axis.sv +188 -0
  46. data/lib/axi/AXI4/full_axi4_to_axis_partition_wr_rd.sv +208 -0
  47. data/lib/axi/AXI4/id_record.sv +55 -0
  48. data/lib/axi/AXI4/idata_pool_axi4.sv +110 -0
  49. data/lib/axi/AXI4/interconnect/AXI4_interconnect_M2S.sv +291 -0
  50. data/lib/axi/AXI4/interconnect/axi4_mix_interconnect_M2S.sv +72 -0
  51. data/lib/axi/AXI4/interconnect/axi4_rd_interconnect_M2S.sv +148 -0
  52. data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S.sv +255 -0
  53. data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S.sv.bak +255 -0
  54. data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S_A1.sv +286 -0
  55. data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S_A2.sv +281 -0
  56. data/lib/axi/AXI4/interconnect/axi4_wr_interconnect_M2S.sv +235 -0
  57. data/lib/axi/AXI4/interconnect/axi4_wr_interconnect_M2S_A1.sv +283 -0
  58. data/lib/axi/AXI4/interconnect/axi4_wr_mix_interconnect_M2S.sv +32 -0
  59. data/lib/axi/AXI4/long_axi4_to_wide_axi4.sv.bak +251 -0
  60. data/lib/axi/AXI4/odata_pool_axi4.sv +134 -0
  61. data/lib/axi/AXI4/odata_pool_axi4_A1.sv +165 -0
  62. data/lib/axi/AXI4/odata_pool_axi4_A2.sv +159 -0
  63. data/lib/axi/AXI4/odata_pool_axi4_A3.sv +183 -0
  64. data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo.sv +61 -0
  65. data/lib/axi/AXI4/packet_fifo/axi4_rd_packet_fifo.sv +282 -0
  66. data/lib/axi/AXI4/packet_fifo/axi4_wr_packet_fifo.sv +181 -0
  67. data/lib/axi/AXI4/packet_merge/axi4_merge.sv +60 -0
  68. data/lib/axi/AXI4/packet_merge/axi4_merge_rd.sv +279 -0
  69. data/lib/axi/AXI4/packet_merge/axi4_merge_wr.sv +267 -0
  70. data/lib/axi/AXI4/packet_partition/axi4_partition.sv +36 -0
  71. data/lib/axi/AXI4/packet_partition/axi4_partition_OD.sv +66 -0
  72. data/lib/axi/AXI4/packet_partition/axi4_partition_rd.sv +211 -0
  73. data/lib/axi/AXI4/packet_partition/axi4_partition_rd_OD.sv +322 -0
  74. data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.rb +80 -0
  75. data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +93 -0
  76. data/lib/axi/AXI4/packet_partition/axi4_partition_wr.sv +239 -0
  77. data/lib/axi/AXI4/packet_partition/axi4_partition_wr_OD.sv +302 -0
  78. data/lib/axi/AXI4/packet_partition/data_inf_partition.rb +293 -0
  79. data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +307 -0
  80. data/lib/axi/AXI4/vcs_axi4_array_comptable.sv +35 -0
  81. data/lib/axi/AXI4/vcs_axi4_comptable.sv +330 -0
  82. data/lib/axi/AXI4/wide_axis_to_axi4_wr.rb +149 -0
  83. data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +140 -0
  84. data/lib/axi/AXI4/width_convert/axi4_data_combin_aflag_pipe.sv +239 -0
  85. data/lib/axi/AXI4/width_convert/axi4_data_combin_aflag_pipe_A1.sv +204 -0
  86. data/lib/axi/AXI4/width_convert/axi4_data_convert.sv +312 -0
  87. data/lib/axi/AXI4/width_convert/axi4_data_convert_A1.sv +217 -0
  88. data/lib/axi/AXI4/width_convert/data_combin.sv +366 -0
  89. data/lib/axi/AXI4/width_convert/data_combin.sv.bak +290 -0
  90. data/lib/axi/AXI4/width_convert/data_destruct.sv +304 -0
  91. data/lib/axi/AXI4/width_convert/feed_check.sv +94 -0
  92. data/lib/axi/AXI4/width_convert/len_convert.sv.bak +61 -0
  93. data/lib/axi/AXI4/width_convert/odd_width_convert.sv +229 -0
  94. data/lib/axi/AXI4/width_convert/odd_width_convert_verb.sv +105 -0
  95. data/lib/axi/AXI4/width_convert/simple_data_pipe.sv +40 -0
  96. data/lib/axi/AXI4/width_convert/simple_data_pipe_slaver.sv +33 -0
  97. data/lib/axi/AXI4/width_convert/width_combin.sv +113 -0
  98. data/lib/axi/AXI4/width_convert/width_convert.sv +87 -0
  99. data/lib/axi/AXI4/width_convert/width_convert_verb.sv +249 -0
  100. data/lib/axi/AXI4/width_convert/width_destruct.sv +206 -0
  101. data/lib/axi/AXI4/width_convert/width_destruct_A1.sv +251 -0
  102. data/lib/axi/AXI_BFM/AXI_BFM_PKG.sv +1039 -0
  103. data/lib/axi/AXI_BFM/Data_C_BFM_PKG.sv +97 -0
  104. data/lib/axi/AXI_BFM/axi4_error_chk.sv +298 -0
  105. data/lib/axi/AXI_BFM/axi4_illegal_bfm_pkg.sv +607 -0
  106. data/lib/axi/AXI_BFM/axi_lite_master.sv +102 -0
  107. data/lib/axi/AXI_BFM/axi_lite_tb.sv +23 -0
  108. data/lib/axi/AXI_BFM/axi_master.sv +185 -0
  109. data/lib/axi/AXI_BFM/axi_mirror.sv +266 -0
  110. data/lib/axi/AXI_BFM/axi_mm_tb.sv +134 -0
  111. data/lib/axi/AXI_BFM/axi_slaver.sv.bak +340 -0
  112. data/lib/axi/AXI_BFM/axistreambfm.sv +117 -0
  113. data/lib/axi/AXI_Lite/axi4_to_lite.sv +36 -0
  114. data/lib/axi/AXI_Lite/axi_lite_configure.sv +356 -0
  115. data/lib/axi/AXI_Lite/axi_lite_configure_inf2.sv +365 -0
  116. data/lib/axi/AXI_Lite/axi_lite_configure_verb.sv.bck +370 -0
  117. data/lib/axi/AXI_Lite/axi_lite_interconnect_M2S.sv +437 -0
  118. data/lib/axi/AXI_Lite/axi_lite_interconnect_S2M.sv +359 -0
  119. data/lib/axi/AXI_Lite/axi_lite_interconnect_S2M.sv.bak +359 -0
  120. data/lib/axi/AXI_Lite/axi_lite_master_empty.sv +30 -0
  121. data/lib/axi/AXI_Lite/axi_lite_slaver_empty.sv +27 -0
  122. data/lib/axi/AXI_Lite/axil_direct.sv +52 -0
  123. data/lib/axi/AXI_Lite/common_configure_reg_interface/common_configure_reg_interface.sv +230 -0
  124. data/lib/axi/AXI_Lite/common_configure_reg_interface/common_configure_reg_interface.sv.bak +109 -0
  125. data/lib/axi/AXI_Lite/common_configure_reg_interface/jtag_to_axilite_wrapper.sv +56 -0
  126. data/lib/axi/AXI_Lite/gen_axi_lite_ctrl.sv +515 -0
  127. data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_C1.sv +369 -0
  128. data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_verb.sv +365 -0
  129. data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_verc.sv +401 -0
  130. data/lib/axi/AXI_Lite/wr_lite_to_axis.sv +141 -0
  131. data/lib/axi/AXI_Lite/wr_lite_to_axis.sv.bak +141 -0
  132. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S.sv +76 -0
  133. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_A1.sv +77 -0
  134. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_A2.sv +71 -0
  135. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_bind_tuser.sv +72 -0
  136. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_noaddr.sv +151 -0
  137. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_with_addr.sv +87 -0
  138. data/lib/axi/AXI_stream/axi_stream_interconnect_S2M.sv +65 -0
  139. data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_auto.sv +50 -0
  140. data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_with_info.sv +64 -0
  141. data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_with_keep.sv.bak +64 -0
  142. data/lib/axi/AXI_stream/axi_stream_packet_fifo_with_info.sv.bak +49 -0
  143. data/lib/axi/AXI_stream/axi_stream_partition.sv +147 -0
  144. data/lib/axi/AXI_stream/axi_stream_partition_A1.sv +63 -0
  145. data/lib/axi/AXI_stream/axi_stream_planer.sv +51 -0
  146. data/lib/axi/AXI_stream/axi_stream_split_channel.rb +56 -0
  147. data/lib/axi/AXI_stream/axi_stream_split_channel.sv +149 -0
  148. data/lib/axi/AXI_stream/axi_streams_combin.sv +151 -0
  149. data/lib/axi/AXI_stream/axi_streams_combin_A1.sv +179 -0
  150. data/lib/axi/AXI_stream/axi_streams_scaler.sv +171 -0
  151. data/lib/axi/AXI_stream/axi_streams_scaler_A1.sv +179 -0
  152. data/lib/axi/AXI_stream/axis_append.sv +79 -0
  153. data/lib/axi/AXI_stream/axis_append_A1.sv +82 -0
  154. data/lib/axi/AXI_stream/axis_base_pipe.sv +184 -0
  155. data/lib/axi/AXI_stream/axis_combin_with_fifo.sv +69 -0
  156. data/lib/axi/AXI_stream/axis_connect_pipe.sv +86 -0
  157. data/lib/axi/AXI_stream/axis_connect_pipe_A1.sv.bak +170 -0
  158. data/lib/axi/AXI_stream/axis_connect_pipe_left_shift.sv +64 -0
  159. data/lib/axi/AXI_stream/axis_connect_pipe_right_shift.sv +64 -0
  160. data/lib/axi/AXI_stream/axis_connect_pipe_right_shift_verb.sv +70 -0
  161. data/lib/axi/AXI_stream/axis_connect_pipe_with_info.sv +93 -0
  162. data/lib/axi/AXI_stream/axis_direct.sv +55 -0
  163. data/lib/axi/AXI_stream/axis_direct_A1.sv +81 -0
  164. data/lib/axi/AXI_stream/axis_filter.sv +38 -0
  165. data/lib/axi/AXI_stream/axis_full_to_data_c.sv +26 -0
  166. data/lib/axi/AXI_stream/axis_head_cut.sv +67 -0
  167. data/lib/axi/AXI_stream/axis_head_cut_verb.sv +60 -0
  168. data/lib/axi/AXI_stream/axis_head_cut_verc.rb +175 -0
  169. data/lib/axi/AXI_stream/axis_head_cut_verc.sv +245 -0
  170. data/lib/axi/AXI_stream/axis_inct_s2m_with_flag.sv +84 -0
  171. data/lib/axi/AXI_stream/axis_insert_copy.rb +59 -0
  172. data/lib/axi/AXI_stream/axis_insert_copy.sv +66 -0
  173. data/lib/axi/AXI_stream/axis_intc_M2S_with_addr_inf.sv +114 -0
  174. data/lib/axi/AXI_stream/axis_intc_S2M_with_addr_inf.sv +85 -0
  175. data/lib/axi/AXI_stream/axis_interconnect_S2M_pipe.sv +75 -0
  176. data/lib/axi/AXI_stream/axis_length_cut.sv +64 -0
  177. data/lib/axi/AXI_stream/axis_length_fill.sv +194 -0
  178. data/lib/axi/AXI_stream/axis_length_split.sv +86 -0
  179. data/lib/axi/AXI_stream/axis_length_split_with_addr.sv +127 -0
  180. data/lib/axi/AXI_stream/axis_length_split_writh_user.sv +87 -0
  181. data/lib/axi/AXI_stream/axis_link_trigger.sv +81 -0
  182. data/lib/axi/AXI_stream/axis_master_empty.sv +26 -0
  183. data/lib/axi/AXI_stream/axis_mirror_to_master.sv +126 -0
  184. data/lib/axi/AXI_stream/axis_mirrors.sv +60 -0
  185. data/lib/axi/AXI_stream/axis_orthogonal.sv +66 -0
  186. data/lib/axi/AXI_stream/axis_ram_buffer.sv +118 -0
  187. data/lib/axi/AXI_stream/axis_rom_contect.rb +97 -0
  188. data/lib/axi/AXI_stream/axis_rom_contect.sv +110 -0
  189. data/lib/axi/AXI_stream/axis_rom_contect_sim.rb +102 -0
  190. data/lib/axi/AXI_stream/axis_rom_contect_sim.sv +113 -0
  191. data/lib/axi/AXI_stream/axis_slaver_empty.sv +22 -0
  192. data/lib/axi/AXI_stream/axis_slaver_pipe.sv +84 -0
  193. data/lib/axi/AXI_stream/axis_slaver_pipe_A1.sv +54 -0
  194. data/lib/axi/AXI_stream/axis_slaver_vector_empty.sv +27 -0
  195. data/lib/axi/AXI_stream/axis_split_channel_verb.rb +42 -0
  196. data/lib/axi/AXI_stream/axis_split_channel_verb.sv +62 -0
  197. data/lib/axi/AXI_stream/axis_to_axi4_or_lite.rb +127 -0
  198. data/lib/axi/AXI_stream/axis_to_axi4_or_lite.sv +153 -0
  199. data/lib/axi/AXI_stream/axis_to_data_inf.sv +34 -0
  200. data/lib/axi/AXI_stream/axis_to_lite_rd.sv +81 -0
  201. data/lib/axi/AXI_stream/axis_to_lite_wr.sv +71 -0
  202. data/lib/axi/AXI_stream/axis_uncompress.sv +147 -0
  203. data/lib/axi/AXI_stream/axis_uncompress_A1.sv +150 -0
  204. data/lib/axi/AXI_stream/axis_uncompress_verb.rb +32 -0
  205. data/lib/axi/AXI_stream/axis_uncompress_verb.sv +54 -0
  206. data/lib/axi/AXI_stream/axis_valve.sv +29 -0
  207. data/lib/axi/AXI_stream/axis_valve_with_pipe.sv +76 -0
  208. data/lib/axi/AXI_stream/axis_vector_master_empty.rb +11 -0
  209. data/lib/axi/AXI_stream/axis_vector_master_empty.sv +35 -0
  210. data/lib/axi/AXI_stream/axis_vector_slaver_empty.rb +11 -0
  211. data/lib/axi/AXI_stream/axis_vector_slaver_empty.sv +35 -0
  212. data/lib/axi/AXI_stream/check_stream_crc.sv +28 -0
  213. data/lib/axi/AXI_stream/data_c_to_axis_full.sv +23 -0
  214. data/lib/axi/AXI_stream/data_to_axis_inf.sv +103 -0
  215. data/lib/axi/AXI_stream/data_to_axis_inf_A1.sv +28 -0
  216. data/lib/axi/AXI_stream/data_width/axis_width_combin.sv +204 -0
  217. data/lib/axi/AXI_stream/data_width/axis_width_combin_A1.sv +220 -0
  218. data/lib/axi/AXI_stream/data_width/axis_width_convert.sv +49 -0
  219. data/lib/axi/AXI_stream/data_width/axis_width_destruct.sv +82 -0
  220. data/lib/axi/AXI_stream/data_width/axis_width_destruct_A1.sv +86 -0
  221. data/lib/axi/AXI_stream/ex_status/axis_ex_status.sv +97 -0
  222. data/lib/axi/AXI_stream/gen_big_field_table.sv +170 -0
  223. data/lib/axi/AXI_stream/gen_common_frame_table.sv +382 -0
  224. data/lib/axi/AXI_stream/gen_common_frame_table_bind_tuser.sv +428 -0
  225. data/lib/axi/AXI_stream/gen_origin_axis.sv +116 -0
  226. data/lib/axi/AXI_stream/gen_origin_axis_A1.sv +129 -0
  227. data/lib/axi/AXI_stream/gen_origin_axis_A2.sv +162 -0
  228. data/lib/axi/AXI_stream/gen_simple_axis.sv +164 -0
  229. data/lib/axi/AXI_stream/packet_fifo/axi_stream_long_fifo.sv +132 -0
  230. data/lib/axi/AXI_stream/packet_fifo/axi_stream_long_fifo_verb.sv +140 -0
  231. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo.sv +125 -0
  232. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1.sv +142 -0
  233. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1E.sv +198 -0
  234. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_verb.sv +120 -0
  235. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_with_info.sv +49 -0
  236. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_long_fifo.sv +197 -0
  237. data/lib/axi/AXI_stream/packet_fifo/axi_stream_wide_fifo.sv +141 -0
  238. data/lib/axi/AXI_stream/packet_fifo/axis_pkt_fifo_filter_keep.sv +164 -0
  239. data/lib/axi/AXI_stream/packet_fifo/axis_pkt_fifo_filter_keep_A1.sv +166 -0
  240. data/lib/axi/AXI_stream/parse_big_field_table.sv +164 -0
  241. data/lib/axi/AXI_stream/parse_big_field_table_A1.sv +162 -0
  242. data/lib/axi/AXI_stream/parse_big_field_table_A2.sv +165 -0
  243. data/lib/axi/AXI_stream/parse_big_field_table_verb.sv +118 -0
  244. data/lib/axi/AXI_stream/parse_common_frame_table.sv +202 -0
  245. data/lib/axi/AXI_stream/parse_common_frame_table_A1.sv +521 -0
  246. data/lib/axi/AXI_stream/parse_common_frame_table_A2.sv +561 -0
  247. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache.sv +46 -0
  248. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_35bit.sv +122 -0
  249. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_36_71bit.sv +71 -0
  250. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_72_95bit.sv +96 -0
  251. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_72_95bit_with_keep.sv +99 -0
  252. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_96_143bit.sv +119 -0
  253. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_A1.sv +49 -0
  254. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_B1.sv +82 -0
  255. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_mirror.sv +44 -0
  256. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_verb.sv +58 -0
  257. data/lib/axi/AXI_stream/stream_cache/axi_stream_long_cache.sv +55 -0
  258. data/lib/axi/AXI_stream/stream_crc.sv +67 -0
  259. data/lib/axi/AXI_stream/vcs_axis_comptable.sv +73 -0
  260. data/lib/axi/LICENSE +504 -0
  261. data/lib/axi/ReadME.md +6 -0
  262. data/lib/axi/SIM/tb_axi4_partition_20201105.sv +115 -0
  263. data/lib/axi/SIM/tb_axis_bfm_0504.sv +61 -0
  264. data/lib/axi/SIM/tb_axis_partitiom_0929.sv +102 -0
  265. data/lib/axi/SIM/tb_axis_s2m_pipe_1023.sv +163 -0
  266. data/lib/axi/SIM/tb_axis_to_axi4_0925.sv +107 -0
  267. data/lib/axi/SIM/tb_data_c_m2s_inf_20200114.sv +222 -0
  268. data/lib/axi/SIM/tb_data_c_m2s_inf_20201103.sv +245 -0
  269. data/lib/axi/SIM/tb_data_c_pipe_inf_20180417.sv +114 -0
  270. data/lib/axi/SIM/tb_wide_axis_to_axi4_wr.sv +81 -0
  271. data/lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip.sv +589 -0
  272. data/lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip_C1.sv +69 -0
  273. data/lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip_verb.sv +388 -0
  274. data/lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip_verc.sv +70 -0
  275. data/lib/axi/axi4_to_xilinx_ddr_native/ddr3_ip_native_to_axi4.sv +194 -0
  276. data/lib/axi/axi4_to_xilinx_ddr_native/ddr3_ip_wrapper_sim.sv +99 -0
  277. data/lib/axi/axi4_to_xilinx_ddr_native/ddr_axi4_to_axis.sv +188 -0
  278. data/lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo.sv +156 -0
  279. data/lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo_A1.sv +180 -0
  280. data/lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo_verb.sv +269 -0
  281. data/lib/axi/axi4_to_xilinx_ddr_native/model_ddr_ip_app.sv +303 -0
  282. data/lib/axi/axi4_to_xilinx_ddr_native/tb_ddr3_ip_wrapper_sim.sv +154 -0
  283. data/lib/axi/cfg.yml +15 -0
  284. data/lib/axi/common/ClockSameDomain.sv +128 -0
  285. data/lib/axi/common/common_ram_sim_wrapper.rb +66 -0
  286. data/lib/axi/common/common_ram_sim_wrapper.sv +75 -0
  287. data/lib/axi/common/common_ram_wrapper.rb +71 -0
  288. data/lib/axi/common/common_ram_wrapper.sv +82 -0
  289. data/lib/axi/common/data_c_interface_dram.rb +90 -0
  290. data/lib/axi/common/data_c_interface_dram.sv +106 -0
  291. data/lib/axi/common/mem_format.coe +60 -0
  292. data/lib/axi/common/pipe_vld.sv +45 -0
  293. data/lib/axi/common/test_write_mem.sv +22 -0
  294. data/lib/axi/common/xilinx_hdl_dpram.sv +142 -0
  295. data/lib/axi/common/xilinx_hdl_dpram_sim.sv +176 -0
  296. data/lib/axi/common_fifo/common_fifo.sv +165 -0
  297. data/lib/axi/common_fifo/common_stack.sv +56 -0
  298. data/lib/axi/common_fifo/independent_clock_fifo.sv +200 -0
  299. data/lib/axi/common_fifo/independent_clock_fifo_a1.sv +202 -0
  300. data/lib/axi/common_fifo/independent_stack.sv +85 -0
  301. data/lib/axi/data_interface/data_connect_pipe.sv +228 -0
  302. data/lib/axi/data_interface/data_inf_A2B.sv +21 -0
  303. data/lib/axi/data_interface/data_inf_B2A.sv +21 -0
  304. data/lib/axi/data_interface/data_inf_c/data_bind.sv +74 -0
  305. data/lib/axi/data_interface/data_inf_c/data_c_cache.sv +49 -0
  306. data/lib/axi/data_interface/data_inf_c/data_c_direct.sv +51 -0
  307. data/lib/axi/data_interface/data_inf_c/data_c_direct_mirror.sv +28 -0
  308. data/lib/axi/data_interface/data_inf_c/data_c_intc_M2S_force_robin.rb.bak +268 -0
  309. data/lib/axi/data_interface/data_inf_c/data_c_intc_M2S_force_robin.sv +301 -0
  310. data/lib/axi/data_interface/data_inf_c/data_c_pipe_force_vld.sv +57 -0
  311. data/lib/axi/data_interface/data_inf_c/data_c_pipe_force_vld_bind_data.sv +81 -0
  312. data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf.sv +130 -0
  313. data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf_A1.sv +135 -0
  314. data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf_left_shift.sv +158 -0
  315. data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf_right_shift.sv +155 -0
  316. data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf_right_shift_verb.sv +174 -0
  317. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_C1.sv +296 -0
  318. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_C1_with_id.sv +58 -0
  319. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_best_last.sv +319 -0
  320. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_best_robin.sv +293 -0
  321. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_robin.sv +296 -0
  322. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_robin_with_id.sv +46 -0
  323. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_verc.sv +405 -0
  324. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_verc_with_addr.sv +226 -0
  325. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_verc_with_id.sv +54 -0
  326. data/lib/axi/data_interface/data_inf_c/data_c_pipe_latency.sv +68 -0
  327. data/lib/axi/data_interface/data_inf_c/data_c_scaler.sv +326 -0
  328. data/lib/axi/data_interface/data_inf_c/data_c_scaler_A1.sv +333 -0
  329. data/lib/axi/data_interface/data_inf_c/data_c_tmp_cache.sv +44 -0
  330. data/lib/axi/data_interface/data_inf_c/data_condition_mirror.sv +64 -0
  331. data/lib/axi/data_interface/data_inf_c/data_condition_valve.sv +53 -0
  332. data/lib/axi/data_interface/data_inf_c/data_connect_pipe_inf.sv +73 -0
  333. data/lib/axi/data_interface/data_inf_c/data_inf_c_M2S_with_addr_and_id.sv +66 -0
  334. data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_M2S_with_id.sv +67 -0
  335. data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_S2M.sv +70 -0
  336. data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_S2M_A1.sv +72 -0
  337. data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_S2M_with_lazy.sv +49 -0
  338. data/lib/axi/data_interface/data_inf_c/data_inf_c_interconnect_M2S.sv +50 -0
  339. data/lib/axi/data_interface/data_inf_c/data_inf_c_pipe_condition.sv +33 -0
  340. data/lib/axi/data_interface/data_inf_c/data_inf_c_planer.sv +50 -0
  341. data/lib/axi/data_interface/data_inf_c/data_inf_c_planer_A1.sv +53 -0
  342. data/lib/axi/data_interface/data_inf_c/data_intc_M2S_force_robin.sv +31 -0
  343. data/lib/axi/data_interface/data_inf_c/data_mirrors.sv +108 -0
  344. data/lib/axi/data_interface/data_inf_c/data_mirrors_verb.sv.bak +101 -0
  345. data/lib/axi/data_interface/data_inf_c/data_uncompress.sv +150 -0
  346. data/lib/axi/data_interface/data_inf_c/data_valve.sv +26 -0
  347. data/lib/axi/data_interface/data_inf_c/next_prio.sv +42 -0
  348. data/lib/axi/data_interface/data_inf_c/trigger_data_inf_c.sv +51 -0
  349. data/lib/axi/data_interface/data_inf_c/trigger_data_inf_c_A1.sv +54 -0
  350. data/lib/axi/data_interface/data_inf_c/trigger_ready_ctrl.sv +33 -0
  351. data/lib/axi/data_interface/data_inf_c/vcs_data_c_comptable.sv +40 -0
  352. data/lib/axi/data_interface/data_inf_cross_clk.sv +40 -0
  353. data/lib/axi/data_interface/data_inf_intc_M2S_force_addr_with_id.sv +62 -0
  354. data/lib/axi/data_interface/data_inf_intc_M2S_prio.sv +152 -0
  355. data/lib/axi/data_interface/data_inf_intc_M2S_prio_with_id.sv +55 -0
  356. data/lib/axi/data_interface/data_inf_interconnect_M2S_noaddr.sv +136 -0
  357. data/lib/axi/data_interface/data_inf_interconnect_M2S_with_id_noaddr.sv +55 -0
  358. data/lib/axi/data_interface/data_inf_planer.sv +59 -0
  359. data/lib/axi/data_interface/data_inf_planer_A1.sv +66 -0
  360. data/lib/axi/data_interface/data_inf_ticktock.sv +154 -0
  361. data/lib/axi/data_interface/data_interface.sv +91 -0
  362. data/lib/axi/data_interface/data_interface_pkg.sv +79 -0
  363. data/lib/axi/data_interface/data_pair_map.sv +152 -0
  364. data/lib/axi/data_interface/data_pair_map_A1.sv +159 -0
  365. data/lib/axi/data_interface/data_pair_map_A2.sv +212 -0
  366. data/lib/axi/data_interface/data_pipe_intc_M2S_addr.sv.bak +231 -0
  367. data/lib/axi/data_interface/data_pipe_interconnect.sv +290 -0
  368. data/lib/axi/data_interface/data_pipe_interconnect_M2S.sv +236 -0
  369. data/lib/axi/data_interface/data_pipe_interconnect_M2S.sv.bak1012 +237 -0
  370. data/lib/axi/data_interface/data_pipe_interconnect_M2S_A1.sv +241 -0
  371. data/lib/axi/data_interface/data_pipe_interconnect_M2S_verb.sv +302 -0
  372. data/lib/axi/data_interface/data_pipe_interconnect_M2S_verb.sv.bad_work +280 -0
  373. data/lib/axi/data_interface/data_pipe_interconnect_S2M.sv +332 -0
  374. data/lib/axi/data_interface/data_pipe_interconnect_S2M_A1.sv +376 -0
  375. data/lib/axi/data_interface/data_pipe_interconnect_S2M_verb.sv +265 -0
  376. data/lib/axi/data_interface/data_streams_combin.sv +592 -0
  377. data/lib/axi/data_interface/data_streams_combin_A1.sv +621 -0
  378. data/lib/axi/data_interface/data_streams_scaler.sv +593 -0
  379. data/lib/axi/data_interface/datainf_c_master_empty.sv +22 -0
  380. data/lib/axi/data_interface/datainf_c_slaver_empty.sv +22 -0
  381. data/lib/axi/data_interface/datainf_master_empty.sv +22 -0
  382. data/lib/axi/data_interface/datainf_slaver_empty.sv +22 -0
  383. data/lib/axi/data_interface/part_data_pair_map.sv +111 -0
  384. data/lib/axi/interface_define/axi_aux_inf.sv +206 -0
  385. data/lib/axi/interface_define/axi_inf.sv +1256 -0
  386. data/lib/axi/interface_define/axi_inf_verb.sv +42 -0
  387. data/lib/axi/interface_define/axi_interface_instance.svo +13 -0
  388. data/lib/axi/interface_define/axi_lite_inf.sv +345 -0
  389. data/lib/axi/interface_define/axi_stream_inf.sv +108 -0
  390. data/lib/axi/interface_define/bak/axi_aux_inf.sv +206 -0
  391. data/lib/axi/interface_define/bak/axi_inf_verb.sv +42 -0
  392. data/lib/axi/interface_define/bak/axi_interface_instance.svo +13 -0
  393. data/lib/axi/interface_define/bak/microblaze_inf.sv +136 -0
  394. data/lib/axi/interface_define/bak/xilinx_axi4_to_axi4.sv +87 -0
  395. data/lib/axi/interface_define/bak/xilinx_lite_to_lite.sv +128 -0
  396. data/lib/axi/interface_define/lite_inf2_to_inf.sv +38 -0
  397. data/lib/axi/interface_define/xilinx_axi4_to_axi4.sv +87 -0
  398. data/lib/axi/interface_define/xilinx_lite_to_lite.sv +128 -0
  399. data/lib/axi/macro/axil_macro.sv +132 -0
  400. data/lib/axi/macro/bak/axi4_base_files_add_to_vivado.tcl +28 -0
  401. data/lib/axi/macro/bak/axi_macro.sv +15 -0
  402. data/lib/axi/macro/bak/axis_base_files_add_to_vivado.tcl +26 -0
  403. data/lib/axi/macro/bak/base_files_add_to_vivado.tcl +24 -0
  404. data/lib/axi/macro/bak/data_inf_base_files_add_to_vivado.tcl +22 -0
  405. data/lib/axi/macro/bak/lite_inf_base_files_add_to_vivado.tcl +4 -0
  406. data/lib/axi/macro/bak/standard_tcl.rb +28 -0
  407. data/lib/axi/macro/bak/system_macro.sv +19 -0
  408. data/lib/axi/macro/bak/tcl_axi4_base_files_add_to_vivado.tcl +28 -0
  409. data/lib/axi/macro/bak/tcl_axis_base_files_add_to_vivado.tcl +26 -0
  410. data/lib/axi/macro/bak/tcl_base_files_add_to_vivado.tcl +24 -0
  411. data/lib/axi/macro/bak/tcl_data_inf_base_files_add_to_vivado.tcl +22 -0
  412. data/lib/axi/macro/bak/tcl_lite_inf_base_files_add_to_vivado.tcl +4 -0
  413. data/lib/axi/macro/bak/tcl_tmp.tcl +12 -0
  414. data/lib/axi/macro/bak/tmp.tcl +13 -0
  415. data/lib/axi/platform_ip/fifo_10_18bit_long.sv +125 -0
  416. data/lib/axi/platform_ip/fifo_145_216bit_A1.sv +167 -0
  417. data/lib/axi/platform_ip/fifo_217_288bit_A1.sv +191 -0
  418. data/lib/axi/platform_ip/fifo_36bit.sv +77 -0
  419. data/lib/axi/platform_ip/fifo_36bit_A1.sv +113 -0
  420. data/lib/axi/platform_ip/fifo_36kb_long.sv +145 -0
  421. data/lib/axi/platform_ip/fifo_37_72bit.sv +77 -0
  422. data/lib/axi/platform_ip/fifo_505_576bit_A1.sv +141 -0
  423. data/lib/axi/platform_ip/fifo_73_96bit.sv +102 -0
  424. data/lib/axi/platform_ip/fifo_97_144bit.sv +102 -0
  425. data/lib/axi/platform_ip/fifo_97_144bit_A1.sv +133 -0
  426. data/lib/axi/platform_ip/fifo_ku.sv +212 -0
  427. data/lib/axi/platform_ip/fifo_ku.sv.bak +488 -0
  428. data/lib/axi/platform_ip/fifo_ku_18bit.sv +138 -0
  429. data/lib/axi/platform_ip/fifo_ku_36bit.sv +148 -0
  430. data/lib/axi/platform_ip/fifo_ku_36kb_long.sv +135 -0
  431. data/lib/axi/platform_ip/fifo_ku_xbit_8192.sv.bak +107 -0
  432. data/lib/axi/platform_ip/fifo_wr_rd_mark.sv +94 -0
  433. data/lib/axi/platform_ip/ku_long_fifo_4bit.sv +189 -0
  434. data/lib/axi/platform_ip/long_fifo.sv +72 -0
  435. data/lib/axi/platform_ip/long_fifo_4bit.sv +156 -0
  436. data/lib/axi/platform_ip/long_fifo_4bit_8192.sv +133 -0
  437. data/lib/axi/platform_ip/long_fifo_4bit_SL8192.sv +133 -0
  438. data/lib/axi/platform_ip/long_fifo_verb.sv +110 -0
  439. data/lib/axi/platform_ip/wide_fifo.sv +66 -0
  440. data/lib/axi/platform_ip/wide_fifo_7series.sv +136 -0
  441. data/lib/axi/platform_ip/xilinx_fifo.sv +174 -0
  442. data/lib/axi/platform_ip/xilinx_fifo_A1.sv +223 -0
  443. data/lib/axi/platform_ip/xilinx_fifo_verb.sv +87 -0
  444. data/lib/axi/platform_ip/xilinx_fifo_verc.sv +87 -0
  445. data/lib/axi/platform_ip/xilinx_stream_packet_fifo_ip.sv +40 -0
  446. data/lib/axi/top/axi4_data_convert_2_20_tb.sv +126 -0
  447. data/lib/axi/top/axi4_data_convert_5_24_tb.sv +156 -0
  448. data/lib/axi/top/axi4_interconnnect_2_24_tb.sv +143 -0
  449. data/lib/axi/top/axi4_interconnnect_5_23_tb.sv +155 -0
  450. data/lib/axi/top/axi4_merge_tb_0331.sv +120 -0
  451. data/lib/axi/top/axi4_packet_fifo_2_28_tb.sv +107 -0
  452. data/lib/axi/top/axi4_partition_2_23_tb.sv +93 -0
  453. data/lib/axi/top/axi_stream_packet_fifo_2_28_tb.sv +78 -0
  454. data/lib/axi/top/axis_length_cut_2_28_tb.sv +79 -0
  455. data/lib/axi/top/axis_length_fill_8_18_tb.sv +81 -0
  456. data/lib/axi/top/common_fifo_2_27_tb.sv +77 -0
  457. data/lib/axi/top/data_convert_2_16_tb.sv +162 -0
  458. data/lib/axi/top/independent_fifo_2_27_tb.sv +90 -0
  459. data/lib/axi/top/long_to_wide_3_1_tb.sv +142 -0
  460. data/lib/axi/top/odd_width_convert_tb_420.sv +83 -0
  461. data/lib/axi/top/tb_axis_m2s_A1_0115.sv +158 -0
  462. data/lib/axi/top/tb_axis_width_combin_0913.sv +57 -0
  463. data/lib/axi/top/tb_axis_width_test_0914.sv +115 -0
  464. data/lib/axi/top/tb_data_c_inf_M2S_0823.sv +154 -0
  465. data/lib/axi/top/tb_data_c_inf_M2S_addr_0824.sv +252 -0
  466. data/lib/axi/top/tb_data_c_pipe_force_vld_1228.sv +96 -0
  467. data/lib/axi/top/tb_data_c_scaler_20180413.sv +187 -0
  468. data/lib/axi/top/tb_data_intc_S2M_0807.sv +168 -0
  469. data/lib/axi/top/tb_test_ku_fifo_0919.sv +98 -0
  470. data/lib/axi/top/width_convert_verb_tb_523.sv +68 -0
  471. data/lib/axi/video/video_stream_2_axi_stream.sv +90 -0
  472. data/lib/axi/video_interface/video_interface.sv +173 -0
  473. data/lib/axi_tdl.rb +6 -0
  474. data/lib/axi_tdl/version.rb +3 -0
  475. data/lib/spec/spec_helper.rb +100 -0
  476. data/lib/tdl/LICENSE +504 -0
  477. data/lib/tdl/Logic/Logic.tar.gz +0 -0
  478. data/lib/tdl/Logic/clock_rst_verb_auto.rb +99 -0
  479. data/lib/tdl/Logic/logic_edge.rb +194 -0
  480. data/lib/tdl/Logic/logic_latency.rb +197 -0
  481. data/lib/tdl/Logic/logic_main.rb +188 -0
  482. data/lib/tdl/Logic/logic_operator.rb.bak +128 -0
  483. data/lib/tdl/Logic/mdio_model_auto.rb +77 -0
  484. data/lib/tdl/Logic/path_lib.rb +7 -0
  485. data/lib/tdl/Logic/redefine_operator.rb +28 -0
  486. data/lib/tdl/ReadMe.md +295 -0
  487. data/lib/tdl/SDL/axi4/AXI4_interconnect_M2S_sdl.rb +10 -0
  488. data/lib/tdl/SDL/axi4/axi4_combin_wr_rd_batch_sdl.rb +10 -0
  489. data/lib/tdl/SDL/axi4/axi4_data_combin_aflag_pipe_A1_sdl.rb +38 -0
  490. data/lib/tdl/SDL/axi4/axi4_data_combin_aflag_pipe_sdl.rb +37 -0
  491. data/lib/tdl/SDL/axi4/axi4_data_convert_A1_sdl.rb +9 -0
  492. data/lib/tdl/SDL/axi4/axi4_data_convert_sdl.rb +9 -0
  493. data/lib/tdl/SDL/axi4/axi4_direct_A1_sdl.rb +14 -0
  494. data/lib/tdl/SDL/axi4/axi4_direct_B1_sdl.rb +9 -0
  495. data/lib/tdl/SDL/axi4/axi4_direct_sdl.rb +14 -0
  496. data/lib/tdl/SDL/axi4/axi4_direct_verb_sdl.rb +9 -0
  497. data/lib/tdl/SDL/axi4/axi4_direct_verc_sdl.rb +16 -0
  498. data/lib/tdl/SDL/axi4/axi4_long_to_axi4_wide_A1_sdl.rb +10 -0
  499. data/lib/tdl/SDL/axi4/axi4_long_to_axi4_wide_sdl.rb +9 -0
  500. data/lib/tdl/SDL/axi4/axi4_long_to_axi4_wide_track_sdl.rb +9 -0
  501. data/lib/tdl/SDL/axi4/axi4_long_to_axi4_wide_verb_sdl.rb +11 -0
  502. data/lib/tdl/SDL/axi4/axi4_merge_rd_sdl.rb +10 -0
  503. data/lib/tdl/SDL/axi4/axi4_merge_sdl.rb +10 -0
  504. data/lib/tdl/SDL/axi4/axi4_merge_wr_sdl.rb +10 -0
  505. data/lib/tdl/SDL/axi4/axi4_mix_interconnect_M2S_sdl.rb +10 -0
  506. data/lib/tdl/SDL/axi4/axi4_packet_fifo_sdl.rb +12 -0
  507. data/lib/tdl/SDL/axi4/axi4_partition_OD_sdl.rb +11 -0
  508. data/lib/tdl/SDL/axi4/axi4_partition_rd_OD_sdl.rb +10 -0
  509. data/lib/tdl/SDL/axi4/axi4_partition_rd_sdl.rb +11 -0
  510. data/lib/tdl/SDL/axi4/axi4_partition_sdl.rb +11 -0
  511. data/lib/tdl/SDL/axi4/axi4_partition_wr_OD_sdl.rb +10 -0
  512. data/lib/tdl/SDL/axi4/axi4_partition_wr_sdl.rb +11 -0
  513. data/lib/tdl/SDL/axi4/axi4_pipe_sdl.rb +9 -0
  514. data/lib/tdl/SDL/axi4/axi4_pipe_verb_sdl.rb +9 -0
  515. data/lib/tdl/SDL/axi4/axi4_rd_auxiliary_batch_gen_sdl.rb +11 -0
  516. data/lib/tdl/SDL/axi4/axi4_rd_auxiliary_gen_A1_sdl.rb +9 -0
  517. data/lib/tdl/SDL/axi4/axi4_rd_auxiliary_gen_sdl.rb +9 -0
  518. data/lib/tdl/SDL/axi4/axi4_rd_burst_track_sdl.rb +10 -0
  519. data/lib/tdl/SDL/axi4/axi4_rd_interconnect_M2S_sdl.rb +10 -0
  520. data/lib/tdl/SDL/axi4/axi4_rd_mix_interconnect_M2S_A1_sdl.rb +10 -0
  521. data/lib/tdl/SDL/axi4/axi4_rd_mix_interconnect_M2S_A2_sdl.rb +10 -0
  522. data/lib/tdl/SDL/axi4/axi4_rd_mix_interconnect_M2S_sdl.rb +10 -0
  523. data/lib/tdl/SDL/axi4/axi4_rd_packet_fifo_sdl.rb +11 -0
  524. data/lib/tdl/SDL/axi4/axi4_rd_pipe_sdl.rb +9 -0
  525. data/lib/tdl/SDL/axi4/axi4_rd_pipe_verb_sdl.rb +9 -0
  526. data/lib/tdl/SDL/axi4/axi4_wr_aux_bind_data_sdl.rb +9 -0
  527. data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_batch_gen_sdl.rb +11 -0
  528. data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_gen_sdl.rb +10 -0
  529. data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_gen_without_resp_sdl.rb +10 -0
  530. data/lib/tdl/SDL/axi4/axi4_wr_burst_track_sdl.rb +10 -0
  531. data/lib/tdl/SDL/axi4/axi4_wr_interconnect_M2S_A1_sdl.rb +10 -0
  532. data/lib/tdl/SDL/axi4/axi4_wr_interconnect_M2S_sdl.rb +10 -0
  533. data/lib/tdl/SDL/axi4/axi4_wr_mix_interconnect_M2S_sdl.rb +10 -0
  534. data/lib/tdl/SDL/axi4/axi4_wr_packet_fifo_sdl.rb +11 -0
  535. data/lib/tdl/SDL/axi4/axi4_wr_pipe_sdl.rb +9 -0
  536. data/lib/tdl/SDL/axi4/axi4_wr_pipe_verb_sdl.rb +9 -0
  537. data/lib/tdl/SDL/axi4/axi_stream_add_addr_len_sdl.rb +11 -0
  538. data/lib/tdl/SDL/axi4/axi_stream_to_axi4_wr_sdl.rb +9 -0
  539. data/lib/tdl/SDL/axi4/data_combin_sdl.rb +20 -0
  540. data/lib/tdl/SDL/axi4/data_destruct_sdl.rb +19 -0
  541. data/lib/tdl/SDL/axi4/feed_check_sdl.rb +18 -0
  542. data/lib/tdl/SDL/axi4/full_axi4_to_axis_partition_wr_rd_sdl.rb +11 -0
  543. data/lib/tdl/SDL/axi4/full_axi4_to_axis_sdl.rb +10 -0
  544. data/lib/tdl/SDL/axi4/id_record_sdl.rb +19 -0
  545. data/lib/tdl/SDL/axi4/idata_pool_axi4_sdl.rb +18 -0
  546. data/lib/tdl/SDL/axi4/odata_pool_axi4_A1_sdl.rb +13 -0
  547. data/lib/tdl/SDL/axi4/odata_pool_axi4_A2_sdl.rb +10 -0
  548. data/lib/tdl/SDL/axi4/odata_pool_axi4_sdl.rb +19 -0
  549. data/lib/tdl/SDL/axi4/odd_width_convert_sdl.rb +19 -0
  550. data/lib/tdl/SDL/axi4/odd_width_convert_verb_sdl.rb +19 -0
  551. data/lib/tdl/SDL/axi4/simple_data_pipe_sdl.rb +16 -0
  552. data/lib/tdl/SDL/axi4/simple_data_pipe_slaver_sdl.rb +16 -0
  553. data/lib/tdl/SDL/axi4/vcs_axi4_array_comptable.rb +9 -0
  554. data/lib/tdl/SDL/axi4/vcs_axi4_array_comptable_sdl.rb +10 -0
  555. data/lib/tdl/SDL/axi4/vcs_axi4_comptable.rb +8 -0
  556. data/lib/tdl/SDL/axi4/vcs_axi4_comptable_sdl.rb +9 -0
  557. data/lib/tdl/SDL/axi4/width_combin_sdl.rb +20 -0
  558. data/lib/tdl/SDL/axi4/width_convert_sdl.rb +20 -0
  559. data/lib/tdl/SDL/axi4/width_convert_verb_sdl.rb +20 -0
  560. data/lib/tdl/SDL/axi4/width_destruct_A1_sdl.rb +22 -0
  561. data/lib/tdl/SDL/axi4/width_destruct_sdl.rb +19 -0
  562. data/lib/tdl/SDL/axistream/axi_stream_cache_35bit_sdl.rb +9 -0
  563. data/lib/tdl/SDL/axistream/axi_stream_cache_36_71bit_sdl.rb +9 -0
  564. data/lib/tdl/SDL/axistream/axi_stream_cache_72_95bit_sdl.rb +9 -0
  565. data/lib/tdl/SDL/axistream/axi_stream_cache_72_95bit_with_keep_sdl.rb +9 -0
  566. data/lib/tdl/SDL/axistream/axi_stream_cache_96_143bit_sdl.rb +9 -0
  567. data/lib/tdl/SDL/axistream/axi_stream_cache_B1_sdl.rb +9 -0
  568. data/lib/tdl/SDL/axistream/axi_stream_cache_mirror_sdl.rb +9 -0
  569. data/lib/tdl/SDL/axistream/axi_stream_cache_sdl.rb +9 -0
  570. data/lib/tdl/SDL/axistream/axi_stream_cache_verb_sdl.rb +9 -0
  571. data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_A1_sdl.rb +11 -0
  572. data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_A2_sdl.rb +13 -0
  573. data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_bind_tuser_sdl.rb +11 -0
  574. data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_noaddr_sdl.rb +11 -0
  575. data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_sdl.rb +12 -0
  576. data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_with_addr_sdl.rb +12 -0
  577. data/lib/tdl/SDL/axistream/axi_stream_interconnect_S2M_auto_sdl.rb +11 -0
  578. data/lib/tdl/SDL/axistream/axi_stream_interconnect_S2M_sdl.rb +12 -0
  579. data/lib/tdl/SDL/axistream/axi_stream_long_cache_sdl.rb +10 -0
  580. data/lib/tdl/SDL/axistream/axi_stream_long_fifo_sdl.rb +11 -0
  581. data/lib/tdl/SDL/axistream/axi_stream_long_fifo_verb_sdl.rb +11 -0
  582. data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_B1E_sdl.rb +16 -0
  583. data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_B1_sdl.rb +14 -0
  584. data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_sdl.rb +10 -0
  585. data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_verb_sdl.rb +13 -0
  586. data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_with_info_sdl.rb +13 -0
  587. data/lib/tdl/SDL/axistream/axi_stream_packet_long_fifo_sdl.rb +11 -0
  588. data/lib/tdl/SDL/axistream/axi_stream_partition_A1_sdl.rb +11 -0
  589. data/lib/tdl/SDL/axistream/axi_stream_partition_sdl.rb +12 -0
  590. data/lib/tdl/SDL/axistream/axi_stream_wide_fifo_sdl.rb +10 -0
  591. data/lib/tdl/SDL/axistream/axi_streams_combin_A1_sdl.rb +15 -0
  592. data/lib/tdl/SDL/axistream/axi_streams_combin_sdl.rb +16 -0
  593. data/lib/tdl/SDL/axistream/axi_streams_scaler_A1_sdl.rb +14 -0
  594. data/lib/tdl/SDL/axistream/axi_streams_scaler_sdl.rb +15 -0
  595. data/lib/tdl/SDL/axistream/axis_append_A1_sdl.rb +18 -0
  596. data/lib/tdl/SDL/axistream/axis_append_sdl.rb +17 -0
  597. data/lib/tdl/SDL/axistream/axis_base_pipe_sdl.rb +10 -0
  598. data/lib/tdl/SDL/axistream/axis_combin_with_fifo_sdl.rb +14 -0
  599. data/lib/tdl/SDL/axistream/axis_connect_pipe_right_shift_sdl.rb +10 -0
  600. data/lib/tdl/SDL/axistream/axis_connect_pipe_sdl.rb +9 -0
  601. data/lib/tdl/SDL/axistream/axis_connect_pipe_with_info_sdl.rb +12 -0
  602. data/lib/tdl/SDL/axistream/axis_direct_A1_sdl.rb +11 -0
  603. data/lib/tdl/SDL/axistream/axis_direct_sdl.rb +9 -0
  604. data/lib/tdl/SDL/axistream/axis_ex_status_sdl.rb +12 -0
  605. data/lib/tdl/SDL/axistream/axis_filter_sdl.rb +10 -0
  606. data/lib/tdl/SDL/axistream/axis_full_to_data_c_sdl.rb +9 -0
  607. data/lib/tdl/SDL/axistream/axis_head_cut_sdl.rb +10 -0
  608. data/lib/tdl/SDL/axistream/axis_inct_s2m_with_flag_sdl.rb +11 -0
  609. data/lib/tdl/SDL/axistream/axis_intc_M2S_with_addr_inf_sdl.rb +11 -0
  610. data/lib/tdl/SDL/axistream/axis_intc_S2M_with_addr_inf_sdl.rb +12 -0
  611. data/lib/tdl/SDL/axistream/axis_interconnect_S2M_pipe_sdl.rb +15 -0
  612. data/lib/tdl/SDL/axistream/axis_length_cut_sdl.rb +10 -0
  613. data/lib/tdl/SDL/axistream/axis_length_fill_sdl.rb +10 -0
  614. data/lib/tdl/SDL/axistream/axis_length_split_sdl.rb +10 -0
  615. data/lib/tdl/SDL/axistream/axis_length_split_with_addr_sdl.rb +13 -0
  616. data/lib/tdl/SDL/axistream/axis_length_split_writh_user_sdl.rb +10 -0
  617. data/lib/tdl/SDL/axistream/axis_link_trigger_sdl.rb +12 -0
  618. data/lib/tdl/SDL/axistream/axis_master_empty_sdl.rb +8 -0
  619. data/lib/tdl/SDL/axistream/axis_mirror_to_master_sdl.rb +10 -0
  620. data/lib/tdl/SDL/axistream/axis_mirrors_sdl.rb +14 -0
  621. data/lib/tdl/SDL/axistream/axis_orthogonal_sdl.rb +10 -0
  622. data/lib/tdl/SDL/axistream/axis_pkt_fifo_filter_keep_A1_sdl.rb +10 -0
  623. data/lib/tdl/SDL/axistream/axis_pkt_fifo_filter_keep_sdl.rb +10 -0
  624. data/lib/tdl/SDL/axistream/axis_ram_buffer_sdl.rb +13 -0
  625. data/lib/tdl/SDL/axistream/axis_slaver_empty_sdl.rb +8 -0
  626. data/lib/tdl/SDL/axistream/axis_slaver_pipe_A1_sdl.rb +10 -0
  627. data/lib/tdl/SDL/axistream/axis_slaver_pipe_sdl.rb +9 -0
  628. data/lib/tdl/SDL/axistream/axis_slaver_vector_empty_sdl.rb +9 -0
  629. data/lib/tdl/SDL/axistream/axis_to_data_inf_sdl.rb +10 -0
  630. data/lib/tdl/SDL/axistream/axis_to_lite_rd_sdl.rb +11 -0
  631. data/lib/tdl/SDL/axistream/axis_to_lite_wr_sdl.rb +10 -0
  632. data/lib/tdl/SDL/axistream/axis_uncompress_A1_sdl.rb +12 -0
  633. data/lib/tdl/SDL/axistream/axis_uncompress_sdl.rb +11 -0
  634. data/lib/tdl/SDL/axistream/axis_valve_sdl.rb +10 -0
  635. data/lib/tdl/SDL/axistream/axis_valve_with_pipe_sdl.rb +11 -0
  636. data/lib/tdl/SDL/axistream/axis_width_combin_A1_sdl.rb +9 -0
  637. data/lib/tdl/SDL/axistream/axis_width_combin_sdl.rb +9 -0
  638. data/lib/tdl/SDL/axistream/axis_width_convert_sdl.rb +9 -0
  639. data/lib/tdl/SDL/axistream/axis_width_destruct_A1_sdl.rb +9 -0
  640. data/lib/tdl/SDL/axistream/axis_width_destruct_sdl.rb +9 -0
  641. data/lib/tdl/SDL/axistream/check_stream_crc_sdl.rb +8 -0
  642. data/lib/tdl/SDL/axistream/data_c_to_axis_full_sdl.rb +9 -0
  643. data/lib/tdl/SDL/axistream/data_to_axis_inf_A1_sdl.rb +10 -0
  644. data/lib/tdl/SDL/axistream/data_to_axis_inf_sdl.rb +11 -0
  645. data/lib/tdl/SDL/axistream/gen_big_field_table_sdl.rb +14 -0
  646. data/lib/tdl/SDL/axistream/gen_common_frame_table_sdl.rb +60 -0
  647. data/lib/tdl/SDL/axistream/gen_origin_axis_A1_sdl.rb +13 -0
  648. data/lib/tdl/SDL/axistream/gen_origin_axis_sdl.rb +12 -0
  649. data/lib/tdl/SDL/axistream/gen_simple_axis_sdl.rb +13 -0
  650. data/lib/tdl/SDL/axistream/parse_big_field_table_A1_sdl.rb +17 -0
  651. data/lib/tdl/SDL/axistream/parse_big_field_table_A2_sdl.rb +17 -0
  652. data/lib/tdl/SDL/axistream/parse_big_field_table_sdl.rb +17 -0
  653. data/lib/tdl/SDL/axistream/stream_crc_sdl.rb +9 -0
  654. data/lib/tdl/SDL/axistream/vcs_axis_comptable.rb +16 -0
  655. data/lib/tdl/SDL/axistream/vcs_axis_comptable_sdl.rb +9 -0
  656. data/lib/tdl/SDL/data_inf_c/data_bind_sdl.rb +10 -0
  657. data/lib/tdl/SDL/data_inf_c/data_c_cache_sdl.rb +9 -0
  658. data/lib/tdl/SDL/data_inf_c/data_c_direct_mirror_sdl.rb +9 -0
  659. data/lib/tdl/SDL/data_inf_c/data_c_direct_sdl.rb +9 -0
  660. data/lib/tdl/SDL/data_inf_c/data_c_intc_M2S_force_robin_sdl.rb +10 -0
  661. data/lib/tdl/SDL/data_inf_c/data_c_pipe_force_vld_bind_data_sdl.rb +13 -0
  662. data/lib/tdl/SDL/data_inf_c/data_c_pipe_force_vld_sdl.rb +9 -0
  663. data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_A1_sdl.rb +10 -0
  664. data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_right_shift_sdl.rb +13 -0
  665. data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_sdl.rb +9 -0
  666. data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_C1_sdl.rb +14 -0
  667. data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_C1_with_id_sdl.rb +16 -0
  668. data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_sdl.rb +13 -0
  669. data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_with_addr_sdl.rb +13 -0
  670. data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_with_id_sdl.rb +15 -0
  671. data/lib/tdl/SDL/data_inf_c/data_c_pipe_latency_sdl.rb +10 -0
  672. data/lib/tdl/SDL/data_inf_c/data_c_scaler_A1_sdl.rb +16 -0
  673. data/lib/tdl/SDL/data_inf_c/data_c_scaler_sdl.rb +15 -0
  674. data/lib/tdl/SDL/data_inf_c/data_c_tmp_cache_sdl.rb +9 -0
  675. data/lib/tdl/SDL/data_inf_c/data_condition_mirror_sdl.rb +13 -0
  676. data/lib/tdl/SDL/data_inf_c/data_condition_valve_sdl.rb +13 -0
  677. data/lib/tdl/SDL/data_inf_c/data_connect_pipe_inf_sdl.rb +9 -0
  678. data/lib/tdl/SDL/data_inf_c/data_connect_pipe_sdl.rb +17 -0
  679. data/lib/tdl/SDL/data_inf_c/data_inf_A2B_sdl.rb +9 -0
  680. data/lib/tdl/SDL/data_inf_c/data_inf_B2A_sdl.rb +9 -0
  681. data/lib/tdl/SDL/data_inf_c/data_inf_c_M2S_with_addr_and_id_sdl.rb +17 -0
  682. data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_M2S_with_id_sdl.rb +15 -0
  683. data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_A1_sdl.rb +13 -0
  684. data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_sdl.rb +12 -0
  685. data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_with_lazy_sdl.rb +15 -0
  686. data/lib/tdl/SDL/data_inf_c/data_inf_c_interconnect_M2S_sdl.rb +12 -0
  687. data/lib/tdl/SDL/data_inf_c/data_inf_c_pipe_condition_sdl.rb +10 -0
  688. data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_A1.rb +12 -0
  689. data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_A1_sdl.rb +14 -0
  690. data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_sdl.rb +13 -0
  691. data/lib/tdl/SDL/data_inf_c/data_inf_cross_clk_sdl.rb +9 -0
  692. data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_force_addr_with_id_sdl.rb +19 -0
  693. data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_prio_sdl.rb +14 -0
  694. data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_prio_with_id_sdl.rb +17 -0
  695. data/lib/tdl/SDL/data_inf_c/data_inf_interconnect_M2S_noaddr_sdl.rb +14 -0
  696. data/lib/tdl/SDL/data_inf_c/data_inf_interconnect_M2S_with_id_noaddr_sdl.rb +17 -0
  697. data/lib/tdl/SDL/data_inf_c/data_inf_planer_A1_sdl.rb +15 -0
  698. data/lib/tdl/SDL/data_inf_c/data_inf_planer_sdl.rb +14 -0
  699. data/lib/tdl/SDL/data_inf_c/data_inf_ticktock_sdl.rb +18 -0
  700. data/lib/tdl/SDL/data_inf_c/data_intc_M2S_force_robin_sdl.rb +10 -0
  701. data/lib/tdl/SDL/data_inf_c/data_mirrors_sdl.rb +14 -0
  702. data/lib/tdl/SDL/data_inf_c/data_pair_map_A1_sdl.rb +16 -0
  703. data/lib/tdl/SDL/data_inf_c/data_pair_map_A2_sdl.rb +19 -0
  704. data/lib/tdl/SDL/data_inf_c/data_pair_map_sdl.rb +14 -0
  705. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_A1_sdl.rb +19 -0
  706. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_sdl.rb +17 -0
  707. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_verb_sdl.rb +16 -0
  708. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_A1_sdl.rb +19 -0
  709. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_sdl.rb +16 -0
  710. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_verb_sdl.rb +15 -0
  711. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_sdl.rb +23 -0
  712. data/lib/tdl/SDL/data_inf_c/data_streams_combin_A1_sdl.rb +20 -0
  713. data/lib/tdl/SDL/data_inf_c/data_streams_combin_sdl.rb +20 -0
  714. data/lib/tdl/SDL/data_inf_c/data_streams_scaler_sdl.rb +19 -0
  715. data/lib/tdl/SDL/data_inf_c/data_uncompress_sdl.rb +11 -0
  716. data/lib/tdl/SDL/data_inf_c/data_valve_sdl.rb +10 -0
  717. data/lib/tdl/SDL/data_inf_c/datainf_c_master_empty_sdl.rb +8 -0
  718. data/lib/tdl/SDL/data_inf_c/datainf_c_slaver_empty_sdl.rb +8 -0
  719. data/lib/tdl/SDL/data_inf_c/datainf_master_empty_sdl.rb +8 -0
  720. data/lib/tdl/SDL/data_inf_c/datainf_slaver_empty_sdl.rb +8 -0
  721. data/lib/tdl/SDL/data_inf_c/latency_sdl.rb +8 -0
  722. data/lib/tdl/SDL/data_inf_c/next_prio_sdl.rb +12 -0
  723. data/lib/tdl/SDL/data_inf_c/part_data_pair_map_sdl.rb +19 -0
  724. data/lib/tdl/SDL/data_inf_c/trigger_data_inf_c_A1_sdl.rb +11 -0
  725. data/lib/tdl/SDL/data_inf_c/trigger_data_inf_c_sdl.rb +11 -0
  726. data/lib/tdl/SDL/data_inf_c/trigger_ready_ctrl_sdl.rb +12 -0
  727. data/lib/tdl/SDL/data_inf_c/vcs_data_c_comptable.rb +8 -0
  728. data/lib/tdl/SDL/data_inf_c/vcs_data_c_comptable_sdl.rb +9 -0
  729. data/lib/tdl/SDL/fifo/common_fifo_sdl.rb +20 -0
  730. data/lib/tdl/SDL/fifo/common_stack_sdl.rb +14 -0
  731. data/lib/tdl/SDL/fifo/independent_clock_fifo_a1_sdl.rb +21 -0
  732. data/lib/tdl/SDL/fifo/independent_clock_fifo_sdl.rb +20 -0
  733. data/lib/tdl/SDL/fifo/independent_stack_sdl.rb +18 -0
  734. data/lib/tdl/SDL/path_lib.rb +6 -0
  735. data/lib/tdl/VideoInf/simple_video_gen.rb +46 -0
  736. data/lib/tdl/VideoInf/video_from_axi4.rb +108 -0
  737. data/lib/tdl/VideoInf/video_lib.rb +8 -0
  738. data/lib/tdl/VideoInf/video_stream_2_axi_stream.rb +67 -0
  739. data/lib/tdl/VideoInf/video_to_axi4.rb +75 -0
  740. data/lib/tdl/auto_script/auto_gen_tdl.rb +49 -0
  741. data/lib/tdl/auto_script/autogensdl.rb +289 -0
  742. data/lib/tdl/auto_script/autogentdl_a2.rb +452 -0
  743. data/lib/tdl/auto_script/import_hdl.rb +35 -0
  744. data/lib/tdl/auto_script/import_sdl.rb +26 -0
  745. data/lib/tdl/auto_script/test_autogensdl.rb +73 -0
  746. data/lib/tdl/auto_script/tmp.rb +6 -0
  747. data/lib/tdl/auto_script/tmp/hdl_test_sdl.rb +12 -0
  748. data/lib/tdl/axi4/axi4_combin_wr_rd_batch_auto.rb +79 -0
  749. data/lib/tdl/axi4/axi4_direct.rb +36 -0
  750. data/lib/tdl/axi4/axi4_direct_A1_auto.rb +137 -0
  751. data/lib/tdl/axi4/axi4_direct_auto.rb +79 -0
  752. data/lib/tdl/axi4/axi4_direct_verb_auto.rb +71 -0
  753. data/lib/tdl/axi4/axi4_interconnect_verb.rb +323 -0
  754. data/lib/tdl/axi4/axi4_lib.rb +9 -0
  755. data/lib/tdl/axi4/axi4_long_to_axi4_wide_A1_auto.rb +79 -0
  756. data/lib/tdl/axi4/axi4_long_to_axi4_wide_auto.rb +71 -0
  757. data/lib/tdl/axi4/axi4_long_to_axi4_wide_verb_auto.rb +86 -0
  758. data/lib/tdl/axi4/axi4_packet_fifo_auto.rb +155 -0
  759. data/lib/tdl/axi4/axi4_pipe_auto.rb +127 -0
  760. data/lib/tdl/axi4/axi4_pipe_verb_auto.rb +127 -0
  761. data/lib/tdl/axi4/axi4_rd_auxiliary_gen_auto.rb +71 -0
  762. data/lib/tdl/axi4/axi4_wr_auxiliary_gen_without_resp_auto.rb +78 -0
  763. data/lib/tdl/axi4/axis_to_axi4_wr_auto.rb +85 -0
  764. data/lib/tdl/axi4/bak/__axi4_wr_auxiliary_gen_without_resp.rb +175 -0
  765. data/lib/tdl/axi4/bak/axi4_combin_wr_rd_batch_auto.rb +153 -0
  766. data/lib/tdl/axi4/bak/axi4_data_convert.rb +74 -0
  767. data/lib/tdl/axi4/bak/axi4_direct_auto.rb +153 -0
  768. data/lib/tdl/axi4/bak/axi4_direct_verb_auto.rb +126 -0
  769. data/lib/tdl/axi4/bak/axi4_interconnect.rb.bak +91 -0
  770. data/lib/tdl/axi4/bak/axi4_long_to_axi4_wide_A1_auto.rb +153 -0
  771. data/lib/tdl/axi4/bak/axi4_long_to_axi4_wide_auto.rb +126 -0
  772. data/lib/tdl/axi4/bak/axi4_long_to_axi4_wide_verb_auto.rb +179 -0
  773. data/lib/tdl/axi4/bak/axi4_packet_fifo.rb.bak +75 -0
  774. data/lib/tdl/axi4/bak/axi4_packet_fifo_auto.rb +259 -0
  775. data/lib/tdl/axi4/bak/axi4_partition_od.rb +84 -0
  776. data/lib/tdl/axi4/bak/axi4_pipe_auto.rb +174 -0
  777. data/lib/tdl/axi4/bak/axi4_wr_auxiliary_gen_without_resp_auto.rb +152 -0
  778. data/lib/tdl/axi4/bak/axis_to_axi4_wr_auto.rb +178 -0
  779. data/lib/tdl/axi4/bak/ddr3.rb +40 -0
  780. data/lib/tdl/axi4/bak/idata_pool_axi4_auto.rb +396 -0
  781. data/lib/tdl/axi4/bak/odata_pool_axi4_A1_auto.rb +230 -0
  782. data/lib/tdl/axi4/bak/odata_pool_axi4_auto.rb +386 -0
  783. data/lib/tdl/axi4/idata_pool_axi4_auto.rb +176 -0
  784. data/lib/tdl/axi4/odata_pool_axi4_A1_auto.rb +99 -0
  785. data/lib/tdl/axi4/odata_pool_axi4_auto.rb +141 -0
  786. data/lib/tdl/axi4/wide_axis_to_axi4_wr.rb +84 -0
  787. data/lib/tdl/axi4/wide_axis_to_axi4_wr_auto.rb +84 -0
  788. data/lib/tdl/axi_lite/axi_lite_master_empty_auto.rb +85 -0
  789. data/lib/tdl/axi_lite/axi_lite_slaver_empty_auto.rb +68 -0
  790. data/lib/tdl/axi_lite/bak/axi_lite_master_empty_auto.rb +95 -0
  791. data/lib/tdl/axi_lite/bak/axi_lite_slaver_empty_auto.rb +88 -0
  792. data/lib/tdl/axi_lite/bak/jtag_to_axilite_wrapper_auto.rb +112 -0
  793. data/lib/tdl/axi_lite/jtag_to_axilite_wrapper_auto.rb +63 -0
  794. data/lib/tdl/axi_lite/lite_cmd.rb +154 -0
  795. data/lib/tdl/axi_lite/prj_lib.rb +6 -0
  796. data/lib/tdl/axi_stream/axi_stream_cache_35bit_auto.rb +127 -0
  797. data/lib/tdl/axi_stream/axi_stream_cache_72_95bit_with_keep_auto.rb +127 -0
  798. data/lib/tdl/axi_stream/axi_stream_cache_B1_auto.rb +127 -0
  799. data/lib/tdl/axi_stream/axi_stream_cache_auto.rb +134 -0
  800. data/lib/tdl/axi_stream/axi_stream_cache_mirror_auto.rb +127 -0
  801. data/lib/tdl/axi_stream/axi_stream_cache_verb_auto.rb +127 -0
  802. data/lib/tdl/axi_stream/axi_stream_interconnect.rb +214 -0
  803. data/lib/tdl/axi_stream/axi_stream_interconnect_M2S.rb +85 -0
  804. data/lib/tdl/axi_stream/axi_stream_interconnect_M2S_A1.rb +129 -0
  805. data/lib/tdl/axi_stream/axi_stream_interconnect_M2S_A1_auto.rb +137 -0
  806. data/lib/tdl/axi_stream/axi_stream_interconnect_M2S_auto.rb +93 -0
  807. data/lib/tdl/axi_stream/axi_stream_interconnect_M2S_bind_tuser_auto.rb +137 -0
  808. data/lib/tdl/axi_stream/axi_stream_interconnect_S2M.rb +86 -0
  809. data/lib/tdl/axi_stream/axi_stream_interconnect_S2M_auto.rb +86 -0
  810. data/lib/tdl/axi_stream/axi_stream_interconnect_S2M_auto_auto.rb +91 -0
  811. data/lib/tdl/axi_stream/axi_stream_interconnect_S2M_with_keep.sv_auto.rb +93 -0
  812. data/lib/tdl/axi_stream/axi_stream_lib.rb +18 -0
  813. data/lib/tdl/axi_stream/axi_stream_long_cache_auto.rb +137 -0
  814. data/lib/tdl/axi_stream/axi_stream_long_fifo_auto.rb +146 -0
  815. data/lib/tdl/axi_stream/axi_stream_long_fifo_verb_auto.rb +146 -0
  816. data/lib/tdl/axi_stream/axi_stream_packet_fifo_auto.rb +137 -0
  817. data/lib/tdl/axi_stream/axi_stream_packet_fifo_with_info_auto.rb +164 -0
  818. data/lib/tdl/axi_stream/axi_stream_partition_A1_auto.rb +145 -0
  819. data/lib/tdl/axi_stream/axi_stream_partition_auto.rb +154 -0
  820. data/lib/tdl/axi_stream/axi_stream_wide_fifo_auto.rb +137 -0
  821. data/lib/tdl/axi_stream/axi_streams_combin_A1_auto.rb +184 -0
  822. data/lib/tdl/axi_stream/axi_streams_combin_auto.rb +193 -0
  823. data/lib/tdl/axi_stream/axi_streams_scaler_A1_auto.rb +175 -0
  824. data/lib/tdl/axi_stream/axi_streams_scaler_auto.rb +184 -0
  825. data/lib/tdl/axi_stream/axis_append_A1_auto.rb +209 -0
  826. data/lib/tdl/axi_stream/axis_append_auto.rb +200 -0
  827. data/lib/tdl/axi_stream/axis_combin_with_fifo_auto.rb +175 -0
  828. data/lib/tdl/axi_stream/axis_connect_pipe_A1.sv_auto.rb +127 -0
  829. data/lib/tdl/axi_stream/axis_connect_pipe_auto.rb +127 -0
  830. data/lib/tdl/axi_stream/axis_connect_pipe_with_info_auto.rb +155 -0
  831. data/lib/tdl/axi_stream/axis_direct_auto.rb +127 -0
  832. data/lib/tdl/axi_stream/axis_filter_auto.rb +136 -0
  833. data/lib/tdl/axi_stream/axis_full_to_data_c_auto.rb +71 -0
  834. data/lib/tdl/axi_stream/axis_head_cut_auto.rb +137 -0
  835. data/lib/tdl/axi_stream/axis_length_fill_auto.rb +136 -0
  836. data/lib/tdl/axi_stream/axis_length_split_auto.rb +136 -0
  837. data/lib/tdl/axi_stream/axis_length_split_with_addr_auto.rb +164 -0
  838. data/lib/tdl/axi_stream/axis_length_split_writh_user_auto.rb +136 -0
  839. data/lib/tdl/axi_stream/axis_link_trigger_auto.rb +93 -0
  840. data/lib/tdl/axi_stream/axis_master_empty_auto.rb +85 -0
  841. data/lib/tdl/axi_stream/axis_mirror_to_master_auto.rb +137 -0
  842. data/lib/tdl/axi_stream/axis_mirrors_auto.rb +173 -0
  843. data/lib/tdl/axi_stream/axis_pkt_fifo_filter_keep_A1_auto.rb +137 -0
  844. data/lib/tdl/axi_stream/axis_pkt_fifo_filter_keep_auto.rb +137 -0
  845. data/lib/tdl/axi_stream/axis_ram_buffer_auto.rb +164 -0
  846. data/lib/tdl/axi_stream/axis_slaver_empty_auto.rb +68 -0
  847. data/lib/tdl/axi_stream/axis_slaver_pipe_A1_auto.rb +137 -0
  848. data/lib/tdl/axi_stream/axis_slaver_pipe_auto.rb +127 -0
  849. data/lib/tdl/axi_stream/axis_to_axi4_or_lite_auto.rb +87 -0
  850. data/lib/tdl/axi_stream/axis_to_data_inf_auto.rb +79 -0
  851. data/lib/tdl/axi_stream/axis_to_lite_rd_auto.rb +87 -0
  852. data/lib/tdl/axi_stream/axis_to_lite_wr_auto.rb +79 -0
  853. data/lib/tdl/axi_stream/axis_uncompress_auto.rb +86 -0
  854. data/lib/tdl/axi_stream/axis_valve_auto.rb +136 -0
  855. data/lib/tdl/axi_stream/axis_valve_with_pipe_auto.rb +153 -0
  856. data/lib/tdl/axi_stream/axis_width_combin_A1_auto.rb +127 -0
  857. data/lib/tdl/axi_stream/axis_width_combin_auto.rb +127 -0
  858. data/lib/tdl/axi_stream/axis_width_convert_auto.rb +127 -0
  859. data/lib/tdl/axi_stream/axis_width_destruct_A1.sv_auto.rb +127 -0
  860. data/lib/tdl/axi_stream/axis_width_destruct_auto.rb +127 -0
  861. data/lib/tdl/axi_stream/bak/__axi_stream_interconnect_S2M.rb +186 -0
  862. data/lib/tdl/axi_stream/bak/_axis_mirrors.rb +270 -0
  863. data/lib/tdl/axi_stream/bak/axi4_to_native_for_ddr_ip_verb_auto.rb +343 -0
  864. data/lib/tdl/axi_stream/bak/axi_stream_S2M.rb +63 -0
  865. data/lib/tdl/axi_stream/bak/axi_stream_cache_35bit_auto.rb +138 -0
  866. data/lib/tdl/axi_stream/bak/axi_stream_cache_72_95bit_with_keep_auto.rb +138 -0
  867. data/lib/tdl/axi_stream/bak/axi_stream_cache_B1_auto.rb +138 -0
  868. data/lib/tdl/axi_stream/bak/axi_stream_cache_auto.rb +138 -0
  869. data/lib/tdl/axi_stream/bak/axi_stream_cache_mirror_auto.rb +138 -0
  870. data/lib/tdl/axi_stream/bak/axi_stream_cache_verb_auto.rb +138 -0
  871. data/lib/tdl/axi_stream/bak/axi_stream_interconnect_S2M_auto.rb +147 -0
  872. data/lib/tdl/axi_stream/bak/axi_stream_interconnect_S2M_with_keep.sv_auto.rb +166 -0
  873. data/lib/tdl/axi_stream/bak/axi_stream_long_fifo_auto.rb +177 -0
  874. data/lib/tdl/axi_stream/bak/axi_stream_packet_fifo_auto.rb +158 -0
  875. data/lib/tdl/axi_stream/bak/axi_stream_packet_fifo_with_info_auto.rb +215 -0
  876. data/lib/tdl/axi_stream/bak/axi_stream_partition_A1_auto.rb +176 -0
  877. data/lib/tdl/axi_stream/bak/axi_stream_partition_auto.rb +195 -0
  878. data/lib/tdl/axi_stream/bak/axi_streams_combin_auto.rb +274 -0
  879. data/lib/tdl/axi_stream/bak/axi_streams_scaler.rb +300 -0
  880. data/lib/tdl/axi_stream/bak/axi_streams_scaler_auto.rb +255 -0
  881. data/lib/tdl/axi_stream/bak/axis_append_A1.rb +265 -0
  882. data/lib/tdl/axi_stream/bak/axis_append_A1_auto.rb +310 -0
  883. data/lib/tdl/axi_stream/bak/axis_append_auto.rb +291 -0
  884. data/lib/tdl/axi_stream/bak/axis_combin_with_fifo_auto.rb +236 -0
  885. data/lib/tdl/axi_stream/bak/axis_connect_pipe.rb.bak +207 -0
  886. data/lib/tdl/axi_stream/bak/axis_connect_pipe_A1.sv_auto.rb +138 -0
  887. data/lib/tdl/axi_stream/bak/axis_connect_pipe_auto.rb +138 -0
  888. data/lib/tdl/axi_stream/bak/axis_connect_pipe_with_info_auto.rb +196 -0
  889. data/lib/tdl/axi_stream/bak/axis_direct_auto.rb +138 -0
  890. data/lib/tdl/axi_stream/bak/axis_filter_auto.rb +157 -0
  891. data/lib/tdl/axi_stream/bak/axis_length_fill_auto.rb +157 -0
  892. data/lib/tdl/axi_stream/bak/axis_length_split_auto.rb +157 -0
  893. data/lib/tdl/axi_stream/bak/axis_length_split_with_addr_auto.rb +215 -0
  894. data/lib/tdl/axi_stream/bak/axis_master_empty_auto.rb +95 -0
  895. data/lib/tdl/axi_stream/bak/axis_mirrors_auto.rb +234 -0
  896. data/lib/tdl/axi_stream/bak/axis_pkt_fifo_filter_keep_auto.rb +158 -0
  897. data/lib/tdl/axi_stream/bak/axis_ram_buffer_auto.rb +215 -0
  898. data/lib/tdl/axi_stream/bak/axis_slaver_empty_auto.rb +88 -0
  899. data/lib/tdl/axi_stream/bak/axis_slaver_pipe_A1_auto.rb +158 -0
  900. data/lib/tdl/axi_stream/bak/axis_slaver_pipe_auto.rb +138 -0
  901. data/lib/tdl/axi_stream/bak/axis_to_axi4_wr_auto.rb +205 -0
  902. data/lib/tdl/axi_stream/bak/axis_to_data_inf_auto.rb +108 -0
  903. data/lib/tdl/axi_stream/bak/axis_uncompress_auto.rb +147 -0
  904. data/lib/tdl/axi_stream/bak/axis_valve_auto.rb +157 -0
  905. data/lib/tdl/axi_stream/bak/axis_valve_with_pipe_auto.rb +157 -0
  906. data/lib/tdl/axi_stream/bak/axis_width_combin_auto.rb +138 -0
  907. data/lib/tdl/axi_stream/bak/axis_width_convert_auto.rb +138 -0
  908. data/lib/tdl/axi_stream/bak/axis_width_destruct_auto.rb +138 -0
  909. data/lib/tdl/axi_stream/bak/axis_wrapper_oled_auto.rb +230 -0
  910. data/lib/tdl/axi_stream/bak/check_stream_crc_auto.rb +88 -0
  911. data/lib/tdl/axi_stream/bak/data_to_axis_inf_A1.rb +129 -0
  912. data/lib/tdl/axi_stream/bak/data_to_axis_inf_A1_auto.rb +127 -0
  913. data/lib/tdl/axi_stream/bak/data_to_axis_inf_auto.rb +146 -0
  914. data/lib/tdl/axi_stream/bak/datainf_c_master_empty_auto.rb +115 -0
  915. data/lib/tdl/axi_stream/bak/datainf_c_slaver_empty_auto.rb +108 -0
  916. data/lib/tdl/axi_stream/bak/datainf_master_empty_auto.rb +115 -0
  917. data/lib/tdl/axi_stream/bak/datainf_slaver_empty_auto.rb +108 -0
  918. data/lib/tdl/axi_stream/bak/dynamic_port_cfg_auto.rb +246 -0
  919. data/lib/tdl/axi_stream/bak/dynnamic_addr_cfg_auto.rb +200 -0
  920. data/lib/tdl/axi_stream/bak/gen_big_field_table_auto.rb +210 -0
  921. data/lib/tdl/axi_stream/bak/gen_origin_axis_auto.rb +172 -0
  922. data/lib/tdl/axi_stream/bak/gen_simple_axis_auto.rb +191 -0
  923. data/lib/tdl/axi_stream/bak/idata_pool_axi4_auto.rb +346 -0
  924. data/lib/tdl/axi_stream/bak/parse_big_field_table_A1_auto.rb +292 -0
  925. data/lib/tdl/axi_stream/bak/parse_big_field_table_A2_auto.rb +292 -0
  926. data/lib/tdl/axi_stream/bak/parse_big_field_table_auto.rb +292 -0
  927. data/lib/tdl/axi_stream/bak/part_data_pair_map_auto.rb +362 -0
  928. data/lib/tdl/axi_stream/bak/simple_video_gen_A2.rb +146 -0
  929. data/lib/tdl/axi_stream/bak/simple_video_gen_A2_auto.rb +151 -0
  930. data/lib/tdl/axi_stream/bak/stream_crc_auto.rb +107 -0
  931. data/lib/tdl/axi_stream/bak/udp_server_bfm_auto.rb +131 -0
  932. data/lib/tdl/axi_stream/bak/udp_server_ctrl_bfm_auto.rb +131 -0
  933. data/lib/tdl/axi_stream/bak/video_to_VDMA.rb +153 -0
  934. data/lib/tdl/axi_stream/bak/video_to_VDMA_auto.rb +158 -0
  935. data/lib/tdl/axi_stream/check_stream_crc_auto.rb +63 -0
  936. data/lib/tdl/axi_stream/data_c_to_axis_full_auto.rb +71 -0
  937. data/lib/tdl/axi_stream/data_to_axis_inf_A1_auto.rb +78 -0
  938. data/lib/tdl/axi_stream/data_to_axis_inf_auto.rb +85 -0
  939. data/lib/tdl/axi_stream/gen_big_field_table_auto.rb +140 -0
  940. data/lib/tdl/axi_stream/gen_origin_axis_A1_auto.rb +131 -0
  941. data/lib/tdl/axi_stream/gen_origin_axis_auto.rb +122 -0
  942. data/lib/tdl/axi_stream/gen_simple_axis_auto.rb +131 -0
  943. data/lib/tdl/axi_stream/parse_big_field_table_A1_auto.rb +201 -0
  944. data/lib/tdl/axi_stream/parse_big_field_table_A2_auto.rb +201 -0
  945. data/lib/tdl/axi_stream/parse_big_field_table_auto.rb +201 -0
  946. data/lib/tdl/axi_stream/stream_crc_auto.rb +70 -0
  947. data/lib/tdl/basefunc.rb +338 -0
  948. data/lib/tdl/bfm/axi4_illegal_bfm.rb +203 -0
  949. data/lib/tdl/bfm/axi_stream/axi_stream_bfm.rb +351 -0
  950. data/lib/tdl/bfm/axi_stream/axis_bfm_exp.yml +38 -0
  951. data/lib/tdl/bfm/axi_stream/axis_bfm_module_build.rb +120 -0
  952. data/lib/tdl/bfm/axi_stream/axis_bfm_parse.rb +10 -0
  953. data/lib/tdl/bfm/axi_stream/axis_slice_to_logic.rb +71 -0
  954. data/lib/tdl/bfm/bfm_lib.rb +7 -0
  955. data/lib/tdl/bfm/logic_initial_block.rb +52 -0
  956. data/lib/tdl/cfg.yml +4 -0
  957. data/lib/tdl/class_hdl/hdl_always_comb.rb +54 -0
  958. data/lib/tdl/class_hdl/hdl_always_ff.rb +175 -0
  959. data/lib/tdl/class_hdl/hdl_assign.rb +49 -0
  960. data/lib/tdl/class_hdl/hdl_block_ifelse.rb +349 -0
  961. data/lib/tdl/class_hdl/hdl_data.rb +24 -0
  962. data/lib/tdl/class_hdl/hdl_ex_defarraychain.rb +231 -0
  963. data/lib/tdl/class_hdl/hdl_foreach.rb +114 -0
  964. data/lib/tdl/class_hdl/hdl_function.rb +277 -0
  965. data/lib/tdl/class_hdl/hdl_generate.rb +218 -0
  966. data/lib/tdl/class_hdl/hdl_initial.rb +147 -0
  967. data/lib/tdl/class_hdl/hdl_module_def.rb +447 -0
  968. data/lib/tdl/class_hdl/hdl_package.rb +150 -0
  969. data/lib/tdl/class_hdl/hdl_parameter.rb +73 -0
  970. data/lib/tdl/class_hdl/hdl_random.rb +31 -0
  971. data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +653 -0
  972. data/lib/tdl/class_hdl/hdl_struct.rb +209 -0
  973. data/lib/tdl/class_hdl/hdl_verify.rb +136 -0
  974. data/lib/tdl/data_inf/_data_mirrors.rb +92 -0
  975. data/lib/tdl/data_inf/bak/_data_mirrors.rb +273 -0
  976. data/lib/tdl/data_inf/bak/common_fifo_auto.rb +279 -0
  977. data/lib/tdl/data_inf/bak/data_bind_auto.rb +128 -0
  978. data/lib/tdl/data_inf/bak/data_c_direct_auto.rb +138 -0
  979. data/lib/tdl/data_inf/bak/data_c_direct_mirror_auto.rb +138 -0
  980. data/lib/tdl/data_inf/bak/data_c_tmp_cache_auto.rb +138 -0
  981. data/lib/tdl/data_inf/bak/data_condition_mirror_auto.rb +216 -0
  982. data/lib/tdl/data_inf/bak/data_condition_valve_auto.rb +215 -0
  983. data/lib/tdl/data_inf/bak/data_connect_pipe.rb +80 -0
  984. data/lib/tdl/data_inf/bak/data_connect_pipe_inf_auto.rb +138 -0
  985. data/lib/tdl/data_inf/bak/data_inf_c_interconnect.rb +86 -0
  986. data/lib/tdl/data_inf/bak/data_inf_c_pipe_condition_auto.rb +157 -0
  987. data/lib/tdl/data_inf/bak/data_inf_cross_clk.rb +60 -0
  988. data/lib/tdl/data_inf/bak/data_inf_interconnect.rb +144 -0
  989. data/lib/tdl/data_inf/bak/data_inf_planer.rb +78 -0
  990. data/lib/tdl/data_inf/bak/data_inf_ticktack.rb +80 -0
  991. data/lib/tdl/data_inf/bak/data_inf_ticktock_auto.rb +0 -0
  992. data/lib/tdl/data_inf/bak/data_mirrors_auto.rb +234 -0
  993. data/lib/tdl/data_inf/bak/data_mirrors_verb.sv_auto.rb +234 -0
  994. data/lib/tdl/data_inf/bak/data_uncompress_auto.rb +177 -0
  995. data/lib/tdl/data_inf/bak/data_valve_auto.rb +127 -0
  996. data/lib/tdl/data_inf/bak/datainf_c_master_empty_auto.rb +95 -0
  997. data/lib/tdl/data_inf/bak/datainf_c_slaver_empty_auto.rb +88 -0
  998. data/lib/tdl/data_inf/bak/datainf_master_empty_auto.rb +95 -0
  999. data/lib/tdl/data_inf/bak/datainf_slaver_empty_auto.rb +88 -0
  1000. data/lib/tdl/data_inf/bak/independent_clock_fifo_auto.rb +298 -0
  1001. data/lib/tdl/data_inf/bak/part_data_pair_map_auto.rb +306 -0
  1002. data/lib/tdl/data_inf/common_fifo_auto.rb +141 -0
  1003. data/lib/tdl/data_inf/data_bind_auto.rb +79 -0
  1004. data/lib/tdl/data_inf/data_c_cache_auto.rb +135 -0
  1005. data/lib/tdl/data_inf/data_c_direct_auto.rb +127 -0
  1006. data/lib/tdl/data_inf/data_c_direct_mirror_auto.rb +127 -0
  1007. data/lib/tdl/data_inf/data_c_interconnect.rb +97 -0
  1008. data/lib/tdl/data_inf/data_c_pipe_force_vld_auto.rb +127 -0
  1009. data/lib/tdl/data_inf/data_c_pipe_inf_auto.rb +127 -0
  1010. data/lib/tdl/data_inf/data_c_pipe_intc_M2S_verc_auto.rb +123 -0
  1011. data/lib/tdl/data_inf/data_c_tmp_cache_auto.rb +127 -0
  1012. data/lib/tdl/data_inf/data_condition_mirror_auto.rb +165 -0
  1013. data/lib/tdl/data_inf/data_condition_valve_auto.rb +164 -0
  1014. data/lib/tdl/data_inf/data_connect_pipe_inf_auto.rb +127 -0
  1015. data/lib/tdl/data_inf/data_inf_c_pipe_condition_auto.rb +136 -0
  1016. data/lib/tdl/data_inf/data_mirrors_auto.rb +173 -0
  1017. data/lib/tdl/data_inf/data_mirrors_verb.sv_auto.rb +173 -0
  1018. data/lib/tdl/data_inf/data_uncompress_auto.rb +146 -0
  1019. data/lib/tdl/data_inf/data_valve_auto.rb +104 -0
  1020. data/lib/tdl/data_inf/datainf_c_master_empty_auto.rb +85 -0
  1021. data/lib/tdl/data_inf/datainf_c_slaver_empty_auto.rb +68 -0
  1022. data/lib/tdl/data_inf/datainf_master_empty_auto.rb +85 -0
  1023. data/lib/tdl/data_inf/datainf_slaver_empty_auto.rb +68 -0
  1024. data/lib/tdl/data_inf/independent_clock_fifo_auto.rb +141 -0
  1025. data/lib/tdl/data_inf/part_data_pair_map_auto.rb +149 -0
  1026. data/lib/tdl/data_inf/path_lib.rb +18 -0
  1027. data/lib/tdl/elements/Reset.rb +153 -0
  1028. data/lib/tdl/elements/axi4.rb +642 -0
  1029. data/lib/tdl/elements/axi_lite.rb +246 -0
  1030. data/lib/tdl/elements/axi_stream.rb +674 -0
  1031. data/lib/tdl/elements/clock.rb +193 -0
  1032. data/lib/tdl/elements/common_configure_reg.rb +135 -0
  1033. data/lib/tdl/elements/data_inf.rb +660 -0
  1034. data/lib/tdl/elements/logic.rb +356 -0
  1035. data/lib/tdl/elements/mail_box.rb +64 -0
  1036. data/lib/tdl/elements/originclass.rb +689 -0
  1037. data/lib/tdl/elements/parameter.rb +318 -0
  1038. data/lib/tdl/elements/track_inf.rb +163 -0
  1039. data/lib/tdl/elements/videoinf.rb +224 -0
  1040. data/lib/tdl/examples/10_random/exp_random.rb +13 -0
  1041. data/lib/tdl/examples/10_random/exp_random.sv +36 -0
  1042. data/lib/tdl/examples/11_test_unit/dve.tcl +64 -0
  1043. data/lib/tdl/examples/11_test_unit/exp_test_unit.rb +58 -0
  1044. data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +35 -0
  1045. data/lib/tdl/examples/11_test_unit/exp_test_unit_constraints.xdc +25 -0
  1046. data/lib/tdl/examples/11_test_unit/modules/sub_md0.rb +23 -0
  1047. data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +41 -0
  1048. data/lib/tdl/examples/11_test_unit/modules/sub_md1.rb +25 -0
  1049. data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv +41 -0
  1050. data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +28 -0
  1051. data/lib/tdl/examples/11_test_unit/tu0.sv +38 -0
  1052. data/lib/tdl/examples/11_test_unit/tu1.sv +28 -0
  1053. data/lib/tdl/examples/1_define_module/example1.rb +39 -0
  1054. data/lib/tdl/examples/1_define_module/exmple_md.sv +50 -0
  1055. data/lib/tdl/examples/2_hdl_class/always_comb.rb +99 -0
  1056. data/lib/tdl/examples/2_hdl_class/always_ff.rb +143 -0
  1057. data/lib/tdl/examples/2_hdl_class/case.rb +93 -0
  1058. data/lib/tdl/examples/2_hdl_class/foreach.rb +21 -0
  1059. data/lib/tdl/examples/2_hdl_class/function.rb +34 -0
  1060. data/lib/tdl/examples/2_hdl_class/generate.rb +62 -0
  1061. data/lib/tdl/examples/2_hdl_class/module_def.rb +33 -0
  1062. data/lib/tdl/examples/2_hdl_class/module_head_import_package.rb +36 -0
  1063. data/lib/tdl/examples/2_hdl_class/module_instance_test.rb +13 -0
  1064. data/lib/tdl/examples/2_hdl_class/package.rb +29 -0
  1065. data/lib/tdl/examples/2_hdl_class/package2.rb +21 -0
  1066. data/lib/tdl/examples/2_hdl_class/simple_assign.rb +39 -0
  1067. data/lib/tdl/examples/2_hdl_class/state_case.rb +65 -0
  1068. data/lib/tdl/examples/2_hdl_class/struct.rb +25 -0
  1069. data/lib/tdl/examples/2_hdl_class/struct_function.rb +28 -0
  1070. data/lib/tdl/examples/2_hdl_class/test_axi4_M2S.rb +16 -0
  1071. data/lib/tdl/examples/2_hdl_class/test_initial_assert.rb +11 -0
  1072. data/lib/tdl/examples/2_hdl_class/test_inst_sugar.rb +28 -0
  1073. data/lib/tdl/examples/2_hdl_class/test_module_port.rb +47 -0
  1074. data/lib/tdl/examples/2_hdl_class/test_module_var.rb +18 -0
  1075. data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv +108 -0
  1076. data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +35 -0
  1077. data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv +105 -0
  1078. data/lib/tdl/examples/2_hdl_class/tmp/head_pkg_module.sv +42 -0
  1079. data/lib/tdl/examples/2_hdl_class/tmp/init_module.sv +110 -0
  1080. data/lib/tdl/examples/2_hdl_class/tmp/module_instance_test.sv +31 -0
  1081. data/lib/tdl/examples/2_hdl_class/tmp/port_module.sv +99 -0
  1082. data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv +27 -0
  1083. data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv +78 -0
  1084. data/lib/tdl/examples/2_hdl_class/tmp/test_axi4_M2S.sv +30 -0
  1085. data/lib/tdl/examples/2_hdl_class/tmp/test_foreach.sv +34 -0
  1086. data/lib/tdl/examples/2_hdl_class/tmp/test_function.sv +52 -0
  1087. data/lib/tdl/examples/2_hdl_class/tmp/test_initial_assert.sv +31 -0
  1088. data/lib/tdl/examples/2_hdl_class/tmp/test_inst_sugar.sv +42 -0
  1089. data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +36 -0
  1090. data/lib/tdl/examples/2_hdl_class/tmp/test_module_port.sv +33 -0
  1091. data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +35 -0
  1092. data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +38 -0
  1093. data/lib/tdl/examples/2_hdl_class/tmp/test_package2.sv +36 -0
  1094. data/lib/tdl/examples/2_hdl_class/tmp/test_struct.sv +38 -0
  1095. data/lib/tdl/examples/2_hdl_class/tmp/test_struct_function.sv +44 -0
  1096. data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +27 -0
  1097. data/lib/tdl/examples/2_hdl_class/tmp/text_generate.sv +54 -0
  1098. data/lib/tdl/examples/2_hdl_class/vcs_string.rb +5 -0
  1099. data/lib/tdl/examples/3_hdl_sdl_instance/hdl_test.sv +13 -0
  1100. data/lib/tdl/examples/3_hdl_sdl_instance/main.rb +26 -0
  1101. data/lib/tdl/examples/3_hdl_sdl_instance/main_md.sv +42 -0
  1102. data/lib/tdl/examples/3_hdl_sdl_instance/sdl_md.sv +30 -0
  1103. data/lib/tdl/examples/3_hdl_sdl_instance/sdl_test.rb +9 -0
  1104. data/lib/tdl/examples/4_generate/example.rb +38 -0
  1105. data/lib/tdl/examples/4_generate/test_generate.sv +59 -0
  1106. data/lib/tdl/examples/5_logic_combin/login_combin.rb +22 -0
  1107. data/lib/tdl/examples/5_logic_combin/test_logic_combin.sv +36 -0
  1108. data/lib/tdl/examples/6_module_with_interface/example.rb +48 -0
  1109. data/lib/tdl/examples/6_module_with_interface/example_interface.sv +40 -0
  1110. data/lib/tdl/examples/6_module_with_interface/inf_collect.rb +54 -0
  1111. data/lib/tdl/examples/6_module_with_interface/inf_collect.sv +63 -0
  1112. data/lib/tdl/examples/7_module_with_package/body_package.rb +3 -0
  1113. data/lib/tdl/examples/7_module_with_package/body_package.sv +25 -0
  1114. data/lib/tdl/examples/7_module_with_package/example_pkg.rb +20 -0
  1115. data/lib/tdl/examples/7_module_with_package/example_pkg.sv +35 -0
  1116. data/lib/tdl/examples/7_module_with_package/head_package.rb +8 -0
  1117. data/lib/tdl/examples/7_module_with_package/head_package.sv +29 -0
  1118. data/lib/tdl/examples/8_top_module/dve.tcl +64 -0
  1119. data/lib/tdl/examples/8_top_module/example.rb +8 -0
  1120. data/lib/tdl/examples/8_top_module/pins.yml +7 -0
  1121. data/lib/tdl/examples/8_top_module/tb_test_top.sv +29 -0
  1122. data/lib/tdl/examples/8_top_module/test_top.sv +28 -0
  1123. data/lib/tdl/examples/8_top_module/test_top_constraints.xdc +37 -0
  1124. data/lib/tdl/examples/9_itegration/A_itgt/a_test_md.sv +29 -0
  1125. data/lib/tdl/examples/9_itegration/A_itgt/a_test_module.rb +6 -0
  1126. data/lib/tdl/examples/9_itegration/A_itgt/itgt_module_a_block.rb +34 -0
  1127. data/lib/tdl/examples/9_itegration/clock_manage/itgt_module_clock_manage.rb +33 -0
  1128. data/lib/tdl/examples/9_itegration/clock_manage/simple_clock.rb +7 -0
  1129. data/lib/tdl/examples/9_itegration/clock_manage/simple_clock.sv +29 -0
  1130. data/lib/tdl/examples/9_itegration/dve.tcl +64 -0
  1131. data/lib/tdl/examples/9_itegration/pins.yml +4 -0
  1132. data/lib/tdl/examples/9_itegration/tb_test_top.sv +29 -0
  1133. data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +29 -0
  1134. data/lib/tdl/examples/9_itegration/test_top.sv +40 -0
  1135. data/lib/tdl/examples/9_itegration/test_top_constraints.xdc +29 -0
  1136. data/lib/tdl/examples/9_itegration/test_tttop.sv +40 -0
  1137. data/lib/tdl/examples/9_itegration/test_tttop_constraints.xdc +29 -0
  1138. data/lib/tdl/examples/9_itegration/top.rb +11 -0
  1139. data/lib/tdl/examples/readme.md +31 -0
  1140. data/lib/tdl/exlib/common_cfg_reg_inf.rb +139 -0
  1141. data/lib/tdl/exlib/constraints.rb +286 -0
  1142. data/lib/tdl/exlib/constraints_verb.rb +304 -0
  1143. data/lib/tdl/exlib/dve_tcl.rb +162 -0
  1144. data/lib/tdl/exlib/element_class_vars.rb +106 -0
  1145. data/lib/tdl/exlib/global_param.rb +108 -0
  1146. data/lib/tdl/exlib/integral_test/bak/integral_test.rb +206 -0
  1147. data/lib/tdl/exlib/integral_test/clock_itest.rb +28 -0
  1148. data/lib/tdl/exlib/integral_test/diff_clock_itest.rb +30 -0
  1149. data/lib/tdl/exlib/integral_test/io_itest.rb +41 -0
  1150. data/lib/tdl/exlib/integral_test/reset_itest.rb +31 -0
  1151. data/lib/tdl/exlib/integral_test/simple_logic_itest.rb +19 -0
  1152. data/lib/tdl/exlib/itegration.rb +307 -0
  1153. data/lib/tdl/exlib/itegration_verb.rb +913 -0
  1154. data/lib/tdl/exlib/parse_argv.rb +43 -0
  1155. data/lib/tdl/exlib/sdlmodule_sim.bak.rb +375 -0
  1156. data/lib/tdl/exlib/test_point.rb +287 -0
  1157. data/lib/tdl/global_scan.rb +134 -0
  1158. data/lib/tdl/rebuild_ele/axi4.rb +141 -0
  1159. data/lib/tdl/rebuild_ele/axi_lite.rb +56 -0
  1160. data/lib/tdl/rebuild_ele/axi_stream.rb +121 -0
  1161. data/lib/tdl/rebuild_ele/cm_ram_inf.sv +105 -0
  1162. data/lib/tdl/rebuild_ele/cm_ram_inf_define.rb +44 -0
  1163. data/lib/tdl/rebuild_ele/data_inf.rb +27 -0
  1164. data/lib/tdl/rebuild_ele/data_inf_c.rb +83 -0
  1165. data/lib/tdl/rebuild_ele/ele_base.rb +822 -0
  1166. data/lib/tdl/rebuild_ele/readme.md +1 -0
  1167. data/lib/tdl/sdlimplement/resource.yml +154 -0
  1168. data/lib/tdl/sdlimplement/sdl_impl_module.rb +391 -0
  1169. data/lib/tdl/sdlimplement/sdl_impl_param.rb +26 -0
  1170. data/lib/tdl/sdlimplement/test.rb +64 -0
  1171. data/lib/tdl/sdlmodule/bak/sdlmodule_varible_ex.rb +120 -0
  1172. data/lib/tdl/sdlmodule/generator_block_module.rb +84 -0
  1173. data/lib/tdl/sdlmodule/sdlmodule.rb +407 -0
  1174. data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb +333 -0
  1175. data/lib/tdl/sdlmodule/sdlmodule_draw.rb +272 -0
  1176. data/lib/tdl/sdlmodule/sdlmodule_head_logo.txt +10 -0
  1177. data/lib/tdl/sdlmodule/sdlmodule_instance.rb +623 -0
  1178. data/lib/tdl/sdlmodule/sdlmodule_port_define.rb +374 -0
  1179. data/lib/tdl/sdlmodule/sdlmodule_varible.rb +160 -0
  1180. data/lib/tdl/sdlmodule/sdlmodule_vcs_comptable.rb +140 -0
  1181. data/lib/tdl/sdlmodule/techbench_module.rb +14 -0
  1182. data/lib/tdl/sdlmodule/test_unit_module.rb +138 -0
  1183. data/lib/tdl/sdlmodule/top_module.rb +543 -0
  1184. data/lib/tdl/tdl.rb +265 -0
  1185. data/lib/tdl/tdlerror/tdlerror.rb +8 -0
  1186. data/lib/tdl/testunit/test_all.rb +4 -0
  1187. data/lib/tdl/testunit/test_array_chain.rb +89 -0
  1188. data/lib/tdl/testunit/test_tmp.rb +47 -0
  1189. metadata +1301 -0
data/lib/axi/AXI4/width_convert/width_destruct_A1.sv ADDED
@@ -0,0 +1,251 @@
1
+ /**********************************************
2
+ _______________________________________
3
+ ___________ Cook Darwin __________
4
+ _______________________________________
5
+ descript:
6
+ author : Cook.Darwin
7
+ Version: VERA.1.0
8
+ add user signal
9
+ creaded: 2016/11/21
10
+ madified:
11
+ ***********************************************/
12
+ `timescale 1ns/1ps
13
+ module width_destruct_A1 #(
14
+ parameter DSIZE = 1,
15
+ parameter NSIZE = 8,
16
+ parameter USIZE = 1
17
+ )(
18
+ input clock,
19
+ input rst_n,
20
+ input [DSIZE*NSIZE-1:0] wr_data,
21
+ input wr_vld,
22
+ output logic wr_ready,
23
+ input [USIZE-1:0] wr_user,
24
+ input wr_last,
25
+ output logic[DSIZE-1:0] rd_data,
26
+ output logic rd_vld,
27
+ output logic rd_last,
28
+ output logic[USIZE-1:0] rd_user,
29
+ input rd_ready
30
+ );
31
+
32
+ // assign rd_vld = wr_vld;
33
+
34
+ localparam RSIZE = (NSIZE<16)? 4 :
35
+ (NSIZE<32)? 5 :
36
+ (NSIZE<64)? 6 :
37
+ (NSIZE<128)? 7 : 8;
38
+
39
+ //
40
+ reg [RSIZE-1:0] point;
41
+
42
+ logic [DSIZE-1:0] overflow_data;
43
+ logic overflow;
44
+ logic overflow_last;
45
+
46
+ always@(posedge clock/*,negedge rst_n*/)begin
47
+ if(~rst_n) point <= {RSIZE{1'b0}};
48
+ else begin
49
+ // if(rd_vld && rd_ready && rd_last)
50
+ // point <= {RSIZE{1'b0}};
51
+ if(wr_vld && wr_ready && wr_last)
52
+ point <= {RSIZE{1'b0}};
53
+ else if(overflow && rd_ready)
54
+ point <= {RSIZE{1'b0}};
55
+ else if(wr_vld && rd_ready)begin
56
+ if(point == NSIZE-1)
57
+ point <= {RSIZE{1'b0}};
58
+ else point <= point + 1'b1;
59
+ end else point <= point;
60
+ end end
61
+
62
+ always@(posedge clock/*,negedge rst_n*/)begin
63
+ if(~rst_n) wr_ready <= 1'b0;
64
+ else begin
65
+ if(point==(NSIZE-2) && wr_vld && rd_ready)
66
+ wr_ready <= 1'b1;
67
+ else if(wr_ready && wr_vld)
68
+ wr_ready <= 1'b0;
69
+ else wr_ready <= wr_ready;
70
+ end
71
+ end
72
+
73
+
74
+ always@(posedge clock/*,negedge rst_n*/)begin
75
+ if(~rst_n) overflow_data <= '0;
76
+ else begin
77
+ if((wr_ready & wr_vld) && (!rd_ready & rd_vld) )
78
+ overflow_data <= wr_data[DSIZE-1:0];
79
+ else overflow_data <= overflow_data;
80
+ end
81
+ end
82
+
83
+ always@(posedge clock/*,negedge rst_n*/)begin
84
+ if(~rst_n) overflow <= '0;
85
+ else begin
86
+ if((wr_ready & wr_vld) && (!rd_ready & rd_vld) )
87
+ overflow <= 1'b1;
88
+ else if(overflow && rd_ready)
89
+ overflow <= 1'b0;
90
+ else overflow <= overflow;
91
+ end
92
+ end
93
+
94
+ always@(posedge clock/*,negedge rst_n*/)begin
95
+ if(~rst_n) overflow_last <= '0;
96
+ else begin
97
+ if((wr_ready & wr_vld) && (!rd_ready & rd_vld) )
98
+ overflow_last <= wr_last;
99
+ else if(overflow && rd_ready && overflow_last)
100
+ overflow_last <= 1'b0;
101
+ else overflow_last <= overflow_last;
102
+ end
103
+ end
104
+
105
+ // logic last_byte;
106
+ //
107
+ // always@(posedge clock/*,negedge rst_n*/)begin
108
+ // if(~rst_n) last_byte <= 1'b0;
109
+ // else begin
110
+ // if(point==(NSIZE-1) && wr_vld && rd_ready)
111
+ // last_byte <= 1'b1;
112
+ // else if(last_byte && wr_vld)
113
+ // last_byte <= 1'b0;
114
+ // else last_byte <= last_byte;
115
+ // end
116
+ // end
117
+
118
+ // always@(posedge clock/*,negedge rst_n*/)begin
119
+ // if(~rst_n) rd_data <= {DSIZE{1'b0}};
120
+ // else begin
121
+ // // if(wr_vld && rd_ready)
122
+ // if(wr_vld)
123
+ // rd_data <= wr_data[DSIZE*(NSIZE-point)-1-:DSIZE];
124
+ // else rd_data <= rd_data;
125
+ //
126
+ // // rd_data <= wr_data[DSIZE*(NSIZE-point)-1-:DSIZE];
127
+ // end
128
+ // end
129
+
130
+ always@(posedge clock/*,negedge rst_n*/)begin
131
+ if(~rst_n) rd_data <= {DSIZE{1'b0}};
132
+ else begin
133
+ case({overflow,wr_vld,rd_vld,rd_ready})
134
+ 4'b1000: rd_data <= rd_data;
135
+ 4'b1001: rd_data <= overflow_data;
136
+ 4'b1010: rd_data <= rd_data;
137
+ 4'b1011: rd_data <= overflow_data;
138
+ 4'b1100: rd_data <= rd_data;
139
+ 4'b1101: rd_data <= overflow_data;
140
+ 4'b1110: rd_data <= rd_data;
141
+ 4'b1111: rd_data <= overflow_data;
142
+
143
+ 4'b0000: rd_data <= rd_data;
144
+ 4'b0001: rd_data <= rd_data;
145
+ 4'b0010: rd_data <= rd_data;
146
+ 4'b0011: rd_data <= rd_data;
147
+ 4'b0100: rd_data <= rd_data;
148
+ 4'b0101: rd_data <= wr_data[DSIZE*(NSIZE-point)-1-:DSIZE];
149
+ 4'b0110: rd_data <= rd_data;
150
+ 4'b0111: rd_data <= wr_data[DSIZE*(NSIZE-point)-1-:DSIZE];
151
+ default: rd_data <= rd_data;
152
+ endcase
153
+ end
154
+ end
155
+
156
+ always@(posedge clock/*,negedge rst_n*/)begin
157
+ if(~rst_n) rd_vld <= 1'b0;
158
+ else begin
159
+ // if(wr_vld && wr_ready && wr_last)
160
+ // rd_vld <= 1'b0;
161
+ // else
162
+ case({overflow,wr_vld,rd_vld,rd_ready})
163
+ 4'b1000: rd_vld <= 1'b0;
164
+ 4'b1001: rd_vld <= 1'b1;
165
+ 4'b1010: rd_vld <= 1'b1;
166
+ 4'b1011: rd_vld <= 1'b1;
167
+ 4'b1100: rd_vld <= 1'b0;
168
+ 4'b1101: rd_vld <= 1'b1;
169
+ 4'b1110: rd_vld <= 1'b1;
170
+ 4'b1111: rd_vld <= 1'b1;
171
+
172
+ 4'b0000: rd_vld <= 1'b0;
173
+ 4'b0001: rd_vld <= 1'b0;
174
+ 4'b0010: rd_vld <= 1'b1;
175
+ 4'b0011: rd_vld <= 1'b0;
176
+ 4'b0100: rd_vld <= 1'b0;
177
+ 4'b0101: rd_vld <= 1'b1;
178
+ 4'b0110: rd_vld <= 1'b1;
179
+ 4'b0111: rd_vld <= 1'b1;
180
+ default: rd_vld <= 1'b0;
181
+ endcase
182
+ end
183
+ end
184
+
185
+
186
+ always@(posedge clock/*,negedge rst_n*/)begin
187
+ if(~rst_n) rd_last <= 1'b0;
188
+ else begin
189
+ case({overflow,wr_vld,rd_vld,rd_ready})
190
+ 4'b1000: rd_last <= 1'b0;
191
+ 4'b1001: rd_last <= overflow_last;
192
+ 4'b1010: rd_last <= rd_last;
193
+ 4'b1011: rd_last <= overflow_last;
194
+ 4'b1100: rd_last <= 1'b0;
195
+ 4'b1101: rd_last <= overflow_last;
196
+ 4'b1110: rd_last <= rd_last;
197
+ 4'b1111: rd_last <= overflow_last;
198
+
199
+ 4'b0000: rd_last <= 1'b0;
200
+ 4'b0001: rd_last <= 1'b0;
201
+ 4'b0010: rd_last <= rd_last;
202
+ 4'b0011: rd_last <= 1'b0;
203
+ 4'b0100: rd_last <= 1'b0;
204
+ 4'b0101: rd_last <= point==(NSIZE-1) && wr_last;
205
+ 4'b0110: rd_last <= rd_last;
206
+ 4'b0111: rd_last <= point==(NSIZE-1) && wr_last;
207
+ default: rd_last <= 1'b0;
208
+ endcase
209
+ end
210
+ end
211
+
212
+
213
+ logic [USIZE-1:0] overflow_user;
214
+
215
+ always@(posedge clock/*,negedge rst_n*/)begin
216
+ if(~rst_n) overflow_user <= '0;
217
+ else begin
218
+ if((wr_ready & wr_vld) && (!rd_ready & rd_vld) )
219
+ overflow_user <= wr_user;
220
+ else overflow_user <= overflow_user;
221
+ end
222
+ end
223
+
224
+ always@(posedge clock/*,negedge rst_n*/)begin
225
+ if(~rst_n) rd_user <= {USIZE{1'b0}};
226
+ else begin
227
+ case({overflow,wr_vld,rd_vld,rd_ready})
228
+ 4'b1000: rd_user <= rd_user;
229
+ 4'b1001: rd_user <= overflow_user;
230
+ 4'b1010: rd_user <= rd_user;
231
+ 4'b1011: rd_user <= overflow_user;
232
+ 4'b1100: rd_user <= rd_user;
233
+ 4'b1101: rd_user <= overflow_user;
234
+ 4'b1110: rd_user <= rd_user;
235
+ 4'b1111: rd_user <= overflow_user;
236
+
237
+ 4'b0000: rd_user <= rd_user;
238
+ 4'b0001: rd_user <= rd_user;
239
+ 4'b0010: rd_user <= rd_user;
240
+ 4'b0011: rd_user <= rd_user;
241
+ 4'b0100: rd_user <= rd_user;
242
+ 4'b0101: rd_user <= wr_user;
243
+ 4'b0110: rd_user <= rd_user;
244
+ 4'b0111: rd_user <= wr_user;
245
+ default: rd_user <= rd_user;
246
+ endcase
247
+ end
248
+ end
249
+
250
+
251
+ endmodule
data/lib/axi/AXI_BFM/AXI_BFM_PKG.sv ADDED
@@ -0,0 +1,1039 @@
1
+ /**********************************************
2
+ _______________________________________
3
+ ___________ Cook Darwin __________
4
+ _______________________________________
5
+ descript:
6
+ author : Cook.Darwin
7
+ Version: VERA.0.0
8
+ creaded: 2016/12/27
9
+ madified:
10
+ ***********************************************/
11
+ package AxiBfmPkg ;
12
+
13
+ typedef struct {
14
+ logic [32-1:0] addr;
15
+ logic [32-1:0] data;
16
+ string name = "";
17
+ } AddrData;
18
+
19
+ typedef struct {
20
+ int id;
21
+ int addr;
22
+ int len;
23
+ } IdAddrLen_S ;
24
+
25
+ task automatic sync_clk_wait(const ref bit clock,ref logic condition);
26
+ forever begin
27
+ @(posedge clock);
28
+ if(condition)
29
+ break;
30
+ end
31
+ endtask:sync_clk_wait
32
+
33
+
34
+ class AxiLiteMasterBfm_c #(
35
+ parameter ASIZE = 12,
36
+ parameter DSIZE = 32,
37
+ parameter FreqM = 1
38
+ );
39
+
40
+ AddrData addr_data [$];
41
+
42
+ virtual axi_lite_inf #(
43
+ .ASIZE (ASIZE ),
44
+ .DSIZE (DSIZE ),
45
+ .FreqM (FreqM )
46
+ )axil;
47
+
48
+ function new (virtual axi_lite_inf #(.ASIZE(ASIZE),.DSIZE(DSIZE),.FreqM(FreqM)) b);
49
+ axil = b;
50
+ endfunction:new
51
+
52
+
53
+ task master_reset;
54
+ begin
55
+ #1 ;
56
+ axil.axi_awvalid = 0;
57
+ axil.axi_awaddr = 0;
58
+ axil.axi_wvalid = 0;
59
+ axil.axi_wdata = 0;
60
+ axil.axi_bready = 0;
61
+ axil.axi_arvalid = 0;
62
+ axil.axi_araddr = 0;
63
+ axil.axi_rready = 0;
64
+ end
65
+ endtask:master_reset
66
+
67
+ task automatic wr_data(ref AddrData addr_data [$],input logic relex_last=0);
68
+ int length;
69
+ length = addr_data.size;
70
+ master_reset;
71
+ @(posedge axil.axi_aclk);
72
+ axil.axi_awlock = 1;
73
+ axil.axi_arlock = 0;
74
+ foreach(addr_data[i])begin
75
+ $write("====>>> WRITING AXI LITE: N[%s] A[%h] D[%d] ...... ",addr_data[i].name,addr_data[i].addr,addr_data[i].data);
76
+ fork:ADDR_DATA_FORK
77
+ fork:CMD_LOOP
78
+ axil.axi_awvalid = #1 1;
79
+ axil.axi_awaddr = #1 addr_data[i].addr;
80
+ if(relex_last)begin
81
+ if(i != length - 1)
82
+ axil.axi_awlock = 1'b1;
83
+ else
84
+ axil.axi_awlock = 1'b0;
85
+ end
86
+
87
+ begin
88
+ forever begin
89
+ @(posedge axil.axi_aclk);
90
+ if(axil.axi_awready)begin
91
+ axil.axi_awvalid = #1 0;
92
+ break;
93
+ end
94
+ end
95
+ $write(" CMD DONE !");
96
+ end
97
+ join
98
+ fork:DATA_LOOP
99
+ axil.axi_wvalid = #1 1;
100
+ axil.axi_wdata = #1 addr_data[i].data;
101
+ begin
102
+ forever begin
103
+ @(posedge axil.axi_aclk);
104
+ if(axil.axi_wready)begin
105
+ axil.axi_wvalid = #1 0;
106
+ break;
107
+ end
108
+ end
109
+ $write(" DONE DONE !");
110
+ end
111
+ join
112
+ join
113
+ fork:RESP_LOOP
114
+ axil.axi_bready = #1 1;
115
+ begin
116
+ forever begin
117
+ @(posedge axil.axi_aclk);
118
+ if(axil.axi_bvalid)
119
+ break;
120
+ end
121
+ $write(" RESP DONE !");
122
+ end
123
+ join
124
+ $write(" DONE!!!\n");
125
+ end
126
+ axil.axi_awlock = 0;
127
+ master_reset;
128
+ endtask:wr_data
129
+
130
+ task automatic rd_data(ref AddrData addr_data [$]);
131
+ master_reset;
132
+ this.addr_data = {};
133
+ @(posedge axil.axi_aclk);
134
+ axil.axi_arlock = 1;
135
+ axil.axi_awlock = 0;
136
+ foreach(addr_data[i])fork
137
+ this.addr_data[i].name = addr_data[i].name;
138
+ $write("====>>> READING AXI LITE: N[%s] A[%h] ...... ",addr_data[i].name,addr_data[i].addr);
139
+ fork:CMD_LOOP
140
+ axil.axi_arvalid = #1 1;
141
+ axil.axi_araddr = #1 addr_data[i].addr;
142
+ this.addr_data[i].addr = addr_data[i].addr;
143
+ begin
144
+ forever begin
145
+ @(posedge axil.axi_aclk);
146
+ if(axil.axi_arready)begin
147
+ axil.axi_arvalid = #1 0;
148
+ break;
149
+ end
150
+ end
151
+ $write(" CMD DONE !");
152
+ end
153
+ join
154
+ fork:DATA_LOOP
155
+ axil.axi_rready = #1 1;
156
+ begin
157
+ forever begin
158
+ @(posedge axil.axi_aclk);
159
+ if(axil.axi_rvalid)begin
160
+ // addr_data[i] = #1 axil.axi_rdata;
161
+ axil.axi_rready = #1 0;
162
+ this.addr_data[i].data = axil.axi_rdata;
163
+ break;
164
+ end
165
+ end
166
+ $write(" >>>D[%h] DATA DONE !!!\n",axil.axi_rdata);
167
+ end
168
+ join
169
+ join
170
+ axil.axi_arlock = 0;
171
+ addr_data = this.addr_data;
172
+ endtask:rd_data
173
+
174
+ endclass:AxiLiteMasterBfm_c
175
+
176
+ class AxiLiteSlaverBfm_c #(
177
+ parameter ASIZE = 12,
178
+ parameter DSIZE = 32,
179
+ parameter FreqM = 1
180
+ );
181
+
182
+ int mem [int];
183
+
184
+ virtual axi_lite_inf #(
185
+ .ASIZE (ASIZE ),
186
+ .DSIZE (DSIZE ),
187
+ .FreqM (FreqM )
188
+ )axil;
189
+
190
+ function new (virtual axi_lite_inf #(.ASIZE(ASIZE),.DSIZE(DSIZE),.FreqM(FreqM)) b);
191
+ axil = b;
192
+ endfunction:new
193
+
194
+ task slaver_wr_reset;
195
+ begin
196
+ #1 ;
197
+ axil.axi_awready = 0;
198
+ axil.axi_wready = 0;
199
+ axil.axi_bresp = 0;
200
+ axil.axi_bvalid = 0;
201
+ end
202
+ endtask:slaver_wr_reset
203
+
204
+ task slaver_rd_reset;
205
+ begin
206
+ #1 ;
207
+ axil.axi_arready = 0;
208
+ axil.axi_rdata = 0;
209
+ axil.axi_rvalid = 0;
210
+ end
211
+ endtask:slaver_rd_reset
212
+
213
+ task automatic wr_data();
214
+ AddrData addr_data;
215
+ slaver_wr_reset;
216
+ @(posedge axil.axi_aclk);
217
+ wait(axil.axi_awvalid);
218
+ begin
219
+ // $write("====>>> WRITING AXI LITE: N[%s] A[%h] D[%d] ...... ",addr_data[i].name,addr_data[i].addr,addr_data[i].data);
220
+ fork:ADDR_DATA_FORK
221
+ fork:CMD_LOOP
222
+ axil.axi_awready = #1 1;
223
+ begin
224
+ forever begin
225
+ @(posedge axil.axi_aclk);
226
+ if(axil.axi_awready && axil.axi_awvalid)begin
227
+ addr_data.addr = axil.axi_awaddr;
228
+ axil.axi_awready = #1 0;
229
+ break;
230
+ end
231
+ end
232
+ end
233
+ join
234
+ fork:DATA_LOOP
235
+ axil.axi_wready = #1 1;
236
+ begin
237
+ forever begin
238
+ @(posedge axil.axi_aclk);
239
+ if(axil.axi_wready && axil.axi_wvalid)begin
240
+ addr_data.data = axil.axi_wdata;
241
+ axil.axi_wready = #1 0;
242
+ break;
243
+ end
244
+ end
245
+ end
246
+ join
247
+ join
248
+ fork:RESP_LOOP
249
+ axil.axi_bvalid = #1 1;
250
+ axil.axi_bresp = 0;
251
+ begin
252
+ forever begin
253
+ @(posedge axil.axi_aclk);
254
+ if(axil.axi_bvalid && axil.axi_bready)begin
255
+ #1;
256
+ axil.axi_bvalid = 0;
257
+ break;
258
+ end
259
+ end
260
+ end
261
+ join
262
+ end
263
+ mem[addr_data.addr] = addr_data.data;
264
+ $write("\n====>>> WRITING AXI LITE: N[%s] A[%h] D[%d]\n",addr_data.name,addr_data.addr,addr_data.data);
265
+ slaver_wr_reset;
266
+ endtask:wr_data
267
+
268
+
269
+ task automatic rd_data();
270
+ AddrData addr_data;
271
+ int data_tmp;
272
+ slaver_rd_reset;
273
+ @(posedge axil.axi_aclk);
274
+ wait(axil.axi_arvalid);
275
+ begin
276
+ fork:CMD_LOOP
277
+ axil.axi_arready = #1 1;
278
+ begin
279
+ forever begin
280
+ @(posedge axil.axi_aclk);
281
+ if(axil.axi_arready && axil.axi_arvalid)begin
282
+ addr_data.addr = axil.axi_araddr;
283
+ data_tmp = mem[addr_data.addr];
284
+ axil.axi_arready = #1 0;
285
+ break;
286
+ end
287
+ end
288
+ $write(" RD Lite CMD DONE !");
289
+ end
290
+ join
291
+ fork:DATA_LOOP
292
+ axil.axi_rvalid = 1;
293
+ // axil.axi_rdata = addr_data.data;
294
+ axil.axi_rdata = data_tmp;
295
+ begin
296
+ forever begin
297
+ @(posedge axil.axi_aclk);
298
+ if(axil.axi_rvalid && axil.axi_rready)begin
299
+ axil.axi_rvalid = #1 0;
300
+ break;
301
+ end
302
+ end
303
+ end
304
+ join
305
+ end
306
+ $write("\n====>>> READING AXI LITE: N[%s] A[%h]\n",addr_data.name,addr_data.addr);
307
+ slaver_rd_reset;
308
+ endtask:rd_data
309
+
310
+ endclass : AxiLiteSlaverBfm_c
311
+
312
+ class AxiStreamSlaverBfm_c #(
313
+ parameter DSIZE = 8,
314
+ parameter FreqM = 1
315
+ );
316
+
317
+ logic[DSIZE-1:0] data_squeue [$];
318
+
319
+ virtual axi_stream_inf #(.DSIZE(DSIZE),.FreqM(FreqM)) axis_inf;
320
+
321
+ function new (virtual axi_stream_inf #(.DSIZE(DSIZE),.FreqM(FreqM)) b);
322
+ axis_inf = b;
323
+ endfunction:new
324
+
325
+ task automatic get_data(int rate = 100,bit info=1);
326
+ int rm;
327
+ wait(axis_inf.aresetn);
328
+ data_squeue = {};
329
+ forever begin
330
+ rm = $urandom_range(0,99);
331
+ if(rm < rate)
332
+ axis_inf.axis_tready = #(1ps) 1;
333
+ else axis_inf.axis_tready = #(1ps) 0;
334
+
335
+ @(posedge axis_inf.aclk)
336
+ if(axis_inf.axis_tvalid && axis_inf.axis_tready)begin
337
+ data_squeue.push_back(axis_inf.axis_tdata);
338
+ if(axis_inf.axis_tlast)
339
+ break;
340
+ end
341
+ end
342
+ #(1ps)
343
+ axis_inf.axis_tready = 0;
344
+ if(info)
345
+ $display("AXI GET LENGTH [%d] DATA DONE!!!",data_squeue.size());
346
+ endtask:get_data
347
+
348
+ endclass:AxiStreamSlaverBfm_c
349
+
350
+ class AxiStreamMasterBfm_c #(
351
+ parameter DSIZE = 8,
352
+ parameter MSG = "ON",
353
+ parameter FreqM = 1
354
+ );
355
+
356
+ virtual axi_stream_inf #(.DSIZE(DSIZE),.FreqM(FreqM)) axis_inf;
357
+
358
+ function new (virtual axi_stream_inf #(.DSIZE(DSIZE),.FreqM(FreqM)) b);
359
+ axis_inf = b;
360
+ axis_inf.axis_tvalid = 0;
361
+ axis_inf.axis_tlast = 0;
362
+ axis_inf.axis_tdata = 0;
363
+ axis_inf.axis_tkeep = 0;
364
+ endfunction:new
365
+
366
+ task automatic resize_queue(
367
+ int len,
368
+ ref logic [DSIZE-1:0] in_queue [$],
369
+ ref logic [DSIZE-1:0] out_queue[$]
370
+ );
371
+ int real_len;
372
+ int d_len;
373
+ int r_len;
374
+ out_queue = {};
375
+ if(len == 0)
376
+ out_queue = in_queue;
377
+ else if(len <= in_queue.size())
378
+ out_queue = in_queue[0:(len-1)];
379
+ else begin
380
+ real_len = in_queue.size();
381
+ d_len = len/real_len;
382
+ r_len = len%real_len;
383
+ for(int i=0;i<d_len;i++)
384
+ out_queue = {out_queue,in_queue};
385
+ out_queue = {out_queue,in_queue[0:(r_len-1)]};
386
+
387
+ end
388
+ // $display("---%d--%d--%d",len,in_queue.size(),out_queue.size());
389
+ endtask:resize_queue
390
+
391
+ task automatic gen_axi_stream (
392
+ int length,
393
+ int valid_ramdon_percent,
394
+ ref [DSIZE-1:0] data_s [$]
395
+
396
+ );
397
+ int rt;
398
+ logic [DSIZE-1:0] data_ss[$];
399
+ resize_queue(length,data_s,data_ss);
400
+ // $display("ORIGIN LENGTH: %d,REAL LENGTH: %d",data_s.size(),data_ss.size());
401
+ @(posedge axis_inf.aclk);
402
+ #(1ps);
403
+ if(MSG=="ON")begin
404
+ $display("_______________SEND___________________");
405
+ $display("%t,GEN AXI STREAM LEN = %d",$time,data_ss.size());
406
+ end
407
+ while(1)begin
408
+ rt = $urandom_range(99,0);
409
+ axis_inf.axis_tvalid = (rt < valid_ramdon_percent);
410
+ if(axis_inf.axis_tvalid)begin
411
+ axis_inf.axis_tdata = data_ss.size() != 0? data_ss.pop_front : axis_inf.axis_tdata;
412
+ axis_inf.axis_tkeep = '1;
413
+ axis_inf.axis_tlast = data_ss.size() == 0;
414
+
415
+ sync_clk_wait(axis_inf.aclk,axis_inf.axis_tready);
416
+
417
+ if(axis_inf.axis_tlast)begin
418
+ // axis_inf.axis_tlast = 0;
419
+ // @(posedge axis_inf.aclk);
420
+ // #(1ps);
421
+ break;
422
+ end
423
+ // @(posedge axis_inf.aclk);
424
+ #(1ps);
425
+ end else begin
426
+ @(posedge axis_inf.aclk);
427
+ end
428
+ end
429
+ #(1ps);
430
+ axis_inf.axis_tvalid = 0;
431
+ axis_inf.axis_tlast = 0;
432
+ axis_inf.axis_tkeep = '0;
433
+ if(MSG=="ON")
434
+ $display("===============SEND===================");
435
+ endtask:gen_axi_stream
436
+
437
+ endclass:AxiStreamMasterBfm_c
438
+
439
+ //---------------------------------------------------------------------
440
+ // AXI 4 Master BFM
441
+ //____________________________________________________________________
442
+ class Axi4MasterBfm_c #(
443
+ parameter IDSIZE = 1,
444
+ parameter ASIZE = 32,
445
+ parameter LSIZE = 1,
446
+ parameter DSIZE = 32,
447
+ parameter MSG = "ON",
448
+ parameter ADDR_STEP = 32'hFFFF_FFFF,
449
+ parameter FreqM = 1
450
+ );
451
+ mailbox wid_box;
452
+ // typedef struct {
453
+ // logic [IDSIZE-1:0] id;
454
+ // logic [ASIZE-1:0] addr;
455
+ // logic [LSIZE-1:0] len;
456
+ // } IdAddrLen_S ;
457
+
458
+ IdAddrLen_S tra_ar_od [$];
459
+
460
+ virtual axi_inf #(
461
+ .IDSIZE (IDSIZE ),
462
+ .ASIZE (ASIZE ),
463
+ .LSIZE (LSIZE ),
464
+ .DSIZE (DSIZE ),
465
+ .ADDR_STEP (ADDR_STEP),
466
+ .FreqM (FreqM )
467
+ ) inf;
468
+
469
+
470
+ function new (virtual axi_inf #(.IDSIZE(IDSIZE),.ASIZE(ASIZE),.LSIZE(LSIZE),.DSIZE(DSIZE),.ADDR_STEP(ADDR_STEP),.FreqM(FreqM)) b);
471
+ inf = b;
472
+ wid_box = new();
473
+ endfunction:new
474
+
475
+ task wr_reset_status;
476
+ inf.axi_awid = 0;
477
+ inf.axi_awaddr = 0;
478
+ inf.axi_awlen = 0;
479
+ inf.axi_awsize = 0;
480
+ inf.axi_awburst = 0;
481
+ inf.axi_awlock = 0;
482
+ inf.axi_awcache = 0;
483
+ inf.axi_awprot = 0;
484
+ inf.axi_awqos = 0;
485
+ inf.axi_awvalid = 0;
486
+
487
+ inf.axi_wdata = 0;
488
+ inf.axi_wstrb = 0;
489
+ inf.axi_wlast = 0;
490
+ inf.axi_wvalid = 0;
491
+
492
+ inf.axi_bready = 0;
493
+ endtask:wr_reset_status
494
+ task rd_reset_status;
495
+ inf.axi_arid = 0;
496
+ inf.axi_araddr = 0;
497
+ inf.axi_arlen = 0;
498
+ inf.axi_arsize = 0;
499
+ inf.axi_arburst = 0;
500
+ inf.axi_arlock = 0;
501
+ inf.axi_arcache = 0;
502
+ inf.axi_arprot = 0;
503
+ inf.axi_arqos = 0;
504
+ inf.axi_arvalid = 0;
505
+ inf.axi_rready = 0;
506
+ endtask:rd_reset_status
507
+
508
+ task automatic init ();
509
+ fork
510
+ wr_reset_status();
511
+ rd_reset_status();
512
+ join
513
+ endtask:init
514
+
515
+ task automatic sync_wait(ref logic condition);
516
+ forever begin
517
+ @(posedge inf.axi_aclk);
518
+ if(condition)
519
+ break;
520
+ end
521
+ endtask:sync_wait
522
+
523
+
524
+ task automatic aw_task(logic [ASIZE-1:0] addr,logic [LSIZE-1:0] len);
525
+ wr_reset_status();
526
+ if(MSG=="ON")
527
+ $display("AXI4 Write ADDR[%h],LEN[%d]",addr,len);
528
+
529
+ @(posedge inf.axi_aclk);
530
+ inf.axi_awvalid = 1;
531
+ inf.axi_awlen = len-1;
532
+ inf.axi_awaddr = addr;
533
+ inf.axi_awid = $urandom_range(10,0);
534
+ sync_wait(inf.axi_awready);
535
+ inf.axi_awvalid = 0;
536
+ // wid_box.put(inf.axi_awid);
537
+ endtask:aw_task
538
+
539
+ task automatic wdata_task(
540
+ int length,
541
+ int valid_ramdon_percent,
542
+ ref [DSIZE-1:0] data_s [$]
543
+ );
544
+ if(MSG=="ON")
545
+ ;
546
+ gen_axi_stream(length,valid_ramdon_percent,data_s);
547
+ endtask:wdata_task
548
+
549
+ task automatic wbrep_task();
550
+ inf.axi_bready = 1;
551
+ sync_wait(inf.axi_bvalid);
552
+ inf.axi_bready = 0;
553
+ if(MSG=="ON")
554
+ $display("WRITE BURST COMPLETE!!!");
555
+ endtask:wbrep_task
556
+
557
+ task automatic ar_task(logic [ASIZE-1:0] addr,logic [LSIZE-1:0] len);
558
+ // @(posedge inf.axi_aclk);
559
+ inf.axi_arvalid = 1;
560
+ // @(posedge inf.axi_aclk);
561
+ // $stop;
562
+ inf.axi_arid = $urandom_range(10,0);
563
+ inf.axi_arlen = len-1;
564
+ inf.axi_araddr = addr;
565
+ sync_wait(inf.axi_arready);
566
+ // forever begin
567
+ // @(negedge inf.axi_aclk);
568
+ // if(inf.axi_arready)begin
569
+ // break;
570
+ // end
571
+ // end
572
+ // @(negedge inf.axi_aclk);
573
+ #(1ps);
574
+ inf.axi_arvalid = 0;
575
+ if(MSG=="ON")
576
+ $display("%t,MASTER AXI4 READ ADDR[%h]",$time,addr);
577
+ endtask:ar_task
578
+
579
+ task automatic ar_od_task(int id,int addr,int len);
580
+ IdAddrLen_S ial;
581
+ inf.axi_arvalid = 1;
582
+ inf.axi_arlen = len-1;
583
+ inf.axi_araddr = addr;
584
+ inf.axi_arid = id;
585
+ sync_wait(inf.axi_arready);
586
+ ial.id = inf.axi_arid;
587
+ ial.addr = inf.axi_araddr;
588
+ ial.len = inf.axi_arlen;
589
+ #(1ps);
590
+ inf.axi_arvalid = 0;
591
+ if(MSG=="ON")
592
+ $display("%t,MASTER AXI4 READ ADDR[%h]",$time,addr);
593
+ tra_ar_od.push_back(ial);
594
+ endtask:ar_od_task
595
+
596
+ task automatic gen_axi_stream (
597
+ int length,
598
+ int valid_ramdon_percent,
599
+ ref [DSIZE-1:0] data_s [$]
600
+
601
+ );
602
+ int index;
603
+ int cc = 0;
604
+ int data_len;
605
+ int rt;
606
+ logic [DSIZE-1:0] data_ss[$];
607
+ logic[DSIZE-1:0] curr_data;
608
+ int real_len;
609
+
610
+ data_len = data_s.size();
611
+ cc=0;
612
+
613
+ if(length==0)
614
+ real_len = data_len;
615
+ else real_len = length;
616
+
617
+ repeat(real_len)begin
618
+ index = cc%data_len;
619
+ data_ss[cc] = data_s[index];
620
+ cc++;
621
+ end
622
+ // $display("ORIGIN LENGTH: %d,REAL LENGTH: %d",data_s.size(),data_ss.size());
623
+ if(MSG=="ON")begin
624
+ $display("__________________________________");
625
+ $display("GEN AXI4 write burst STREAM LEN = %d",data_ss.size());
626
+ end
627
+ while(1)begin
628
+ rt = $urandom_range(99,0);
629
+
630
+ if(rt < valid_ramdon_percent)begin
631
+ inf.axi_wvalid = 1;
632
+ #(1ps);
633
+ inf.axi_wdata = data_ss.size() != 0? data_ss.pop_front : inf.axi_wdata;
634
+ inf.axi_wlast = data_ss.size() == 0;
635
+ sync_wait(inf.axi_wready);
636
+ // forever begin
637
+ // @(negedge inf.axi_aclk);
638
+ // if(inf.axi_wready)begin
639
+ // break;
640
+ // end
641
+ // end
642
+ if(inf.axi_wlast)
643
+ break;
644
+ end else begin
645
+ inf.axi_wvalid = 0;
646
+ inf.axi_wlast = 0;
647
+ @(posedge inf.axi_aclk);
648
+ end
649
+
650
+ end
651
+
652
+ #(1ps)
653
+ // @(negedge inf.axi_aclk);
654
+ inf.axi_wvalid = 0;
655
+ inf.axi_wlast = 0;
656
+ if(MSG=="ON")
657
+ $display("==================================");
658
+ endtask:gen_axi_stream
659
+
660
+ task automatic get_axi_data(int rate = 100,ref logic [DSIZE-1:0] data [$]);
661
+ int rm;
662
+ data = {};
663
+ forever begin
664
+ rm = $urandom_range(0,99);
665
+ if(rm < rate)
666
+ inf.axi_rready = 1;
667
+ else inf.axi_rready = 0;
668
+ if(inf.axi_rready)begin
669
+ sync_wait(inf.axi_rvalid);
670
+ // forever begin
671
+ // @(negedge inf.axi_aclk);
672
+ // if(inf.axi_rvalid)begin
673
+ // // @(posedge inf.axi_aclk);
674
+ // break;
675
+ // end
676
+ // end
677
+
678
+ data.push_back(inf.axi_rdata);
679
+ if(inf.axi_rlast)begin
680
+ // @(posedge inf.axi_aclk);
681
+ break;
682
+ end
683
+ end else begin
684
+ @(posedge inf.axi_aclk);
685
+ end
686
+ end
687
+ #(1ps);
688
+ inf.axi_rready = 0;
689
+ if(MSG=="ON")
690
+ $display("%t,MASTER AXI4 READ LENGTH [%d] DATA DONE!!!",$time,data.size());
691
+ endtask:get_axi_data
692
+
693
+ //public
694
+ task automatic write_burst(
695
+ logic[ASIZE-1:0] addr,
696
+ int length,
697
+ int valid_ramdon_percent,
698
+ ref [DSIZE-1:0] data_s [$]
699
+ );
700
+ int len ;
701
+ if(length==0)
702
+ len = data_s.size();
703
+ else len = length;
704
+
705
+ aw_task(addr,len);
706
+ wdata_task(len,valid_ramdon_percent,data_s);
707
+ wbrep_task();
708
+ endtask:write_burst
709
+
710
+ task automatic read_burst(
711
+ logic[ASIZE-1:0] addr,
712
+ int length,
713
+ int ready_ramdon_percent,
714
+ ref [DSIZE-1:0] data_s [$]
715
+ );
716
+ ar_task(addr,length);
717
+ get_axi_data(ready_ramdon_percent,data_s);
718
+ endtask:read_burst
719
+
720
+ logic [DSIZE-1:0] rd_queue [$];
721
+
722
+ task automatic out_of_order_read_burst(
723
+ ref IdAddrLen_S ial [$],
724
+ int ready_ramdon_percent,
725
+ ref [DSIZE-1:0] data_s [$]
726
+ );
727
+ fork
728
+ foreach(ial[i])
729
+ ar_od_task(ial[i].id,ial[i].addr,ial[i].len);
730
+ foreach(ial[i])
731
+ get_axi_data(ready_ramdon_percent,data_s);
732
+ join
733
+ if(MSG=="ON")
734
+ $display("%t,MASTER AXI4 OUT OF ORDER READ BURST DONE!!!",$time);
735
+ endtask:out_of_order_read_burst
736
+
737
+
738
+ endclass:Axi4MasterBfm_c
739
+ //----------------------------------------------------------------------
740
+ // AXI 4 Slaver BFM
741
+ //____________________________________________________________________
742
+ class Axi4SlaverBfm_c #(
743
+ parameter IDSIZE = 1,
744
+ parameter ASIZE = 32,
745
+ parameter LSIZE = 1,
746
+ parameter DSIZE = 32,
747
+ parameter MSG = "ON",
748
+ parameter ADDR_STEP = 32'hFFFF_FFFF,
749
+ parameter FreqM = 1
750
+ );
751
+ mailbox wid_box;
752
+ mailbox rid_box;
753
+
754
+ virtual axi_inf #(
755
+ .IDSIZE (IDSIZE ),
756
+ .ASIZE (ASIZE ),
757
+ .LSIZE (LSIZE ),
758
+ .DSIZE (DSIZE ),
759
+ .ADDR_STEP (ADDR_STEP),
760
+ .FreqM (FreqM )
761
+ ) inf;
762
+
763
+
764
+ IdAddrLen_S rev_ar_OD [$];
765
+
766
+ function new (virtual axi_inf #(.IDSIZE(IDSIZE),.ASIZE(ASIZE),.LSIZE(LSIZE),.DSIZE(DSIZE),.ADDR_STEP(ADDR_STEP),.FreqM(FreqM)) b);
767
+ inf = b;
768
+ wid_box = new();
769
+ rid_box = new();
770
+
771
+ inf.axi_rvalid = 0;
772
+ inf.axi_arready = 0;
773
+ endfunction:new
774
+
775
+ task automatic sync_wait(ref logic condition);
776
+ forever begin
777
+ @(negedge inf.axi_aclk);
778
+ if(condition)begin
779
+ @(posedge inf.axi_aclk);
780
+ break;
781
+ end
782
+ end
783
+ endtask:sync_wait
784
+
785
+ task automatic create_wr_transaction();
786
+ inf.axi_awready = 1;
787
+ inf.axi_wready = 1;
788
+ inf.axi_bid = 0;
789
+ inf.axi_bvalid = 0;
790
+ inf.axi_bresp = 0;
791
+ endtask:create_wr_transaction
792
+
793
+ task automatic create_rd_transaction();
794
+ inf.axi_arready = 1;
795
+ inf.axi_rvalid = 0;
796
+ inf.axi_rid = 0;
797
+ inf.axi_rdata = 0;
798
+ inf.axi_rlast = 0;
799
+ inf.axi_rresp = 0;
800
+ endtask:create_rd_transaction
801
+
802
+ task automatic create_transaction();
803
+ create_wr_transaction();
804
+ create_rd_transaction();
805
+ endtask:create_transaction
806
+
807
+ task automatic aw_task(ref logic[ASIZE-1:0] addr,ref logic[LSIZE-1:0] len);
808
+ inf.axi_awready = 1;
809
+ sync_wait(inf.axi_awvalid);
810
+ if(MSG=="ON")begin
811
+ $display("%t,SLAVER AXI4 WRITE BURST REQ ADDR[%h],LEN[%d]",$time,inf.axi_awaddr,inf.axi_awlen);
812
+ end
813
+ addr = inf.axi_awaddr;
814
+ len = inf.axi_awlen;
815
+ wid_box.put(inf.axi_awid);
816
+ endtask:aw_task
817
+
818
+ task automatic ar_task(ref logic[ASIZE-1:0] addr,ref logic[LSIZE-1:0] len);
819
+ inf.axi_arready = 1;
820
+ sync_wait(inf.axi_arvalid);
821
+ inf.axi_arready = 0;
822
+ if(MSG=="ON")begin
823
+ $display("%t,SLAVER AXI4 READ BURST REQ ADDR[%h],LEN[%d]",$time,inf.axi_araddr,inf.axi_arlen);
824
+ end
825
+ addr = inf.axi_araddr;
826
+ len = inf.axi_arlen;
827
+ rid_box.put(inf.axi_arid);
828
+ endtask:ar_task
829
+
830
+
831
+ task automatic ar_od_task();
832
+ IdAddrLen_S ial;
833
+ inf.axi_arready = 1;
834
+ sync_wait(inf.axi_arvalid);
835
+ ial.id = inf.axi_arid;
836
+ ial.addr = inf.axi_araddr;
837
+ ial.len = inf.axi_arlen;
838
+ rid_box.put(inf.axi_arid);
839
+ if(MSG=="ON")begin
840
+ $display("%t,SLAVER AXI4 READ BURST REQ ID [%d] ADDR[%h],LEN[%d]",$time,ial.id,ial.addr,ial.len);
841
+ end
842
+ rev_ar_OD.push_back(ial);
843
+ endtask:ar_od_task
844
+
845
+ task automatic wdata_task(
846
+ int ready_ramdon_percent,
847
+ ref logic[DSIZE-1:0] data [$]);
848
+ int rt;
849
+ data = {};
850
+ forever begin
851
+ rt = $urandom_range(99,0);
852
+ if(rt < ready_ramdon_percent)begin
853
+ inf.axi_wready = 1;
854
+ sync_wait(inf.axi_wvalid);
855
+ data = {data,inf.axi_wdata};
856
+ if(inf.axi_wlast)
857
+ break;
858
+ end else begin
859
+ inf.axi_wready = 0;
860
+ @(posedge inf.axi_aclk);
861
+ end
862
+ end
863
+ if(MSG=="ON")
864
+ $display("%t,AXI4 GET DATA LEN [%d]",$time,data.size());
865
+ endtask:wdata_task
866
+
867
+ task automatic rdata_task(
868
+ int len,
869
+ int valid_ramdon_percent,
870
+ ref logic[DSIZE-1:0] data [$]
871
+ );
872
+ int rt;
873
+ logic[DSIZE-1:0] data_queue[$];
874
+ resize_queue(len+1,data,data_queue);
875
+ // $display("AXI4 READ BURST SLAVER DONE !!! LEN [%d]",len);
876
+ rid_box.get(inf.axi_rid);
877
+ forever begin
878
+ rt = $urandom_range(99,0);
879
+ if(rt < valid_ramdon_percent)begin
880
+ inf.axi_rvalid = 1;
881
+ inf.axi_rdata = data_queue.size() != 0? data_queue.pop_front : inf.axi_rdata;
882
+ inf.axi_rlast = data_queue.size() == 0;
883
+ sync_wait(inf.axi_rready);
884
+ if(inf.axi_rlast)
885
+ break;
886
+ end else begin
887
+ inf.axi_rvalid = 0;
888
+ inf.axi_rlast = 0;
889
+ @(posedge inf.axi_aclk);
890
+ end
891
+ end
892
+ inf.axi_rvalid = 0;
893
+ inf.axi_rlast = 0;
894
+ inf.axi_arready = 1;
895
+ if(MSG=="ON")
896
+ $display("%t,AXI4 READ BURST SLAVER DONE !!! LEN [%0d]",$time,len);
897
+ endtask:rdata_task
898
+
899
+ task automatic rdata_od_task(
900
+ int id,
901
+ int len,
902
+ int valid_ramdon_percent,
903
+ ref logic[DSIZE-1:0] data [$]
904
+ );
905
+ int rt;
906
+ logic[DSIZE-1:0] data_queue[$];
907
+ resize_queue(len,data,data_queue);
908
+ // $display(">>>>>>AXI4 READ BURST SLAVER DONE !!! LEN [%d][%d]",len,data_queue.size());
909
+ rid_box.get(inf.axi_rid);
910
+ forever begin
911
+ rt = $urandom_range(99,0);
912
+ // inf.axi_rid = id;
913
+ if(rt < valid_ramdon_percent)begin
914
+ inf.axi_rvalid = 1;
915
+ inf.axi_rdata = data_queue.size() != 0? data_queue.pop_front : inf.axi_rdata;
916
+ inf.axi_rlast = data_queue.size() == 0;
917
+ sync_wait(inf.axi_rready);
918
+ if(inf.axi_rlast)begin
919
+ @(posedge inf.axi_aclk);
920
+ break;
921
+ end
922
+ end else begin
923
+ inf.axi_rvalid = 0;
924
+ inf.axi_rlast = 0;
925
+ @(posedge inf.axi_aclk);
926
+ end
927
+ end
928
+ inf.axi_rvalid = 0;
929
+ inf.axi_rlast = 0;
930
+ if(MSG=="ON")
931
+ $display("%t,AXI4 READ BURST SLAVER DONE !!! LEN [%d]",$time,len);
932
+ endtask:rdata_od_task
933
+
934
+ task automatic wbresp_task();
935
+ inf.axi_bresp = '0;
936
+ inf.axi_bvalid = 1;
937
+ wid_box.get(inf.axi_bid);
938
+ sync_wait(inf.axi_bready);
939
+ inf.axi_bvalid = 0;
940
+ if(MSG=="ON")
941
+ $display("%t,AXI4 WRITE BUSRT BRESP DONE !!!",$time);
942
+ endtask:wbresp_task
943
+
944
+ task automatic resize_queue(
945
+ int len,
946
+ ref logic [DSIZE-1:0] in_queue [$],
947
+ ref logic [DSIZE-1:0] out_queue[$]
948
+ );
949
+ int real_len;
950
+ int d_len;
951
+ int r_len;
952
+ out_queue = {};
953
+ if(len == 0)
954
+ out_queue = in_queue;
955
+ else if(len <= in_queue.size())
956
+ out_queue = in_queue[0:(len-1)];
957
+ else begin
958
+ real_len = in_queue.size();
959
+ d_len = len/real_len;
960
+ r_len = len%real_len;
961
+ for(int i=0;i<d_len;i++)
962
+ out_queue = {out_queue,in_queue};
963
+ out_queue = {out_queue,in_queue[0:(r_len-1)]};
964
+
965
+ end
966
+ // $display("---%d--%d--%d",len,in_queue.size(),out_queue.size());
967
+ endtask:resize_queue
968
+
969
+ task automatic burst_write(
970
+ ref logic[ASIZE-1:0] addr,
971
+ ref logic[LSIZE-1:0] length,
972
+ input int ready_ramdon_percent,
973
+ ref [DSIZE-1:0] data_s [$]
974
+ );
975
+ aw_task(addr,length);
976
+ wdata_task(ready_ramdon_percent,data_s);
977
+ wbresp_task();
978
+ endtask:burst_write
979
+
980
+ task automatic burst_read(
981
+ ref logic[ASIZE-1:0] addr,
982
+ ref logic[LSIZE-1:0] length,
983
+ int valid_ramdon_percent,
984
+ ref [DSIZE-1:0] data_s [$]
985
+ );
986
+
987
+ ar_task(addr,length);
988
+ rdata_task(int'(length),valid_ramdon_percent,data_s);
989
+ endtask:burst_read
990
+
991
+
992
+ logic [ASIZE-1:0] wr_addr,rd_addr;
993
+ logic [LSIZE-1:0] wr_len,rd_len;
994
+ logic [DSIZE-1:0] wr_queue [$];
995
+ logic [DSIZE-1:0] rd_queue [$];
996
+
997
+ task automatic run (int valid_ramdon_percent,int ready_ramdon_percent);
998
+ create_transaction();
999
+ fork
1000
+ forever begin
1001
+ burst_write(wr_addr,wr_len,ready_ramdon_percent,wr_queue);
1002
+ end
1003
+ forever begin
1004
+ burst_read(rd_addr,rd_len,valid_ramdon_percent,rd_queue);
1005
+ end
1006
+ join_none
1007
+ endtask:run
1008
+
1009
+ task automatic out_fo_order_burst_read(
1010
+ int valid_ramdon_percent
1011
+ );
1012
+ IdAddrLen_S idl;
1013
+ logic [DSIZE-1:0] rd_queue [$];
1014
+ rd_queue = {0,1,2,3,4,5,6,7,8,9};
1015
+ fork
1016
+ forever begin
1017
+ ar_od_task();
1018
+ end
1019
+ forever begin
1020
+ forever begin
1021
+ @(posedge inf.axi_aclk);
1022
+ if(rev_ar_OD.size()>0)
1023
+ break;
1024
+ end
1025
+ idl = rev_ar_OD.pop_front();
1026
+ rdata_od_task(idl.id,int'(idl.len+1),valid_ramdon_percent,rd_queue);
1027
+ end
1028
+ join_none
1029
+ endtask:out_fo_order_burst_read
1030
+
1031
+
1032
+ endclass:Axi4SlaverBfm_c
1033
+
1034
+ endpackage:AxiBfmPkg
1035
+
1036
+ // package AXI_BFM_PKG;
1037
+ // import AxiBfmPkg::*;
1038
+ // export AxiBfmPkg::*;
1039
+ // endpackage