axi_tdl 0.0.2

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Files changed (1189) hide show
  1. checksums.yaml +7 -0
  2. data/.gitignore +8 -0
  3. data/CODE_OF_CONDUCT.md +74 -0
  4. data/Gemfile +6 -0
  5. data/Gemfile.lock +43 -0
  6. data/LICENSE +504 -0
  7. data/README.md +311 -0
  8. data/Rakefile +18 -0
  9. data/axi_tdl.gemspec +43 -0
  10. data/bin/console +14 -0
  11. data/bin/setup +8 -0
  12. data/lib/.rspec +1 -0
  13. data/lib/axi/AXI4/axi4_combin_wr_rd_batch.sv +59 -0
  14. data/lib/axi/AXI4/axi4_direct.sv +137 -0
  15. data/lib/axi/AXI4/axi4_direct_A1.sv +229 -0
  16. data/lib/axi/AXI4/axi4_direct_B1.sv +74 -0
  17. data/lib/axi/AXI4/axi4_direct_verb.sv +79 -0
  18. data/lib/axi/AXI4/axi4_direct_verc.sv +146 -0
  19. data/lib/axi/AXI4/axi4_dpram_cache.rb +106 -0
  20. data/lib/axi/AXI4/axi4_dpram_cache.sv +112 -0
  21. data/lib/axi/AXI4/axi4_long_to_axi4_wide.sv +85 -0
  22. data/lib/axi/AXI4/axi4_long_to_axi4_wide_A1.sv +96 -0
  23. data/lib/axi/AXI4/axi4_long_to_axi4_wide_track.sv +118 -0
  24. data/lib/axi/AXI4/axi4_long_to_axi4_wide_verb.sv +131 -0
  25. data/lib/axi/AXI4/axi4_pipe/axi4_pipe.sv +44 -0
  26. data/lib/axi/AXI4/axi4_pipe/axi4_pipe_verb.sv +45 -0
  27. data/lib/axi/AXI4/axi4_pipe/axi4_rd_pipe.sv +111 -0
  28. data/lib/axi/AXI4/axi4_pipe/axi4_rd_pipe_verb.sv +113 -0
  29. data/lib/axi/AXI4/axi4_pipe/axi4_wr_pipe.sv +142 -0
  30. data/lib/axi/AXI4/axi4_pipe/axi4_wr_pipe_verb.sv +146 -0
  31. data/lib/axi/AXI4/axi4_rd_auxiliary_batch_gen.sv +134 -0
  32. data/lib/axi/AXI4/axi4_rd_auxiliary_gen.sv +89 -0
  33. data/lib/axi/AXI4/axi4_rd_auxiliary_gen_A1.sv +109 -0
  34. data/lib/axi/AXI4/axi4_rd_burst_track.sv +164 -0
  35. data/lib/axi/AXI4/axi4_wr_aux_bind_data.sv +121 -0
  36. data/lib/axi/AXI4/axi4_wr_auxiliary_batch_gen.sv +140 -0
  37. data/lib/axi/AXI4/axi4_wr_auxiliary_gen.sv +102 -0
  38. data/lib/axi/AXI4/axi4_wr_auxiliary_gen_without_resp.sv +91 -0
  39. data/lib/axi/AXI4/axi4_wr_burst_track.sv +146 -0
  40. data/lib/axi/AXI4/axi_stream_add_addr_len.sv +50 -0
  41. data/lib/axi/AXI4/axi_stream_to_axi4_wr.sv +61 -0
  42. data/lib/axi/AXI4/axi_stream_to_axi4_wr_verb.sv.bak +123 -0
  43. data/lib/axi/AXI4/axis_to_axi4_wr.rb +149 -0
  44. data/lib/axi/AXI4/axis_to_axi4_wr.sv +141 -0
  45. data/lib/axi/AXI4/full_axi4_to_axis.sv +188 -0
  46. data/lib/axi/AXI4/full_axi4_to_axis_partition_wr_rd.sv +208 -0
  47. data/lib/axi/AXI4/id_record.sv +55 -0
  48. data/lib/axi/AXI4/idata_pool_axi4.sv +110 -0
  49. data/lib/axi/AXI4/interconnect/AXI4_interconnect_M2S.sv +291 -0
  50. data/lib/axi/AXI4/interconnect/axi4_mix_interconnect_M2S.sv +72 -0
  51. data/lib/axi/AXI4/interconnect/axi4_rd_interconnect_M2S.sv +148 -0
  52. data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S.sv +255 -0
  53. data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S.sv.bak +255 -0
  54. data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S_A1.sv +286 -0
  55. data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S_A2.sv +281 -0
  56. data/lib/axi/AXI4/interconnect/axi4_wr_interconnect_M2S.sv +235 -0
  57. data/lib/axi/AXI4/interconnect/axi4_wr_interconnect_M2S_A1.sv +283 -0
  58. data/lib/axi/AXI4/interconnect/axi4_wr_mix_interconnect_M2S.sv +32 -0
  59. data/lib/axi/AXI4/long_axi4_to_wide_axi4.sv.bak +251 -0
  60. data/lib/axi/AXI4/odata_pool_axi4.sv +134 -0
  61. data/lib/axi/AXI4/odata_pool_axi4_A1.sv +165 -0
  62. data/lib/axi/AXI4/odata_pool_axi4_A2.sv +159 -0
  63. data/lib/axi/AXI4/odata_pool_axi4_A3.sv +183 -0
  64. data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo.sv +61 -0
  65. data/lib/axi/AXI4/packet_fifo/axi4_rd_packet_fifo.sv +282 -0
  66. data/lib/axi/AXI4/packet_fifo/axi4_wr_packet_fifo.sv +181 -0
  67. data/lib/axi/AXI4/packet_merge/axi4_merge.sv +60 -0
  68. data/lib/axi/AXI4/packet_merge/axi4_merge_rd.sv +279 -0
  69. data/lib/axi/AXI4/packet_merge/axi4_merge_wr.sv +267 -0
  70. data/lib/axi/AXI4/packet_partition/axi4_partition.sv +36 -0
  71. data/lib/axi/AXI4/packet_partition/axi4_partition_OD.sv +66 -0
  72. data/lib/axi/AXI4/packet_partition/axi4_partition_rd.sv +211 -0
  73. data/lib/axi/AXI4/packet_partition/axi4_partition_rd_OD.sv +322 -0
  74. data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.rb +80 -0
  75. data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +93 -0
  76. data/lib/axi/AXI4/packet_partition/axi4_partition_wr.sv +239 -0
  77. data/lib/axi/AXI4/packet_partition/axi4_partition_wr_OD.sv +302 -0
  78. data/lib/axi/AXI4/packet_partition/data_inf_partition.rb +293 -0
  79. data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +307 -0
  80. data/lib/axi/AXI4/vcs_axi4_array_comptable.sv +35 -0
  81. data/lib/axi/AXI4/vcs_axi4_comptable.sv +330 -0
  82. data/lib/axi/AXI4/wide_axis_to_axi4_wr.rb +149 -0
  83. data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +140 -0
  84. data/lib/axi/AXI4/width_convert/axi4_data_combin_aflag_pipe.sv +239 -0
  85. data/lib/axi/AXI4/width_convert/axi4_data_combin_aflag_pipe_A1.sv +204 -0
  86. data/lib/axi/AXI4/width_convert/axi4_data_convert.sv +312 -0
  87. data/lib/axi/AXI4/width_convert/axi4_data_convert_A1.sv +217 -0
  88. data/lib/axi/AXI4/width_convert/data_combin.sv +366 -0
  89. data/lib/axi/AXI4/width_convert/data_combin.sv.bak +290 -0
  90. data/lib/axi/AXI4/width_convert/data_destruct.sv +304 -0
  91. data/lib/axi/AXI4/width_convert/feed_check.sv +94 -0
  92. data/lib/axi/AXI4/width_convert/len_convert.sv.bak +61 -0
  93. data/lib/axi/AXI4/width_convert/odd_width_convert.sv +229 -0
  94. data/lib/axi/AXI4/width_convert/odd_width_convert_verb.sv +105 -0
  95. data/lib/axi/AXI4/width_convert/simple_data_pipe.sv +40 -0
  96. data/lib/axi/AXI4/width_convert/simple_data_pipe_slaver.sv +33 -0
  97. data/lib/axi/AXI4/width_convert/width_combin.sv +113 -0
  98. data/lib/axi/AXI4/width_convert/width_convert.sv +87 -0
  99. data/lib/axi/AXI4/width_convert/width_convert_verb.sv +249 -0
  100. data/lib/axi/AXI4/width_convert/width_destruct.sv +206 -0
  101. data/lib/axi/AXI4/width_convert/width_destruct_A1.sv +251 -0
  102. data/lib/axi/AXI_BFM/AXI_BFM_PKG.sv +1039 -0
  103. data/lib/axi/AXI_BFM/Data_C_BFM_PKG.sv +97 -0
  104. data/lib/axi/AXI_BFM/axi4_error_chk.sv +298 -0
  105. data/lib/axi/AXI_BFM/axi4_illegal_bfm_pkg.sv +607 -0
  106. data/lib/axi/AXI_BFM/axi_lite_master.sv +102 -0
  107. data/lib/axi/AXI_BFM/axi_lite_tb.sv +23 -0
  108. data/lib/axi/AXI_BFM/axi_master.sv +185 -0
  109. data/lib/axi/AXI_BFM/axi_mirror.sv +266 -0
  110. data/lib/axi/AXI_BFM/axi_mm_tb.sv +134 -0
  111. data/lib/axi/AXI_BFM/axi_slaver.sv.bak +340 -0
  112. data/lib/axi/AXI_BFM/axistreambfm.sv +117 -0
  113. data/lib/axi/AXI_Lite/axi4_to_lite.sv +36 -0
  114. data/lib/axi/AXI_Lite/axi_lite_configure.sv +356 -0
  115. data/lib/axi/AXI_Lite/axi_lite_configure_inf2.sv +365 -0
  116. data/lib/axi/AXI_Lite/axi_lite_configure_verb.sv.bck +370 -0
  117. data/lib/axi/AXI_Lite/axi_lite_interconnect_M2S.sv +437 -0
  118. data/lib/axi/AXI_Lite/axi_lite_interconnect_S2M.sv +359 -0
  119. data/lib/axi/AXI_Lite/axi_lite_interconnect_S2M.sv.bak +359 -0
  120. data/lib/axi/AXI_Lite/axi_lite_master_empty.sv +30 -0
  121. data/lib/axi/AXI_Lite/axi_lite_slaver_empty.sv +27 -0
  122. data/lib/axi/AXI_Lite/axil_direct.sv +52 -0
  123. data/lib/axi/AXI_Lite/common_configure_reg_interface/common_configure_reg_interface.sv +230 -0
  124. data/lib/axi/AXI_Lite/common_configure_reg_interface/common_configure_reg_interface.sv.bak +109 -0
  125. data/lib/axi/AXI_Lite/common_configure_reg_interface/jtag_to_axilite_wrapper.sv +56 -0
  126. data/lib/axi/AXI_Lite/gen_axi_lite_ctrl.sv +515 -0
  127. data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_C1.sv +369 -0
  128. data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_verb.sv +365 -0
  129. data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_verc.sv +401 -0
  130. data/lib/axi/AXI_Lite/wr_lite_to_axis.sv +141 -0
  131. data/lib/axi/AXI_Lite/wr_lite_to_axis.sv.bak +141 -0
  132. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S.sv +76 -0
  133. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_A1.sv +77 -0
  134. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_A2.sv +71 -0
  135. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_bind_tuser.sv +72 -0
  136. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_noaddr.sv +151 -0
  137. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_with_addr.sv +87 -0
  138. data/lib/axi/AXI_stream/axi_stream_interconnect_S2M.sv +65 -0
  139. data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_auto.sv +50 -0
  140. data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_with_info.sv +64 -0
  141. data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_with_keep.sv.bak +64 -0
  142. data/lib/axi/AXI_stream/axi_stream_packet_fifo_with_info.sv.bak +49 -0
  143. data/lib/axi/AXI_stream/axi_stream_partition.sv +147 -0
  144. data/lib/axi/AXI_stream/axi_stream_partition_A1.sv +63 -0
  145. data/lib/axi/AXI_stream/axi_stream_planer.sv +51 -0
  146. data/lib/axi/AXI_stream/axi_stream_split_channel.rb +56 -0
  147. data/lib/axi/AXI_stream/axi_stream_split_channel.sv +149 -0
  148. data/lib/axi/AXI_stream/axi_streams_combin.sv +151 -0
  149. data/lib/axi/AXI_stream/axi_streams_combin_A1.sv +179 -0
  150. data/lib/axi/AXI_stream/axi_streams_scaler.sv +171 -0
  151. data/lib/axi/AXI_stream/axi_streams_scaler_A1.sv +179 -0
  152. data/lib/axi/AXI_stream/axis_append.sv +79 -0
  153. data/lib/axi/AXI_stream/axis_append_A1.sv +82 -0
  154. data/lib/axi/AXI_stream/axis_base_pipe.sv +184 -0
  155. data/lib/axi/AXI_stream/axis_combin_with_fifo.sv +69 -0
  156. data/lib/axi/AXI_stream/axis_connect_pipe.sv +86 -0
  157. data/lib/axi/AXI_stream/axis_connect_pipe_A1.sv.bak +170 -0
  158. data/lib/axi/AXI_stream/axis_connect_pipe_left_shift.sv +64 -0
  159. data/lib/axi/AXI_stream/axis_connect_pipe_right_shift.sv +64 -0
  160. data/lib/axi/AXI_stream/axis_connect_pipe_right_shift_verb.sv +70 -0
  161. data/lib/axi/AXI_stream/axis_connect_pipe_with_info.sv +93 -0
  162. data/lib/axi/AXI_stream/axis_direct.sv +55 -0
  163. data/lib/axi/AXI_stream/axis_direct_A1.sv +81 -0
  164. data/lib/axi/AXI_stream/axis_filter.sv +38 -0
  165. data/lib/axi/AXI_stream/axis_full_to_data_c.sv +26 -0
  166. data/lib/axi/AXI_stream/axis_head_cut.sv +67 -0
  167. data/lib/axi/AXI_stream/axis_head_cut_verb.sv +60 -0
  168. data/lib/axi/AXI_stream/axis_head_cut_verc.rb +175 -0
  169. data/lib/axi/AXI_stream/axis_head_cut_verc.sv +245 -0
  170. data/lib/axi/AXI_stream/axis_inct_s2m_with_flag.sv +84 -0
  171. data/lib/axi/AXI_stream/axis_insert_copy.rb +59 -0
  172. data/lib/axi/AXI_stream/axis_insert_copy.sv +66 -0
  173. data/lib/axi/AXI_stream/axis_intc_M2S_with_addr_inf.sv +114 -0
  174. data/lib/axi/AXI_stream/axis_intc_S2M_with_addr_inf.sv +85 -0
  175. data/lib/axi/AXI_stream/axis_interconnect_S2M_pipe.sv +75 -0
  176. data/lib/axi/AXI_stream/axis_length_cut.sv +64 -0
  177. data/lib/axi/AXI_stream/axis_length_fill.sv +194 -0
  178. data/lib/axi/AXI_stream/axis_length_split.sv +86 -0
  179. data/lib/axi/AXI_stream/axis_length_split_with_addr.sv +127 -0
  180. data/lib/axi/AXI_stream/axis_length_split_writh_user.sv +87 -0
  181. data/lib/axi/AXI_stream/axis_link_trigger.sv +81 -0
  182. data/lib/axi/AXI_stream/axis_master_empty.sv +26 -0
  183. data/lib/axi/AXI_stream/axis_mirror_to_master.sv +126 -0
  184. data/lib/axi/AXI_stream/axis_mirrors.sv +60 -0
  185. data/lib/axi/AXI_stream/axis_orthogonal.sv +66 -0
  186. data/lib/axi/AXI_stream/axis_ram_buffer.sv +118 -0
  187. data/lib/axi/AXI_stream/axis_rom_contect.rb +97 -0
  188. data/lib/axi/AXI_stream/axis_rom_contect.sv +110 -0
  189. data/lib/axi/AXI_stream/axis_rom_contect_sim.rb +102 -0
  190. data/lib/axi/AXI_stream/axis_rom_contect_sim.sv +113 -0
  191. data/lib/axi/AXI_stream/axis_slaver_empty.sv +22 -0
  192. data/lib/axi/AXI_stream/axis_slaver_pipe.sv +84 -0
  193. data/lib/axi/AXI_stream/axis_slaver_pipe_A1.sv +54 -0
  194. data/lib/axi/AXI_stream/axis_slaver_vector_empty.sv +27 -0
  195. data/lib/axi/AXI_stream/axis_split_channel_verb.rb +42 -0
  196. data/lib/axi/AXI_stream/axis_split_channel_verb.sv +62 -0
  197. data/lib/axi/AXI_stream/axis_to_axi4_or_lite.rb +127 -0
  198. data/lib/axi/AXI_stream/axis_to_axi4_or_lite.sv +153 -0
  199. data/lib/axi/AXI_stream/axis_to_data_inf.sv +34 -0
  200. data/lib/axi/AXI_stream/axis_to_lite_rd.sv +81 -0
  201. data/lib/axi/AXI_stream/axis_to_lite_wr.sv +71 -0
  202. data/lib/axi/AXI_stream/axis_uncompress.sv +147 -0
  203. data/lib/axi/AXI_stream/axis_uncompress_A1.sv +150 -0
  204. data/lib/axi/AXI_stream/axis_uncompress_verb.rb +32 -0
  205. data/lib/axi/AXI_stream/axis_uncompress_verb.sv +54 -0
  206. data/lib/axi/AXI_stream/axis_valve.sv +29 -0
  207. data/lib/axi/AXI_stream/axis_valve_with_pipe.sv +76 -0
  208. data/lib/axi/AXI_stream/axis_vector_master_empty.rb +11 -0
  209. data/lib/axi/AXI_stream/axis_vector_master_empty.sv +35 -0
  210. data/lib/axi/AXI_stream/axis_vector_slaver_empty.rb +11 -0
  211. data/lib/axi/AXI_stream/axis_vector_slaver_empty.sv +35 -0
  212. data/lib/axi/AXI_stream/check_stream_crc.sv +28 -0
  213. data/lib/axi/AXI_stream/data_c_to_axis_full.sv +23 -0
  214. data/lib/axi/AXI_stream/data_to_axis_inf.sv +103 -0
  215. data/lib/axi/AXI_stream/data_to_axis_inf_A1.sv +28 -0
  216. data/lib/axi/AXI_stream/data_width/axis_width_combin.sv +204 -0
  217. data/lib/axi/AXI_stream/data_width/axis_width_combin_A1.sv +220 -0
  218. data/lib/axi/AXI_stream/data_width/axis_width_convert.sv +49 -0
  219. data/lib/axi/AXI_stream/data_width/axis_width_destruct.sv +82 -0
  220. data/lib/axi/AXI_stream/data_width/axis_width_destruct_A1.sv +86 -0
  221. data/lib/axi/AXI_stream/ex_status/axis_ex_status.sv +97 -0
  222. data/lib/axi/AXI_stream/gen_big_field_table.sv +170 -0
  223. data/lib/axi/AXI_stream/gen_common_frame_table.sv +382 -0
  224. data/lib/axi/AXI_stream/gen_common_frame_table_bind_tuser.sv +428 -0
  225. data/lib/axi/AXI_stream/gen_origin_axis.sv +116 -0
  226. data/lib/axi/AXI_stream/gen_origin_axis_A1.sv +129 -0
  227. data/lib/axi/AXI_stream/gen_origin_axis_A2.sv +162 -0
  228. data/lib/axi/AXI_stream/gen_simple_axis.sv +164 -0
  229. data/lib/axi/AXI_stream/packet_fifo/axi_stream_long_fifo.sv +132 -0
  230. data/lib/axi/AXI_stream/packet_fifo/axi_stream_long_fifo_verb.sv +140 -0
  231. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo.sv +125 -0
  232. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1.sv +142 -0
  233. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1E.sv +198 -0
  234. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_verb.sv +120 -0
  235. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_with_info.sv +49 -0
  236. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_long_fifo.sv +197 -0
  237. data/lib/axi/AXI_stream/packet_fifo/axi_stream_wide_fifo.sv +141 -0
  238. data/lib/axi/AXI_stream/packet_fifo/axis_pkt_fifo_filter_keep.sv +164 -0
  239. data/lib/axi/AXI_stream/packet_fifo/axis_pkt_fifo_filter_keep_A1.sv +166 -0
  240. data/lib/axi/AXI_stream/parse_big_field_table.sv +164 -0
  241. data/lib/axi/AXI_stream/parse_big_field_table_A1.sv +162 -0
  242. data/lib/axi/AXI_stream/parse_big_field_table_A2.sv +165 -0
  243. data/lib/axi/AXI_stream/parse_big_field_table_verb.sv +118 -0
  244. data/lib/axi/AXI_stream/parse_common_frame_table.sv +202 -0
  245. data/lib/axi/AXI_stream/parse_common_frame_table_A1.sv +521 -0
  246. data/lib/axi/AXI_stream/parse_common_frame_table_A2.sv +561 -0
  247. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache.sv +46 -0
  248. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_35bit.sv +122 -0
  249. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_36_71bit.sv +71 -0
  250. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_72_95bit.sv +96 -0
  251. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_72_95bit_with_keep.sv +99 -0
  252. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_96_143bit.sv +119 -0
  253. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_A1.sv +49 -0
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  255. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_mirror.sv +44 -0
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  257. data/lib/axi/AXI_stream/stream_cache/axi_stream_long_cache.sv +55 -0
  258. data/lib/axi/AXI_stream/stream_crc.sv +67 -0
  259. data/lib/axi/AXI_stream/vcs_axis_comptable.sv +73 -0
  260. data/lib/axi/LICENSE +504 -0
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  263. data/lib/axi/SIM/tb_axis_bfm_0504.sv +61 -0
  264. data/lib/axi/SIM/tb_axis_partitiom_0929.sv +102 -0
  265. data/lib/axi/SIM/tb_axis_s2m_pipe_1023.sv +163 -0
  266. data/lib/axi/SIM/tb_axis_to_axi4_0925.sv +107 -0
  267. data/lib/axi/SIM/tb_data_c_m2s_inf_20200114.sv +222 -0
  268. data/lib/axi/SIM/tb_data_c_m2s_inf_20201103.sv +245 -0
  269. data/lib/axi/SIM/tb_data_c_pipe_inf_20180417.sv +114 -0
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  275. data/lib/axi/axi4_to_xilinx_ddr_native/ddr3_ip_native_to_axi4.sv +194 -0
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  283. data/lib/axi/cfg.yml +15 -0
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  285. data/lib/axi/common/common_ram_sim_wrapper.rb +66 -0
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  287. data/lib/axi/common/common_ram_wrapper.rb +71 -0
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  289. data/lib/axi/common/data_c_interface_dram.rb +90 -0
  290. data/lib/axi/common/data_c_interface_dram.sv +106 -0
  291. data/lib/axi/common/mem_format.coe +60 -0
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  311. data/lib/axi/data_interface/data_inf_c/data_c_pipe_force_vld_bind_data.sv +81 -0
  312. data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf.sv +130 -0
  313. data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf_A1.sv +135 -0
  314. data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf_left_shift.sv +158 -0
  315. data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf_right_shift.sv +155 -0
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  319. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_best_last.sv +319 -0
  320. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_best_robin.sv +293 -0
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  322. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_robin_with_id.sv +46 -0
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  324. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_verc_with_addr.sv +226 -0
  325. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_verc_with_id.sv +54 -0
  326. data/lib/axi/data_interface/data_inf_c/data_c_pipe_latency.sv +68 -0
  327. data/lib/axi/data_interface/data_inf_c/data_c_scaler.sv +326 -0
  328. data/lib/axi/data_interface/data_inf_c/data_c_scaler_A1.sv +333 -0
  329. data/lib/axi/data_interface/data_inf_c/data_c_tmp_cache.sv +44 -0
  330. data/lib/axi/data_interface/data_inf_c/data_condition_mirror.sv +64 -0
  331. data/lib/axi/data_interface/data_inf_c/data_condition_valve.sv +53 -0
  332. data/lib/axi/data_interface/data_inf_c/data_connect_pipe_inf.sv +73 -0
  333. data/lib/axi/data_interface/data_inf_c/data_inf_c_M2S_with_addr_and_id.sv +66 -0
  334. data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_M2S_with_id.sv +67 -0
  335. data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_S2M.sv +70 -0
  336. data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_S2M_A1.sv +72 -0
  337. data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_S2M_with_lazy.sv +49 -0
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  339. data/lib/axi/data_interface/data_inf_c/data_inf_c_pipe_condition.sv +33 -0
  340. data/lib/axi/data_interface/data_inf_c/data_inf_c_planer.sv +50 -0
  341. data/lib/axi/data_interface/data_inf_c/data_inf_c_planer_A1.sv +53 -0
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  347. data/lib/axi/data_interface/data_inf_c/next_prio.sv +42 -0
  348. data/lib/axi/data_interface/data_inf_c/trigger_data_inf_c.sv +51 -0
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  354. data/lib/axi/data_interface/data_inf_intc_M2S_prio.sv +152 -0
  355. data/lib/axi/data_interface/data_inf_intc_M2S_prio_with_id.sv +55 -0
  356. data/lib/axi/data_interface/data_inf_interconnect_M2S_noaddr.sv +136 -0
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  358. data/lib/axi/data_interface/data_inf_planer.sv +59 -0
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  382. data/lib/axi/data_interface/datainf_slaver_empty.sv +22 -0
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  384. data/lib/axi/interface_define/axi_aux_inf.sv +206 -0
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  423. data/lib/axi/platform_ip/fifo_73_96bit.sv +102 -0
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  468. data/lib/axi/top/tb_data_intc_S2M_0807.sv +168 -0
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  482. data/lib/tdl/Logic/logic_operator.rb.bak +128 -0
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  486. data/lib/tdl/ReadMe.md +295 -0
  487. data/lib/tdl/SDL/axi4/AXI4_interconnect_M2S_sdl.rb +10 -0
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  498. data/lib/tdl/SDL/axi4/axi4_long_to_axi4_wide_A1_sdl.rb +10 -0
  499. data/lib/tdl/SDL/axi4/axi4_long_to_axi4_wide_sdl.rb +9 -0
  500. data/lib/tdl/SDL/axi4/axi4_long_to_axi4_wide_track_sdl.rb +9 -0
  501. data/lib/tdl/SDL/axi4/axi4_long_to_axi4_wide_verb_sdl.rb +11 -0
  502. data/lib/tdl/SDL/axi4/axi4_merge_rd_sdl.rb +10 -0
  503. data/lib/tdl/SDL/axi4/axi4_merge_sdl.rb +10 -0
  504. data/lib/tdl/SDL/axi4/axi4_merge_wr_sdl.rb +10 -0
  505. data/lib/tdl/SDL/axi4/axi4_mix_interconnect_M2S_sdl.rb +10 -0
  506. data/lib/tdl/SDL/axi4/axi4_packet_fifo_sdl.rb +12 -0
  507. data/lib/tdl/SDL/axi4/axi4_partition_OD_sdl.rb +11 -0
  508. data/lib/tdl/SDL/axi4/axi4_partition_rd_OD_sdl.rb +10 -0
  509. data/lib/tdl/SDL/axi4/axi4_partition_rd_sdl.rb +11 -0
  510. data/lib/tdl/SDL/axi4/axi4_partition_sdl.rb +11 -0
  511. data/lib/tdl/SDL/axi4/axi4_partition_wr_OD_sdl.rb +10 -0
  512. data/lib/tdl/SDL/axi4/axi4_partition_wr_sdl.rb +11 -0
  513. data/lib/tdl/SDL/axi4/axi4_pipe_sdl.rb +9 -0
  514. data/lib/tdl/SDL/axi4/axi4_pipe_verb_sdl.rb +9 -0
  515. data/lib/tdl/SDL/axi4/axi4_rd_auxiliary_batch_gen_sdl.rb +11 -0
  516. data/lib/tdl/SDL/axi4/axi4_rd_auxiliary_gen_A1_sdl.rb +9 -0
  517. data/lib/tdl/SDL/axi4/axi4_rd_auxiliary_gen_sdl.rb +9 -0
  518. data/lib/tdl/SDL/axi4/axi4_rd_burst_track_sdl.rb +10 -0
  519. data/lib/tdl/SDL/axi4/axi4_rd_interconnect_M2S_sdl.rb +10 -0
  520. data/lib/tdl/SDL/axi4/axi4_rd_mix_interconnect_M2S_A1_sdl.rb +10 -0
  521. data/lib/tdl/SDL/axi4/axi4_rd_mix_interconnect_M2S_A2_sdl.rb +10 -0
  522. data/lib/tdl/SDL/axi4/axi4_rd_mix_interconnect_M2S_sdl.rb +10 -0
  523. data/lib/tdl/SDL/axi4/axi4_rd_packet_fifo_sdl.rb +11 -0
  524. data/lib/tdl/SDL/axi4/axi4_rd_pipe_sdl.rb +9 -0
  525. data/lib/tdl/SDL/axi4/axi4_rd_pipe_verb_sdl.rb +9 -0
  526. data/lib/tdl/SDL/axi4/axi4_wr_aux_bind_data_sdl.rb +9 -0
  527. data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_batch_gen_sdl.rb +11 -0
  528. data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_gen_sdl.rb +10 -0
  529. data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_gen_without_resp_sdl.rb +10 -0
  530. data/lib/tdl/SDL/axi4/axi4_wr_burst_track_sdl.rb +10 -0
  531. data/lib/tdl/SDL/axi4/axi4_wr_interconnect_M2S_A1_sdl.rb +10 -0
  532. data/lib/tdl/SDL/axi4/axi4_wr_interconnect_M2S_sdl.rb +10 -0
  533. data/lib/tdl/SDL/axi4/axi4_wr_mix_interconnect_M2S_sdl.rb +10 -0
  534. data/lib/tdl/SDL/axi4/axi4_wr_packet_fifo_sdl.rb +11 -0
  535. data/lib/tdl/SDL/axi4/axi4_wr_pipe_sdl.rb +9 -0
  536. data/lib/tdl/SDL/axi4/axi4_wr_pipe_verb_sdl.rb +9 -0
  537. data/lib/tdl/SDL/axi4/axi_stream_add_addr_len_sdl.rb +11 -0
  538. data/lib/tdl/SDL/axi4/axi_stream_to_axi4_wr_sdl.rb +9 -0
  539. data/lib/tdl/SDL/axi4/data_combin_sdl.rb +20 -0
  540. data/lib/tdl/SDL/axi4/data_destruct_sdl.rb +19 -0
  541. data/lib/tdl/SDL/axi4/feed_check_sdl.rb +18 -0
  542. data/lib/tdl/SDL/axi4/full_axi4_to_axis_partition_wr_rd_sdl.rb +11 -0
  543. data/lib/tdl/SDL/axi4/full_axi4_to_axis_sdl.rb +10 -0
  544. data/lib/tdl/SDL/axi4/id_record_sdl.rb +19 -0
  545. data/lib/tdl/SDL/axi4/idata_pool_axi4_sdl.rb +18 -0
  546. data/lib/tdl/SDL/axi4/odata_pool_axi4_A1_sdl.rb +13 -0
  547. data/lib/tdl/SDL/axi4/odata_pool_axi4_A2_sdl.rb +10 -0
  548. data/lib/tdl/SDL/axi4/odata_pool_axi4_sdl.rb +19 -0
  549. data/lib/tdl/SDL/axi4/odd_width_convert_sdl.rb +19 -0
  550. data/lib/tdl/SDL/axi4/odd_width_convert_verb_sdl.rb +19 -0
  551. data/lib/tdl/SDL/axi4/simple_data_pipe_sdl.rb +16 -0
  552. data/lib/tdl/SDL/axi4/simple_data_pipe_slaver_sdl.rb +16 -0
  553. data/lib/tdl/SDL/axi4/vcs_axi4_array_comptable.rb +9 -0
  554. data/lib/tdl/SDL/axi4/vcs_axi4_array_comptable_sdl.rb +10 -0
  555. data/lib/tdl/SDL/axi4/vcs_axi4_comptable.rb +8 -0
  556. data/lib/tdl/SDL/axi4/vcs_axi4_comptable_sdl.rb +9 -0
  557. data/lib/tdl/SDL/axi4/width_combin_sdl.rb +20 -0
  558. data/lib/tdl/SDL/axi4/width_convert_sdl.rb +20 -0
  559. data/lib/tdl/SDL/axi4/width_convert_verb_sdl.rb +20 -0
  560. data/lib/tdl/SDL/axi4/width_destruct_A1_sdl.rb +22 -0
  561. data/lib/tdl/SDL/axi4/width_destruct_sdl.rb +19 -0
  562. data/lib/tdl/SDL/axistream/axi_stream_cache_35bit_sdl.rb +9 -0
  563. data/lib/tdl/SDL/axistream/axi_stream_cache_36_71bit_sdl.rb +9 -0
  564. data/lib/tdl/SDL/axistream/axi_stream_cache_72_95bit_sdl.rb +9 -0
  565. data/lib/tdl/SDL/axistream/axi_stream_cache_72_95bit_with_keep_sdl.rb +9 -0
  566. data/lib/tdl/SDL/axistream/axi_stream_cache_96_143bit_sdl.rb +9 -0
  567. data/lib/tdl/SDL/axistream/axi_stream_cache_B1_sdl.rb +9 -0
  568. data/lib/tdl/SDL/axistream/axi_stream_cache_mirror_sdl.rb +9 -0
  569. data/lib/tdl/SDL/axistream/axi_stream_cache_sdl.rb +9 -0
  570. data/lib/tdl/SDL/axistream/axi_stream_cache_verb_sdl.rb +9 -0
  571. data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_A1_sdl.rb +11 -0
  572. data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_A2_sdl.rb +13 -0
  573. data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_bind_tuser_sdl.rb +11 -0
  574. data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_noaddr_sdl.rb +11 -0
  575. data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_sdl.rb +12 -0
  576. data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_with_addr_sdl.rb +12 -0
  577. data/lib/tdl/SDL/axistream/axi_stream_interconnect_S2M_auto_sdl.rb +11 -0
  578. data/lib/tdl/SDL/axistream/axi_stream_interconnect_S2M_sdl.rb +12 -0
  579. data/lib/tdl/SDL/axistream/axi_stream_long_cache_sdl.rb +10 -0
  580. data/lib/tdl/SDL/axistream/axi_stream_long_fifo_sdl.rb +11 -0
  581. data/lib/tdl/SDL/axistream/axi_stream_long_fifo_verb_sdl.rb +11 -0
  582. data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_B1E_sdl.rb +16 -0
  583. data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_B1_sdl.rb +14 -0
  584. data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_sdl.rb +10 -0
  585. data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_verb_sdl.rb +13 -0
  586. data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_with_info_sdl.rb +13 -0
  587. data/lib/tdl/SDL/axistream/axi_stream_packet_long_fifo_sdl.rb +11 -0
  588. data/lib/tdl/SDL/axistream/axi_stream_partition_A1_sdl.rb +11 -0
  589. data/lib/tdl/SDL/axistream/axi_stream_partition_sdl.rb +12 -0
  590. data/lib/tdl/SDL/axistream/axi_stream_wide_fifo_sdl.rb +10 -0
  591. data/lib/tdl/SDL/axistream/axi_streams_combin_A1_sdl.rb +15 -0
  592. data/lib/tdl/SDL/axistream/axi_streams_combin_sdl.rb +16 -0
  593. data/lib/tdl/SDL/axistream/axi_streams_scaler_A1_sdl.rb +14 -0
  594. data/lib/tdl/SDL/axistream/axi_streams_scaler_sdl.rb +15 -0
  595. data/lib/tdl/SDL/axistream/axis_append_A1_sdl.rb +18 -0
  596. data/lib/tdl/SDL/axistream/axis_append_sdl.rb +17 -0
  597. data/lib/tdl/SDL/axistream/axis_base_pipe_sdl.rb +10 -0
  598. data/lib/tdl/SDL/axistream/axis_combin_with_fifo_sdl.rb +14 -0
  599. data/lib/tdl/SDL/axistream/axis_connect_pipe_right_shift_sdl.rb +10 -0
  600. data/lib/tdl/SDL/axistream/axis_connect_pipe_sdl.rb +9 -0
  601. data/lib/tdl/SDL/axistream/axis_connect_pipe_with_info_sdl.rb +12 -0
  602. data/lib/tdl/SDL/axistream/axis_direct_A1_sdl.rb +11 -0
  603. data/lib/tdl/SDL/axistream/axis_direct_sdl.rb +9 -0
  604. data/lib/tdl/SDL/axistream/axis_ex_status_sdl.rb +12 -0
  605. data/lib/tdl/SDL/axistream/axis_filter_sdl.rb +10 -0
  606. data/lib/tdl/SDL/axistream/axis_full_to_data_c_sdl.rb +9 -0
  607. data/lib/tdl/SDL/axistream/axis_head_cut_sdl.rb +10 -0
  608. data/lib/tdl/SDL/axistream/axis_inct_s2m_with_flag_sdl.rb +11 -0
  609. data/lib/tdl/SDL/axistream/axis_intc_M2S_with_addr_inf_sdl.rb +11 -0
  610. data/lib/tdl/SDL/axistream/axis_intc_S2M_with_addr_inf_sdl.rb +12 -0
  611. data/lib/tdl/SDL/axistream/axis_interconnect_S2M_pipe_sdl.rb +15 -0
  612. data/lib/tdl/SDL/axistream/axis_length_cut_sdl.rb +10 -0
  613. data/lib/tdl/SDL/axistream/axis_length_fill_sdl.rb +10 -0
  614. data/lib/tdl/SDL/axistream/axis_length_split_sdl.rb +10 -0
  615. data/lib/tdl/SDL/axistream/axis_length_split_with_addr_sdl.rb +13 -0
  616. data/lib/tdl/SDL/axistream/axis_length_split_writh_user_sdl.rb +10 -0
  617. data/lib/tdl/SDL/axistream/axis_link_trigger_sdl.rb +12 -0
  618. data/lib/tdl/SDL/axistream/axis_master_empty_sdl.rb +8 -0
  619. data/lib/tdl/SDL/axistream/axis_mirror_to_master_sdl.rb +10 -0
  620. data/lib/tdl/SDL/axistream/axis_mirrors_sdl.rb +14 -0
  621. data/lib/tdl/SDL/axistream/axis_orthogonal_sdl.rb +10 -0
  622. data/lib/tdl/SDL/axistream/axis_pkt_fifo_filter_keep_A1_sdl.rb +10 -0
  623. data/lib/tdl/SDL/axistream/axis_pkt_fifo_filter_keep_sdl.rb +10 -0
  624. data/lib/tdl/SDL/axistream/axis_ram_buffer_sdl.rb +13 -0
  625. data/lib/tdl/SDL/axistream/axis_slaver_empty_sdl.rb +8 -0
  626. data/lib/tdl/SDL/axistream/axis_slaver_pipe_A1_sdl.rb +10 -0
  627. data/lib/tdl/SDL/axistream/axis_slaver_pipe_sdl.rb +9 -0
  628. data/lib/tdl/SDL/axistream/axis_slaver_vector_empty_sdl.rb +9 -0
  629. data/lib/tdl/SDL/axistream/axis_to_data_inf_sdl.rb +10 -0
  630. data/lib/tdl/SDL/axistream/axis_to_lite_rd_sdl.rb +11 -0
  631. data/lib/tdl/SDL/axistream/axis_to_lite_wr_sdl.rb +10 -0
  632. data/lib/tdl/SDL/axistream/axis_uncompress_A1_sdl.rb +12 -0
  633. data/lib/tdl/SDL/axistream/axis_uncompress_sdl.rb +11 -0
  634. data/lib/tdl/SDL/axistream/axis_valve_sdl.rb +10 -0
  635. data/lib/tdl/SDL/axistream/axis_valve_with_pipe_sdl.rb +11 -0
  636. data/lib/tdl/SDL/axistream/axis_width_combin_A1_sdl.rb +9 -0
  637. data/lib/tdl/SDL/axistream/axis_width_combin_sdl.rb +9 -0
  638. data/lib/tdl/SDL/axistream/axis_width_convert_sdl.rb +9 -0
  639. data/lib/tdl/SDL/axistream/axis_width_destruct_A1_sdl.rb +9 -0
  640. data/lib/tdl/SDL/axistream/axis_width_destruct_sdl.rb +9 -0
  641. data/lib/tdl/SDL/axistream/check_stream_crc_sdl.rb +8 -0
  642. data/lib/tdl/SDL/axistream/data_c_to_axis_full_sdl.rb +9 -0
  643. data/lib/tdl/SDL/axistream/data_to_axis_inf_A1_sdl.rb +10 -0
  644. data/lib/tdl/SDL/axistream/data_to_axis_inf_sdl.rb +11 -0
  645. data/lib/tdl/SDL/axistream/gen_big_field_table_sdl.rb +14 -0
  646. data/lib/tdl/SDL/axistream/gen_common_frame_table_sdl.rb +60 -0
  647. data/lib/tdl/SDL/axistream/gen_origin_axis_A1_sdl.rb +13 -0
  648. data/lib/tdl/SDL/axistream/gen_origin_axis_sdl.rb +12 -0
  649. data/lib/tdl/SDL/axistream/gen_simple_axis_sdl.rb +13 -0
  650. data/lib/tdl/SDL/axistream/parse_big_field_table_A1_sdl.rb +17 -0
  651. data/lib/tdl/SDL/axistream/parse_big_field_table_A2_sdl.rb +17 -0
  652. data/lib/tdl/SDL/axistream/parse_big_field_table_sdl.rb +17 -0
  653. data/lib/tdl/SDL/axistream/stream_crc_sdl.rb +9 -0
  654. data/lib/tdl/SDL/axistream/vcs_axis_comptable.rb +16 -0
  655. data/lib/tdl/SDL/axistream/vcs_axis_comptable_sdl.rb +9 -0
  656. data/lib/tdl/SDL/data_inf_c/data_bind_sdl.rb +10 -0
  657. data/lib/tdl/SDL/data_inf_c/data_c_cache_sdl.rb +9 -0
  658. data/lib/tdl/SDL/data_inf_c/data_c_direct_mirror_sdl.rb +9 -0
  659. data/lib/tdl/SDL/data_inf_c/data_c_direct_sdl.rb +9 -0
  660. data/lib/tdl/SDL/data_inf_c/data_c_intc_M2S_force_robin_sdl.rb +10 -0
  661. data/lib/tdl/SDL/data_inf_c/data_c_pipe_force_vld_bind_data_sdl.rb +13 -0
  662. data/lib/tdl/SDL/data_inf_c/data_c_pipe_force_vld_sdl.rb +9 -0
  663. data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_A1_sdl.rb +10 -0
  664. data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_right_shift_sdl.rb +13 -0
  665. data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_sdl.rb +9 -0
  666. data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_C1_sdl.rb +14 -0
  667. data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_C1_with_id_sdl.rb +16 -0
  668. data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_sdl.rb +13 -0
  669. data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_with_addr_sdl.rb +13 -0
  670. data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_with_id_sdl.rb +15 -0
  671. data/lib/tdl/SDL/data_inf_c/data_c_pipe_latency_sdl.rb +10 -0
  672. data/lib/tdl/SDL/data_inf_c/data_c_scaler_A1_sdl.rb +16 -0
  673. data/lib/tdl/SDL/data_inf_c/data_c_scaler_sdl.rb +15 -0
  674. data/lib/tdl/SDL/data_inf_c/data_c_tmp_cache_sdl.rb +9 -0
  675. data/lib/tdl/SDL/data_inf_c/data_condition_mirror_sdl.rb +13 -0
  676. data/lib/tdl/SDL/data_inf_c/data_condition_valve_sdl.rb +13 -0
  677. data/lib/tdl/SDL/data_inf_c/data_connect_pipe_inf_sdl.rb +9 -0
  678. data/lib/tdl/SDL/data_inf_c/data_connect_pipe_sdl.rb +17 -0
  679. data/lib/tdl/SDL/data_inf_c/data_inf_A2B_sdl.rb +9 -0
  680. data/lib/tdl/SDL/data_inf_c/data_inf_B2A_sdl.rb +9 -0
  681. data/lib/tdl/SDL/data_inf_c/data_inf_c_M2S_with_addr_and_id_sdl.rb +17 -0
  682. data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_M2S_with_id_sdl.rb +15 -0
  683. data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_A1_sdl.rb +13 -0
  684. data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_sdl.rb +12 -0
  685. data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_with_lazy_sdl.rb +15 -0
  686. data/lib/tdl/SDL/data_inf_c/data_inf_c_interconnect_M2S_sdl.rb +12 -0
  687. data/lib/tdl/SDL/data_inf_c/data_inf_c_pipe_condition_sdl.rb +10 -0
  688. data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_A1.rb +12 -0
  689. data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_A1_sdl.rb +14 -0
  690. data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_sdl.rb +13 -0
  691. data/lib/tdl/SDL/data_inf_c/data_inf_cross_clk_sdl.rb +9 -0
  692. data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_force_addr_with_id_sdl.rb +19 -0
  693. data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_prio_sdl.rb +14 -0
  694. data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_prio_with_id_sdl.rb +17 -0
  695. data/lib/tdl/SDL/data_inf_c/data_inf_interconnect_M2S_noaddr_sdl.rb +14 -0
  696. data/lib/tdl/SDL/data_inf_c/data_inf_interconnect_M2S_with_id_noaddr_sdl.rb +17 -0
  697. data/lib/tdl/SDL/data_inf_c/data_inf_planer_A1_sdl.rb +15 -0
  698. data/lib/tdl/SDL/data_inf_c/data_inf_planer_sdl.rb +14 -0
  699. data/lib/tdl/SDL/data_inf_c/data_inf_ticktock_sdl.rb +18 -0
  700. data/lib/tdl/SDL/data_inf_c/data_intc_M2S_force_robin_sdl.rb +10 -0
  701. data/lib/tdl/SDL/data_inf_c/data_mirrors_sdl.rb +14 -0
  702. data/lib/tdl/SDL/data_inf_c/data_pair_map_A1_sdl.rb +16 -0
  703. data/lib/tdl/SDL/data_inf_c/data_pair_map_A2_sdl.rb +19 -0
  704. data/lib/tdl/SDL/data_inf_c/data_pair_map_sdl.rb +14 -0
  705. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_A1_sdl.rb +19 -0
  706. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_sdl.rb +17 -0
  707. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_verb_sdl.rb +16 -0
  708. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_A1_sdl.rb +19 -0
  709. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_sdl.rb +16 -0
  710. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_verb_sdl.rb +15 -0
  711. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_sdl.rb +23 -0
  712. data/lib/tdl/SDL/data_inf_c/data_streams_combin_A1_sdl.rb +20 -0
  713. data/lib/tdl/SDL/data_inf_c/data_streams_combin_sdl.rb +20 -0
  714. data/lib/tdl/SDL/data_inf_c/data_streams_scaler_sdl.rb +19 -0
  715. data/lib/tdl/SDL/data_inf_c/data_uncompress_sdl.rb +11 -0
  716. data/lib/tdl/SDL/data_inf_c/data_valve_sdl.rb +10 -0
  717. data/lib/tdl/SDL/data_inf_c/datainf_c_master_empty_sdl.rb +8 -0
  718. data/lib/tdl/SDL/data_inf_c/datainf_c_slaver_empty_sdl.rb +8 -0
  719. data/lib/tdl/SDL/data_inf_c/datainf_master_empty_sdl.rb +8 -0
  720. data/lib/tdl/SDL/data_inf_c/datainf_slaver_empty_sdl.rb +8 -0
  721. data/lib/tdl/SDL/data_inf_c/latency_sdl.rb +8 -0
  722. data/lib/tdl/SDL/data_inf_c/next_prio_sdl.rb +12 -0
  723. data/lib/tdl/SDL/data_inf_c/part_data_pair_map_sdl.rb +19 -0
  724. data/lib/tdl/SDL/data_inf_c/trigger_data_inf_c_A1_sdl.rb +11 -0
  725. data/lib/tdl/SDL/data_inf_c/trigger_data_inf_c_sdl.rb +11 -0
  726. data/lib/tdl/SDL/data_inf_c/trigger_ready_ctrl_sdl.rb +12 -0
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  967. data/lib/tdl/class_hdl/hdl_module_def.rb +447 -0
  968. data/lib/tdl/class_hdl/hdl_package.rb +150 -0
  969. data/lib/tdl/class_hdl/hdl_parameter.rb +73 -0
  970. data/lib/tdl/class_hdl/hdl_random.rb +31 -0
  971. data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +653 -0
  972. data/lib/tdl/class_hdl/hdl_struct.rb +209 -0
  973. data/lib/tdl/class_hdl/hdl_verify.rb +136 -0
  974. data/lib/tdl/data_inf/_data_mirrors.rb +92 -0
  975. data/lib/tdl/data_inf/bak/_data_mirrors.rb +273 -0
  976. data/lib/tdl/data_inf/bak/common_fifo_auto.rb +279 -0
  977. data/lib/tdl/data_inf/bak/data_bind_auto.rb +128 -0
  978. data/lib/tdl/data_inf/bak/data_c_direct_auto.rb +138 -0
  979. data/lib/tdl/data_inf/bak/data_c_direct_mirror_auto.rb +138 -0
  980. data/lib/tdl/data_inf/bak/data_c_tmp_cache_auto.rb +138 -0
  981. data/lib/tdl/data_inf/bak/data_condition_mirror_auto.rb +216 -0
  982. data/lib/tdl/data_inf/bak/data_condition_valve_auto.rb +215 -0
  983. data/lib/tdl/data_inf/bak/data_connect_pipe.rb +80 -0
  984. data/lib/tdl/data_inf/bak/data_connect_pipe_inf_auto.rb +138 -0
  985. data/lib/tdl/data_inf/bak/data_inf_c_interconnect.rb +86 -0
  986. data/lib/tdl/data_inf/bak/data_inf_c_pipe_condition_auto.rb +157 -0
  987. data/lib/tdl/data_inf/bak/data_inf_cross_clk.rb +60 -0
  988. data/lib/tdl/data_inf/bak/data_inf_interconnect.rb +144 -0
  989. data/lib/tdl/data_inf/bak/data_inf_planer.rb +78 -0
  990. data/lib/tdl/data_inf/bak/data_inf_ticktack.rb +80 -0
  991. data/lib/tdl/data_inf/bak/data_inf_ticktock_auto.rb +0 -0
  992. data/lib/tdl/data_inf/bak/data_mirrors_auto.rb +234 -0
  993. data/lib/tdl/data_inf/bak/data_mirrors_verb.sv_auto.rb +234 -0
  994. data/lib/tdl/data_inf/bak/data_uncompress_auto.rb +177 -0
  995. data/lib/tdl/data_inf/bak/data_valve_auto.rb +127 -0
  996. data/lib/tdl/data_inf/bak/datainf_c_master_empty_auto.rb +95 -0
  997. data/lib/tdl/data_inf/bak/datainf_c_slaver_empty_auto.rb +88 -0
  998. data/lib/tdl/data_inf/bak/datainf_master_empty_auto.rb +95 -0
  999. data/lib/tdl/data_inf/bak/datainf_slaver_empty_auto.rb +88 -0
  1000. data/lib/tdl/data_inf/bak/independent_clock_fifo_auto.rb +298 -0
  1001. data/lib/tdl/data_inf/bak/part_data_pair_map_auto.rb +306 -0
  1002. data/lib/tdl/data_inf/common_fifo_auto.rb +141 -0
  1003. data/lib/tdl/data_inf/data_bind_auto.rb +79 -0
  1004. data/lib/tdl/data_inf/data_c_cache_auto.rb +135 -0
  1005. data/lib/tdl/data_inf/data_c_direct_auto.rb +127 -0
  1006. data/lib/tdl/data_inf/data_c_direct_mirror_auto.rb +127 -0
  1007. data/lib/tdl/data_inf/data_c_interconnect.rb +97 -0
  1008. data/lib/tdl/data_inf/data_c_pipe_force_vld_auto.rb +127 -0
  1009. data/lib/tdl/data_inf/data_c_pipe_inf_auto.rb +127 -0
  1010. data/lib/tdl/data_inf/data_c_pipe_intc_M2S_verc_auto.rb +123 -0
  1011. data/lib/tdl/data_inf/data_c_tmp_cache_auto.rb +127 -0
  1012. data/lib/tdl/data_inf/data_condition_mirror_auto.rb +165 -0
  1013. data/lib/tdl/data_inf/data_condition_valve_auto.rb +164 -0
  1014. data/lib/tdl/data_inf/data_connect_pipe_inf_auto.rb +127 -0
  1015. data/lib/tdl/data_inf/data_inf_c_pipe_condition_auto.rb +136 -0
  1016. data/lib/tdl/data_inf/data_mirrors_auto.rb +173 -0
  1017. data/lib/tdl/data_inf/data_mirrors_verb.sv_auto.rb +173 -0
  1018. data/lib/tdl/data_inf/data_uncompress_auto.rb +146 -0
  1019. data/lib/tdl/data_inf/data_valve_auto.rb +104 -0
  1020. data/lib/tdl/data_inf/datainf_c_master_empty_auto.rb +85 -0
  1021. data/lib/tdl/data_inf/datainf_c_slaver_empty_auto.rb +68 -0
  1022. data/lib/tdl/data_inf/datainf_master_empty_auto.rb +85 -0
  1023. data/lib/tdl/data_inf/datainf_slaver_empty_auto.rb +68 -0
  1024. data/lib/tdl/data_inf/independent_clock_fifo_auto.rb +141 -0
  1025. data/lib/tdl/data_inf/part_data_pair_map_auto.rb +149 -0
  1026. data/lib/tdl/data_inf/path_lib.rb +18 -0
  1027. data/lib/tdl/elements/Reset.rb +153 -0
  1028. data/lib/tdl/elements/axi4.rb +642 -0
  1029. data/lib/tdl/elements/axi_lite.rb +246 -0
  1030. data/lib/tdl/elements/axi_stream.rb +674 -0
  1031. data/lib/tdl/elements/clock.rb +193 -0
  1032. data/lib/tdl/elements/common_configure_reg.rb +135 -0
  1033. data/lib/tdl/elements/data_inf.rb +660 -0
  1034. data/lib/tdl/elements/logic.rb +356 -0
  1035. data/lib/tdl/elements/mail_box.rb +64 -0
  1036. data/lib/tdl/elements/originclass.rb +689 -0
  1037. data/lib/tdl/elements/parameter.rb +318 -0
  1038. data/lib/tdl/elements/track_inf.rb +163 -0
  1039. data/lib/tdl/elements/videoinf.rb +224 -0
  1040. data/lib/tdl/examples/10_random/exp_random.rb +13 -0
  1041. data/lib/tdl/examples/10_random/exp_random.sv +36 -0
  1042. data/lib/tdl/examples/11_test_unit/dve.tcl +64 -0
  1043. data/lib/tdl/examples/11_test_unit/exp_test_unit.rb +58 -0
  1044. data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +35 -0
  1045. data/lib/tdl/examples/11_test_unit/exp_test_unit_constraints.xdc +25 -0
  1046. data/lib/tdl/examples/11_test_unit/modules/sub_md0.rb +23 -0
  1047. data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +41 -0
  1048. data/lib/tdl/examples/11_test_unit/modules/sub_md1.rb +25 -0
  1049. data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv +41 -0
  1050. data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +28 -0
  1051. data/lib/tdl/examples/11_test_unit/tu0.sv +38 -0
  1052. data/lib/tdl/examples/11_test_unit/tu1.sv +28 -0
  1053. data/lib/tdl/examples/1_define_module/example1.rb +39 -0
  1054. data/lib/tdl/examples/1_define_module/exmple_md.sv +50 -0
  1055. data/lib/tdl/examples/2_hdl_class/always_comb.rb +99 -0
  1056. data/lib/tdl/examples/2_hdl_class/always_ff.rb +143 -0
  1057. data/lib/tdl/examples/2_hdl_class/case.rb +93 -0
  1058. data/lib/tdl/examples/2_hdl_class/foreach.rb +21 -0
  1059. data/lib/tdl/examples/2_hdl_class/function.rb +34 -0
  1060. data/lib/tdl/examples/2_hdl_class/generate.rb +62 -0
  1061. data/lib/tdl/examples/2_hdl_class/module_def.rb +33 -0
  1062. data/lib/tdl/examples/2_hdl_class/module_head_import_package.rb +36 -0
  1063. data/lib/tdl/examples/2_hdl_class/module_instance_test.rb +13 -0
  1064. data/lib/tdl/examples/2_hdl_class/package.rb +29 -0
  1065. data/lib/tdl/examples/2_hdl_class/package2.rb +21 -0
  1066. data/lib/tdl/examples/2_hdl_class/simple_assign.rb +39 -0
  1067. data/lib/tdl/examples/2_hdl_class/state_case.rb +65 -0
  1068. data/lib/tdl/examples/2_hdl_class/struct.rb +25 -0
  1069. data/lib/tdl/examples/2_hdl_class/struct_function.rb +28 -0
  1070. data/lib/tdl/examples/2_hdl_class/test_axi4_M2S.rb +16 -0
  1071. data/lib/tdl/examples/2_hdl_class/test_initial_assert.rb +11 -0
  1072. data/lib/tdl/examples/2_hdl_class/test_inst_sugar.rb +28 -0
  1073. data/lib/tdl/examples/2_hdl_class/test_module_port.rb +47 -0
  1074. data/lib/tdl/examples/2_hdl_class/test_module_var.rb +18 -0
  1075. data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv +108 -0
  1076. data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +35 -0
  1077. data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv +105 -0
  1078. data/lib/tdl/examples/2_hdl_class/tmp/head_pkg_module.sv +42 -0
  1079. data/lib/tdl/examples/2_hdl_class/tmp/init_module.sv +110 -0
  1080. data/lib/tdl/examples/2_hdl_class/tmp/module_instance_test.sv +31 -0
  1081. data/lib/tdl/examples/2_hdl_class/tmp/port_module.sv +99 -0
  1082. data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv +27 -0
  1083. data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv +78 -0
  1084. data/lib/tdl/examples/2_hdl_class/tmp/test_axi4_M2S.sv +30 -0
  1085. data/lib/tdl/examples/2_hdl_class/tmp/test_foreach.sv +34 -0
  1086. data/lib/tdl/examples/2_hdl_class/tmp/test_function.sv +52 -0
  1087. data/lib/tdl/examples/2_hdl_class/tmp/test_initial_assert.sv +31 -0
  1088. data/lib/tdl/examples/2_hdl_class/tmp/test_inst_sugar.sv +42 -0
  1089. data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +36 -0
  1090. data/lib/tdl/examples/2_hdl_class/tmp/test_module_port.sv +33 -0
  1091. data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +35 -0
  1092. data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +38 -0
  1093. data/lib/tdl/examples/2_hdl_class/tmp/test_package2.sv +36 -0
  1094. data/lib/tdl/examples/2_hdl_class/tmp/test_struct.sv +38 -0
  1095. data/lib/tdl/examples/2_hdl_class/tmp/test_struct_function.sv +44 -0
  1096. data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +27 -0
  1097. data/lib/tdl/examples/2_hdl_class/tmp/text_generate.sv +54 -0
  1098. data/lib/tdl/examples/2_hdl_class/vcs_string.rb +5 -0
  1099. data/lib/tdl/examples/3_hdl_sdl_instance/hdl_test.sv +13 -0
  1100. data/lib/tdl/examples/3_hdl_sdl_instance/main.rb +26 -0
  1101. data/lib/tdl/examples/3_hdl_sdl_instance/main_md.sv +42 -0
  1102. data/lib/tdl/examples/3_hdl_sdl_instance/sdl_md.sv +30 -0
  1103. data/lib/tdl/examples/3_hdl_sdl_instance/sdl_test.rb +9 -0
  1104. data/lib/tdl/examples/4_generate/example.rb +38 -0
  1105. data/lib/tdl/examples/4_generate/test_generate.sv +59 -0
  1106. data/lib/tdl/examples/5_logic_combin/login_combin.rb +22 -0
  1107. data/lib/tdl/examples/5_logic_combin/test_logic_combin.sv +36 -0
  1108. data/lib/tdl/examples/6_module_with_interface/example.rb +48 -0
  1109. data/lib/tdl/examples/6_module_with_interface/example_interface.sv +40 -0
  1110. data/lib/tdl/examples/6_module_with_interface/inf_collect.rb +54 -0
  1111. data/lib/tdl/examples/6_module_with_interface/inf_collect.sv +63 -0
  1112. data/lib/tdl/examples/7_module_with_package/body_package.rb +3 -0
  1113. data/lib/tdl/examples/7_module_with_package/body_package.sv +25 -0
  1114. data/lib/tdl/examples/7_module_with_package/example_pkg.rb +20 -0
  1115. data/lib/tdl/examples/7_module_with_package/example_pkg.sv +35 -0
  1116. data/lib/tdl/examples/7_module_with_package/head_package.rb +8 -0
  1117. data/lib/tdl/examples/7_module_with_package/head_package.sv +29 -0
  1118. data/lib/tdl/examples/8_top_module/dve.tcl +64 -0
  1119. data/lib/tdl/examples/8_top_module/example.rb +8 -0
  1120. data/lib/tdl/examples/8_top_module/pins.yml +7 -0
  1121. data/lib/tdl/examples/8_top_module/tb_test_top.sv +29 -0
  1122. data/lib/tdl/examples/8_top_module/test_top.sv +28 -0
  1123. data/lib/tdl/examples/8_top_module/test_top_constraints.xdc +37 -0
  1124. data/lib/tdl/examples/9_itegration/A_itgt/a_test_md.sv +29 -0
  1125. data/lib/tdl/examples/9_itegration/A_itgt/a_test_module.rb +6 -0
  1126. data/lib/tdl/examples/9_itegration/A_itgt/itgt_module_a_block.rb +34 -0
  1127. data/lib/tdl/examples/9_itegration/clock_manage/itgt_module_clock_manage.rb +33 -0
  1128. data/lib/tdl/examples/9_itegration/clock_manage/simple_clock.rb +7 -0
  1129. data/lib/tdl/examples/9_itegration/clock_manage/simple_clock.sv +29 -0
  1130. data/lib/tdl/examples/9_itegration/dve.tcl +64 -0
  1131. data/lib/tdl/examples/9_itegration/pins.yml +4 -0
  1132. data/lib/tdl/examples/9_itegration/tb_test_top.sv +29 -0
  1133. data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +29 -0
  1134. data/lib/tdl/examples/9_itegration/test_top.sv +40 -0
  1135. data/lib/tdl/examples/9_itegration/test_top_constraints.xdc +29 -0
  1136. data/lib/tdl/examples/9_itegration/test_tttop.sv +40 -0
  1137. data/lib/tdl/examples/9_itegration/test_tttop_constraints.xdc +29 -0
  1138. data/lib/tdl/examples/9_itegration/top.rb +11 -0
  1139. data/lib/tdl/examples/readme.md +31 -0
  1140. data/lib/tdl/exlib/common_cfg_reg_inf.rb +139 -0
  1141. data/lib/tdl/exlib/constraints.rb +286 -0
  1142. data/lib/tdl/exlib/constraints_verb.rb +304 -0
  1143. data/lib/tdl/exlib/dve_tcl.rb +162 -0
  1144. data/lib/tdl/exlib/element_class_vars.rb +106 -0
  1145. data/lib/tdl/exlib/global_param.rb +108 -0
  1146. data/lib/tdl/exlib/integral_test/bak/integral_test.rb +206 -0
  1147. data/lib/tdl/exlib/integral_test/clock_itest.rb +28 -0
  1148. data/lib/tdl/exlib/integral_test/diff_clock_itest.rb +30 -0
  1149. data/lib/tdl/exlib/integral_test/io_itest.rb +41 -0
  1150. data/lib/tdl/exlib/integral_test/reset_itest.rb +31 -0
  1151. data/lib/tdl/exlib/integral_test/simple_logic_itest.rb +19 -0
  1152. data/lib/tdl/exlib/itegration.rb +307 -0
  1153. data/lib/tdl/exlib/itegration_verb.rb +913 -0
  1154. data/lib/tdl/exlib/parse_argv.rb +43 -0
  1155. data/lib/tdl/exlib/sdlmodule_sim.bak.rb +375 -0
  1156. data/lib/tdl/exlib/test_point.rb +287 -0
  1157. data/lib/tdl/global_scan.rb +134 -0
  1158. data/lib/tdl/rebuild_ele/axi4.rb +141 -0
  1159. data/lib/tdl/rebuild_ele/axi_lite.rb +56 -0
  1160. data/lib/tdl/rebuild_ele/axi_stream.rb +121 -0
  1161. data/lib/tdl/rebuild_ele/cm_ram_inf.sv +105 -0
  1162. data/lib/tdl/rebuild_ele/cm_ram_inf_define.rb +44 -0
  1163. data/lib/tdl/rebuild_ele/data_inf.rb +27 -0
  1164. data/lib/tdl/rebuild_ele/data_inf_c.rb +83 -0
  1165. data/lib/tdl/rebuild_ele/ele_base.rb +822 -0
  1166. data/lib/tdl/rebuild_ele/readme.md +1 -0
  1167. data/lib/tdl/sdlimplement/resource.yml +154 -0
  1168. data/lib/tdl/sdlimplement/sdl_impl_module.rb +391 -0
  1169. data/lib/tdl/sdlimplement/sdl_impl_param.rb +26 -0
  1170. data/lib/tdl/sdlimplement/test.rb +64 -0
  1171. data/lib/tdl/sdlmodule/bak/sdlmodule_varible_ex.rb +120 -0
  1172. data/lib/tdl/sdlmodule/generator_block_module.rb +84 -0
  1173. data/lib/tdl/sdlmodule/sdlmodule.rb +407 -0
  1174. data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb +333 -0
  1175. data/lib/tdl/sdlmodule/sdlmodule_draw.rb +272 -0
  1176. data/lib/tdl/sdlmodule/sdlmodule_head_logo.txt +10 -0
  1177. data/lib/tdl/sdlmodule/sdlmodule_instance.rb +623 -0
  1178. data/lib/tdl/sdlmodule/sdlmodule_port_define.rb +374 -0
  1179. data/lib/tdl/sdlmodule/sdlmodule_varible.rb +160 -0
  1180. data/lib/tdl/sdlmodule/sdlmodule_vcs_comptable.rb +140 -0
  1181. data/lib/tdl/sdlmodule/techbench_module.rb +14 -0
  1182. data/lib/tdl/sdlmodule/test_unit_module.rb +138 -0
  1183. data/lib/tdl/sdlmodule/top_module.rb +543 -0
  1184. data/lib/tdl/tdl.rb +265 -0
  1185. data/lib/tdl/tdlerror/tdlerror.rb +8 -0
  1186. data/lib/tdl/testunit/test_all.rb +4 -0
  1187. data/lib/tdl/testunit/test_array_chain.rb +89 -0
  1188. data/lib/tdl/testunit/test_tmp.rb +47 -0
  1189. metadata +1301 -0
data/lib/axi/AXI_stream/parse_big_field_table_verb.sv ADDED
@@ -0,0 +1,118 @@
1
+ /**********************************************
2
+ _______________________________________
3
+ ___________ Cook Darwin __________
4
+ _______________________________________
5
+ descript: 解析大块的值域用于 common_frame_table
6
+ author : Cook.Darwin
7
+ Version: VERA.2.0 2017/9/11
8
+ resever value
9
+ Version: VERA.2.0 2017/12/11
10
+ use parse_common_frame_table_A2
11
+ Version: VERB.0.0 ###### Tue Oct 20 09:42:34 CST 2020
12
+ rebuild
13
+ creaded: 2016/12/22
14
+ madified:
15
+ ***********************************************/
16
+ `timescale 1ns/1ps
17
+ module parse_big_field_table_verb #(
18
+ parameter DSIZE = 8,
19
+ parameter FIELD_LEN = 16*8, //MAX 16*8
20
+ parameter TRY_PARSE = "OFF"
21
+ )(
22
+ output logic[0:DSIZE*FIELD_LEN-1] value,
23
+ output logic out_valid,
24
+ axi_stream_inf.slaver cm_tb_s,
25
+ axi_stream_inf.master cm_tb_m,
26
+ axi_stream_inf.mirror cm_mirror
27
+ );
28
+
29
+ import SystemPkg::*;
30
+
31
+ initial begin
32
+ assert(DSIZE == cm_tb_s.DSIZE)
33
+ else begin
34
+ $error("DSIZE<%d> != stream.DSIZE<%d>",DSIZE, cm_tb_s.DSIZE);
35
+ end
36
+ end
37
+
38
+ wire clock,rst_n,clken;
39
+
40
+ axi_stream_inf #(.DSIZE(DSIZE)) parse_stream (.aclk(clock),.aresetn(rst_n),.aclken(clken));
41
+
42
+ generate
43
+ if(TRY_PARSE == "ON")begin
44
+
45
+ assign clock = cm_mirror.aclk;
46
+ assign rst_n = cm_mirror.aresetn;
47
+ assign clken = cm_mirror.aclken;
48
+
49
+ assign parse_stream.axis_tkeep = cm_mirror.axis_tkeep ;
50
+ assign parse_stream.axis_tuser = cm_mirror.axis_tuser ;
51
+ assign parse_stream.axis_tlast = cm_mirror.axis_tlast ;
52
+ assign parse_stream.axis_tdata = cm_mirror.axis_tdata ;
53
+ assign parse_stream.axis_tvalid= cm_mirror.axis_tvalid;
54
+ assign parse_stream.axis_tready= cm_mirror.axis_tready;
55
+ if(SIM=="FALSE" || SIM =="OFF")
56
+ assign cm_tb_s.axis_tready = cm_mirror.axis_tready;
57
+ end else begin
58
+
59
+ assign clock = cm_tb_s.aclk;
60
+ assign rst_n = cm_tb_s.aresetn;
61
+ assign clken = cm_tb_s.aclken;
62
+
63
+
64
+ assign parse_stream.axis_tkeep = cm_tb_s.axis_tkeep ;
65
+ assign parse_stream.axis_tuser = cm_tb_s.axis_tuser ;
66
+ assign parse_stream.axis_tlast = cm_tb_s.axis_tlast ;
67
+ assign parse_stream.axis_tdata = cm_tb_s.axis_tdata ;
68
+ assign parse_stream.axis_tvalid= cm_tb_s.axis_tvalid;
69
+ assign parse_stream.axis_tready= cm_tb_m.axis_tready;
70
+ assign cm_tb_s.axis_tready = cm_tb_m.axis_tready;
71
+ end
72
+ endgenerate
73
+
74
+ logic region_valid;
75
+
76
+ always_ff@(posedge clock,negedge rst_n)begin
77
+ if(~rst_n) region_valid <= 1'b1;
78
+ else begin
79
+ if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tlast)
80
+ region_valid <= 1'b1;
81
+ else if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tcnt == (FIELD_LEN-1'b1))
82
+ region_valid <= 1'b0;
83
+ else region_valid <= region_valid;
84
+ end
85
+ end
86
+
87
+ localparam VSIZE = $clog2(FIELD_LEN);
88
+ logic[DSIZE-1:0] value_array [0:FIELD_LEN-1];
89
+
90
+ always_ff@(posedge clock,negedge rst_n)begin
91
+ if(~rst_n)
92
+ foreach(value_array[i])
93
+ value_array[i] <= '0;
94
+ else begin
95
+ if(region_valid)begin
96
+ value_array[parse_stream.axis_tcnt[VSIZE-1:0]] <= parse_stream.axis_tdata;
97
+ end
98
+ end
99
+ end
100
+
101
+ assign value = {>>{value_array}};
102
+
103
+ always_ff@(posedge clock,negedge rst_n)begin
104
+ if(~rst_n) out_valid <= 1'b0;
105
+ else begin
106
+ if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tlast)
107
+ if(out_valid)
108
+ out_valid <= 1'b0;
109
+ else out_valid <= 1'b1;
110
+ else if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tcnt == (FIELD_LEN-1'b1))
111
+ out_valid <= 1'b1;
112
+ else if(region_valid)
113
+ out_valid <= 1'b0;
114
+ else out_valid <= out_valid;
115
+ end
116
+ end
117
+
118
+ endmodule
data/lib/axi/AXI_stream/parse_common_frame_table.sv ADDED
@@ -0,0 +1,202 @@
1
+ /**********************************************
2
+ _______________________________________
3
+ ___________ Cook Darwin __________
4
+ _______________________________________
5
+ descript: 通用报文格式解析器
6
+ author : Cook.Darwin
7
+ Version: VERA.0.0 2017/1/22
8
+ backup old file
9
+ this use A1
10
+ creaded: 2016/12/16
11
+ madified:2017/1/3
12
+ ***********************************************/
13
+ `timescale 1ns/1ps
14
+ // (* axi_stream = "true" *)
15
+ module parse_common_frame_table #(
16
+ parameter FIELD_TOTLE = 11, // MAX 16 :: default IP Frame
17
+ parameter DSIZE = 8,
18
+ parameter TRY_PARSE = "OFF", // just check frame, bypass data
19
+ //Field 0
20
+ //---------------------
21
+ parameter F0_LEN = 1,
22
+ parameter F0_NAME = "version+head length",
23
+ //Field 1
24
+ //---------------------
25
+ parameter F1_LEN = 1,
26
+ parameter F1_NAME = "TOS",
27
+ //Field 2
28
+ //---------------------
29
+ parameter F2_LEN = 2,
30
+ parameter F2_NAME = "totle length",
31
+ //Field 3
32
+ //---------------------
33
+ parameter F3_LEN = 2,
34
+ parameter F3_NAME = "identify",
35
+ //Field 4
36
+ //---------------------
37
+ parameter F4_LEN = 1,
38
+ parameter F4_NAME = "flag + offset MSB",
39
+ //Field 5
40
+ //---------------------
41
+ parameter F5_LEN = 1,
42
+ parameter F5_NAME = "offset LSB",
43
+ //Field 6
44
+ //---------------------
45
+ parameter F6_LEN = 1,
46
+ parameter F6_NAME = "TTL",
47
+ //Field 7
48
+ //---------------------
49
+ parameter F7_LEN = 1,
50
+ parameter F7_NAME = "sub protocol",
51
+ //Field 8
52
+ //---------------------
53
+ parameter F8_LEN = 2,
54
+ parameter F8_NAME = "head CRC",
55
+ //Field 9
56
+ //---------------------
57
+ parameter F9_LEN = 4,
58
+ parameter F9_NAME = "source ip addr",
59
+ //Field 10
60
+ //---------------------
61
+ parameter F10_LEN = 4,
62
+ parameter F10_NAME = "destination ip addr",
63
+ //Field 11
64
+ //---------------------
65
+ parameter F11_LEN = 1,
66
+ parameter F11_NAME = "Filed 11",
67
+ //Field 12
68
+ //---------------------
69
+ parameter F12_LEN = 1,
70
+ parameter F12_NAME = "Filed 12",
71
+ //Field 13
72
+ //---------------------
73
+ parameter F13_LEN = 1,
74
+ parameter F13_NAME = "Field 13",
75
+ //Field 14
76
+ //---------------------
77
+ parameter F14_LEN = 1,
78
+ parameter F14_NAME = "Field 14",
79
+ //Field 15
80
+ //---------------------
81
+ parameter F15_LEN = 1,
82
+ parameter F15_NAME = "Field 15"
83
+ )(
84
+ input enable,
85
+ output logic [F0_LEN *DSIZE-1:0] f0_value,
86
+ output logic [F1_LEN *DSIZE-1:0] f1_value,
87
+ output logic [F2_LEN *DSIZE-1:0] f2_value,
88
+ output logic [F3_LEN *DSIZE-1:0] f3_value,
89
+ output logic [F4_LEN *DSIZE-1:0] f4_value,
90
+ output logic [F5_LEN *DSIZE-1:0] f5_value,
91
+ output logic [F6_LEN *DSIZE-1:0] f6_value,
92
+ output logic [F7_LEN *DSIZE-1:0] f7_value,
93
+ output logic [F8_LEN *DSIZE-1:0] f8_value,
94
+ output logic [F9_LEN *DSIZE-1:0] f9_value,
95
+ output logic [F10_LEN*DSIZE-1:0] f10_value,
96
+ output logic [F11_LEN*DSIZE-1:0] f11_value,
97
+ output logic [F12_LEN*DSIZE-1:0] f12_value,
98
+ output logic [F13_LEN*DSIZE-1:0] f13_value,
99
+ output logic [F14_LEN*DSIZE-1:0] f14_value,
100
+ output logic [F15_LEN*DSIZE-1:0] f15_value,
101
+ output logic out_valid,
102
+ (* up_stream = "true" *)
103
+ axi_stream_inf.slaver cm_tb_s,
104
+ (* down_stream = "true" *)
105
+ axi_stream_inf.master cm_tb_m,
106
+ axi_stream_inf.mirror cm_mirror
107
+ );
108
+
109
+ parse_common_frame_table_A1 #(
110
+ .FIELD_TOTLE (FIELD_TOTLE), // MAX 16 :: default IP Frame
111
+ .DSIZE (DSIZE ),
112
+ .TRY_PARSE (TRY_PARSE ), // just check frame, bypass data
113
+ //Field 0
114
+ //---------------------
115
+ .F0_LEN (F0_LEN ),
116
+ .F0_NAME (F0_NAME ),
117
+ //Field 1
118
+ //---------------------
119
+ .F1_LEN (F1_LEN ),
120
+ .F1_NAME (F1_NAME ),
121
+ //Field 2
122
+ //---------------------
123
+ .F2_LEN (F2_LEN ),
124
+ .F2_NAME (F2_NAME ),
125
+ //Field 3
126
+ //---------------------
127
+ .F3_LEN (F3_LEN ),
128
+ .F3_NAME (F3_NAME ),
129
+ //Field 4
130
+ //---------------------
131
+ .F4_LEN (F4_LEN ),
132
+ .F4_NAME (F4_NAME ),
133
+ //Field 5
134
+ //---------------------
135
+ .F5_LEN (F5_LEN ),
136
+ .F5_NAME (F5_NAME ),
137
+ //Field 6
138
+ //---------------------
139
+ .F6_LEN (F6_LEN ),
140
+ .F6_NAME (F6_NAME ),
141
+ //Field 7
142
+ //---------------------
143
+ .F7_LEN (F7_LEN ),
144
+ .F7_NAME (F7_NAME ),
145
+ //Field 8
146
+ //---------------------
147
+ .F8_LEN (F8_LEN ),
148
+ .F8_NAME (F8_NAME ),
149
+ //Field 9
150
+ //---------------------
151
+ .F9_LEN (F9_LEN ),
152
+ .F9_NAME (F9_NAME ),
153
+ //Field 10
154
+ //---------------------
155
+ .F10_LEN (F10_LEN ),
156
+ .F10_NAME (F10_NAME ),
157
+ //Field 11
158
+ //---------------------
159
+ .F11_LEN (F11_LEN ),
160
+ .F11_NAME (F11_NAME ),
161
+ //Field 12
162
+ //---------------------
163
+ .F12_LEN (F12_LEN ),
164
+ .F12_NAME (F12_NAME ),
165
+ //Field 13
166
+ //---------------------
167
+ .F13_LEN (F13_LEN ),
168
+ .F13_NAME (F13_NAME ),
169
+ //Field 14
170
+ //---------------------
171
+ .F14_LEN (F14_LEN ),
172
+ .F14_NAME (F14_NAME ),
173
+ //Field 15
174
+ //---------------------
175
+ .F15_LEN (F15_LEN ),
176
+ .F15_NAME (F15_NAME )
177
+ )parse_common_frame_table_inst(
178
+ /* input */ .enable (1'b1 ),
179
+ /* output logic [F0_LEN *DSIZE-1:0] */ .f0_value (f0_value ),
180
+ /* output logic [F1_LEN *DSIZE-1:0] */ .f1_value (f1_value ),
181
+ /* output logic [F2_LEN *DSIZE-1:0] */ .f2_value (f2_value ),
182
+ /* output logic [F3_LEN *DSIZE-1:0] */ .f3_value (f3_value ),
183
+ /* output logic [F4_LEN *DSIZE-1:0] */ .f4_value (f4_value ),
184
+ /* output logic [F5_LEN *DSIZE-1:0] */ .f5_value (f5_value ),
185
+ /* output logic [F6_LEN *DSIZE-1:0] */ .f6_value (f6_value ),
186
+ /* output logic [F7_LEN *DSIZE-1:0] */ .f7_value (f7_value ),
187
+ /* output logic [F8_LEN *DSIZE-1:0] */ .f8_value (f8_value ),
188
+ /* output logic [F9_LEN *DSIZE-1:0] */ .f9_value (f9_value ),
189
+ /* output logic [F10_LEN*DSIZE-1:0] */ .f10_value (f10_value ),
190
+ /* output logic [F11_LEN*DSIZE-1:0] */ .f11_value (f11_value ),
191
+ /* output logic [F12_LEN*DSIZE-1:0] */ .f12_value (f12_value ),
192
+ /* output logic [F13_LEN*DSIZE-1:0] */ .f13_value (f13_value ),
193
+ /* output logic [F14_LEN*DSIZE-1:0] */ .f14_value (f14_value ),
194
+ /* output logic [F15_LEN*DSIZE-1:0] */ .f15_value (f15_value ),
195
+ /* output logic */ .out_valid (out_valid ),
196
+ /* axi_stream_inf.slaver */ .cm_tb_s (cm_tb_s ),
197
+ /* axi_stream_inf.master */ .cm_tb_m (cm_tb_m ),
198
+ /* axi_stream_inf.mirror */ .cm_mirror (cm_mirror )
199
+ );
200
+
201
+
202
+ endmodule
data/lib/axi/AXI_stream/parse_common_frame_table_A1.sv ADDED
@@ -0,0 +1,521 @@
1
+ /**********************************************
2
+ _______________________________________
3
+ ___________ Cook Darwin __________
4
+ _______________________________________
5
+ descript: 通用报文格式解析器
6
+ author : Cook.Darwin
7
+ Version: VERA.0.1
8
+ add out valid signal
9
+ Version: VERA.1.0
10
+ add enable signal
11
+ creaded: 2016/12/16
12
+ madified:2017/1/3
13
+ ***********************************************/
14
+ `timescale 1ns/1ps
15
+ module parse_common_frame_table_A1 #(
16
+ parameter FIELD_TOTLE = 11, // MAX 16 :: default IP Frame
17
+ parameter DSIZE = 8,
18
+ parameter TRY_PARSE = "OFF", // just check frame, bypass data
19
+ //Field 0
20
+ //---------------------
21
+ parameter F0_LEN = 1,
22
+ parameter F0_NAME = "version+head length",
23
+ //Field 1
24
+ //---------------------
25
+ parameter F1_LEN = 1,
26
+ parameter F1_NAME = "TOS",
27
+ //Field 2
28
+ //---------------------
29
+ parameter F2_LEN = 2,
30
+ parameter F2_NAME = "totle length",
31
+ //Field 3
32
+ //---------------------
33
+ parameter F3_LEN = 2,
34
+ parameter F3_NAME = "identify",
35
+ //Field 4
36
+ //---------------------
37
+ parameter F4_LEN = 1,
38
+ parameter F4_NAME = "flag + offset MSB",
39
+ //Field 5
40
+ //---------------------
41
+ parameter F5_LEN = 1,
42
+ parameter F5_NAME = "offset LSB",
43
+ //Field 6
44
+ //---------------------
45
+ parameter F6_LEN = 1,
46
+ parameter F6_NAME = "TTL",
47
+ //Field 7
48
+ //---------------------
49
+ parameter F7_LEN = 1,
50
+ parameter F7_NAME = "sub protocol",
51
+ //Field 8
52
+ //---------------------
53
+ parameter F8_LEN = 2,
54
+ parameter F8_NAME = "head CRC",
55
+ //Field 9
56
+ //---------------------
57
+ parameter F9_LEN = 4,
58
+ parameter F9_NAME = "source ip addr",
59
+ //Field 10
60
+ //---------------------
61
+ parameter F10_LEN = 4,
62
+ parameter F10_NAME = "destination ip addr",
63
+ //Field 11
64
+ //---------------------
65
+ parameter F11_LEN = 1,
66
+ parameter F11_NAME = "Filed 11",
67
+ //Field 12
68
+ //---------------------
69
+ parameter F12_LEN = 1,
70
+ parameter F12_NAME = "Filed 12",
71
+ //Field 13
72
+ //---------------------
73
+ parameter F13_LEN = 1,
74
+ parameter F13_NAME = "Field 13",
75
+ //Field 14
76
+ //---------------------
77
+ parameter F14_LEN = 1,
78
+ parameter F14_NAME = "Field 14",
79
+ //Field 15
80
+ //---------------------
81
+ parameter F15_LEN = 1,
82
+ parameter F15_NAME = "Field 15"
83
+ )(
84
+ input enable,
85
+ output logic [F0_LEN *DSIZE-1:0] f0_value,
86
+ output logic [F1_LEN *DSIZE-1:0] f1_value,
87
+ output logic [F2_LEN *DSIZE-1:0] f2_value,
88
+ output logic [F3_LEN *DSIZE-1:0] f3_value,
89
+ output logic [F4_LEN *DSIZE-1:0] f4_value,
90
+ output logic [F5_LEN *DSIZE-1:0] f5_value,
91
+ output logic [F6_LEN *DSIZE-1:0] f6_value,
92
+ output logic [F7_LEN *DSIZE-1:0] f7_value,
93
+ output logic [F8_LEN *DSIZE-1:0] f8_value,
94
+ output logic [F9_LEN *DSIZE-1:0] f9_value,
95
+ output logic [F10_LEN*DSIZE-1:0] f10_value,
96
+ output logic [F11_LEN*DSIZE-1:0] f11_value,
97
+ output logic [F12_LEN*DSIZE-1:0] f12_value,
98
+ output logic [F13_LEN*DSIZE-1:0] f13_value,
99
+ output logic [F14_LEN*DSIZE-1:0] f14_value,
100
+ output logic [F15_LEN*DSIZE-1:0] f15_value,
101
+ output logic out_valid,
102
+ axi_stream_inf.slaver cm_tb_s,
103
+ axi_stream_inf.master cm_tb_m,
104
+ axi_stream_inf.mirror cm_mirror
105
+ );
106
+ import SystemPkg::*;
107
+ import DataInterfacePkg::*;
108
+
109
+ wire clock,rst_n,clken;
110
+
111
+ axi_stream_inf #(.DSIZE(DSIZE)) parse_stream (.aclk(clock),.aresetn(rst_n),.aclken(clken));
112
+
113
+ generate
114
+ if(TRY_PARSE == "ON")begin
115
+
116
+ assign clock = cm_mirror.aclk;
117
+ assign rst_n = cm_mirror.aresetn;
118
+ assign clken = cm_mirror.aclken;
119
+
120
+ assign parse_stream.axis_tkeep = cm_mirror.axis_tkeep ;
121
+ assign parse_stream.axis_tuser = cm_mirror.axis_tuser ;
122
+ assign parse_stream.axis_tlast = cm_mirror.axis_tlast ;
123
+ assign parse_stream.axis_tdata = cm_mirror.axis_tdata ;
124
+ assign parse_stream.axis_tvalid= cm_mirror.axis_tvalid;
125
+ assign parse_stream.axis_tready= cm_mirror.axis_tready;
126
+ if(SIM=="FALSE" || SIM =="OFF")
127
+ assign cm_tb_s.axis_tready = cm_mirror.axis_tready;
128
+ end else begin
129
+
130
+ assign clock = cm_tb_s.aclk;
131
+ assign rst_n = cm_tb_s.aresetn;
132
+ assign clken = cm_tb_s.aclken;
133
+
134
+
135
+ assign parse_stream.axis_tkeep = cm_tb_s.axis_tkeep ;
136
+ assign parse_stream.axis_tuser = cm_tb_s.axis_tuser ;
137
+ assign parse_stream.axis_tlast = cm_tb_s.axis_tlast ;
138
+ assign parse_stream.axis_tdata = cm_tb_s.axis_tdata ;
139
+ assign parse_stream.axis_tvalid= cm_tb_s.axis_tvalid;
140
+ assign parse_stream.axis_tready= cm_tb_m.axis_tready;
141
+ assign cm_tb_s.axis_tready = cm_tb_m.axis_tready;
142
+ end
143
+ endgenerate
144
+
145
+ assign cm_tb_m.axis_tkeep = {(DSIZE/8){1'b1}};
146
+ assign cm_tb_m.axis_tuser = 1'b0;
147
+
148
+ import DataInterfacePkg::*;
149
+
150
+ localparam F0_SUM_LEN = F0_LEN;
151
+ localparam F1_SUM_LEN = F0_SUM_LEN + F1_LEN;
152
+ localparam F2_SUM_LEN = F1_SUM_LEN + F2_LEN;
153
+ localparam F3_SUM_LEN = F2_SUM_LEN + F3_LEN;
154
+ localparam F4_SUM_LEN = F3_SUM_LEN + F4_LEN;
155
+ localparam F5_SUM_LEN = F4_SUM_LEN + F5_LEN;
156
+ localparam F6_SUM_LEN = F5_SUM_LEN + F6_LEN;
157
+ localparam F7_SUM_LEN = F6_SUM_LEN + F7_LEN;
158
+
159
+ localparam F8_SUM_LEN = F7_SUM_LEN + F8_LEN;
160
+ localparam F9_SUM_LEN = F8_SUM_LEN + F9_LEN;
161
+ localparam F10_SUM_LEN = F9_SUM_LEN + F10_LEN;
162
+ localparam F11_SUM_LEN = F10_SUM_LEN+ F11_LEN;
163
+ localparam F12_SUM_LEN = F11_SUM_LEN+ F12_LEN;
164
+ localparam F13_SUM_LEN = F12_SUM_LEN+ F13_LEN;
165
+ localparam F14_SUM_LEN = F13_SUM_LEN+ F14_LEN;
166
+ localparam F15_SUM_LEN = F14_SUM_LEN+ F15_LEN;
167
+
168
+ localparam FIELD_LENGTH = FIELD_TOTLE==1 ? F0_SUM_LEN :
169
+ FIELD_TOTLE==2 ? F1_SUM_LEN :
170
+ FIELD_TOTLE==3 ? F2_SUM_LEN :
171
+ FIELD_TOTLE==4 ? F3_SUM_LEN :
172
+ FIELD_TOTLE==5 ? F4_SUM_LEN :
173
+ FIELD_TOTLE==6 ? F5_SUM_LEN :
174
+ FIELD_TOTLE==7 ? F6_SUM_LEN :
175
+ FIELD_TOTLE==8 ? F7_SUM_LEN :
176
+ FIELD_TOTLE==9 ? F8_SUM_LEN :
177
+ FIELD_TOTLE==10? F9_SUM_LEN :
178
+ FIELD_TOTLE==11? F10_SUM_LEN :
179
+ FIELD_TOTLE==12? F11_SUM_LEN :
180
+ FIELD_TOTLE==13? F12_SUM_LEN :
181
+ FIELD_TOTLE==14? F13_SUM_LEN :
182
+ FIELD_TOTLE==15? F14_SUM_LEN : F15_SUM_LEN ;
183
+
184
+
185
+ typedef enum {IDLE,START,F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,F14,F15,DONE,DLAST} STATUS;
186
+
187
+ STATUS cstate,nstate;
188
+
189
+
190
+ logic f0_pack_ok;
191
+ logic f1_pack_ok;
192
+ logic f2_pack_ok;
193
+ logic f3_pack_ok;
194
+ logic f4_pack_ok;
195
+ logic f5_pack_ok;
196
+ logic f6_pack_ok;
197
+ logic f7_pack_ok;
198
+ logic f8_pack_ok;
199
+ logic f9_pack_ok;
200
+ logic f10_pack_ok;
201
+ logic f11_pack_ok;
202
+ logic f12_pack_ok;
203
+ logic f13_pack_ok;
204
+ logic f14_pack_ok;
205
+ logic f15_pack_ok;
206
+
207
+ logic force_jump;
208
+
209
+ logic last_part_ok;
210
+ logic no_data;
211
+
212
+ always@(posedge clock,negedge rst_n)
213
+ if(~rst_n) cstate <= IDLE;
214
+ else cstate <= nstate;
215
+
216
+ always@(*)
217
+ case(cstate)
218
+ IDLE:
219
+ if(parse_stream.axis_tvalid && enable)
220
+ // if(parse_stream.axis_tvalid)
221
+ nstate = F0;
222
+ else nstate = IDLE;
223
+ F0 : if(force_jump) nstate = (TRY_PARSE=="ON")? DLAST : IDLE ;else if(f0_pack_ok) begin nstate = (FIELD_TOTLE!= 1)? F1 : DONE; end else nstate = F0;
224
+ F1 : if(force_jump) nstate = (TRY_PARSE=="ON")? DLAST : IDLE ;else if(f1_pack_ok) begin nstate = (FIELD_TOTLE!= 2)? F2 : DONE; end else nstate = F1;
225
+ F2 : if(force_jump) nstate = (TRY_PARSE=="ON")? DLAST : IDLE ;else if(f2_pack_ok) begin nstate = (FIELD_TOTLE!= 3)? F3 : DONE; end else nstate = F2;
226
+ F3 : if(force_jump) nstate = (TRY_PARSE=="ON")? DLAST : IDLE ;else if(f3_pack_ok) begin nstate = (FIELD_TOTLE!= 4)? F4 : DONE; end else nstate = F3;
227
+ F4 : if(force_jump) nstate = (TRY_PARSE=="ON")? DLAST : IDLE ;else if(f4_pack_ok) begin nstate = (FIELD_TOTLE!= 5)? F5 : DONE; end else nstate = F4;
228
+ F5 : if(force_jump) nstate = (TRY_PARSE=="ON")? DLAST : IDLE ;else if(f5_pack_ok) begin nstate = (FIELD_TOTLE!= 6)? F6 : DONE; end else nstate = F5;
229
+ F6 : if(force_jump) nstate = (TRY_PARSE=="ON")? DLAST : IDLE ;else if(f6_pack_ok) begin nstate = (FIELD_TOTLE!= 7)? F7 : DONE; end else nstate = F6;
230
+ F7 : if(force_jump) nstate = (TRY_PARSE=="ON")? DLAST : IDLE ;else if(f7_pack_ok) begin nstate = (FIELD_TOTLE!= 8)? F8 : DONE; end else nstate = F7;
231
+ F8 : if(force_jump) nstate = (TRY_PARSE=="ON")? DLAST : IDLE ;else if(f8_pack_ok) begin nstate = (FIELD_TOTLE!= 9)? F9 : DONE; end else nstate = F8;
232
+ F9 : if(force_jump) nstate = (TRY_PARSE=="ON")? DLAST : IDLE ;else if(f9_pack_ok) begin nstate = (FIELD_TOTLE!=10)? F10 : DONE; end else nstate = F9;
233
+ F10: if(force_jump) nstate = (TRY_PARSE=="ON")? DLAST : IDLE ;else if(f10_pack_ok)begin nstate = (FIELD_TOTLE!=11)? F11 : DONE; end else nstate = F10;
234
+ F11: if(force_jump) nstate = (TRY_PARSE=="ON")? DLAST : IDLE ;else if(f11_pack_ok)begin nstate = (FIELD_TOTLE!=12)? F12 : DONE; end else nstate = F11;
235
+ F12: if(force_jump) nstate = (TRY_PARSE=="ON")? DLAST : IDLE ;else if(f12_pack_ok)begin nstate = (FIELD_TOTLE!=13)? F13 : DONE; end else nstate = F12;
236
+ F13: if(force_jump) nstate = (TRY_PARSE=="ON")? DLAST : IDLE ;else if(f13_pack_ok)begin nstate = (FIELD_TOTLE!=14)? F14 : DONE; end else nstate = F13;
237
+ F14: if(force_jump) nstate = (TRY_PARSE=="ON")? DLAST : IDLE ;else if(f14_pack_ok)begin nstate = (FIELD_TOTLE!=15)? F15 : DONE; end else nstate = F14;
238
+ F15: if(force_jump) nstate = (TRY_PARSE=="ON")? DLAST : IDLE ;else if(f15_pack_ok)begin nstate = DONE ; end else nstate = F15;
239
+ DONE:if(last_part_ok) nstate = DLAST; else nstate = DONE;
240
+ DLAST:
241
+ if(TRY_PARSE=="ON")
242
+ nstate = IDLE;
243
+ // else if(force_jump && parse_stream.aclken)
244
+ // nstate = IDLE;
245
+ // else if(cm_tb_m.axis_tvalid && cm_tb_m.axis_tready && cm_tb_m.axis_tlast && cm_tb_m.aclken)
246
+ // else if(cm_tb_m.axis_tvalid && cm_tb_m.axis_tready && cm_tb_m.aclken)
247
+ // nstate = IDLE;
248
+ else if(cm_tb_m.axis_tvalid && cm_tb_m.axis_tready && cm_tb_m.aclken )begin
249
+ if(parse_stream.axis_tvalid)
250
+ nstate = F0;
251
+ else nstate = IDLE;
252
+ end else nstate = DLAST;
253
+ default:nstate = IDLE;
254
+ endcase
255
+
256
+ //---->> STATUS SEQUEN CTRL <<---------------------
257
+ localparam CSIZE = FIELD_LENGTH <= 8 ? 3 :
258
+ FIELD_LENGTH <= 16 ? 4 :
259
+ FIELD_LENGTH <= 32 ? 5 :
260
+ FIELD_LENGTH <= 64 ? 6 :
261
+ FIELD_LENGTH <= 128? 7 :
262
+ FIELD_LENGTH <= 512? 8 :
263
+ FIELD_LENGTH <= 1024?9 : 16;
264
+
265
+ logic[CSIZE-1:0] cnt;
266
+ reg[2:0] subcnt;
267
+
268
+ always@(posedge clock/*,negedge rst_n*/)
269
+ if(~rst_n) cnt <= {CSIZE{1'b0}};
270
+ else
271
+ case(nstate)
272
+ IDLE,DLAST:
273
+ cnt <= {CSIZE{1'b0}};
274
+ default:begin
275
+ // if(parse_stream.axis_tready && parse_stream.axis_tvalid && parse_stream.aclken && enable && cnt == '0)
276
+ // cnt <= cnt + 1'b1;
277
+ // else if(parse_stream.axis_tready && parse_stream.axis_tvalid && parse_stream.aclken && cnt != '0)
278
+ // cnt <= cnt + 1'b1;
279
+ // else cnt <= cnt;
280
+
281
+ if(parse_stream.axis_tready && parse_stream.axis_tvalid && parse_stream.aclken)
282
+ cnt <= cnt + 1'b1;
283
+ else cnt <= cnt;
284
+ end
285
+ endcase
286
+
287
+ always@(posedge clock/*,negedge rst_n*/)begin
288
+ f0_pack_ok <= parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F0_SUM_LEN - 1;
289
+ f1_pack_ok <= parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F1_SUM_LEN - 1;
290
+ f2_pack_ok <= parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F2_SUM_LEN - 1;
291
+ f3_pack_ok <= parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F3_SUM_LEN - 1;
292
+ f4_pack_ok <= parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F4_SUM_LEN - 1;
293
+ f5_pack_ok <= parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F5_SUM_LEN - 1;
294
+ f6_pack_ok <= parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F6_SUM_LEN - 1;
295
+ f7_pack_ok <= parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F7_SUM_LEN - 1;
296
+ f8_pack_ok <= parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F8_SUM_LEN - 1;
297
+ f9_pack_ok <= parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F9_SUM_LEN - 1;
298
+ f10_pack_ok <= parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F10_SUM_LEN- 1;
299
+ f11_pack_ok <= parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F11_SUM_LEN- 1;
300
+ f12_pack_ok <= parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F12_SUM_LEN- 1;
301
+ f13_pack_ok <= parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F13_SUM_LEN- 1;
302
+ f14_pack_ok <= parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F14_SUM_LEN- 1;
303
+ f15_pack_ok <= parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F15_SUM_LEN- 1;
304
+ end
305
+
306
+ assign last_part_ok = (parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && parse_stream.axis_tlast) || no_data;
307
+
308
+ always@(posedge clock/*,negedge rst_n*/)
309
+ if(~rst_n) force_jump <= 1'b0;
310
+ else begin
311
+ if(last_part_ok)
312
+ force_jump <= 1'b1;
313
+ else if(parse_stream.aclken)
314
+ force_jump <= 1'b0;
315
+ else force_jump <= force_jump;
316
+ end
317
+
318
+ always@(posedge clock/*,negedge rst_n*/)
319
+ if(~rst_n) no_data <= 1'b0;
320
+ else
321
+ case(nstate)
322
+ IDLE: no_data <= 1'b0;
323
+ F0 ,
324
+ F1 ,
325
+ F2 ,
326
+ F3 ,
327
+ F4 ,
328
+ F5 ,
329
+ F6 ,
330
+ F7 ,
331
+ F8 ,
332
+ F9 ,
333
+ F10,
334
+ F11,
335
+ F12,
336
+ F13,
337
+ F14,
338
+ F15: no_data <= parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && parse_stream.axis_tlast;
339
+ default: no_data <= no_data;
340
+ endcase
341
+
342
+ //----<< STATUS SEQUEN CTRL >>---------------------
343
+ //---->> SUB SEQUEN CTRL <<------------------------
344
+
345
+ always@(posedge clock/*,negedge rst_n*/)
346
+ if(~rst_n) subcnt <= 3'd0;
347
+ else begin
348
+ if( parse_stream.aclken)begin
349
+ case(nstate)
350
+ IDLE,DONE,DLAST:
351
+ subcnt <= 3'd0;
352
+ default:begin
353
+ if(parse_stream.axis_tready && parse_stream.axis_tvalid)begin
354
+ if(~parse_stream.axis_tlast)begin
355
+ case(cnt)
356
+ (F0_SUM_LEN - 1),
357
+ (F1_SUM_LEN - 1),
358
+ (F2_SUM_LEN - 1),
359
+ (F3_SUM_LEN - 1),
360
+ (F4_SUM_LEN - 1),
361
+ (F5_SUM_LEN - 1),
362
+ (F6_SUM_LEN - 1),
363
+ (F7_SUM_LEN - 1),
364
+ (F8_SUM_LEN - 1),
365
+ (F9_SUM_LEN - 1),
366
+ (F10_SUM_LEN- 1),
367
+ (F11_SUM_LEN- 1),
368
+ (F12_SUM_LEN- 1),
369
+ (F13_SUM_LEN- 1),
370
+ (F14_SUM_LEN- 1),
371
+ (F15_SUM_LEN- 1): subcnt <= 3'd0;
372
+ default: subcnt <= subcnt + 1'b1;
373
+ endcase
374
+ end else subcnt <= 3'd0;
375
+ end else subcnt <= subcnt;
376
+ end
377
+ endcase
378
+ end else subcnt <= subcnt;
379
+ end
380
+ //----<< SUB SEQUEN CTRL >>------------------------
381
+ //---->> RD DATA <<--------------------------------
382
+
383
+ always@(posedge clock/*,negedge rst_n*/)
384
+ if(~rst_n) begin
385
+ f0_value <= '0;
386
+ f1_value <= '0;
387
+ f2_value <= '0;
388
+ f3_value <= '0;
389
+ f4_value <= '0;
390
+ f5_value <= '0;
391
+ f6_value <= '0;
392
+ f7_value <= '0;
393
+ f8_value <= '0;
394
+ f9_value <= '0;
395
+ f10_value <= '0;
396
+ f11_value <= '0;
397
+ f12_value <= '0;
398
+ f13_value <= '0;
399
+ f14_value <= '0;
400
+ f15_value <= '0;
401
+ end else
402
+ if(parse_stream.axis_tready && parse_stream.axis_tvalid)begin
403
+ case(nstate)
404
+ F0 : f0_value[(F0_LEN-subcnt)*DSIZE-1-:DSIZE] <= enable? parse_stream.axis_tdata : f0_value[(F0_LEN-subcnt)*DSIZE-1-:DSIZE] ;
405
+ F1 : f1_value[( F1_LEN-0-subcnt)*DSIZE-1-:DSIZE] <= enable? parse_stream.axis_tdata : f1_value[( F1_LEN-0-subcnt)*DSIZE-1-:DSIZE];
406
+ F2 : f2_value[( F2_LEN-0-subcnt)*DSIZE-1-:DSIZE] <= enable? parse_stream.axis_tdata : f2_value[( F2_LEN-0-subcnt)*DSIZE-1-:DSIZE];
407
+ F3 : f3_value[( F3_LEN-0-subcnt)*DSIZE-1-:DSIZE] <= enable? parse_stream.axis_tdata : f3_value[( F3_LEN-0-subcnt)*DSIZE-1-:DSIZE];
408
+ F4 : f4_value[( F4_LEN-0-subcnt)*DSIZE-1-:DSIZE] <= enable? parse_stream.axis_tdata : f4_value[( F4_LEN-0-subcnt)*DSIZE-1-:DSIZE];
409
+ F5 : f5_value[( F5_LEN-0-subcnt)*DSIZE-1-:DSIZE] <= enable? parse_stream.axis_tdata : f5_value[( F5_LEN-0-subcnt)*DSIZE-1-:DSIZE];
410
+ F6 : f6_value[( F6_LEN-0-subcnt)*DSIZE-1-:DSIZE] <= enable? parse_stream.axis_tdata : f6_value[( F6_LEN-0-subcnt)*DSIZE-1-:DSIZE];
411
+ F7 : f7_value[( F7_LEN-0-subcnt)*DSIZE-1-:DSIZE] <= enable? parse_stream.axis_tdata : f7_value[( F7_LEN-0-subcnt)*DSIZE-1-:DSIZE];
412
+ F8 : f8_value[( F8_LEN-0-subcnt)*DSIZE-1-:DSIZE] <= enable? parse_stream.axis_tdata : f8_value[( F8_LEN-0-subcnt)*DSIZE-1-:DSIZE];
413
+ F9 : f9_value[( F9_LEN-0-subcnt)*DSIZE-1-:DSIZE] <= enable? parse_stream.axis_tdata : f9_value[( F9_LEN-0-subcnt)*DSIZE-1-:DSIZE];
414
+ F10: f10_value[(F10_LEN-0-subcnt)*DSIZE-1-:DSIZE] <= enable? parse_stream.axis_tdata : f10_value[(F10_LEN-0-subcnt)*DSIZE-1-:DSIZE];
415
+ F11: f11_value[(F11_LEN-0-subcnt)*DSIZE-1-:DSIZE] <= enable? parse_stream.axis_tdata : f11_value[(F11_LEN-0-subcnt)*DSIZE-1-:DSIZE];
416
+ F12: f12_value[(F12_LEN-0-subcnt)*DSIZE-1-:DSIZE] <= enable? parse_stream.axis_tdata : f12_value[(F12_LEN-0-subcnt)*DSIZE-1-:DSIZE];
417
+ F13: f13_value[(F13_LEN-0-subcnt)*DSIZE-1-:DSIZE] <= enable? parse_stream.axis_tdata : f13_value[(F13_LEN-0-subcnt)*DSIZE-1-:DSIZE];
418
+ F14: f14_value[(F14_LEN-0-subcnt)*DSIZE-1-:DSIZE] <= enable? parse_stream.axis_tdata : f14_value[(F14_LEN-0-subcnt)*DSIZE-1-:DSIZE];
419
+ F15: f15_value[(F15_LEN-0-subcnt)*DSIZE-1-:DSIZE] <= enable? parse_stream.axis_tdata : f15_value[(F15_LEN-0-subcnt)*DSIZE-1-:DSIZE];
420
+ default:;
421
+ endcase
422
+ end else begin
423
+ ;
424
+ end
425
+
426
+ //----<< RD DATA >>--------------------------------
427
+ // ---->> AXI STREAM <<-----------------------------
428
+ always@(posedge clock/*,negedge rst_n*/)
429
+ if(~rst_n) cm_tb_m.axis_tdata <= 8'd0;
430
+ else
431
+ case(nstate)
432
+ DONE,DLAST:begin
433
+ if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.aclken)
434
+ cm_tb_m.axis_tdata <= parse_stream.axis_tdata;
435
+ else cm_tb_m.axis_tdata <= cm_tb_m.axis_tdata;
436
+ end
437
+ default:;
438
+ endcase
439
+
440
+ //
441
+ always@(posedge clock/*,negedge rst_n*/)
442
+ if(~rst_n) cm_tb_m.axis_tlast <= 1'd0;
443
+ else
444
+ // if(cm_tb_m.axis_tvalid && cm_tb_m.axis_tready && cm_tb_m.aclken)
445
+ case(nstate)
446
+ DLAST:begin
447
+ cm_tb_m.axis_tlast <= 1'd1;
448
+ end
449
+ default:cm_tb_m.axis_tlast <= 1'd0;
450
+ endcase
451
+ // else cm_tb_m.axis_tlast <= cm_tb_m.axis_tlast;
452
+
453
+ always@(posedge clock/*,negedge rst_n*/)
454
+ if(~rst_n) cm_tb_m.axis_tvalid <= 1'd0;
455
+ else begin
456
+ // if(cm_tb_m.axis_tvalid && cm_tb_m.axis_tready && cm_tb_m.aclken)begin
457
+ case(nstate)
458
+ DONE,DLAST:begin
459
+ if(cm_tb_m.aclken)
460
+ cm_tb_m.axis_tvalid <= pipe_valid_func(parse_stream.axis_tvalid,cm_tb_m.axis_tready,cm_tb_m.axis_tvalid);
461
+ else cm_tb_m.axis_tvalid <= cm_tb_m.axis_tvalid;
462
+ end
463
+ default:cm_tb_m.axis_tvalid <= 1'd0;
464
+ endcase
465
+ // end else cm_tb_m.axis_tvalid <= cm_tb_m.axis_tvalid;
466
+ end
467
+ // ---->> AXI STREAM <<-----------------------------
468
+ //----->> OUTD VALID <<-----------------------------
469
+ always@(posedge clock/*,negedge rst_n*/)
470
+ if(~rst_n) out_valid <= 1'b0;
471
+ else begin
472
+ if(parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && parse_stream.axis_tlast)
473
+ out_valid <= 1'b0;
474
+ else
475
+ case(FIELD_TOTLE)
476
+ 1 : out_valid <= (parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F0_SUM_LEN - 1) || out_valid;
477
+ 2 : out_valid <= (parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F1_SUM_LEN - 1) || out_valid;
478
+ 3 : out_valid <= (parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F2_SUM_LEN - 1) || out_valid;
479
+ 4 : out_valid <= (parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F3_SUM_LEN - 1) || out_valid;
480
+ 5 : out_valid <= (parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F4_SUM_LEN - 1) || out_valid;
481
+ 6 : out_valid <= (parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F5_SUM_LEN - 1) || out_valid;
482
+ 7 : out_valid <= (parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F6_SUM_LEN - 1) || out_valid;
483
+ 8 : out_valid <= (parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F7_SUM_LEN - 1) || out_valid;
484
+ 9 : out_valid <= (parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F8_SUM_LEN - 1) || out_valid;
485
+ 10: out_valid <= (parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F9_SUM_LEN - 1) || out_valid;
486
+ 11: out_valid <= (parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F10_SUM_LEN- 1) || out_valid;
487
+ 12: out_valid <= (parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F11_SUM_LEN- 1) || out_valid;
488
+ 13: out_valid <= (parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F12_SUM_LEN- 1) || out_valid;
489
+ 14: out_valid <= (parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F13_SUM_LEN- 1) || out_valid;
490
+ 15: out_valid <= (parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F14_SUM_LEN- 1) || out_valid;
491
+ 16: out_valid <= (parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F15_SUM_LEN- 1) || out_valid;
492
+ default:;
493
+ endcase
494
+ end
495
+ //-----<< OUTD VALID >>-----------------------------
496
+ //--->> SIM <<--------------------------------------
497
+ // string str = "";
498
+ //
499
+ // always@(*)
500
+ // case(cstate)
501
+ // F0 : str = F0_NAME;
502
+ // F1 : str = F1_NAME;
503
+ // F2 : str = F2_NAME;
504
+ // F3 : str = F3_NAME;
505
+ // F4 : str = F4_NAME;
506
+ // F5 : str = F5_NAME;
507
+ // F6 : str = F6_NAME;
508
+ // F7 : str = F7_NAME;
509
+ // F8 : str = F8_NAME;
510
+ // F9 : str = F9_NAME;
511
+ // F10: str = F10_NAME;
512
+ // F11: str = F11_NAME;
513
+ // F12: str = F12_NAME;
514
+ // F13: str = F13_NAME;
515
+ // F14: str = F14_NAME;
516
+ // F15: str = F15_NAME;
517
+ // default:str = "IDLE";
518
+ // endcase
519
+ //---<< SIM >>--------------------------------------
520
+
521
+ endmodule