axi_tdl 0.0.2
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- checksums.yaml +7 -0
- data/.gitignore +8 -0
- data/CODE_OF_CONDUCT.md +74 -0
- data/Gemfile +6 -0
- data/Gemfile.lock +43 -0
- data/LICENSE +504 -0
- data/README.md +311 -0
- data/Rakefile +18 -0
- data/axi_tdl.gemspec +43 -0
- data/bin/console +14 -0
- data/bin/setup +8 -0
- data/lib/.rspec +1 -0
- data/lib/axi/AXI4/axi4_combin_wr_rd_batch.sv +59 -0
- data/lib/axi/AXI4/axi4_direct.sv +137 -0
- data/lib/axi/AXI4/axi4_direct_A1.sv +229 -0
- data/lib/axi/AXI4/axi4_direct_B1.sv +74 -0
- data/lib/axi/AXI4/axi4_direct_verb.sv +79 -0
- data/lib/axi/AXI4/axi4_direct_verc.sv +146 -0
- data/lib/axi/AXI4/axi4_dpram_cache.rb +106 -0
- data/lib/axi/AXI4/axi4_dpram_cache.sv +112 -0
- data/lib/axi/AXI4/axi4_long_to_axi4_wide.sv +85 -0
- data/lib/axi/AXI4/axi4_long_to_axi4_wide_A1.sv +96 -0
- data/lib/axi/AXI4/axi4_long_to_axi4_wide_track.sv +118 -0
- data/lib/axi/AXI4/axi4_long_to_axi4_wide_verb.sv +131 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_pipe.sv +44 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_pipe_verb.sv +45 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_rd_pipe.sv +111 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_rd_pipe_verb.sv +113 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_wr_pipe.sv +142 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_wr_pipe_verb.sv +146 -0
- data/lib/axi/AXI4/axi4_rd_auxiliary_batch_gen.sv +134 -0
- data/lib/axi/AXI4/axi4_rd_auxiliary_gen.sv +89 -0
- data/lib/axi/AXI4/axi4_rd_auxiliary_gen_A1.sv +109 -0
- data/lib/axi/AXI4/axi4_rd_burst_track.sv +164 -0
- data/lib/axi/AXI4/axi4_wr_aux_bind_data.sv +121 -0
- data/lib/axi/AXI4/axi4_wr_auxiliary_batch_gen.sv +140 -0
- data/lib/axi/AXI4/axi4_wr_auxiliary_gen.sv +102 -0
- data/lib/axi/AXI4/axi4_wr_auxiliary_gen_without_resp.sv +91 -0
- data/lib/axi/AXI4/axi4_wr_burst_track.sv +146 -0
- data/lib/axi/AXI4/axi_stream_add_addr_len.sv +50 -0
- data/lib/axi/AXI4/axi_stream_to_axi4_wr.sv +61 -0
- data/lib/axi/AXI4/axi_stream_to_axi4_wr_verb.sv.bak +123 -0
- data/lib/axi/AXI4/axis_to_axi4_wr.rb +149 -0
- data/lib/axi/AXI4/axis_to_axi4_wr.sv +141 -0
- data/lib/axi/AXI4/full_axi4_to_axis.sv +188 -0
- data/lib/axi/AXI4/full_axi4_to_axis_partition_wr_rd.sv +208 -0
- data/lib/axi/AXI4/id_record.sv +55 -0
- data/lib/axi/AXI4/idata_pool_axi4.sv +110 -0
- data/lib/axi/AXI4/interconnect/AXI4_interconnect_M2S.sv +291 -0
- data/lib/axi/AXI4/interconnect/axi4_mix_interconnect_M2S.sv +72 -0
- data/lib/axi/AXI4/interconnect/axi4_rd_interconnect_M2S.sv +148 -0
- data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S.sv +255 -0
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- data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S_A2.sv +281 -0
- data/lib/axi/AXI4/interconnect/axi4_wr_interconnect_M2S.sv +235 -0
- data/lib/axi/AXI4/interconnect/axi4_wr_interconnect_M2S_A1.sv +283 -0
- data/lib/axi/AXI4/interconnect/axi4_wr_mix_interconnect_M2S.sv +32 -0
- data/lib/axi/AXI4/long_axi4_to_wide_axi4.sv.bak +251 -0
- data/lib/axi/AXI4/odata_pool_axi4.sv +134 -0
- data/lib/axi/AXI4/odata_pool_axi4_A1.sv +165 -0
- data/lib/axi/AXI4/odata_pool_axi4_A2.sv +159 -0
- data/lib/axi/AXI4/odata_pool_axi4_A3.sv +183 -0
- data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo.sv +61 -0
- data/lib/axi/AXI4/packet_fifo/axi4_rd_packet_fifo.sv +282 -0
- data/lib/axi/AXI4/packet_fifo/axi4_wr_packet_fifo.sv +181 -0
- data/lib/axi/AXI4/packet_merge/axi4_merge.sv +60 -0
- data/lib/axi/AXI4/packet_merge/axi4_merge_rd.sv +279 -0
- data/lib/axi/AXI4/packet_merge/axi4_merge_wr.sv +267 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition.sv +36 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_OD.sv +66 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd.sv +211 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_OD.sv +322 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.rb +80 -0
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- data/lib/axi/AXI4/packet_partition/data_inf_partition.rb +293 -0
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- data/lib/axi/AXI4/width_convert/axi4_data_combin_aflag_pipe.sv +239 -0
- data/lib/axi/AXI4/width_convert/axi4_data_combin_aflag_pipe_A1.sv +204 -0
- data/lib/axi/AXI4/width_convert/axi4_data_convert.sv +312 -0
- data/lib/axi/AXI4/width_convert/axi4_data_convert_A1.sv +217 -0
- data/lib/axi/AXI4/width_convert/data_combin.sv +366 -0
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- data/lib/axi/AXI4/width_convert/data_destruct.sv +304 -0
- data/lib/axi/AXI4/width_convert/feed_check.sv +94 -0
- data/lib/axi/AXI4/width_convert/len_convert.sv.bak +61 -0
- data/lib/axi/AXI4/width_convert/odd_width_convert.sv +229 -0
- data/lib/axi/AXI4/width_convert/odd_width_convert_verb.sv +105 -0
- data/lib/axi/AXI4/width_convert/simple_data_pipe.sv +40 -0
- data/lib/axi/AXI4/width_convert/simple_data_pipe_slaver.sv +33 -0
- data/lib/axi/AXI4/width_convert/width_combin.sv +113 -0
- data/lib/axi/AXI4/width_convert/width_convert.sv +87 -0
- data/lib/axi/AXI4/width_convert/width_convert_verb.sv +249 -0
- data/lib/axi/AXI4/width_convert/width_destruct.sv +206 -0
- data/lib/axi/AXI4/width_convert/width_destruct_A1.sv +251 -0
- data/lib/axi/AXI_BFM/AXI_BFM_PKG.sv +1039 -0
- data/lib/axi/AXI_BFM/Data_C_BFM_PKG.sv +97 -0
- data/lib/axi/AXI_BFM/axi4_error_chk.sv +298 -0
- data/lib/axi/AXI_BFM/axi4_illegal_bfm_pkg.sv +607 -0
- data/lib/axi/AXI_BFM/axi_lite_master.sv +102 -0
- data/lib/axi/AXI_BFM/axi_lite_tb.sv +23 -0
- data/lib/axi/AXI_BFM/axi_master.sv +185 -0
- data/lib/axi/AXI_BFM/axi_mirror.sv +266 -0
- data/lib/axi/AXI_BFM/axi_mm_tb.sv +134 -0
- data/lib/axi/AXI_BFM/axi_slaver.sv.bak +340 -0
- data/lib/axi/AXI_BFM/axistreambfm.sv +117 -0
- data/lib/axi/AXI_Lite/axi4_to_lite.sv +36 -0
- data/lib/axi/AXI_Lite/axi_lite_configure.sv +356 -0
- data/lib/axi/AXI_Lite/axi_lite_configure_inf2.sv +365 -0
- data/lib/axi/AXI_Lite/axi_lite_configure_verb.sv.bck +370 -0
- data/lib/axi/AXI_Lite/axi_lite_interconnect_M2S.sv +437 -0
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- data/lib/axi/AXI_Lite/axi_lite_slaver_empty.sv +27 -0
- data/lib/axi/AXI_Lite/axil_direct.sv +52 -0
- data/lib/axi/AXI_Lite/common_configure_reg_interface/common_configure_reg_interface.sv +230 -0
- data/lib/axi/AXI_Lite/common_configure_reg_interface/common_configure_reg_interface.sv.bak +109 -0
- data/lib/axi/AXI_Lite/common_configure_reg_interface/jtag_to_axilite_wrapper.sv +56 -0
- data/lib/axi/AXI_Lite/gen_axi_lite_ctrl.sv +515 -0
- data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_C1.sv +369 -0
- data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_verb.sv +365 -0
- data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_verc.sv +401 -0
- data/lib/axi/AXI_Lite/wr_lite_to_axis.sv +141 -0
- data/lib/axi/AXI_Lite/wr_lite_to_axis.sv.bak +141 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S.sv +76 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_A1.sv +77 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_A2.sv +71 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_bind_tuser.sv +72 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_noaddr.sv +151 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_with_addr.sv +87 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_S2M.sv +65 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_auto.sv +50 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_with_info.sv +64 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_with_keep.sv.bak +64 -0
- data/lib/axi/AXI_stream/axi_stream_packet_fifo_with_info.sv.bak +49 -0
- data/lib/axi/AXI_stream/axi_stream_partition.sv +147 -0
- data/lib/axi/AXI_stream/axi_stream_partition_A1.sv +63 -0
- data/lib/axi/AXI_stream/axi_stream_planer.sv +51 -0
- data/lib/axi/AXI_stream/axi_stream_split_channel.rb +56 -0
- data/lib/axi/AXI_stream/axi_stream_split_channel.sv +149 -0
- data/lib/axi/AXI_stream/axi_streams_combin.sv +151 -0
- data/lib/axi/AXI_stream/axi_streams_combin_A1.sv +179 -0
- data/lib/axi/AXI_stream/axi_streams_scaler.sv +171 -0
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- data/lib/axi/AXI_stream/axis_append.sv +79 -0
- data/lib/axi/AXI_stream/axis_append_A1.sv +82 -0
- data/lib/axi/AXI_stream/axis_base_pipe.sv +184 -0
- data/lib/axi/AXI_stream/axis_combin_with_fifo.sv +69 -0
- data/lib/axi/AXI_stream/axis_connect_pipe.sv +86 -0
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- data/lib/axi/AXI_stream/axis_connect_pipe_left_shift.sv +64 -0
- data/lib/axi/AXI_stream/axis_connect_pipe_right_shift.sv +64 -0
- data/lib/axi/AXI_stream/axis_connect_pipe_right_shift_verb.sv +70 -0
- data/lib/axi/AXI_stream/axis_connect_pipe_with_info.sv +93 -0
- data/lib/axi/AXI_stream/axis_direct.sv +55 -0
- data/lib/axi/AXI_stream/axis_direct_A1.sv +81 -0
- data/lib/axi/AXI_stream/axis_filter.sv +38 -0
- data/lib/axi/AXI_stream/axis_full_to_data_c.sv +26 -0
- data/lib/axi/AXI_stream/axis_head_cut.sv +67 -0
- data/lib/axi/AXI_stream/axis_head_cut_verb.sv +60 -0
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- data/lib/axi/AXI_stream/axis_head_cut_verc.sv +245 -0
- data/lib/axi/AXI_stream/axis_inct_s2m_with_flag.sv +84 -0
- data/lib/axi/AXI_stream/axis_insert_copy.rb +59 -0
- data/lib/axi/AXI_stream/axis_insert_copy.sv +66 -0
- data/lib/axi/AXI_stream/axis_intc_M2S_with_addr_inf.sv +114 -0
- data/lib/axi/AXI_stream/axis_intc_S2M_with_addr_inf.sv +85 -0
- data/lib/axi/AXI_stream/axis_interconnect_S2M_pipe.sv +75 -0
- data/lib/axi/AXI_stream/axis_length_cut.sv +64 -0
- data/lib/axi/AXI_stream/axis_length_fill.sv +194 -0
- data/lib/axi/AXI_stream/axis_length_split.sv +86 -0
- data/lib/axi/AXI_stream/axis_length_split_with_addr.sv +127 -0
- data/lib/axi/AXI_stream/axis_length_split_writh_user.sv +87 -0
- data/lib/axi/AXI_stream/axis_link_trigger.sv +81 -0
- data/lib/axi/AXI_stream/axis_master_empty.sv +26 -0
- data/lib/axi/AXI_stream/axis_mirror_to_master.sv +126 -0
- data/lib/axi/AXI_stream/axis_mirrors.sv +60 -0
- data/lib/axi/AXI_stream/axis_orthogonal.sv +66 -0
- data/lib/axi/AXI_stream/axis_ram_buffer.sv +118 -0
- data/lib/axi/AXI_stream/axis_rom_contect.rb +97 -0
- data/lib/axi/AXI_stream/axis_rom_contect.sv +110 -0
- data/lib/axi/AXI_stream/axis_rom_contect_sim.rb +102 -0
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- data/lib/axi/AXI_stream/axis_slaver_empty.sv +22 -0
- data/lib/axi/AXI_stream/axis_slaver_pipe.sv +84 -0
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- data/lib/axi/AXI_stream/axis_split_channel_verb.rb +42 -0
- data/lib/axi/AXI_stream/axis_split_channel_verb.sv +62 -0
- data/lib/axi/AXI_stream/axis_to_axi4_or_lite.rb +127 -0
- data/lib/axi/AXI_stream/axis_to_axi4_or_lite.sv +153 -0
- data/lib/axi/AXI_stream/axis_to_data_inf.sv +34 -0
- data/lib/axi/AXI_stream/axis_to_lite_rd.sv +81 -0
- data/lib/axi/AXI_stream/axis_to_lite_wr.sv +71 -0
- data/lib/axi/AXI_stream/axis_uncompress.sv +147 -0
- data/lib/axi/AXI_stream/axis_uncompress_A1.sv +150 -0
- data/lib/axi/AXI_stream/axis_uncompress_verb.rb +32 -0
- data/lib/axi/AXI_stream/axis_uncompress_verb.sv +54 -0
- data/lib/axi/AXI_stream/axis_valve.sv +29 -0
- data/lib/axi/AXI_stream/axis_valve_with_pipe.sv +76 -0
- data/lib/axi/AXI_stream/axis_vector_master_empty.rb +11 -0
- data/lib/axi/AXI_stream/axis_vector_master_empty.sv +35 -0
- data/lib/axi/AXI_stream/axis_vector_slaver_empty.rb +11 -0
- data/lib/axi/AXI_stream/axis_vector_slaver_empty.sv +35 -0
- data/lib/axi/AXI_stream/check_stream_crc.sv +28 -0
- data/lib/axi/AXI_stream/data_c_to_axis_full.sv +23 -0
- data/lib/axi/AXI_stream/data_to_axis_inf.sv +103 -0
- data/lib/axi/AXI_stream/data_to_axis_inf_A1.sv +28 -0
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- data/lib/axi/AXI_stream/data_width/axis_width_combin_A1.sv +220 -0
- data/lib/axi/AXI_stream/data_width/axis_width_convert.sv +49 -0
- data/lib/axi/AXI_stream/data_width/axis_width_destruct.sv +82 -0
- data/lib/axi/AXI_stream/data_width/axis_width_destruct_A1.sv +86 -0
- data/lib/axi/AXI_stream/ex_status/axis_ex_status.sv +97 -0
- data/lib/axi/AXI_stream/gen_big_field_table.sv +170 -0
- data/lib/axi/AXI_stream/gen_common_frame_table.sv +382 -0
- data/lib/axi/AXI_stream/gen_common_frame_table_bind_tuser.sv +428 -0
- data/lib/axi/AXI_stream/gen_origin_axis.sv +116 -0
- data/lib/axi/AXI_stream/gen_origin_axis_A1.sv +129 -0
- data/lib/axi/AXI_stream/gen_origin_axis_A2.sv +162 -0
- data/lib/axi/AXI_stream/gen_simple_axis.sv +164 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_long_fifo.sv +132 -0
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- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo.sv +125 -0
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- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1E.sv +198 -0
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- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_B1.sv +82 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_mirror.sv +44 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_verb.sv +58 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_long_cache.sv +55 -0
- data/lib/axi/AXI_stream/stream_crc.sv +67 -0
- data/lib/axi/AXI_stream/vcs_axis_comptable.sv +73 -0
- data/lib/axi/LICENSE +504 -0
- data/lib/axi/ReadME.md +6 -0
- data/lib/axi/SIM/tb_axi4_partition_20201105.sv +115 -0
- data/lib/axi/SIM/tb_axis_bfm_0504.sv +61 -0
- data/lib/axi/SIM/tb_axis_partitiom_0929.sv +102 -0
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- data/lib/axi/SIM/tb_axis_to_axi4_0925.sv +107 -0
- data/lib/axi/SIM/tb_data_c_m2s_inf_20200114.sv +222 -0
- data/lib/axi/SIM/tb_data_c_m2s_inf_20201103.sv +245 -0
- data/lib/axi/SIM/tb_data_c_pipe_inf_20180417.sv +114 -0
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- data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_gen_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_gen_without_resp_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_wr_burst_track_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_wr_interconnect_M2S_A1_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_wr_interconnect_M2S_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_wr_mix_interconnect_M2S_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_wr_packet_fifo_sdl.rb +11 -0
- data/lib/tdl/SDL/axi4/axi4_wr_pipe_sdl.rb +9 -0
- data/lib/tdl/SDL/axi4/axi4_wr_pipe_verb_sdl.rb +9 -0
- data/lib/tdl/SDL/axi4/axi_stream_add_addr_len_sdl.rb +11 -0
- data/lib/tdl/SDL/axi4/axi_stream_to_axi4_wr_sdl.rb +9 -0
- data/lib/tdl/SDL/axi4/data_combin_sdl.rb +20 -0
- data/lib/tdl/SDL/axi4/data_destruct_sdl.rb +19 -0
- data/lib/tdl/SDL/axi4/feed_check_sdl.rb +18 -0
- data/lib/tdl/SDL/axi4/full_axi4_to_axis_partition_wr_rd_sdl.rb +11 -0
- data/lib/tdl/SDL/axi4/full_axi4_to_axis_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/id_record_sdl.rb +19 -0
- data/lib/tdl/SDL/axi4/idata_pool_axi4_sdl.rb +18 -0
- data/lib/tdl/SDL/axi4/odata_pool_axi4_A1_sdl.rb +13 -0
- data/lib/tdl/SDL/axi4/odata_pool_axi4_A2_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/odata_pool_axi4_sdl.rb +19 -0
- data/lib/tdl/SDL/axi4/odd_width_convert_sdl.rb +19 -0
- data/lib/tdl/SDL/axi4/odd_width_convert_verb_sdl.rb +19 -0
- data/lib/tdl/SDL/axi4/simple_data_pipe_sdl.rb +16 -0
- data/lib/tdl/SDL/axi4/simple_data_pipe_slaver_sdl.rb +16 -0
- data/lib/tdl/SDL/axi4/vcs_axi4_array_comptable.rb +9 -0
- data/lib/tdl/SDL/axi4/vcs_axi4_array_comptable_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/vcs_axi4_comptable.rb +8 -0
- data/lib/tdl/SDL/axi4/vcs_axi4_comptable_sdl.rb +9 -0
- data/lib/tdl/SDL/axi4/width_combin_sdl.rb +20 -0
- data/lib/tdl/SDL/axi4/width_convert_sdl.rb +20 -0
- data/lib/tdl/SDL/axi4/width_convert_verb_sdl.rb +20 -0
- data/lib/tdl/SDL/axi4/width_destruct_A1_sdl.rb +22 -0
- data/lib/tdl/SDL/axi4/width_destruct_sdl.rb +19 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_35bit_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_36_71bit_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_72_95bit_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_72_95bit_with_keep_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_96_143bit_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_B1_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_mirror_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_verb_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_A1_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_A2_sdl.rb +13 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_bind_tuser_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_noaddr_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_with_addr_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_S2M_auto_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_S2M_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axi_stream_long_cache_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axi_stream_long_fifo_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axi_stream_long_fifo_verb_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_B1E_sdl.rb +16 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_B1_sdl.rb +14 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_verb_sdl.rb +13 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_with_info_sdl.rb +13 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_long_fifo_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axi_stream_partition_A1_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axi_stream_partition_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axi_stream_wide_fifo_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axi_streams_combin_A1_sdl.rb +15 -0
- data/lib/tdl/SDL/axistream/axi_streams_combin_sdl.rb +16 -0
- data/lib/tdl/SDL/axistream/axi_streams_scaler_A1_sdl.rb +14 -0
- data/lib/tdl/SDL/axistream/axi_streams_scaler_sdl.rb +15 -0
- data/lib/tdl/SDL/axistream/axis_append_A1_sdl.rb +18 -0
- data/lib/tdl/SDL/axistream/axis_append_sdl.rb +17 -0
- data/lib/tdl/SDL/axistream/axis_base_pipe_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_combin_with_fifo_sdl.rb +14 -0
- data/lib/tdl/SDL/axistream/axis_connect_pipe_right_shift_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_connect_pipe_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_connect_pipe_with_info_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axis_direct_A1_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axis_direct_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_ex_status_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axis_filter_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_full_to_data_c_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_head_cut_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_inct_s2m_with_flag_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axis_intc_M2S_with_addr_inf_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axis_intc_S2M_with_addr_inf_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axis_interconnect_S2M_pipe_sdl.rb +15 -0
- data/lib/tdl/SDL/axistream/axis_length_cut_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_length_fill_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_length_split_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_length_split_with_addr_sdl.rb +13 -0
- data/lib/tdl/SDL/axistream/axis_length_split_writh_user_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_link_trigger_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axis_master_empty_sdl.rb +8 -0
- data/lib/tdl/SDL/axistream/axis_mirror_to_master_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_mirrors_sdl.rb +14 -0
- data/lib/tdl/SDL/axistream/axis_orthogonal_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_pkt_fifo_filter_keep_A1_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_pkt_fifo_filter_keep_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_ram_buffer_sdl.rb +13 -0
- data/lib/tdl/SDL/axistream/axis_slaver_empty_sdl.rb +8 -0
- data/lib/tdl/SDL/axistream/axis_slaver_pipe_A1_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_slaver_pipe_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_slaver_vector_empty_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_to_data_inf_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_to_lite_rd_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axis_to_lite_wr_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_uncompress_A1_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axis_uncompress_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axis_valve_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_valve_with_pipe_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axis_width_combin_A1_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_width_combin_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_width_convert_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_width_destruct_A1_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_width_destruct_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/check_stream_crc_sdl.rb +8 -0
- data/lib/tdl/SDL/axistream/data_c_to_axis_full_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/data_to_axis_inf_A1_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/data_to_axis_inf_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/gen_big_field_table_sdl.rb +14 -0
- data/lib/tdl/SDL/axistream/gen_common_frame_table_sdl.rb +60 -0
- data/lib/tdl/SDL/axistream/gen_origin_axis_A1_sdl.rb +13 -0
- data/lib/tdl/SDL/axistream/gen_origin_axis_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/gen_simple_axis_sdl.rb +13 -0
- data/lib/tdl/SDL/axistream/parse_big_field_table_A1_sdl.rb +17 -0
- data/lib/tdl/SDL/axistream/parse_big_field_table_A2_sdl.rb +17 -0
- data/lib/tdl/SDL/axistream/parse_big_field_table_sdl.rb +17 -0
- data/lib/tdl/SDL/axistream/stream_crc_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/vcs_axis_comptable.rb +16 -0
- data/lib/tdl/SDL/axistream/vcs_axis_comptable_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_bind_sdl.rb +10 -0
- data/lib/tdl/SDL/data_inf_c/data_c_cache_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_c_direct_mirror_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_c_direct_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_c_intc_M2S_force_robin_sdl.rb +10 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_force_vld_bind_data_sdl.rb +13 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_force_vld_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_A1_sdl.rb +10 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_right_shift_sdl.rb +13 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_C1_sdl.rb +14 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_C1_with_id_sdl.rb +16 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_sdl.rb +13 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_with_addr_sdl.rb +13 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_with_id_sdl.rb +15 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_latency_sdl.rb +10 -0
- data/lib/tdl/SDL/data_inf_c/data_c_scaler_A1_sdl.rb +16 -0
- data/lib/tdl/SDL/data_inf_c/data_c_scaler_sdl.rb +15 -0
- data/lib/tdl/SDL/data_inf_c/data_c_tmp_cache_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_condition_mirror_sdl.rb +13 -0
- data/lib/tdl/SDL/data_inf_c/data_condition_valve_sdl.rb +13 -0
- data/lib/tdl/SDL/data_inf_c/data_connect_pipe_inf_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_connect_pipe_sdl.rb +17 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_A2B_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_B2A_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_M2S_with_addr_and_id_sdl.rb +17 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_M2S_with_id_sdl.rb +15 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_A1_sdl.rb +13 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_sdl.rb +12 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_with_lazy_sdl.rb +15 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_interconnect_M2S_sdl.rb +12 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_pipe_condition_sdl.rb +10 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_A1.rb +12 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_A1_sdl.rb +14 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_sdl.rb +13 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_cross_clk_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_force_addr_with_id_sdl.rb +19 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_prio_sdl.rb +14 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_prio_with_id_sdl.rb +17 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_interconnect_M2S_noaddr_sdl.rb +14 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_interconnect_M2S_with_id_noaddr_sdl.rb +17 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_planer_A1_sdl.rb +15 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_planer_sdl.rb +14 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_ticktock_sdl.rb +18 -0
- data/lib/tdl/SDL/data_inf_c/data_intc_M2S_force_robin_sdl.rb +10 -0
- data/lib/tdl/SDL/data_inf_c/data_mirrors_sdl.rb +14 -0
- data/lib/tdl/SDL/data_inf_c/data_pair_map_A1_sdl.rb +16 -0
- data/lib/tdl/SDL/data_inf_c/data_pair_map_A2_sdl.rb +19 -0
- data/lib/tdl/SDL/data_inf_c/data_pair_map_sdl.rb +14 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_A1_sdl.rb +19 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_sdl.rb +17 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_verb_sdl.rb +16 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_A1_sdl.rb +19 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_sdl.rb +16 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_verb_sdl.rb +15 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_sdl.rb +23 -0
- data/lib/tdl/SDL/data_inf_c/data_streams_combin_A1_sdl.rb +20 -0
- data/lib/tdl/SDL/data_inf_c/data_streams_combin_sdl.rb +20 -0
- data/lib/tdl/SDL/data_inf_c/data_streams_scaler_sdl.rb +19 -0
- data/lib/tdl/SDL/data_inf_c/data_uncompress_sdl.rb +11 -0
- data/lib/tdl/SDL/data_inf_c/data_valve_sdl.rb +10 -0
- data/lib/tdl/SDL/data_inf_c/datainf_c_master_empty_sdl.rb +8 -0
- data/lib/tdl/SDL/data_inf_c/datainf_c_slaver_empty_sdl.rb +8 -0
- data/lib/tdl/SDL/data_inf_c/datainf_master_empty_sdl.rb +8 -0
- data/lib/tdl/SDL/data_inf_c/datainf_slaver_empty_sdl.rb +8 -0
- data/lib/tdl/SDL/data_inf_c/latency_sdl.rb +8 -0
- data/lib/tdl/SDL/data_inf_c/next_prio_sdl.rb +12 -0
- data/lib/tdl/SDL/data_inf_c/part_data_pair_map_sdl.rb +19 -0
- data/lib/tdl/SDL/data_inf_c/trigger_data_inf_c_A1_sdl.rb +11 -0
- data/lib/tdl/SDL/data_inf_c/trigger_data_inf_c_sdl.rb +11 -0
- data/lib/tdl/SDL/data_inf_c/trigger_ready_ctrl_sdl.rb +12 -0
- data/lib/tdl/SDL/data_inf_c/vcs_data_c_comptable.rb +8 -0
- data/lib/tdl/SDL/data_inf_c/vcs_data_c_comptable_sdl.rb +9 -0
- data/lib/tdl/SDL/fifo/common_fifo_sdl.rb +20 -0
- data/lib/tdl/SDL/fifo/common_stack_sdl.rb +14 -0
- data/lib/tdl/SDL/fifo/independent_clock_fifo_a1_sdl.rb +21 -0
- data/lib/tdl/SDL/fifo/independent_clock_fifo_sdl.rb +20 -0
- data/lib/tdl/SDL/fifo/independent_stack_sdl.rb +18 -0
- data/lib/tdl/SDL/path_lib.rb +6 -0
- data/lib/tdl/VideoInf/simple_video_gen.rb +46 -0
- data/lib/tdl/VideoInf/video_from_axi4.rb +108 -0
- data/lib/tdl/VideoInf/video_lib.rb +8 -0
- data/lib/tdl/VideoInf/video_stream_2_axi_stream.rb +67 -0
- data/lib/tdl/VideoInf/video_to_axi4.rb +75 -0
- data/lib/tdl/auto_script/auto_gen_tdl.rb +49 -0
- data/lib/tdl/auto_script/autogensdl.rb +289 -0
- data/lib/tdl/auto_script/autogentdl_a2.rb +452 -0
- data/lib/tdl/auto_script/import_hdl.rb +35 -0
- data/lib/tdl/auto_script/import_sdl.rb +26 -0
- data/lib/tdl/auto_script/test_autogensdl.rb +73 -0
- data/lib/tdl/auto_script/tmp.rb +6 -0
- data/lib/tdl/auto_script/tmp/hdl_test_sdl.rb +12 -0
- data/lib/tdl/axi4/axi4_combin_wr_rd_batch_auto.rb +79 -0
- data/lib/tdl/axi4/axi4_direct.rb +36 -0
- data/lib/tdl/axi4/axi4_direct_A1_auto.rb +137 -0
- data/lib/tdl/axi4/axi4_direct_auto.rb +79 -0
- data/lib/tdl/axi4/axi4_direct_verb_auto.rb +71 -0
- data/lib/tdl/axi4/axi4_interconnect_verb.rb +323 -0
- data/lib/tdl/axi4/axi4_lib.rb +9 -0
- data/lib/tdl/axi4/axi4_long_to_axi4_wide_A1_auto.rb +79 -0
- data/lib/tdl/axi4/axi4_long_to_axi4_wide_auto.rb +71 -0
- data/lib/tdl/axi4/axi4_long_to_axi4_wide_verb_auto.rb +86 -0
- data/lib/tdl/axi4/axi4_packet_fifo_auto.rb +155 -0
- data/lib/tdl/axi4/axi4_pipe_auto.rb +127 -0
- data/lib/tdl/axi4/axi4_pipe_verb_auto.rb +127 -0
- data/lib/tdl/axi4/axi4_rd_auxiliary_gen_auto.rb +71 -0
- data/lib/tdl/axi4/axi4_wr_auxiliary_gen_without_resp_auto.rb +78 -0
- data/lib/tdl/axi4/axis_to_axi4_wr_auto.rb +85 -0
- data/lib/tdl/axi4/bak/__axi4_wr_auxiliary_gen_without_resp.rb +175 -0
- data/lib/tdl/axi4/bak/axi4_combin_wr_rd_batch_auto.rb +153 -0
- data/lib/tdl/axi4/bak/axi4_data_convert.rb +74 -0
- data/lib/tdl/axi4/bak/axi4_direct_auto.rb +153 -0
- data/lib/tdl/axi4/bak/axi4_direct_verb_auto.rb +126 -0
- data/lib/tdl/axi4/bak/axi4_interconnect.rb.bak +91 -0
- data/lib/tdl/axi4/bak/axi4_long_to_axi4_wide_A1_auto.rb +153 -0
- data/lib/tdl/axi4/bak/axi4_long_to_axi4_wide_auto.rb +126 -0
- data/lib/tdl/axi4/bak/axi4_long_to_axi4_wide_verb_auto.rb +179 -0
- data/lib/tdl/axi4/bak/axi4_packet_fifo.rb.bak +75 -0
- data/lib/tdl/axi4/bak/axi4_packet_fifo_auto.rb +259 -0
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- data/lib/tdl/examples/11_test_unit/dve.tcl +64 -0
- data/lib/tdl/examples/11_test_unit/exp_test_unit.rb +58 -0
- data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +35 -0
- data/lib/tdl/examples/11_test_unit/exp_test_unit_constraints.xdc +25 -0
- data/lib/tdl/examples/11_test_unit/modules/sub_md0.rb +23 -0
- data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +41 -0
- data/lib/tdl/examples/11_test_unit/modules/sub_md1.rb +25 -0
- data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv +41 -0
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +28 -0
- data/lib/tdl/examples/11_test_unit/tu0.sv +38 -0
- data/lib/tdl/examples/11_test_unit/tu1.sv +28 -0
- data/lib/tdl/examples/1_define_module/example1.rb +39 -0
- data/lib/tdl/examples/1_define_module/exmple_md.sv +50 -0
- data/lib/tdl/examples/2_hdl_class/always_comb.rb +99 -0
- data/lib/tdl/examples/2_hdl_class/always_ff.rb +143 -0
- data/lib/tdl/examples/2_hdl_class/case.rb +93 -0
- data/lib/tdl/examples/2_hdl_class/foreach.rb +21 -0
- data/lib/tdl/examples/2_hdl_class/function.rb +34 -0
- data/lib/tdl/examples/2_hdl_class/generate.rb +62 -0
- data/lib/tdl/examples/2_hdl_class/module_def.rb +33 -0
- data/lib/tdl/examples/2_hdl_class/module_head_import_package.rb +36 -0
- data/lib/tdl/examples/2_hdl_class/module_instance_test.rb +13 -0
- data/lib/tdl/examples/2_hdl_class/package.rb +29 -0
- data/lib/tdl/examples/2_hdl_class/package2.rb +21 -0
- data/lib/tdl/examples/2_hdl_class/simple_assign.rb +39 -0
- data/lib/tdl/examples/2_hdl_class/state_case.rb +65 -0
- data/lib/tdl/examples/2_hdl_class/struct.rb +25 -0
- data/lib/tdl/examples/2_hdl_class/struct_function.rb +28 -0
- data/lib/tdl/examples/2_hdl_class/test_axi4_M2S.rb +16 -0
- data/lib/tdl/examples/2_hdl_class/test_initial_assert.rb +11 -0
- data/lib/tdl/examples/2_hdl_class/test_inst_sugar.rb +28 -0
- data/lib/tdl/examples/2_hdl_class/test_module_port.rb +47 -0
- data/lib/tdl/examples/2_hdl_class/test_module_var.rb +18 -0
- data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv +108 -0
- data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +35 -0
- data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv +105 -0
- data/lib/tdl/examples/2_hdl_class/tmp/head_pkg_module.sv +42 -0
- data/lib/tdl/examples/2_hdl_class/tmp/init_module.sv +110 -0
- data/lib/tdl/examples/2_hdl_class/tmp/module_instance_test.sv +31 -0
- data/lib/tdl/examples/2_hdl_class/tmp/port_module.sv +99 -0
- data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv +27 -0
- data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv +78 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_axi4_M2S.sv +30 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_foreach.sv +34 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_function.sv +52 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_initial_assert.sv +31 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_inst_sugar.sv +42 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +36 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_port.sv +33 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +35 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +38 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_package2.sv +36 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_struct.sv +38 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_struct_function.sv +44 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +27 -0
- data/lib/tdl/examples/2_hdl_class/tmp/text_generate.sv +54 -0
- data/lib/tdl/examples/2_hdl_class/vcs_string.rb +5 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/hdl_test.sv +13 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/main.rb +26 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/main_md.sv +42 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/sdl_md.sv +30 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/sdl_test.rb +9 -0
- data/lib/tdl/examples/4_generate/example.rb +38 -0
- data/lib/tdl/examples/4_generate/test_generate.sv +59 -0
- data/lib/tdl/examples/5_logic_combin/login_combin.rb +22 -0
- data/lib/tdl/examples/5_logic_combin/test_logic_combin.sv +36 -0
- data/lib/tdl/examples/6_module_with_interface/example.rb +48 -0
- data/lib/tdl/examples/6_module_with_interface/example_interface.sv +40 -0
- data/lib/tdl/examples/6_module_with_interface/inf_collect.rb +54 -0
- data/lib/tdl/examples/6_module_with_interface/inf_collect.sv +63 -0
- data/lib/tdl/examples/7_module_with_package/body_package.rb +3 -0
- data/lib/tdl/examples/7_module_with_package/body_package.sv +25 -0
- data/lib/tdl/examples/7_module_with_package/example_pkg.rb +20 -0
- data/lib/tdl/examples/7_module_with_package/example_pkg.sv +35 -0
- data/lib/tdl/examples/7_module_with_package/head_package.rb +8 -0
- data/lib/tdl/examples/7_module_with_package/head_package.sv +29 -0
- data/lib/tdl/examples/8_top_module/dve.tcl +64 -0
- data/lib/tdl/examples/8_top_module/example.rb +8 -0
- data/lib/tdl/examples/8_top_module/pins.yml +7 -0
- data/lib/tdl/examples/8_top_module/tb_test_top.sv +29 -0
- data/lib/tdl/examples/8_top_module/test_top.sv +28 -0
- data/lib/tdl/examples/8_top_module/test_top_constraints.xdc +37 -0
- data/lib/tdl/examples/9_itegration/A_itgt/a_test_md.sv +29 -0
- data/lib/tdl/examples/9_itegration/A_itgt/a_test_module.rb +6 -0
- data/lib/tdl/examples/9_itegration/A_itgt/itgt_module_a_block.rb +34 -0
- data/lib/tdl/examples/9_itegration/clock_manage/itgt_module_clock_manage.rb +33 -0
- data/lib/tdl/examples/9_itegration/clock_manage/simple_clock.rb +7 -0
- data/lib/tdl/examples/9_itegration/clock_manage/simple_clock.sv +29 -0
- data/lib/tdl/examples/9_itegration/dve.tcl +64 -0
- data/lib/tdl/examples/9_itegration/pins.yml +4 -0
- data/lib/tdl/examples/9_itegration/tb_test_top.sv +29 -0
- data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +29 -0
- data/lib/tdl/examples/9_itegration/test_top.sv +40 -0
- data/lib/tdl/examples/9_itegration/test_top_constraints.xdc +29 -0
- data/lib/tdl/examples/9_itegration/test_tttop.sv +40 -0
- data/lib/tdl/examples/9_itegration/test_tttop_constraints.xdc +29 -0
- data/lib/tdl/examples/9_itegration/top.rb +11 -0
- data/lib/tdl/examples/readme.md +31 -0
- data/lib/tdl/exlib/common_cfg_reg_inf.rb +139 -0
- data/lib/tdl/exlib/constraints.rb +286 -0
- data/lib/tdl/exlib/constraints_verb.rb +304 -0
- data/lib/tdl/exlib/dve_tcl.rb +162 -0
- data/lib/tdl/exlib/element_class_vars.rb +106 -0
- data/lib/tdl/exlib/global_param.rb +108 -0
- data/lib/tdl/exlib/integral_test/bak/integral_test.rb +206 -0
- data/lib/tdl/exlib/integral_test/clock_itest.rb +28 -0
- data/lib/tdl/exlib/integral_test/diff_clock_itest.rb +30 -0
- data/lib/tdl/exlib/integral_test/io_itest.rb +41 -0
- data/lib/tdl/exlib/integral_test/reset_itest.rb +31 -0
- data/lib/tdl/exlib/integral_test/simple_logic_itest.rb +19 -0
- data/lib/tdl/exlib/itegration.rb +307 -0
- data/lib/tdl/exlib/itegration_verb.rb +913 -0
- data/lib/tdl/exlib/parse_argv.rb +43 -0
- data/lib/tdl/exlib/sdlmodule_sim.bak.rb +375 -0
- data/lib/tdl/exlib/test_point.rb +287 -0
- data/lib/tdl/global_scan.rb +134 -0
- data/lib/tdl/rebuild_ele/axi4.rb +141 -0
- data/lib/tdl/rebuild_ele/axi_lite.rb +56 -0
- data/lib/tdl/rebuild_ele/axi_stream.rb +121 -0
- data/lib/tdl/rebuild_ele/cm_ram_inf.sv +105 -0
- data/lib/tdl/rebuild_ele/cm_ram_inf_define.rb +44 -0
- data/lib/tdl/rebuild_ele/data_inf.rb +27 -0
- data/lib/tdl/rebuild_ele/data_inf_c.rb +83 -0
- data/lib/tdl/rebuild_ele/ele_base.rb +822 -0
- data/lib/tdl/rebuild_ele/readme.md +1 -0
- data/lib/tdl/sdlimplement/resource.yml +154 -0
- data/lib/tdl/sdlimplement/sdl_impl_module.rb +391 -0
- data/lib/tdl/sdlimplement/sdl_impl_param.rb +26 -0
- data/lib/tdl/sdlimplement/test.rb +64 -0
- data/lib/tdl/sdlmodule/bak/sdlmodule_varible_ex.rb +120 -0
- data/lib/tdl/sdlmodule/generator_block_module.rb +84 -0
- data/lib/tdl/sdlmodule/sdlmodule.rb +407 -0
- data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb +333 -0
- data/lib/tdl/sdlmodule/sdlmodule_draw.rb +272 -0
- data/lib/tdl/sdlmodule/sdlmodule_head_logo.txt +10 -0
- data/lib/tdl/sdlmodule/sdlmodule_instance.rb +623 -0
- data/lib/tdl/sdlmodule/sdlmodule_port_define.rb +374 -0
- data/lib/tdl/sdlmodule/sdlmodule_varible.rb +160 -0
- data/lib/tdl/sdlmodule/sdlmodule_vcs_comptable.rb +140 -0
- data/lib/tdl/sdlmodule/techbench_module.rb +14 -0
- data/lib/tdl/sdlmodule/test_unit_module.rb +138 -0
- data/lib/tdl/sdlmodule/top_module.rb +543 -0
- data/lib/tdl/tdl.rb +265 -0
- data/lib/tdl/tdlerror/tdlerror.rb +8 -0
- data/lib/tdl/testunit/test_all.rb +4 -0
- data/lib/tdl/testunit/test_array_chain.rb +89 -0
- data/lib/tdl/testunit/test_tmp.rb +47 -0
- metadata +1301 -0
@@ -0,0 +1,50 @@
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/**********************************************
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_______________________________________
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___________ Cook Darwin __________
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_______________________________________
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descript:
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author : Cook.Darwin
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Version: VERA.0.0
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creaded: 2017/3/1
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madified:
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***********************************************/
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`timescale 1ns/1ps
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module axi_stream_add_addr_len (
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input [31:0] addr,
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input [31:0] length,
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axi_stream_inf.slaver axis_in,
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axi_stream_inf.master axis_out
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);
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localparam FIELD_LEN = 64/axis_in.DSIZE + (64%axis_in.DSIZE != 0);
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axi_stream_inf #(.DSIZE(axis_in.DSIZE)) addr_len_inf (.aclk(axis_in.aclk),.aresetn(axis_in.aresetn),.aclken(axis_in.aclken));
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// axi_stream_inf #(.DSIZE(axis_in.DSIZE)) mix_inf (.aclk(axis_in.aclk),.aresetn(axis_in.aresetn),.aclken(axis_in.aclken));
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axi_stream_inf #(.DSIZE(axis_in.DSIZE)) end_inf (.aclk(axis_in.aclk),.aresetn(axis_in.aresetn),.aclken(axis_in.aclken));
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gen_big_field_table #(
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.MASTER_MODE ("OFF" ),
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.DSIZE (axis_in.DSIZE ),
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.FIELD_LEN (FIELD_LEN ), //MAX 16*8
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.FIELD_NAME ("Big Filed" )
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)gen_big_field_table_inst(
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/* input */ .enable (1'b1 ),
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/* input [DSIZE*FIELD_LEN-1:0] */ .value ({addr,length} ),
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/* axi_stream_inf.master */ .cm_tb (addr_len_inf )
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);
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axi_streams_combin #(
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.MODE ("HEAD" ), //HEAD END
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.CUT_OR_COMBIN_BODY ("OFF" ), //ON OFF
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.DSIZE (axis_in.DSIZE )
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)axi_streams_combin_inst(
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/* input [15:0] */ .new_body_len (length[15:0] ),
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/* input */ .trigger_signal (1'b1 ),
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/* axi_stream_inf.slaver */ .head_inf (addr_len_inf ),
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/* axi_stream_inf.slaver */ .body_inf (axis_in ),
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/* axi_stream_inf.slaver */ .end_inf (end_inf ),
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/* axi_stream_inf.master */ .m00 (axis_out )
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);
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endmodule
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/**********************************************
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2
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_______________________________________
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3
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___________ Cook Darwin __________
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4
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_______________________________________
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descript:
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author : Cook.Darwin
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7
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Version: VERA.0.0
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8
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creaded: 2017/3/1
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madified:
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***********************************************/
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`timescale 1ns/1ps
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module axi_stream_to_axi4_wr (
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axi_stream_inf.slaver axis_in,
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axi_inf.master_wr axi_wr_inf
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);
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localparam FIELD_LEN = 64/axis_in.DSIZE + (64%axis_in.DSIZE != 0);
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axi_stream_inf #(.DSIZE(axis_in.DSIZE)) ps_inf (.aclk(axis_in.aclk),.aresetn(axis_in.aresetn),.aclken(axis_in.aclken));
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axi_stream_inf #(.DSIZE(axi_wr_inf.IDSIZE+axi_wr_inf.ASIZE+axi_wr_inf.LSIZE))
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id_add_len_inf (.aclk(axis_in.aclk),.aresetn(axis_in.aresetn),.aclken(axis_in.aclken));
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logic[axis_in.DSIZE*FIELD_LEN-1:0] value;
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logic [31:0] addr;
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logic [31:0] length;
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logic addr_len_vld;
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assign {addr,length} = value[63:0];
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parse_big_field_table #(
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.DSIZE (axis_in.DSIZE ),
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.FIELD_LEN (FIELD_LEN ), //MAX 16*8
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.FIELD_NAME ("Big Filed" ),
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.TRY_PARSE ("OFF" )
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)parse_big_field_table_inst(
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/* input */ .enable (1'b1 ),
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/* input [DSIZE*FIELD_LEN-1:0] */ .value (value ),
|
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/* output logic */ .out_valid (addr_len_vld ),
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/* axi_stream_inf.slaver */ .cm_tb_s (axis_in ),
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/* axi_stream_inf.master */ .cm_tb_m (ps_inf ),
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/* axi_stream_inf.mirror */ .cm_mirror (axis_in )
|
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);
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assign ps_inf.axis_tready = axi_wr_inf.axi_awready || axi_wr_inf.axi_wready;
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assign id_add_len_inf.axis_tvalid = addr_len_vld;
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assign id_add_len_inf.axis_tdata = {{axi_wr_inf.IDSIZE{1'b0}},addr[axi_wr_inf.ASIZE-1:0],length[axi_wr_inf.LSIZE-1:0]};
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axi4_wr_auxiliary_gen axi4_wr_auxiliary_gen_inst(
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/* axi_stream_inf.slaver */ .id_add_len_in (id_add_len_inf ), //tlast is not necessary
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/* axi_inf.master_wr_aux */ .axi_wr_aux (axi_wr_inf )
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);
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assign axi_wr_inf.axi_wdata = ps_inf.axis_tdata;
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assign axi_wr_inf.axi_wvalid = ps_inf.axis_tvalid;
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assign axi_wr_inf.axi_wlast = ps_inf.axis_tlast;
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assign axi_wr_inf.axi_wstrb = '1;
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endmodule
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/**********************************************
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_______________________________________
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___________ Cook Darwin __________
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4
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_______________________________________
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descript:
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author : Cook.Darwin
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7
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Version: VERB.0.0 2017/9/25
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use fifo cache
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creaded: 2017/3/1
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madified:
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***********************************************/
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`timescale 1ns/1ps
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module axi_stream_to_axi4_wr_verb (
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input [31:0] addr,
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15
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axi_stream_inf.slaver axis_in,
|
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axi_inf.master_wr axi_wr_inf
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);
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initial begin
|
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assert(axis_in.DSIZE == axi_wr_inf.DSIZE)
|
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else begin
|
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$error(\n"STREAM DSIZE[%d] MUST EQL AXI4 DSIZE[%d]\n",axis_in.DSIZE,axi_wr_inf.DSIZE);
|
23
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$finish;
|
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end
|
25
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end
|
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27
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parameter MAX_LENGTH = (axis_in.DSIZE <= 8)? 2**11 :
|
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(axis_in.DSIZE <= 16)? 2**10 :
|
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(axis_in.DSIZE <= 32)? 2**9 :
|
30
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(axis_in.DSIZE <= 64)? 2**8 :
|
31
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(axis_in.DSIZE <= 128)? 2**7 :
|
32
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(axis_in.DSIZE <= 256)? 2**6 :
|
33
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(axis_in.DSIZE <= 512)? 2**5 : 2**4;
|
34
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//--->> DATA FIFO <<--------------------------
|
35
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logic data_fifo_empty;
|
36
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logic data_fifo_full;
|
37
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|
38
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axis_valve axis_valve_inst(
|
39
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input button, //[1] OPEN ; [0] CLOSE
|
40
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axi_stream_inf.slaver axis_in,
|
41
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axi_stream_inf.master axis_out
|
42
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);
|
43
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|
44
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long_fifo_verb #(
|
45
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.DSIZE (axis_in.DSIZE+axis_in.KSIZE),
|
46
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.LENGTH (8192)
|
47
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)long_fifo_verb_inst(
|
48
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/* input */ wr_clk (axis_in.aclk ),
|
49
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/* input */ wr_rst (!axis_in.aresetn ),
|
50
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/* input */ rd_clk (axi_wr_inf.axi_aclk ),
|
51
|
+
/* input */ rd_rst (!axi_wr_inf.axi_aresetn ),
|
52
|
+
/* input [DSIZE-1:0] */ din ({axis_in.axis_tkeep,axis_in.axis_tdata} ),
|
53
|
+
/* input */ wr_en (axis_in.axis_tvalid && axis_in.axis_tready ),
|
54
|
+
/* input */ rd_en (),
|
55
|
+
/* output [DSIZE-1:0]*/ dout (),
|
56
|
+
/* output */ full (data_fifo_full ),
|
57
|
+
/* output */ empty (data_fifo_empty )
|
58
|
+
);
|
59
|
+
//---<< DATA FIFO >>--------------------------
|
60
|
+
//----->> SPLIT STREAM <<----------------------------------
|
61
|
+
logic [11:0] cnt;
|
62
|
+
always@(posedge axis_in.aclk,negedge axis_in.aresetn)
|
63
|
+
if(~axis_in.aresetn) cnt <= '0;
|
64
|
+
else begin
|
65
|
+
if(axis_in.axis_tvalid && axis_in.axis_tready && axis_in.axis_tlast)
|
66
|
+
cnt <= '0;
|
67
|
+
else if(axis_in.axis_tvalid && axis_in.axis_tready)begin
|
68
|
+
if(cnt >= MAX_LENGTH - 1)
|
69
|
+
cnt <= '0;
|
70
|
+
else cnt <= cnt + 1'b1;
|
71
|
+
end else begin
|
72
|
+
cnt <= cnt;
|
73
|
+
end
|
74
|
+
end
|
75
|
+
//-----<< SPLIT STREAM >>----------------------------------
|
76
|
+
//----->> LEN FIFO <<--------------------------------------
|
77
|
+
logic len_fifo_wr_en;
|
78
|
+
logic len_fifo_rd_en;
|
79
|
+
logic [11:0] len_fifo_wr_data;
|
80
|
+
logic [11:0] len_fifo_rd_data;
|
81
|
+
logic len_fifo_empty;
|
82
|
+
logic len_fifo_full;
|
83
|
+
|
84
|
+
always@(posedge axis_in.aclk,negedge axis_in.aresetn)
|
85
|
+
if(~axis_in.aresetn) len_fifo_wr_en <= 1'b0;
|
86
|
+
else begin
|
87
|
+
if(axis_in.axis_tvalid && axis_in.axis_tready && axis_in.axis_tlast)
|
88
|
+
len_fifo_wr_en <= 1'b1;
|
89
|
+
else if(axis_in.axis_tvalid && axis_in.axis_tready && (cnt >= MAX_LENGTH - 1) )
|
90
|
+
len_fifo_wr_en <= 1'b1;
|
91
|
+
else
|
92
|
+
len_fifo_wr_en <= 1'b0;
|
93
|
+
end
|
94
|
+
|
95
|
+
always@(posedge axis_in.aclk,negedge axis_in.aresetn)
|
96
|
+
if(~axis_in.aresetn) len_fifo_wr_data <= '0;
|
97
|
+
else begin
|
98
|
+
if(axis_in.axis_tvalid && axis_in.axis_tready && axis_in.axis_tlast)
|
99
|
+
len_fifo_wr_data <= cnt;
|
100
|
+
else if(axis_in.axis_tvalid && axis_in.axis_tready && (cnt >= MAX_LENGTH - 1) )
|
101
|
+
len_fifo_wr_data <= cnt;
|
102
|
+
else
|
103
|
+
len_fifo_wr_data <= len_fifo_wr_data;
|
104
|
+
end
|
105
|
+
|
106
|
+
|
107
|
+
independent_clock_fifo #(
|
108
|
+
.DEPTH (4 ),
|
109
|
+
.DSIZE (12 )
|
110
|
+
)independent_clock_fifo_inst(
|
111
|
+
/* input */ .wr_clk (axis_in.aclk ),
|
112
|
+
/* input */ .wr_rst_n (axis_in.aresetn ),
|
113
|
+
/* input */ .rd_clk (axi_wr_inf.axi_aclk ),
|
114
|
+
/* input */ .rd_rst_n (axi_wr_inf.axi_aresetn ),
|
115
|
+
/* input [DSIZE-1:0] */ .wdata (len_fifo_wr_data ),
|
116
|
+
/* input */ .wr_en (len_fifo_wr_en ),
|
117
|
+
/* output logic[DSIZE-1:0] */ .rdata (len_fifo_rd_data ),
|
118
|
+
/* input */ .rd_en (len_fifo_rd_en ),
|
119
|
+
/* output logic */ .empty (len_fifo_empty ),
|
120
|
+
/* output logic */ .full (len_fifo_full )
|
121
|
+
);
|
122
|
+
//-----<< LEN FIFO >>--------------------------------------
|
123
|
+
endmodule
|
@@ -0,0 +1,149 @@
|
|
1
|
+
# require_relative "../prj_lib"
|
2
|
+
|
3
|
+
## raise TdlError.new("The module have be abandon\n Path:[#{__dir__}]\n Name:[#{__FILE__}]")
|
4
|
+
|
5
|
+
new_m = SdlModule.new(name:File.basename(__FILE__,".rb"),out_sv_path:__dir__)
|
6
|
+
|
7
|
+
# Parameter :ADDR_STEP,1.0
|
8
|
+
new_m.instance_exec do
|
9
|
+
Input :addr,dsize:32
|
10
|
+
Input :max_length,dsize:32
|
11
|
+
# AxiStream().slaver :axis_in
|
12
|
+
# Axi4().master_wr :axi_wr
|
13
|
+
|
14
|
+
port.axis.slaver - 'axis_in'
|
15
|
+
port.axi4.master_wr - 'axi_wr'
|
16
|
+
|
17
|
+
ADDR_STEP = axi_wr.ADDR_STEP
|
18
|
+
|
19
|
+
|
20
|
+
Def().logic(name:"addr_cur",dsize:32)
|
21
|
+
|
22
|
+
axis_region = {clock:axis_in.aclk,reset:axis_in.aresetn,dsize:axis_in.dsize}
|
23
|
+
|
24
|
+
self.ex_up_code =
|
25
|
+
%Q{
|
26
|
+
//int MAX_LENGTH;
|
27
|
+
//assign MAX_LENGTH = (axis_in.DSIZE <= 8)? 2**11 :
|
28
|
+
// (axis_in.DSIZE <= 16)? 2**10 :
|
29
|
+
// (axis_in.DSIZE <= 32)? 2**9 :
|
30
|
+
// (axis_in.DSIZE <= 64)? 2**8 :
|
31
|
+
// (axis_in.DSIZE <= 128)? 2**7 :
|
32
|
+
// (axis_in.DSIZE <= 256)? 2**6 :
|
33
|
+
// (axis_in.DSIZE <= 512)? 2**5 : 2**4;
|
34
|
+
|
35
|
+
initial begin
|
36
|
+
assert(#{axis_in}.DSIZE == #{axi_wr}.DSIZE)
|
37
|
+
else begin
|
38
|
+
$error("STREAM DSIZE should eql AXI4 DSIZE");
|
39
|
+
$finish;
|
40
|
+
end
|
41
|
+
// assert(#{axi_wr}.LSIZE >= $clog2(MAX_LENGTH))
|
42
|
+
// else begin
|
43
|
+
// $error("AXIS LSIZE is too smaller");
|
44
|
+
// $finish;
|
45
|
+
// end
|
46
|
+
end
|
47
|
+
}
|
48
|
+
|
49
|
+
# split_out = AxiStream.axis_length_split_with_addr(
|
50
|
+
# addr_step:ADDR_STEP,
|
51
|
+
# length:max_length,
|
52
|
+
# up_stream:axis_in,
|
53
|
+
# origin_addr:addr,
|
54
|
+
# band_addr:addr_cur,
|
55
|
+
# belong_to_module:self
|
56
|
+
# )
|
57
|
+
|
58
|
+
axis_length_split_with_addr.axis_length_split_with_addr_inst do |h|
|
59
|
+
h.param.ADDR_STEP ADDR_STEP #//1024 := 1
|
60
|
+
h.input[32].origin_addr addr
|
61
|
+
h.input[32].length max_length
|
62
|
+
h.output.logic[32].band_addr addr_cur
|
63
|
+
h.port.axi_stream_inf.slaver.axis_in axis_in
|
64
|
+
h.port.axi_stream_inf.master.axis_out axis_in.copy(name: 'split_out')
|
65
|
+
end
|
66
|
+
|
67
|
+
|
68
|
+
# packet_fifo = Tdl.inst_axi_stream_packet_fifo(
|
69
|
+
# depth:4,
|
70
|
+
# # esize:32,
|
71
|
+
# # info_in: addr_cur,
|
72
|
+
# # info_out: {name:"burst_addr",dsize:32},
|
73
|
+
# axis_in: split_out,
|
74
|
+
# axis_out: {clock:axi_wr.axi_aclk,reset:axi_wr.axi_aresetn,dsize:axi_wr.dsize})
|
75
|
+
|
76
|
+
packet_fifo = Instance(:axi_stream_long_fifo,"axi_stream_long_fifo_inst") do |h|
|
77
|
+
h[:DEPTH] = 8
|
78
|
+
h[:BYTE_DEPTH] = 8192
|
79
|
+
h[:axis_in] = split_out
|
80
|
+
h[:axis_out] = axis_in.copy(name:"long_fifo_axis_out",clock:axi_wr.axi_aclk,reset:axi_wr.axi_aresetn)
|
81
|
+
end
|
82
|
+
|
83
|
+
Def().logic(name: :id,dsize:axi_wr.idsize)
|
84
|
+
Def().logic(name: :addr_s,dsize:axi_wr.asize)
|
85
|
+
Def().logic(name: :len_s,dsize:axi_wr.lsize)
|
86
|
+
|
87
|
+
Instance(:independent_clock_fifo,"independent_clock_fifo_inst") do |h|
|
88
|
+
h[:DEPTH] = 4
|
89
|
+
h[:DSIZE] = "#{axi_wr.idsize} + #{axi_wr.asize} + #{axi_wr.lsize}".to_nq
|
90
|
+
h[:wr_clk] = axis_in.aclk
|
91
|
+
h[:wr_rst_n] = axis_in.aresetn
|
92
|
+
h[:rd_clk] = axi_wr.axi_aclk
|
93
|
+
h[:rd_rst_n] = axi_wr.axi_aresetn
|
94
|
+
h[:wdata] = "{#{id},#{addr_s},#{len_s}}".to_nq
|
95
|
+
h[:wr_en] = packet_fifo[:axis_in].vld_rdy_last
|
96
|
+
h[:rdata] = Def().logic(name:"fifo_rdata",dsize:"#{axi_wr.idsize} + #{axi_wr.asize} + #{axi_wr.lsize}")
|
97
|
+
h[:rd_en] = Def().logic(name:'rd_en')
|
98
|
+
h[:empty] = Def().logic(name:'fifo_empty')
|
99
|
+
h[:full] = Def().logic(name:'fifo_full')
|
100
|
+
end
|
101
|
+
|
102
|
+
axi4_wr_auxiliary = Instance(:axi4_wr_auxiliary_gen_without_resp,"axi4_wr_auxiliary_gen_without_resp_inst") do |h|
|
103
|
+
h[:stream_en] = Def().logic(name:"stream_en")
|
104
|
+
# h[:id_add_len_in] = Def().axi_stream(name:"id_add_len_in",clock:axi_wr.axi_aclk,reset:axi_wr.axi_aresetn,dsize:"#{axi_wr.idsize} + #{axi_wr.asize} + #{axi_wr.lsize}")
|
105
|
+
h[:id_add_len_in] = axi_stream_inf(clock:axi_wr.axi_aclk,reset:axi_wr.axi_aresetn,dsize:"#{axi_wr.idsize} + #{axi_wr.asize} + #{axi_wr.lsize}".to_nq).id_add_len_in
|
106
|
+
h[:axi_wr_aux] = axi_wr
|
107
|
+
end
|
108
|
+
|
109
|
+
|
110
|
+
Always(posedge:axis_in.aclk,negedge:axis_in.aresetn) do
|
111
|
+
IF ~axis_in.aresetn do
|
112
|
+
id <= 0
|
113
|
+
end
|
114
|
+
ELSIF split_out.vld_rdy_last do
|
115
|
+
id <= id + 1
|
116
|
+
end
|
117
|
+
ELSE do
|
118
|
+
id <= id
|
119
|
+
end
|
120
|
+
end
|
121
|
+
|
122
|
+
Assign do
|
123
|
+
addr_s <= addr_cur
|
124
|
+
len_s <= split_out.axis_tcnt
|
125
|
+
axi4_wr_auxiliary[:id_add_len_in].axis_tvalid <= ~independent_clock_fifo_inst[:empty]
|
126
|
+
axi4_wr_auxiliary[:id_add_len_in].axis_tdata <= independent_clock_fifo_inst[:rdata]
|
127
|
+
axi4_wr_auxiliary[:id_add_len_in].axis_tlast <= "1'b1"
|
128
|
+
independent_clock_fifo_inst[:rd_en] <= axi4_wr_auxiliary[:id_add_len_in].axis_tready
|
129
|
+
end
|
130
|
+
|
131
|
+
# pipe_axis = AxiStream.axis_valve_with_pipe(button:axi4_wr_auxiliary[:stream_en],up_stream:packet_fifo[:axis_out])
|
132
|
+
axis_valve_with_pipe.axis_valve_with_pipe_inst do |h|
|
133
|
+
h.parameter.MODE "BOTH"
|
134
|
+
h.input.button axi4_wr_auxiliary[:stream_en] # //[1] OPEN ; [0] CLOSE
|
135
|
+
h.axis_in packet_fifo[:axis_out]
|
136
|
+
h.axis_out packet_fifo[:axis_out].copy(name: 'pipe_axis')
|
137
|
+
end
|
138
|
+
|
139
|
+
Assign do
|
140
|
+
axi_wr.axi_wdata <= pipe_axis.axis_tdata
|
141
|
+
axi_wr.axi_wstrb <= ~pipe_axis.axis_tkeep
|
142
|
+
axi_wr.axi_wvalid <= pipe_axis.axis_tvalid
|
143
|
+
axi_wr.axi_wlast <= pipe_axis.axis_tlast
|
144
|
+
axi_wr.axi_bready <= "1'b1".to_nq
|
145
|
+
pipe_axis.axis_tready <= axi_wr.axi_wready
|
146
|
+
end
|
147
|
+
end
|
148
|
+
|
149
|
+
new_m.gen_sv_module
|
@@ -0,0 +1,141 @@
|
|
1
|
+
/**********************************************
|
2
|
+
_______________________________________
|
3
|
+
___________ Cook Darwin __________
|
4
|
+
_______________________________________
|
5
|
+
descript:
|
6
|
+
author : Cook.Darwin
|
7
|
+
Version: VERA.0.0
|
8
|
+
created: xxxx.xx.xx
|
9
|
+
madified:
|
10
|
+
***********************************************/
|
11
|
+
`timescale 1ns/1ps
|
12
|
+
|
13
|
+
module axis_to_axi4_wr(
|
14
|
+
input logic[31:0] addr,
|
15
|
+
input logic[31:0] max_length,
|
16
|
+
axi_stream_inf.slaver axis_in,
|
17
|
+
axi_inf.master_wr axi_wr
|
18
|
+
);
|
19
|
+
|
20
|
+
//------>> EX CODE <<-------------------
|
21
|
+
|
22
|
+
//int MAX_LENGTH;
|
23
|
+
//assign MAX_LENGTH = (axis_in.DSIZE <= 8)? 2**11 :
|
24
|
+
// (axis_in.DSIZE <= 16)? 2**10 :
|
25
|
+
// (axis_in.DSIZE <= 32)? 2**9 :
|
26
|
+
// (axis_in.DSIZE <= 64)? 2**8 :
|
27
|
+
// (axis_in.DSIZE <= 128)? 2**7 :
|
28
|
+
// (axis_in.DSIZE <= 256)? 2**6 :
|
29
|
+
// (axis_in.DSIZE <= 512)? 2**5 : 2**4;
|
30
|
+
|
31
|
+
initial begin
|
32
|
+
assert(axis_in.DSIZE == axi_wr.DSIZE)
|
33
|
+
else begin
|
34
|
+
$error("STREAM DSIZE should eql AXI4 DSIZE");
|
35
|
+
$finish;
|
36
|
+
end
|
37
|
+
// assert(axi_wr.LSIZE >= $clog2(MAX_LENGTH))
|
38
|
+
// else begin
|
39
|
+
// $error("AXIS LSIZE is too smaller");
|
40
|
+
// $finish;
|
41
|
+
// end
|
42
|
+
end
|
43
|
+
//------<< EX CODE >>-------------------
|
44
|
+
|
45
|
+
//==========================================================================
|
46
|
+
//-------- define ----------------------------------------------------------
|
47
|
+
logic [32-1:0] addr_cur ;
|
48
|
+
logic [axi_wr.IDSIZE-1:0] id ;
|
49
|
+
logic [axi_wr.ASIZE-1:0] addr_s ;
|
50
|
+
logic [axi_wr.LSIZE-1:0] len_s ;
|
51
|
+
logic [axi_wr.IDSIZE + axi_wr.ASIZE + axi_wr.LSIZE-1:0] fifo_rdata ;
|
52
|
+
logic rd_en;
|
53
|
+
logic fifo_empty;
|
54
|
+
logic fifo_full;
|
55
|
+
logic stream_en;
|
56
|
+
axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) split_out (.aclk(axis_in.aclk),.aresetn(axis_in.aresetn),.aclken(1'b1)) ;
|
57
|
+
axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) long_fifo_axis_out (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
|
58
|
+
axi_stream_inf #(.DSIZE(axi_wr.IDSIZE + axi_wr.ASIZE + axi_wr.LSIZE),.USIZE(1)) id_add_len_in (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
|
59
|
+
axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP)) axi_wr_vcs_cp_R442 (.axi_aclk(axi_wr.axi_aclk),.axi_aresetn(axi_wr.axi_aresetn)) ;
|
60
|
+
axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) pipe_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
|
61
|
+
//==========================================================================
|
62
|
+
//-------- instance --------------------------------------------------------
|
63
|
+
axis_length_split_with_addr #(
|
64
|
+
.ADDR_STEP (axi_wr.ADDR_STEP )
|
65
|
+
)axis_length_split_with_addr_inst(
|
66
|
+
/* input */.origin_addr (addr ),
|
67
|
+
/* input */.length (max_length ),
|
68
|
+
/* output */.band_addr (addr_cur ),
|
69
|
+
/* axi_stream_inf.slaver */.axis_in (axis_in ),
|
70
|
+
/* axi_stream_inf.master */.axis_out (split_out )
|
71
|
+
);
|
72
|
+
axi_stream_long_fifo #(
|
73
|
+
.DEPTH (8 ),
|
74
|
+
.BYTE_DEPTH (8192 )
|
75
|
+
)axi_stream_long_fifo_inst(
|
76
|
+
/* axi_stream_inf.slaver */.axis_in (split_out ),
|
77
|
+
/* axi_stream_inf.master */.axis_out (long_fifo_axis_out )
|
78
|
+
);
|
79
|
+
independent_clock_fifo #(
|
80
|
+
.DEPTH (4 ),
|
81
|
+
.DSIZE (axi_wr.IDSIZE + axi_wr.ASIZE + axi_wr.LSIZE )
|
82
|
+
)independent_clock_fifo_inst(
|
83
|
+
/* input */.wr_clk (axis_in.aclk ),
|
84
|
+
/* input */.wr_rst_n (axis_in.aresetn ),
|
85
|
+
/* input */.rd_clk (axi_wr.axi_aclk ),
|
86
|
+
/* input */.rd_rst_n (axi_wr.axi_aresetn ),
|
87
|
+
/* input */.wdata ({id,addr_s,len_s} ),
|
88
|
+
/* input */.wr_en (split_out.axis_tvalid && split_out.axis_tready && split_out.axis_tlast ),
|
89
|
+
/* output */.rdata (fifo_rdata ),
|
90
|
+
/* input */.rd_en (rd_en ),
|
91
|
+
/* output */.empty (fifo_empty ),
|
92
|
+
/* output */.full (fifo_full )
|
93
|
+
);
|
94
|
+
axi4_wr_auxiliary_gen_without_resp axi4_wr_auxiliary_gen_without_resp_inst(
|
95
|
+
/* output */.stream_en (stream_en ),
|
96
|
+
/* axi_stream_inf.slaver */.id_add_len_in (id_add_len_in ),
|
97
|
+
/* axi_inf.master_wr_aux_no_resp */.axi_wr_aux (axi_wr_vcs_cp_R442 )
|
98
|
+
);
|
99
|
+
vcs_axi4_comptable #(
|
100
|
+
.ORIGIN ("master_wr_aux_no_resp" ),
|
101
|
+
.TO ("master_wr" )
|
102
|
+
)vcs_axi4_comptable_axi_wr_aux_R1813_axi_wr_inst(
|
103
|
+
/* input */.origin (axi_wr_vcs_cp_R442 ),
|
104
|
+
/* output */.to (axi_wr )
|
105
|
+
);
|
106
|
+
axis_valve_with_pipe #(
|
107
|
+
.MODE ("BOTH" )
|
108
|
+
)axis_valve_with_pipe_inst(
|
109
|
+
/* input */.button (stream_en ),
|
110
|
+
/* axi_stream_inf.slaver */.axis_in (long_fifo_axis_out ),
|
111
|
+
/* axi_stream_inf.master */.axis_out (pipe_axis )
|
112
|
+
);
|
113
|
+
//==========================================================================
|
114
|
+
//-------- expression ------------------------------------------------------
|
115
|
+
always_ff@(posedge axis_in.aclk,negedge axis_in.aresetn) begin
|
116
|
+
if(~axis_in.aresetn)begin
|
117
|
+
id <= 0;
|
118
|
+
end
|
119
|
+
else if(split_out.axis_tvalid && split_out.axis_tready && split_out.axis_tlast)begin
|
120
|
+
id <= ( id+1);
|
121
|
+
end
|
122
|
+
else begin
|
123
|
+
id <= id;
|
124
|
+
end
|
125
|
+
end
|
126
|
+
|
127
|
+
assign addr_s = addr_cur;
|
128
|
+
assign len_s = split_out.axis_tcnt;
|
129
|
+
assign id_add_len_in.axis_tvalid = ~fifo_empty;
|
130
|
+
assign id_add_len_in.axis_tdata = fifo_rdata;
|
131
|
+
assign id_add_len_in.axis_tlast = "1'b1";
|
132
|
+
assign rd_en = id_add_len_in.axis_tready;
|
133
|
+
|
134
|
+
assign axi_wr.axi_wdata = pipe_axis.axis_tdata;
|
135
|
+
assign axi_wr.axi_wstrb = ~pipe_axis.axis_tkeep;
|
136
|
+
assign axi_wr.axi_wvalid = pipe_axis.axis_tvalid;
|
137
|
+
assign axi_wr.axi_wlast = pipe_axis.axis_tlast;
|
138
|
+
assign axi_wr.axi_bready = 1'b1;
|
139
|
+
assign pipe_axis.axis_tready = axi_wr.axi_wready;
|
140
|
+
|
141
|
+
endmodule
|