axi_tdl 0.0.2

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Files changed (1189) hide show
  1. checksums.yaml +7 -0
  2. data/.gitignore +8 -0
  3. data/CODE_OF_CONDUCT.md +74 -0
  4. data/Gemfile +6 -0
  5. data/Gemfile.lock +43 -0
  6. data/LICENSE +504 -0
  7. data/README.md +311 -0
  8. data/Rakefile +18 -0
  9. data/axi_tdl.gemspec +43 -0
  10. data/bin/console +14 -0
  11. data/bin/setup +8 -0
  12. data/lib/.rspec +1 -0
  13. data/lib/axi/AXI4/axi4_combin_wr_rd_batch.sv +59 -0
  14. data/lib/axi/AXI4/axi4_direct.sv +137 -0
  15. data/lib/axi/AXI4/axi4_direct_A1.sv +229 -0
  16. data/lib/axi/AXI4/axi4_direct_B1.sv +74 -0
  17. data/lib/axi/AXI4/axi4_direct_verb.sv +79 -0
  18. data/lib/axi/AXI4/axi4_direct_verc.sv +146 -0
  19. data/lib/axi/AXI4/axi4_dpram_cache.rb +106 -0
  20. data/lib/axi/AXI4/axi4_dpram_cache.sv +112 -0
  21. data/lib/axi/AXI4/axi4_long_to_axi4_wide.sv +85 -0
  22. data/lib/axi/AXI4/axi4_long_to_axi4_wide_A1.sv +96 -0
  23. data/lib/axi/AXI4/axi4_long_to_axi4_wide_track.sv +118 -0
  24. data/lib/axi/AXI4/axi4_long_to_axi4_wide_verb.sv +131 -0
  25. data/lib/axi/AXI4/axi4_pipe/axi4_pipe.sv +44 -0
  26. data/lib/axi/AXI4/axi4_pipe/axi4_pipe_verb.sv +45 -0
  27. data/lib/axi/AXI4/axi4_pipe/axi4_rd_pipe.sv +111 -0
  28. data/lib/axi/AXI4/axi4_pipe/axi4_rd_pipe_verb.sv +113 -0
  29. data/lib/axi/AXI4/axi4_pipe/axi4_wr_pipe.sv +142 -0
  30. data/lib/axi/AXI4/axi4_pipe/axi4_wr_pipe_verb.sv +146 -0
  31. data/lib/axi/AXI4/axi4_rd_auxiliary_batch_gen.sv +134 -0
  32. data/lib/axi/AXI4/axi4_rd_auxiliary_gen.sv +89 -0
  33. data/lib/axi/AXI4/axi4_rd_auxiliary_gen_A1.sv +109 -0
  34. data/lib/axi/AXI4/axi4_rd_burst_track.sv +164 -0
  35. data/lib/axi/AXI4/axi4_wr_aux_bind_data.sv +121 -0
  36. data/lib/axi/AXI4/axi4_wr_auxiliary_batch_gen.sv +140 -0
  37. data/lib/axi/AXI4/axi4_wr_auxiliary_gen.sv +102 -0
  38. data/lib/axi/AXI4/axi4_wr_auxiliary_gen_without_resp.sv +91 -0
  39. data/lib/axi/AXI4/axi4_wr_burst_track.sv +146 -0
  40. data/lib/axi/AXI4/axi_stream_add_addr_len.sv +50 -0
  41. data/lib/axi/AXI4/axi_stream_to_axi4_wr.sv +61 -0
  42. data/lib/axi/AXI4/axi_stream_to_axi4_wr_verb.sv.bak +123 -0
  43. data/lib/axi/AXI4/axis_to_axi4_wr.rb +149 -0
  44. data/lib/axi/AXI4/axis_to_axi4_wr.sv +141 -0
  45. data/lib/axi/AXI4/full_axi4_to_axis.sv +188 -0
  46. data/lib/axi/AXI4/full_axi4_to_axis_partition_wr_rd.sv +208 -0
  47. data/lib/axi/AXI4/id_record.sv +55 -0
  48. data/lib/axi/AXI4/idata_pool_axi4.sv +110 -0
  49. data/lib/axi/AXI4/interconnect/AXI4_interconnect_M2S.sv +291 -0
  50. data/lib/axi/AXI4/interconnect/axi4_mix_interconnect_M2S.sv +72 -0
  51. data/lib/axi/AXI4/interconnect/axi4_rd_interconnect_M2S.sv +148 -0
  52. data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S.sv +255 -0
  53. data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S.sv.bak +255 -0
  54. data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S_A1.sv +286 -0
  55. data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S_A2.sv +281 -0
  56. data/lib/axi/AXI4/interconnect/axi4_wr_interconnect_M2S.sv +235 -0
  57. data/lib/axi/AXI4/interconnect/axi4_wr_interconnect_M2S_A1.sv +283 -0
  58. data/lib/axi/AXI4/interconnect/axi4_wr_mix_interconnect_M2S.sv +32 -0
  59. data/lib/axi/AXI4/long_axi4_to_wide_axi4.sv.bak +251 -0
  60. data/lib/axi/AXI4/odata_pool_axi4.sv +134 -0
  61. data/lib/axi/AXI4/odata_pool_axi4_A1.sv +165 -0
  62. data/lib/axi/AXI4/odata_pool_axi4_A2.sv +159 -0
  63. data/lib/axi/AXI4/odata_pool_axi4_A3.sv +183 -0
  64. data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo.sv +61 -0
  65. data/lib/axi/AXI4/packet_fifo/axi4_rd_packet_fifo.sv +282 -0
  66. data/lib/axi/AXI4/packet_fifo/axi4_wr_packet_fifo.sv +181 -0
  67. data/lib/axi/AXI4/packet_merge/axi4_merge.sv +60 -0
  68. data/lib/axi/AXI4/packet_merge/axi4_merge_rd.sv +279 -0
  69. data/lib/axi/AXI4/packet_merge/axi4_merge_wr.sv +267 -0
  70. data/lib/axi/AXI4/packet_partition/axi4_partition.sv +36 -0
  71. data/lib/axi/AXI4/packet_partition/axi4_partition_OD.sv +66 -0
  72. data/lib/axi/AXI4/packet_partition/axi4_partition_rd.sv +211 -0
  73. data/lib/axi/AXI4/packet_partition/axi4_partition_rd_OD.sv +322 -0
  74. data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.rb +80 -0
  75. data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +93 -0
  76. data/lib/axi/AXI4/packet_partition/axi4_partition_wr.sv +239 -0
  77. data/lib/axi/AXI4/packet_partition/axi4_partition_wr_OD.sv +302 -0
  78. data/lib/axi/AXI4/packet_partition/data_inf_partition.rb +293 -0
  79. data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +307 -0
  80. data/lib/axi/AXI4/vcs_axi4_array_comptable.sv +35 -0
  81. data/lib/axi/AXI4/vcs_axi4_comptable.sv +330 -0
  82. data/lib/axi/AXI4/wide_axis_to_axi4_wr.rb +149 -0
  83. data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +140 -0
  84. data/lib/axi/AXI4/width_convert/axi4_data_combin_aflag_pipe.sv +239 -0
  85. data/lib/axi/AXI4/width_convert/axi4_data_combin_aflag_pipe_A1.sv +204 -0
  86. data/lib/axi/AXI4/width_convert/axi4_data_convert.sv +312 -0
  87. data/lib/axi/AXI4/width_convert/axi4_data_convert_A1.sv +217 -0
  88. data/lib/axi/AXI4/width_convert/data_combin.sv +366 -0
  89. data/lib/axi/AXI4/width_convert/data_combin.sv.bak +290 -0
  90. data/lib/axi/AXI4/width_convert/data_destruct.sv +304 -0
  91. data/lib/axi/AXI4/width_convert/feed_check.sv +94 -0
  92. data/lib/axi/AXI4/width_convert/len_convert.sv.bak +61 -0
  93. data/lib/axi/AXI4/width_convert/odd_width_convert.sv +229 -0
  94. data/lib/axi/AXI4/width_convert/odd_width_convert_verb.sv +105 -0
  95. data/lib/axi/AXI4/width_convert/simple_data_pipe.sv +40 -0
  96. data/lib/axi/AXI4/width_convert/simple_data_pipe_slaver.sv +33 -0
  97. data/lib/axi/AXI4/width_convert/width_combin.sv +113 -0
  98. data/lib/axi/AXI4/width_convert/width_convert.sv +87 -0
  99. data/lib/axi/AXI4/width_convert/width_convert_verb.sv +249 -0
  100. data/lib/axi/AXI4/width_convert/width_destruct.sv +206 -0
  101. data/lib/axi/AXI4/width_convert/width_destruct_A1.sv +251 -0
  102. data/lib/axi/AXI_BFM/AXI_BFM_PKG.sv +1039 -0
  103. data/lib/axi/AXI_BFM/Data_C_BFM_PKG.sv +97 -0
  104. data/lib/axi/AXI_BFM/axi4_error_chk.sv +298 -0
  105. data/lib/axi/AXI_BFM/axi4_illegal_bfm_pkg.sv +607 -0
  106. data/lib/axi/AXI_BFM/axi_lite_master.sv +102 -0
  107. data/lib/axi/AXI_BFM/axi_lite_tb.sv +23 -0
  108. data/lib/axi/AXI_BFM/axi_master.sv +185 -0
  109. data/lib/axi/AXI_BFM/axi_mirror.sv +266 -0
  110. data/lib/axi/AXI_BFM/axi_mm_tb.sv +134 -0
  111. data/lib/axi/AXI_BFM/axi_slaver.sv.bak +340 -0
  112. data/lib/axi/AXI_BFM/axistreambfm.sv +117 -0
  113. data/lib/axi/AXI_Lite/axi4_to_lite.sv +36 -0
  114. data/lib/axi/AXI_Lite/axi_lite_configure.sv +356 -0
  115. data/lib/axi/AXI_Lite/axi_lite_configure_inf2.sv +365 -0
  116. data/lib/axi/AXI_Lite/axi_lite_configure_verb.sv.bck +370 -0
  117. data/lib/axi/AXI_Lite/axi_lite_interconnect_M2S.sv +437 -0
  118. data/lib/axi/AXI_Lite/axi_lite_interconnect_S2M.sv +359 -0
  119. data/lib/axi/AXI_Lite/axi_lite_interconnect_S2M.sv.bak +359 -0
  120. data/lib/axi/AXI_Lite/axi_lite_master_empty.sv +30 -0
  121. data/lib/axi/AXI_Lite/axi_lite_slaver_empty.sv +27 -0
  122. data/lib/axi/AXI_Lite/axil_direct.sv +52 -0
  123. data/lib/axi/AXI_Lite/common_configure_reg_interface/common_configure_reg_interface.sv +230 -0
  124. data/lib/axi/AXI_Lite/common_configure_reg_interface/common_configure_reg_interface.sv.bak +109 -0
  125. data/lib/axi/AXI_Lite/common_configure_reg_interface/jtag_to_axilite_wrapper.sv +56 -0
  126. data/lib/axi/AXI_Lite/gen_axi_lite_ctrl.sv +515 -0
  127. data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_C1.sv +369 -0
  128. data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_verb.sv +365 -0
  129. data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_verc.sv +401 -0
  130. data/lib/axi/AXI_Lite/wr_lite_to_axis.sv +141 -0
  131. data/lib/axi/AXI_Lite/wr_lite_to_axis.sv.bak +141 -0
  132. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S.sv +76 -0
  133. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_A1.sv +77 -0
  134. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_A2.sv +71 -0
  135. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_bind_tuser.sv +72 -0
  136. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_noaddr.sv +151 -0
  137. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_with_addr.sv +87 -0
  138. data/lib/axi/AXI_stream/axi_stream_interconnect_S2M.sv +65 -0
  139. data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_auto.sv +50 -0
  140. data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_with_info.sv +64 -0
  141. data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_with_keep.sv.bak +64 -0
  142. data/lib/axi/AXI_stream/axi_stream_packet_fifo_with_info.sv.bak +49 -0
  143. data/lib/axi/AXI_stream/axi_stream_partition.sv +147 -0
  144. data/lib/axi/AXI_stream/axi_stream_partition_A1.sv +63 -0
  145. data/lib/axi/AXI_stream/axi_stream_planer.sv +51 -0
  146. data/lib/axi/AXI_stream/axi_stream_split_channel.rb +56 -0
  147. data/lib/axi/AXI_stream/axi_stream_split_channel.sv +149 -0
  148. data/lib/axi/AXI_stream/axi_streams_combin.sv +151 -0
  149. data/lib/axi/AXI_stream/axi_streams_combin_A1.sv +179 -0
  150. data/lib/axi/AXI_stream/axi_streams_scaler.sv +171 -0
  151. data/lib/axi/AXI_stream/axi_streams_scaler_A1.sv +179 -0
  152. data/lib/axi/AXI_stream/axis_append.sv +79 -0
  153. data/lib/axi/AXI_stream/axis_append_A1.sv +82 -0
  154. data/lib/axi/AXI_stream/axis_base_pipe.sv +184 -0
  155. data/lib/axi/AXI_stream/axis_combin_with_fifo.sv +69 -0
  156. data/lib/axi/AXI_stream/axis_connect_pipe.sv +86 -0
  157. data/lib/axi/AXI_stream/axis_connect_pipe_A1.sv.bak +170 -0
  158. data/lib/axi/AXI_stream/axis_connect_pipe_left_shift.sv +64 -0
  159. data/lib/axi/AXI_stream/axis_connect_pipe_right_shift.sv +64 -0
  160. data/lib/axi/AXI_stream/axis_connect_pipe_right_shift_verb.sv +70 -0
  161. data/lib/axi/AXI_stream/axis_connect_pipe_with_info.sv +93 -0
  162. data/lib/axi/AXI_stream/axis_direct.sv +55 -0
  163. data/lib/axi/AXI_stream/axis_direct_A1.sv +81 -0
  164. data/lib/axi/AXI_stream/axis_filter.sv +38 -0
  165. data/lib/axi/AXI_stream/axis_full_to_data_c.sv +26 -0
  166. data/lib/axi/AXI_stream/axis_head_cut.sv +67 -0
  167. data/lib/axi/AXI_stream/axis_head_cut_verb.sv +60 -0
  168. data/lib/axi/AXI_stream/axis_head_cut_verc.rb +175 -0
  169. data/lib/axi/AXI_stream/axis_head_cut_verc.sv +245 -0
  170. data/lib/axi/AXI_stream/axis_inct_s2m_with_flag.sv +84 -0
  171. data/lib/axi/AXI_stream/axis_insert_copy.rb +59 -0
  172. data/lib/axi/AXI_stream/axis_insert_copy.sv +66 -0
  173. data/lib/axi/AXI_stream/axis_intc_M2S_with_addr_inf.sv +114 -0
  174. data/lib/axi/AXI_stream/axis_intc_S2M_with_addr_inf.sv +85 -0
  175. data/lib/axi/AXI_stream/axis_interconnect_S2M_pipe.sv +75 -0
  176. data/lib/axi/AXI_stream/axis_length_cut.sv +64 -0
  177. data/lib/axi/AXI_stream/axis_length_fill.sv +194 -0
  178. data/lib/axi/AXI_stream/axis_length_split.sv +86 -0
  179. data/lib/axi/AXI_stream/axis_length_split_with_addr.sv +127 -0
  180. data/lib/axi/AXI_stream/axis_length_split_writh_user.sv +87 -0
  181. data/lib/axi/AXI_stream/axis_link_trigger.sv +81 -0
  182. data/lib/axi/AXI_stream/axis_master_empty.sv +26 -0
  183. data/lib/axi/AXI_stream/axis_mirror_to_master.sv +126 -0
  184. data/lib/axi/AXI_stream/axis_mirrors.sv +60 -0
  185. data/lib/axi/AXI_stream/axis_orthogonal.sv +66 -0
  186. data/lib/axi/AXI_stream/axis_ram_buffer.sv +118 -0
  187. data/lib/axi/AXI_stream/axis_rom_contect.rb +97 -0
  188. data/lib/axi/AXI_stream/axis_rom_contect.sv +110 -0
  189. data/lib/axi/AXI_stream/axis_rom_contect_sim.rb +102 -0
  190. data/lib/axi/AXI_stream/axis_rom_contect_sim.sv +113 -0
  191. data/lib/axi/AXI_stream/axis_slaver_empty.sv +22 -0
  192. data/lib/axi/AXI_stream/axis_slaver_pipe.sv +84 -0
  193. data/lib/axi/AXI_stream/axis_slaver_pipe_A1.sv +54 -0
  194. data/lib/axi/AXI_stream/axis_slaver_vector_empty.sv +27 -0
  195. data/lib/axi/AXI_stream/axis_split_channel_verb.rb +42 -0
  196. data/lib/axi/AXI_stream/axis_split_channel_verb.sv +62 -0
  197. data/lib/axi/AXI_stream/axis_to_axi4_or_lite.rb +127 -0
  198. data/lib/axi/AXI_stream/axis_to_axi4_or_lite.sv +153 -0
  199. data/lib/axi/AXI_stream/axis_to_data_inf.sv +34 -0
  200. data/lib/axi/AXI_stream/axis_to_lite_rd.sv +81 -0
  201. data/lib/axi/AXI_stream/axis_to_lite_wr.sv +71 -0
  202. data/lib/axi/AXI_stream/axis_uncompress.sv +147 -0
  203. data/lib/axi/AXI_stream/axis_uncompress_A1.sv +150 -0
  204. data/lib/axi/AXI_stream/axis_uncompress_verb.rb +32 -0
  205. data/lib/axi/AXI_stream/axis_uncompress_verb.sv +54 -0
  206. data/lib/axi/AXI_stream/axis_valve.sv +29 -0
  207. data/lib/axi/AXI_stream/axis_valve_with_pipe.sv +76 -0
  208. data/lib/axi/AXI_stream/axis_vector_master_empty.rb +11 -0
  209. data/lib/axi/AXI_stream/axis_vector_master_empty.sv +35 -0
  210. data/lib/axi/AXI_stream/axis_vector_slaver_empty.rb +11 -0
  211. data/lib/axi/AXI_stream/axis_vector_slaver_empty.sv +35 -0
  212. data/lib/axi/AXI_stream/check_stream_crc.sv +28 -0
  213. data/lib/axi/AXI_stream/data_c_to_axis_full.sv +23 -0
  214. data/lib/axi/AXI_stream/data_to_axis_inf.sv +103 -0
  215. data/lib/axi/AXI_stream/data_to_axis_inf_A1.sv +28 -0
  216. data/lib/axi/AXI_stream/data_width/axis_width_combin.sv +204 -0
  217. data/lib/axi/AXI_stream/data_width/axis_width_combin_A1.sv +220 -0
  218. data/lib/axi/AXI_stream/data_width/axis_width_convert.sv +49 -0
  219. data/lib/axi/AXI_stream/data_width/axis_width_destruct.sv +82 -0
  220. data/lib/axi/AXI_stream/data_width/axis_width_destruct_A1.sv +86 -0
  221. data/lib/axi/AXI_stream/ex_status/axis_ex_status.sv +97 -0
  222. data/lib/axi/AXI_stream/gen_big_field_table.sv +170 -0
  223. data/lib/axi/AXI_stream/gen_common_frame_table.sv +382 -0
  224. data/lib/axi/AXI_stream/gen_common_frame_table_bind_tuser.sv +428 -0
  225. data/lib/axi/AXI_stream/gen_origin_axis.sv +116 -0
  226. data/lib/axi/AXI_stream/gen_origin_axis_A1.sv +129 -0
  227. data/lib/axi/AXI_stream/gen_origin_axis_A2.sv +162 -0
  228. data/lib/axi/AXI_stream/gen_simple_axis.sv +164 -0
  229. data/lib/axi/AXI_stream/packet_fifo/axi_stream_long_fifo.sv +132 -0
  230. data/lib/axi/AXI_stream/packet_fifo/axi_stream_long_fifo_verb.sv +140 -0
  231. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo.sv +125 -0
  232. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1.sv +142 -0
  233. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1E.sv +198 -0
  234. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_verb.sv +120 -0
  235. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_with_info.sv +49 -0
  236. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_long_fifo.sv +197 -0
  237. data/lib/axi/AXI_stream/packet_fifo/axi_stream_wide_fifo.sv +141 -0
  238. data/lib/axi/AXI_stream/packet_fifo/axis_pkt_fifo_filter_keep.sv +164 -0
  239. data/lib/axi/AXI_stream/packet_fifo/axis_pkt_fifo_filter_keep_A1.sv +166 -0
  240. data/lib/axi/AXI_stream/parse_big_field_table.sv +164 -0
  241. data/lib/axi/AXI_stream/parse_big_field_table_A1.sv +162 -0
  242. data/lib/axi/AXI_stream/parse_big_field_table_A2.sv +165 -0
  243. data/lib/axi/AXI_stream/parse_big_field_table_verb.sv +118 -0
  244. data/lib/axi/AXI_stream/parse_common_frame_table.sv +202 -0
  245. data/lib/axi/AXI_stream/parse_common_frame_table_A1.sv +521 -0
  246. data/lib/axi/AXI_stream/parse_common_frame_table_A2.sv +561 -0
  247. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache.sv +46 -0
  248. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_35bit.sv +122 -0
  249. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_36_71bit.sv +71 -0
  250. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_72_95bit.sv +96 -0
  251. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_72_95bit_with_keep.sv +99 -0
  252. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_96_143bit.sv +119 -0
  253. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_A1.sv +49 -0
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  255. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_mirror.sv +44 -0
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  257. data/lib/axi/AXI_stream/stream_cache/axi_stream_long_cache.sv +55 -0
  258. data/lib/axi/AXI_stream/stream_crc.sv +67 -0
  259. data/lib/axi/AXI_stream/vcs_axis_comptable.sv +73 -0
  260. data/lib/axi/LICENSE +504 -0
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  263. data/lib/axi/SIM/tb_axis_bfm_0504.sv +61 -0
  264. data/lib/axi/SIM/tb_axis_partitiom_0929.sv +102 -0
  265. data/lib/axi/SIM/tb_axis_s2m_pipe_1023.sv +163 -0
  266. data/lib/axi/SIM/tb_axis_to_axi4_0925.sv +107 -0
  267. data/lib/axi/SIM/tb_data_c_m2s_inf_20200114.sv +222 -0
  268. data/lib/axi/SIM/tb_data_c_m2s_inf_20201103.sv +245 -0
  269. data/lib/axi/SIM/tb_data_c_pipe_inf_20180417.sv +114 -0
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  275. data/lib/axi/axi4_to_xilinx_ddr_native/ddr3_ip_native_to_axi4.sv +194 -0
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  283. data/lib/axi/cfg.yml +15 -0
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  285. data/lib/axi/common/common_ram_sim_wrapper.rb +66 -0
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  287. data/lib/axi/common/common_ram_wrapper.rb +71 -0
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  289. data/lib/axi/common/data_c_interface_dram.rb +90 -0
  290. data/lib/axi/common/data_c_interface_dram.sv +106 -0
  291. data/lib/axi/common/mem_format.coe +60 -0
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  311. data/lib/axi/data_interface/data_inf_c/data_c_pipe_force_vld_bind_data.sv +81 -0
  312. data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf.sv +130 -0
  313. data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf_A1.sv +135 -0
  314. data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf_left_shift.sv +158 -0
  315. data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf_right_shift.sv +155 -0
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  319. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_best_last.sv +319 -0
  320. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_best_robin.sv +293 -0
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  322. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_robin_with_id.sv +46 -0
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  324. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_verc_with_addr.sv +226 -0
  325. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_verc_with_id.sv +54 -0
  326. data/lib/axi/data_interface/data_inf_c/data_c_pipe_latency.sv +68 -0
  327. data/lib/axi/data_interface/data_inf_c/data_c_scaler.sv +326 -0
  328. data/lib/axi/data_interface/data_inf_c/data_c_scaler_A1.sv +333 -0
  329. data/lib/axi/data_interface/data_inf_c/data_c_tmp_cache.sv +44 -0
  330. data/lib/axi/data_interface/data_inf_c/data_condition_mirror.sv +64 -0
  331. data/lib/axi/data_interface/data_inf_c/data_condition_valve.sv +53 -0
  332. data/lib/axi/data_interface/data_inf_c/data_connect_pipe_inf.sv +73 -0
  333. data/lib/axi/data_interface/data_inf_c/data_inf_c_M2S_with_addr_and_id.sv +66 -0
  334. data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_M2S_with_id.sv +67 -0
  335. data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_S2M.sv +70 -0
  336. data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_S2M_A1.sv +72 -0
  337. data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_S2M_with_lazy.sv +49 -0
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  339. data/lib/axi/data_interface/data_inf_c/data_inf_c_pipe_condition.sv +33 -0
  340. data/lib/axi/data_interface/data_inf_c/data_inf_c_planer.sv +50 -0
  341. data/lib/axi/data_interface/data_inf_c/data_inf_c_planer_A1.sv +53 -0
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  347. data/lib/axi/data_interface/data_inf_c/next_prio.sv +42 -0
  348. data/lib/axi/data_interface/data_inf_c/trigger_data_inf_c.sv +51 -0
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  354. data/lib/axi/data_interface/data_inf_intc_M2S_prio.sv +152 -0
  355. data/lib/axi/data_interface/data_inf_intc_M2S_prio_with_id.sv +55 -0
  356. data/lib/axi/data_interface/data_inf_interconnect_M2S_noaddr.sv +136 -0
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  358. data/lib/axi/data_interface/data_inf_planer.sv +59 -0
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  382. data/lib/axi/data_interface/datainf_slaver_empty.sv +22 -0
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  384. data/lib/axi/interface_define/axi_aux_inf.sv +206 -0
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  423. data/lib/axi/platform_ip/fifo_73_96bit.sv +102 -0
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  468. data/lib/axi/top/tb_data_intc_S2M_0807.sv +168 -0
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  482. data/lib/tdl/Logic/logic_operator.rb.bak +128 -0
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  486. data/lib/tdl/ReadMe.md +295 -0
  487. data/lib/tdl/SDL/axi4/AXI4_interconnect_M2S_sdl.rb +10 -0
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  498. data/lib/tdl/SDL/axi4/axi4_long_to_axi4_wide_A1_sdl.rb +10 -0
  499. data/lib/tdl/SDL/axi4/axi4_long_to_axi4_wide_sdl.rb +9 -0
  500. data/lib/tdl/SDL/axi4/axi4_long_to_axi4_wide_track_sdl.rb +9 -0
  501. data/lib/tdl/SDL/axi4/axi4_long_to_axi4_wide_verb_sdl.rb +11 -0
  502. data/lib/tdl/SDL/axi4/axi4_merge_rd_sdl.rb +10 -0
  503. data/lib/tdl/SDL/axi4/axi4_merge_sdl.rb +10 -0
  504. data/lib/tdl/SDL/axi4/axi4_merge_wr_sdl.rb +10 -0
  505. data/lib/tdl/SDL/axi4/axi4_mix_interconnect_M2S_sdl.rb +10 -0
  506. data/lib/tdl/SDL/axi4/axi4_packet_fifo_sdl.rb +12 -0
  507. data/lib/tdl/SDL/axi4/axi4_partition_OD_sdl.rb +11 -0
  508. data/lib/tdl/SDL/axi4/axi4_partition_rd_OD_sdl.rb +10 -0
  509. data/lib/tdl/SDL/axi4/axi4_partition_rd_sdl.rb +11 -0
  510. data/lib/tdl/SDL/axi4/axi4_partition_sdl.rb +11 -0
  511. data/lib/tdl/SDL/axi4/axi4_partition_wr_OD_sdl.rb +10 -0
  512. data/lib/tdl/SDL/axi4/axi4_partition_wr_sdl.rb +11 -0
  513. data/lib/tdl/SDL/axi4/axi4_pipe_sdl.rb +9 -0
  514. data/lib/tdl/SDL/axi4/axi4_pipe_verb_sdl.rb +9 -0
  515. data/lib/tdl/SDL/axi4/axi4_rd_auxiliary_batch_gen_sdl.rb +11 -0
  516. data/lib/tdl/SDL/axi4/axi4_rd_auxiliary_gen_A1_sdl.rb +9 -0
  517. data/lib/tdl/SDL/axi4/axi4_rd_auxiliary_gen_sdl.rb +9 -0
  518. data/lib/tdl/SDL/axi4/axi4_rd_burst_track_sdl.rb +10 -0
  519. data/lib/tdl/SDL/axi4/axi4_rd_interconnect_M2S_sdl.rb +10 -0
  520. data/lib/tdl/SDL/axi4/axi4_rd_mix_interconnect_M2S_A1_sdl.rb +10 -0
  521. data/lib/tdl/SDL/axi4/axi4_rd_mix_interconnect_M2S_A2_sdl.rb +10 -0
  522. data/lib/tdl/SDL/axi4/axi4_rd_mix_interconnect_M2S_sdl.rb +10 -0
  523. data/lib/tdl/SDL/axi4/axi4_rd_packet_fifo_sdl.rb +11 -0
  524. data/lib/tdl/SDL/axi4/axi4_rd_pipe_sdl.rb +9 -0
  525. data/lib/tdl/SDL/axi4/axi4_rd_pipe_verb_sdl.rb +9 -0
  526. data/lib/tdl/SDL/axi4/axi4_wr_aux_bind_data_sdl.rb +9 -0
  527. data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_batch_gen_sdl.rb +11 -0
  528. data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_gen_sdl.rb +10 -0
  529. data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_gen_without_resp_sdl.rb +10 -0
  530. data/lib/tdl/SDL/axi4/axi4_wr_burst_track_sdl.rb +10 -0
  531. data/lib/tdl/SDL/axi4/axi4_wr_interconnect_M2S_A1_sdl.rb +10 -0
  532. data/lib/tdl/SDL/axi4/axi4_wr_interconnect_M2S_sdl.rb +10 -0
  533. data/lib/tdl/SDL/axi4/axi4_wr_mix_interconnect_M2S_sdl.rb +10 -0
  534. data/lib/tdl/SDL/axi4/axi4_wr_packet_fifo_sdl.rb +11 -0
  535. data/lib/tdl/SDL/axi4/axi4_wr_pipe_sdl.rb +9 -0
  536. data/lib/tdl/SDL/axi4/axi4_wr_pipe_verb_sdl.rb +9 -0
  537. data/lib/tdl/SDL/axi4/axi_stream_add_addr_len_sdl.rb +11 -0
  538. data/lib/tdl/SDL/axi4/axi_stream_to_axi4_wr_sdl.rb +9 -0
  539. data/lib/tdl/SDL/axi4/data_combin_sdl.rb +20 -0
  540. data/lib/tdl/SDL/axi4/data_destruct_sdl.rb +19 -0
  541. data/lib/tdl/SDL/axi4/feed_check_sdl.rb +18 -0
  542. data/lib/tdl/SDL/axi4/full_axi4_to_axis_partition_wr_rd_sdl.rb +11 -0
  543. data/lib/tdl/SDL/axi4/full_axi4_to_axis_sdl.rb +10 -0
  544. data/lib/tdl/SDL/axi4/id_record_sdl.rb +19 -0
  545. data/lib/tdl/SDL/axi4/idata_pool_axi4_sdl.rb +18 -0
  546. data/lib/tdl/SDL/axi4/odata_pool_axi4_A1_sdl.rb +13 -0
  547. data/lib/tdl/SDL/axi4/odata_pool_axi4_A2_sdl.rb +10 -0
  548. data/lib/tdl/SDL/axi4/odata_pool_axi4_sdl.rb +19 -0
  549. data/lib/tdl/SDL/axi4/odd_width_convert_sdl.rb +19 -0
  550. data/lib/tdl/SDL/axi4/odd_width_convert_verb_sdl.rb +19 -0
  551. data/lib/tdl/SDL/axi4/simple_data_pipe_sdl.rb +16 -0
  552. data/lib/tdl/SDL/axi4/simple_data_pipe_slaver_sdl.rb +16 -0
  553. data/lib/tdl/SDL/axi4/vcs_axi4_array_comptable.rb +9 -0
  554. data/lib/tdl/SDL/axi4/vcs_axi4_array_comptable_sdl.rb +10 -0
  555. data/lib/tdl/SDL/axi4/vcs_axi4_comptable.rb +8 -0
  556. data/lib/tdl/SDL/axi4/vcs_axi4_comptable_sdl.rb +9 -0
  557. data/lib/tdl/SDL/axi4/width_combin_sdl.rb +20 -0
  558. data/lib/tdl/SDL/axi4/width_convert_sdl.rb +20 -0
  559. data/lib/tdl/SDL/axi4/width_convert_verb_sdl.rb +20 -0
  560. data/lib/tdl/SDL/axi4/width_destruct_A1_sdl.rb +22 -0
  561. data/lib/tdl/SDL/axi4/width_destruct_sdl.rb +19 -0
  562. data/lib/tdl/SDL/axistream/axi_stream_cache_35bit_sdl.rb +9 -0
  563. data/lib/tdl/SDL/axistream/axi_stream_cache_36_71bit_sdl.rb +9 -0
  564. data/lib/tdl/SDL/axistream/axi_stream_cache_72_95bit_sdl.rb +9 -0
  565. data/lib/tdl/SDL/axistream/axi_stream_cache_72_95bit_with_keep_sdl.rb +9 -0
  566. data/lib/tdl/SDL/axistream/axi_stream_cache_96_143bit_sdl.rb +9 -0
  567. data/lib/tdl/SDL/axistream/axi_stream_cache_B1_sdl.rb +9 -0
  568. data/lib/tdl/SDL/axistream/axi_stream_cache_mirror_sdl.rb +9 -0
  569. data/lib/tdl/SDL/axistream/axi_stream_cache_sdl.rb +9 -0
  570. data/lib/tdl/SDL/axistream/axi_stream_cache_verb_sdl.rb +9 -0
  571. data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_A1_sdl.rb +11 -0
  572. data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_A2_sdl.rb +13 -0
  573. data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_bind_tuser_sdl.rb +11 -0
  574. data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_noaddr_sdl.rb +11 -0
  575. data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_sdl.rb +12 -0
  576. data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_with_addr_sdl.rb +12 -0
  577. data/lib/tdl/SDL/axistream/axi_stream_interconnect_S2M_auto_sdl.rb +11 -0
  578. data/lib/tdl/SDL/axistream/axi_stream_interconnect_S2M_sdl.rb +12 -0
  579. data/lib/tdl/SDL/axistream/axi_stream_long_cache_sdl.rb +10 -0
  580. data/lib/tdl/SDL/axistream/axi_stream_long_fifo_sdl.rb +11 -0
  581. data/lib/tdl/SDL/axistream/axi_stream_long_fifo_verb_sdl.rb +11 -0
  582. data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_B1E_sdl.rb +16 -0
  583. data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_B1_sdl.rb +14 -0
  584. data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_sdl.rb +10 -0
  585. data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_verb_sdl.rb +13 -0
  586. data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_with_info_sdl.rb +13 -0
  587. data/lib/tdl/SDL/axistream/axi_stream_packet_long_fifo_sdl.rb +11 -0
  588. data/lib/tdl/SDL/axistream/axi_stream_partition_A1_sdl.rb +11 -0
  589. data/lib/tdl/SDL/axistream/axi_stream_partition_sdl.rb +12 -0
  590. data/lib/tdl/SDL/axistream/axi_stream_wide_fifo_sdl.rb +10 -0
  591. data/lib/tdl/SDL/axistream/axi_streams_combin_A1_sdl.rb +15 -0
  592. data/lib/tdl/SDL/axistream/axi_streams_combin_sdl.rb +16 -0
  593. data/lib/tdl/SDL/axistream/axi_streams_scaler_A1_sdl.rb +14 -0
  594. data/lib/tdl/SDL/axistream/axi_streams_scaler_sdl.rb +15 -0
  595. data/lib/tdl/SDL/axistream/axis_append_A1_sdl.rb +18 -0
  596. data/lib/tdl/SDL/axistream/axis_append_sdl.rb +17 -0
  597. data/lib/tdl/SDL/axistream/axis_base_pipe_sdl.rb +10 -0
  598. data/lib/tdl/SDL/axistream/axis_combin_with_fifo_sdl.rb +14 -0
  599. data/lib/tdl/SDL/axistream/axis_connect_pipe_right_shift_sdl.rb +10 -0
  600. data/lib/tdl/SDL/axistream/axis_connect_pipe_sdl.rb +9 -0
  601. data/lib/tdl/SDL/axistream/axis_connect_pipe_with_info_sdl.rb +12 -0
  602. data/lib/tdl/SDL/axistream/axis_direct_A1_sdl.rb +11 -0
  603. data/lib/tdl/SDL/axistream/axis_direct_sdl.rb +9 -0
  604. data/lib/tdl/SDL/axistream/axis_ex_status_sdl.rb +12 -0
  605. data/lib/tdl/SDL/axistream/axis_filter_sdl.rb +10 -0
  606. data/lib/tdl/SDL/axistream/axis_full_to_data_c_sdl.rb +9 -0
  607. data/lib/tdl/SDL/axistream/axis_head_cut_sdl.rb +10 -0
  608. data/lib/tdl/SDL/axistream/axis_inct_s2m_with_flag_sdl.rb +11 -0
  609. data/lib/tdl/SDL/axistream/axis_intc_M2S_with_addr_inf_sdl.rb +11 -0
  610. data/lib/tdl/SDL/axistream/axis_intc_S2M_with_addr_inf_sdl.rb +12 -0
  611. data/lib/tdl/SDL/axistream/axis_interconnect_S2M_pipe_sdl.rb +15 -0
  612. data/lib/tdl/SDL/axistream/axis_length_cut_sdl.rb +10 -0
  613. data/lib/tdl/SDL/axistream/axis_length_fill_sdl.rb +10 -0
  614. data/lib/tdl/SDL/axistream/axis_length_split_sdl.rb +10 -0
  615. data/lib/tdl/SDL/axistream/axis_length_split_with_addr_sdl.rb +13 -0
  616. data/lib/tdl/SDL/axistream/axis_length_split_writh_user_sdl.rb +10 -0
  617. data/lib/tdl/SDL/axistream/axis_link_trigger_sdl.rb +12 -0
  618. data/lib/tdl/SDL/axistream/axis_master_empty_sdl.rb +8 -0
  619. data/lib/tdl/SDL/axistream/axis_mirror_to_master_sdl.rb +10 -0
  620. data/lib/tdl/SDL/axistream/axis_mirrors_sdl.rb +14 -0
  621. data/lib/tdl/SDL/axistream/axis_orthogonal_sdl.rb +10 -0
  622. data/lib/tdl/SDL/axistream/axis_pkt_fifo_filter_keep_A1_sdl.rb +10 -0
  623. data/lib/tdl/SDL/axistream/axis_pkt_fifo_filter_keep_sdl.rb +10 -0
  624. data/lib/tdl/SDL/axistream/axis_ram_buffer_sdl.rb +13 -0
  625. data/lib/tdl/SDL/axistream/axis_slaver_empty_sdl.rb +8 -0
  626. data/lib/tdl/SDL/axistream/axis_slaver_pipe_A1_sdl.rb +10 -0
  627. data/lib/tdl/SDL/axistream/axis_slaver_pipe_sdl.rb +9 -0
  628. data/lib/tdl/SDL/axistream/axis_slaver_vector_empty_sdl.rb +9 -0
  629. data/lib/tdl/SDL/axistream/axis_to_data_inf_sdl.rb +10 -0
  630. data/lib/tdl/SDL/axistream/axis_to_lite_rd_sdl.rb +11 -0
  631. data/lib/tdl/SDL/axistream/axis_to_lite_wr_sdl.rb +10 -0
  632. data/lib/tdl/SDL/axistream/axis_uncompress_A1_sdl.rb +12 -0
  633. data/lib/tdl/SDL/axistream/axis_uncompress_sdl.rb +11 -0
  634. data/lib/tdl/SDL/axistream/axis_valve_sdl.rb +10 -0
  635. data/lib/tdl/SDL/axistream/axis_valve_with_pipe_sdl.rb +11 -0
  636. data/lib/tdl/SDL/axistream/axis_width_combin_A1_sdl.rb +9 -0
  637. data/lib/tdl/SDL/axistream/axis_width_combin_sdl.rb +9 -0
  638. data/lib/tdl/SDL/axistream/axis_width_convert_sdl.rb +9 -0
  639. data/lib/tdl/SDL/axistream/axis_width_destruct_A1_sdl.rb +9 -0
  640. data/lib/tdl/SDL/axistream/axis_width_destruct_sdl.rb +9 -0
  641. data/lib/tdl/SDL/axistream/check_stream_crc_sdl.rb +8 -0
  642. data/lib/tdl/SDL/axistream/data_c_to_axis_full_sdl.rb +9 -0
  643. data/lib/tdl/SDL/axistream/data_to_axis_inf_A1_sdl.rb +10 -0
  644. data/lib/tdl/SDL/axistream/data_to_axis_inf_sdl.rb +11 -0
  645. data/lib/tdl/SDL/axistream/gen_big_field_table_sdl.rb +14 -0
  646. data/lib/tdl/SDL/axistream/gen_common_frame_table_sdl.rb +60 -0
  647. data/lib/tdl/SDL/axistream/gen_origin_axis_A1_sdl.rb +13 -0
  648. data/lib/tdl/SDL/axistream/gen_origin_axis_sdl.rb +12 -0
  649. data/lib/tdl/SDL/axistream/gen_simple_axis_sdl.rb +13 -0
  650. data/lib/tdl/SDL/axistream/parse_big_field_table_A1_sdl.rb +17 -0
  651. data/lib/tdl/SDL/axistream/parse_big_field_table_A2_sdl.rb +17 -0
  652. data/lib/tdl/SDL/axistream/parse_big_field_table_sdl.rb +17 -0
  653. data/lib/tdl/SDL/axistream/stream_crc_sdl.rb +9 -0
  654. data/lib/tdl/SDL/axistream/vcs_axis_comptable.rb +16 -0
  655. data/lib/tdl/SDL/axistream/vcs_axis_comptable_sdl.rb +9 -0
  656. data/lib/tdl/SDL/data_inf_c/data_bind_sdl.rb +10 -0
  657. data/lib/tdl/SDL/data_inf_c/data_c_cache_sdl.rb +9 -0
  658. data/lib/tdl/SDL/data_inf_c/data_c_direct_mirror_sdl.rb +9 -0
  659. data/lib/tdl/SDL/data_inf_c/data_c_direct_sdl.rb +9 -0
  660. data/lib/tdl/SDL/data_inf_c/data_c_intc_M2S_force_robin_sdl.rb +10 -0
  661. data/lib/tdl/SDL/data_inf_c/data_c_pipe_force_vld_bind_data_sdl.rb +13 -0
  662. data/lib/tdl/SDL/data_inf_c/data_c_pipe_force_vld_sdl.rb +9 -0
  663. data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_A1_sdl.rb +10 -0
  664. data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_right_shift_sdl.rb +13 -0
  665. data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_sdl.rb +9 -0
  666. data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_C1_sdl.rb +14 -0
  667. data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_C1_with_id_sdl.rb +16 -0
  668. data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_sdl.rb +13 -0
  669. data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_with_addr_sdl.rb +13 -0
  670. data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_with_id_sdl.rb +15 -0
  671. data/lib/tdl/SDL/data_inf_c/data_c_pipe_latency_sdl.rb +10 -0
  672. data/lib/tdl/SDL/data_inf_c/data_c_scaler_A1_sdl.rb +16 -0
  673. data/lib/tdl/SDL/data_inf_c/data_c_scaler_sdl.rb +15 -0
  674. data/lib/tdl/SDL/data_inf_c/data_c_tmp_cache_sdl.rb +9 -0
  675. data/lib/tdl/SDL/data_inf_c/data_condition_mirror_sdl.rb +13 -0
  676. data/lib/tdl/SDL/data_inf_c/data_condition_valve_sdl.rb +13 -0
  677. data/lib/tdl/SDL/data_inf_c/data_connect_pipe_inf_sdl.rb +9 -0
  678. data/lib/tdl/SDL/data_inf_c/data_connect_pipe_sdl.rb +17 -0
  679. data/lib/tdl/SDL/data_inf_c/data_inf_A2B_sdl.rb +9 -0
  680. data/lib/tdl/SDL/data_inf_c/data_inf_B2A_sdl.rb +9 -0
  681. data/lib/tdl/SDL/data_inf_c/data_inf_c_M2S_with_addr_and_id_sdl.rb +17 -0
  682. data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_M2S_with_id_sdl.rb +15 -0
  683. data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_A1_sdl.rb +13 -0
  684. data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_sdl.rb +12 -0
  685. data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_with_lazy_sdl.rb +15 -0
  686. data/lib/tdl/SDL/data_inf_c/data_inf_c_interconnect_M2S_sdl.rb +12 -0
  687. data/lib/tdl/SDL/data_inf_c/data_inf_c_pipe_condition_sdl.rb +10 -0
  688. data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_A1.rb +12 -0
  689. data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_A1_sdl.rb +14 -0
  690. data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_sdl.rb +13 -0
  691. data/lib/tdl/SDL/data_inf_c/data_inf_cross_clk_sdl.rb +9 -0
  692. data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_force_addr_with_id_sdl.rb +19 -0
  693. data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_prio_sdl.rb +14 -0
  694. data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_prio_with_id_sdl.rb +17 -0
  695. data/lib/tdl/SDL/data_inf_c/data_inf_interconnect_M2S_noaddr_sdl.rb +14 -0
  696. data/lib/tdl/SDL/data_inf_c/data_inf_interconnect_M2S_with_id_noaddr_sdl.rb +17 -0
  697. data/lib/tdl/SDL/data_inf_c/data_inf_planer_A1_sdl.rb +15 -0
  698. data/lib/tdl/SDL/data_inf_c/data_inf_planer_sdl.rb +14 -0
  699. data/lib/tdl/SDL/data_inf_c/data_inf_ticktock_sdl.rb +18 -0
  700. data/lib/tdl/SDL/data_inf_c/data_intc_M2S_force_robin_sdl.rb +10 -0
  701. data/lib/tdl/SDL/data_inf_c/data_mirrors_sdl.rb +14 -0
  702. data/lib/tdl/SDL/data_inf_c/data_pair_map_A1_sdl.rb +16 -0
  703. data/lib/tdl/SDL/data_inf_c/data_pair_map_A2_sdl.rb +19 -0
  704. data/lib/tdl/SDL/data_inf_c/data_pair_map_sdl.rb +14 -0
  705. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_A1_sdl.rb +19 -0
  706. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_sdl.rb +17 -0
  707. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_verb_sdl.rb +16 -0
  708. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_A1_sdl.rb +19 -0
  709. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_sdl.rb +16 -0
  710. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_verb_sdl.rb +15 -0
  711. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_sdl.rb +23 -0
  712. data/lib/tdl/SDL/data_inf_c/data_streams_combin_A1_sdl.rb +20 -0
  713. data/lib/tdl/SDL/data_inf_c/data_streams_combin_sdl.rb +20 -0
  714. data/lib/tdl/SDL/data_inf_c/data_streams_scaler_sdl.rb +19 -0
  715. data/lib/tdl/SDL/data_inf_c/data_uncompress_sdl.rb +11 -0
  716. data/lib/tdl/SDL/data_inf_c/data_valve_sdl.rb +10 -0
  717. data/lib/tdl/SDL/data_inf_c/datainf_c_master_empty_sdl.rb +8 -0
  718. data/lib/tdl/SDL/data_inf_c/datainf_c_slaver_empty_sdl.rb +8 -0
  719. data/lib/tdl/SDL/data_inf_c/datainf_master_empty_sdl.rb +8 -0
  720. data/lib/tdl/SDL/data_inf_c/datainf_slaver_empty_sdl.rb +8 -0
  721. data/lib/tdl/SDL/data_inf_c/latency_sdl.rb +8 -0
  722. data/lib/tdl/SDL/data_inf_c/next_prio_sdl.rb +12 -0
  723. data/lib/tdl/SDL/data_inf_c/part_data_pair_map_sdl.rb +19 -0
  724. data/lib/tdl/SDL/data_inf_c/trigger_data_inf_c_A1_sdl.rb +11 -0
  725. data/lib/tdl/SDL/data_inf_c/trigger_data_inf_c_sdl.rb +11 -0
  726. data/lib/tdl/SDL/data_inf_c/trigger_ready_ctrl_sdl.rb +12 -0
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  969. data/lib/tdl/class_hdl/hdl_parameter.rb +73 -0
  970. data/lib/tdl/class_hdl/hdl_random.rb +31 -0
  971. data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +653 -0
  972. data/lib/tdl/class_hdl/hdl_struct.rb +209 -0
  973. data/lib/tdl/class_hdl/hdl_verify.rb +136 -0
  974. data/lib/tdl/data_inf/_data_mirrors.rb +92 -0
  975. data/lib/tdl/data_inf/bak/_data_mirrors.rb +273 -0
  976. data/lib/tdl/data_inf/bak/common_fifo_auto.rb +279 -0
  977. data/lib/tdl/data_inf/bak/data_bind_auto.rb +128 -0
  978. data/lib/tdl/data_inf/bak/data_c_direct_auto.rb +138 -0
  979. data/lib/tdl/data_inf/bak/data_c_direct_mirror_auto.rb +138 -0
  980. data/lib/tdl/data_inf/bak/data_c_tmp_cache_auto.rb +138 -0
  981. data/lib/tdl/data_inf/bak/data_condition_mirror_auto.rb +216 -0
  982. data/lib/tdl/data_inf/bak/data_condition_valve_auto.rb +215 -0
  983. data/lib/tdl/data_inf/bak/data_connect_pipe.rb +80 -0
  984. data/lib/tdl/data_inf/bak/data_connect_pipe_inf_auto.rb +138 -0
  985. data/lib/tdl/data_inf/bak/data_inf_c_interconnect.rb +86 -0
  986. data/lib/tdl/data_inf/bak/data_inf_c_pipe_condition_auto.rb +157 -0
  987. data/lib/tdl/data_inf/bak/data_inf_cross_clk.rb +60 -0
  988. data/lib/tdl/data_inf/bak/data_inf_interconnect.rb +144 -0
  989. data/lib/tdl/data_inf/bak/data_inf_planer.rb +78 -0
  990. data/lib/tdl/data_inf/bak/data_inf_ticktack.rb +80 -0
  991. data/lib/tdl/data_inf/bak/data_inf_ticktock_auto.rb +0 -0
  992. data/lib/tdl/data_inf/bak/data_mirrors_auto.rb +234 -0
  993. data/lib/tdl/data_inf/bak/data_mirrors_verb.sv_auto.rb +234 -0
  994. data/lib/tdl/data_inf/bak/data_uncompress_auto.rb +177 -0
  995. data/lib/tdl/data_inf/bak/data_valve_auto.rb +127 -0
  996. data/lib/tdl/data_inf/bak/datainf_c_master_empty_auto.rb +95 -0
  997. data/lib/tdl/data_inf/bak/datainf_c_slaver_empty_auto.rb +88 -0
  998. data/lib/tdl/data_inf/bak/datainf_master_empty_auto.rb +95 -0
  999. data/lib/tdl/data_inf/bak/datainf_slaver_empty_auto.rb +88 -0
  1000. data/lib/tdl/data_inf/bak/independent_clock_fifo_auto.rb +298 -0
  1001. data/lib/tdl/data_inf/bak/part_data_pair_map_auto.rb +306 -0
  1002. data/lib/tdl/data_inf/common_fifo_auto.rb +141 -0
  1003. data/lib/tdl/data_inf/data_bind_auto.rb +79 -0
  1004. data/lib/tdl/data_inf/data_c_cache_auto.rb +135 -0
  1005. data/lib/tdl/data_inf/data_c_direct_auto.rb +127 -0
  1006. data/lib/tdl/data_inf/data_c_direct_mirror_auto.rb +127 -0
  1007. data/lib/tdl/data_inf/data_c_interconnect.rb +97 -0
  1008. data/lib/tdl/data_inf/data_c_pipe_force_vld_auto.rb +127 -0
  1009. data/lib/tdl/data_inf/data_c_pipe_inf_auto.rb +127 -0
  1010. data/lib/tdl/data_inf/data_c_pipe_intc_M2S_verc_auto.rb +123 -0
  1011. data/lib/tdl/data_inf/data_c_tmp_cache_auto.rb +127 -0
  1012. data/lib/tdl/data_inf/data_condition_mirror_auto.rb +165 -0
  1013. data/lib/tdl/data_inf/data_condition_valve_auto.rb +164 -0
  1014. data/lib/tdl/data_inf/data_connect_pipe_inf_auto.rb +127 -0
  1015. data/lib/tdl/data_inf/data_inf_c_pipe_condition_auto.rb +136 -0
  1016. data/lib/tdl/data_inf/data_mirrors_auto.rb +173 -0
  1017. data/lib/tdl/data_inf/data_mirrors_verb.sv_auto.rb +173 -0
  1018. data/lib/tdl/data_inf/data_uncompress_auto.rb +146 -0
  1019. data/lib/tdl/data_inf/data_valve_auto.rb +104 -0
  1020. data/lib/tdl/data_inf/datainf_c_master_empty_auto.rb +85 -0
  1021. data/lib/tdl/data_inf/datainf_c_slaver_empty_auto.rb +68 -0
  1022. data/lib/tdl/data_inf/datainf_master_empty_auto.rb +85 -0
  1023. data/lib/tdl/data_inf/datainf_slaver_empty_auto.rb +68 -0
  1024. data/lib/tdl/data_inf/independent_clock_fifo_auto.rb +141 -0
  1025. data/lib/tdl/data_inf/part_data_pair_map_auto.rb +149 -0
  1026. data/lib/tdl/data_inf/path_lib.rb +18 -0
  1027. data/lib/tdl/elements/Reset.rb +153 -0
  1028. data/lib/tdl/elements/axi4.rb +642 -0
  1029. data/lib/tdl/elements/axi_lite.rb +246 -0
  1030. data/lib/tdl/elements/axi_stream.rb +674 -0
  1031. data/lib/tdl/elements/clock.rb +193 -0
  1032. data/lib/tdl/elements/common_configure_reg.rb +135 -0
  1033. data/lib/tdl/elements/data_inf.rb +660 -0
  1034. data/lib/tdl/elements/logic.rb +356 -0
  1035. data/lib/tdl/elements/mail_box.rb +64 -0
  1036. data/lib/tdl/elements/originclass.rb +689 -0
  1037. data/lib/tdl/elements/parameter.rb +318 -0
  1038. data/lib/tdl/elements/track_inf.rb +163 -0
  1039. data/lib/tdl/elements/videoinf.rb +224 -0
  1040. data/lib/tdl/examples/10_random/exp_random.rb +13 -0
  1041. data/lib/tdl/examples/10_random/exp_random.sv +36 -0
  1042. data/lib/tdl/examples/11_test_unit/dve.tcl +64 -0
  1043. data/lib/tdl/examples/11_test_unit/exp_test_unit.rb +58 -0
  1044. data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +35 -0
  1045. data/lib/tdl/examples/11_test_unit/exp_test_unit_constraints.xdc +25 -0
  1046. data/lib/tdl/examples/11_test_unit/modules/sub_md0.rb +23 -0
  1047. data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +41 -0
  1048. data/lib/tdl/examples/11_test_unit/modules/sub_md1.rb +25 -0
  1049. data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv +41 -0
  1050. data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +28 -0
  1051. data/lib/tdl/examples/11_test_unit/tu0.sv +38 -0
  1052. data/lib/tdl/examples/11_test_unit/tu1.sv +28 -0
  1053. data/lib/tdl/examples/1_define_module/example1.rb +39 -0
  1054. data/lib/tdl/examples/1_define_module/exmple_md.sv +50 -0
  1055. data/lib/tdl/examples/2_hdl_class/always_comb.rb +99 -0
  1056. data/lib/tdl/examples/2_hdl_class/always_ff.rb +143 -0
  1057. data/lib/tdl/examples/2_hdl_class/case.rb +93 -0
  1058. data/lib/tdl/examples/2_hdl_class/foreach.rb +21 -0
  1059. data/lib/tdl/examples/2_hdl_class/function.rb +34 -0
  1060. data/lib/tdl/examples/2_hdl_class/generate.rb +62 -0
  1061. data/lib/tdl/examples/2_hdl_class/module_def.rb +33 -0
  1062. data/lib/tdl/examples/2_hdl_class/module_head_import_package.rb +36 -0
  1063. data/lib/tdl/examples/2_hdl_class/module_instance_test.rb +13 -0
  1064. data/lib/tdl/examples/2_hdl_class/package.rb +29 -0
  1065. data/lib/tdl/examples/2_hdl_class/package2.rb +21 -0
  1066. data/lib/tdl/examples/2_hdl_class/simple_assign.rb +39 -0
  1067. data/lib/tdl/examples/2_hdl_class/state_case.rb +65 -0
  1068. data/lib/tdl/examples/2_hdl_class/struct.rb +25 -0
  1069. data/lib/tdl/examples/2_hdl_class/struct_function.rb +28 -0
  1070. data/lib/tdl/examples/2_hdl_class/test_axi4_M2S.rb +16 -0
  1071. data/lib/tdl/examples/2_hdl_class/test_initial_assert.rb +11 -0
  1072. data/lib/tdl/examples/2_hdl_class/test_inst_sugar.rb +28 -0
  1073. data/lib/tdl/examples/2_hdl_class/test_module_port.rb +47 -0
  1074. data/lib/tdl/examples/2_hdl_class/test_module_var.rb +18 -0
  1075. data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv +108 -0
  1076. data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +35 -0
  1077. data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv +105 -0
  1078. data/lib/tdl/examples/2_hdl_class/tmp/head_pkg_module.sv +42 -0
  1079. data/lib/tdl/examples/2_hdl_class/tmp/init_module.sv +110 -0
  1080. data/lib/tdl/examples/2_hdl_class/tmp/module_instance_test.sv +31 -0
  1081. data/lib/tdl/examples/2_hdl_class/tmp/port_module.sv +99 -0
  1082. data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv +27 -0
  1083. data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv +78 -0
  1084. data/lib/tdl/examples/2_hdl_class/tmp/test_axi4_M2S.sv +30 -0
  1085. data/lib/tdl/examples/2_hdl_class/tmp/test_foreach.sv +34 -0
  1086. data/lib/tdl/examples/2_hdl_class/tmp/test_function.sv +52 -0
  1087. data/lib/tdl/examples/2_hdl_class/tmp/test_initial_assert.sv +31 -0
  1088. data/lib/tdl/examples/2_hdl_class/tmp/test_inst_sugar.sv +42 -0
  1089. data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +36 -0
  1090. data/lib/tdl/examples/2_hdl_class/tmp/test_module_port.sv +33 -0
  1091. data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +35 -0
  1092. data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +38 -0
  1093. data/lib/tdl/examples/2_hdl_class/tmp/test_package2.sv +36 -0
  1094. data/lib/tdl/examples/2_hdl_class/tmp/test_struct.sv +38 -0
  1095. data/lib/tdl/examples/2_hdl_class/tmp/test_struct_function.sv +44 -0
  1096. data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +27 -0
  1097. data/lib/tdl/examples/2_hdl_class/tmp/text_generate.sv +54 -0
  1098. data/lib/tdl/examples/2_hdl_class/vcs_string.rb +5 -0
  1099. data/lib/tdl/examples/3_hdl_sdl_instance/hdl_test.sv +13 -0
  1100. data/lib/tdl/examples/3_hdl_sdl_instance/main.rb +26 -0
  1101. data/lib/tdl/examples/3_hdl_sdl_instance/main_md.sv +42 -0
  1102. data/lib/tdl/examples/3_hdl_sdl_instance/sdl_md.sv +30 -0
  1103. data/lib/tdl/examples/3_hdl_sdl_instance/sdl_test.rb +9 -0
  1104. data/lib/tdl/examples/4_generate/example.rb +38 -0
  1105. data/lib/tdl/examples/4_generate/test_generate.sv +59 -0
  1106. data/lib/tdl/examples/5_logic_combin/login_combin.rb +22 -0
  1107. data/lib/tdl/examples/5_logic_combin/test_logic_combin.sv +36 -0
  1108. data/lib/tdl/examples/6_module_with_interface/example.rb +48 -0
  1109. data/lib/tdl/examples/6_module_with_interface/example_interface.sv +40 -0
  1110. data/lib/tdl/examples/6_module_with_interface/inf_collect.rb +54 -0
  1111. data/lib/tdl/examples/6_module_with_interface/inf_collect.sv +63 -0
  1112. data/lib/tdl/examples/7_module_with_package/body_package.rb +3 -0
  1113. data/lib/tdl/examples/7_module_with_package/body_package.sv +25 -0
  1114. data/lib/tdl/examples/7_module_with_package/example_pkg.rb +20 -0
  1115. data/lib/tdl/examples/7_module_with_package/example_pkg.sv +35 -0
  1116. data/lib/tdl/examples/7_module_with_package/head_package.rb +8 -0
  1117. data/lib/tdl/examples/7_module_with_package/head_package.sv +29 -0
  1118. data/lib/tdl/examples/8_top_module/dve.tcl +64 -0
  1119. data/lib/tdl/examples/8_top_module/example.rb +8 -0
  1120. data/lib/tdl/examples/8_top_module/pins.yml +7 -0
  1121. data/lib/tdl/examples/8_top_module/tb_test_top.sv +29 -0
  1122. data/lib/tdl/examples/8_top_module/test_top.sv +28 -0
  1123. data/lib/tdl/examples/8_top_module/test_top_constraints.xdc +37 -0
  1124. data/lib/tdl/examples/9_itegration/A_itgt/a_test_md.sv +29 -0
  1125. data/lib/tdl/examples/9_itegration/A_itgt/a_test_module.rb +6 -0
  1126. data/lib/tdl/examples/9_itegration/A_itgt/itgt_module_a_block.rb +34 -0
  1127. data/lib/tdl/examples/9_itegration/clock_manage/itgt_module_clock_manage.rb +33 -0
  1128. data/lib/tdl/examples/9_itegration/clock_manage/simple_clock.rb +7 -0
  1129. data/lib/tdl/examples/9_itegration/clock_manage/simple_clock.sv +29 -0
  1130. data/lib/tdl/examples/9_itegration/dve.tcl +64 -0
  1131. data/lib/tdl/examples/9_itegration/pins.yml +4 -0
  1132. data/lib/tdl/examples/9_itegration/tb_test_top.sv +29 -0
  1133. data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +29 -0
  1134. data/lib/tdl/examples/9_itegration/test_top.sv +40 -0
  1135. data/lib/tdl/examples/9_itegration/test_top_constraints.xdc +29 -0
  1136. data/lib/tdl/examples/9_itegration/test_tttop.sv +40 -0
  1137. data/lib/tdl/examples/9_itegration/test_tttop_constraints.xdc +29 -0
  1138. data/lib/tdl/examples/9_itegration/top.rb +11 -0
  1139. data/lib/tdl/examples/readme.md +31 -0
  1140. data/lib/tdl/exlib/common_cfg_reg_inf.rb +139 -0
  1141. data/lib/tdl/exlib/constraints.rb +286 -0
  1142. data/lib/tdl/exlib/constraints_verb.rb +304 -0
  1143. data/lib/tdl/exlib/dve_tcl.rb +162 -0
  1144. data/lib/tdl/exlib/element_class_vars.rb +106 -0
  1145. data/lib/tdl/exlib/global_param.rb +108 -0
  1146. data/lib/tdl/exlib/integral_test/bak/integral_test.rb +206 -0
  1147. data/lib/tdl/exlib/integral_test/clock_itest.rb +28 -0
  1148. data/lib/tdl/exlib/integral_test/diff_clock_itest.rb +30 -0
  1149. data/lib/tdl/exlib/integral_test/io_itest.rb +41 -0
  1150. data/lib/tdl/exlib/integral_test/reset_itest.rb +31 -0
  1151. data/lib/tdl/exlib/integral_test/simple_logic_itest.rb +19 -0
  1152. data/lib/tdl/exlib/itegration.rb +307 -0
  1153. data/lib/tdl/exlib/itegration_verb.rb +913 -0
  1154. data/lib/tdl/exlib/parse_argv.rb +43 -0
  1155. data/lib/tdl/exlib/sdlmodule_sim.bak.rb +375 -0
  1156. data/lib/tdl/exlib/test_point.rb +287 -0
  1157. data/lib/tdl/global_scan.rb +134 -0
  1158. data/lib/tdl/rebuild_ele/axi4.rb +141 -0
  1159. data/lib/tdl/rebuild_ele/axi_lite.rb +56 -0
  1160. data/lib/tdl/rebuild_ele/axi_stream.rb +121 -0
  1161. data/lib/tdl/rebuild_ele/cm_ram_inf.sv +105 -0
  1162. data/lib/tdl/rebuild_ele/cm_ram_inf_define.rb +44 -0
  1163. data/lib/tdl/rebuild_ele/data_inf.rb +27 -0
  1164. data/lib/tdl/rebuild_ele/data_inf_c.rb +83 -0
  1165. data/lib/tdl/rebuild_ele/ele_base.rb +822 -0
  1166. data/lib/tdl/rebuild_ele/readme.md +1 -0
  1167. data/lib/tdl/sdlimplement/resource.yml +154 -0
  1168. data/lib/tdl/sdlimplement/sdl_impl_module.rb +391 -0
  1169. data/lib/tdl/sdlimplement/sdl_impl_param.rb +26 -0
  1170. data/lib/tdl/sdlimplement/test.rb +64 -0
  1171. data/lib/tdl/sdlmodule/bak/sdlmodule_varible_ex.rb +120 -0
  1172. data/lib/tdl/sdlmodule/generator_block_module.rb +84 -0
  1173. data/lib/tdl/sdlmodule/sdlmodule.rb +407 -0
  1174. data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb +333 -0
  1175. data/lib/tdl/sdlmodule/sdlmodule_draw.rb +272 -0
  1176. data/lib/tdl/sdlmodule/sdlmodule_head_logo.txt +10 -0
  1177. data/lib/tdl/sdlmodule/sdlmodule_instance.rb +623 -0
  1178. data/lib/tdl/sdlmodule/sdlmodule_port_define.rb +374 -0
  1179. data/lib/tdl/sdlmodule/sdlmodule_varible.rb +160 -0
  1180. data/lib/tdl/sdlmodule/sdlmodule_vcs_comptable.rb +140 -0
  1181. data/lib/tdl/sdlmodule/techbench_module.rb +14 -0
  1182. data/lib/tdl/sdlmodule/test_unit_module.rb +138 -0
  1183. data/lib/tdl/sdlmodule/top_module.rb +543 -0
  1184. data/lib/tdl/tdl.rb +265 -0
  1185. data/lib/tdl/tdlerror/tdlerror.rb +8 -0
  1186. data/lib/tdl/testunit/test_all.rb +4 -0
  1187. data/lib/tdl/testunit/test_array_chain.rb +89 -0
  1188. data/lib/tdl/testunit/test_tmp.rb +47 -0
  1189. metadata +1301 -0
data/lib/axi/AXI_Lite/common_configure_reg_interface/common_configure_reg_interface.sv ADDED
@@ -0,0 +1,230 @@
1
+
2
+ /**********************************************
3
+ _______________________________________
4
+ ___________ Cook Darwin __________
5
+ _______________________________________
6
+ descript: 通用配置寄存器接口 用于配置模块寄存器
7
+ author : Cook.Darwin
8
+ Version: VERA.0.0
9
+ creaded: 2017/1/9
10
+ madified:
11
+ ***********************************************/
12
+ interface common_configure_reg_interface #(
13
+ parameter ASIZE = 8,
14
+ parameter DSIZE = 32
15
+ )();
16
+
17
+ // `include "E:/work/xilinx_exp/digilent_aritx_ethernet_1205/RTL/data_interface/cfg_reg_define.svh"
18
+
19
+ // logic [ASIZE-1:0] bus_addr;
20
+ logic [DSIZE-1:0] wdata;
21
+ logic [DSIZE-1:0] rdata;
22
+ logic [ASIZE-1:0] addr;
23
+ logic [DSIZE-1:0] default_value;
24
+ logic rst;
25
+ logic interrupt_enable;
26
+ logic interrupt_trigger;
27
+
28
+
29
+ modport master ( //configure centor
30
+ output wdata,
31
+ input rdata,
32
+ input addr,
33
+ input default_value,
34
+ input rst,
35
+ input interrupt_enable,
36
+ input interrupt_trigger
37
+ // import function logic[DSIZE-1:0] SET_REG(
38
+ // input int faddr,
39
+ // // output [cfg_inf.DSIZE-1:0] fwdata,
40
+ // input int fdefault_value,
41
+ // input int frdata,
42
+ // input int frst)
43
+ );
44
+
45
+ modport slaver (
46
+ input wdata,
47
+ output rdata,
48
+ output addr,
49
+ output default_value,
50
+ output rst,
51
+ output interrupt_enable,
52
+ output interrupt_trigger
53
+ );
54
+
55
+ // function logic [DSIZE-1:0] SET_REG(
56
+ // input int faddr,
57
+ // // output [cfg_inf.DSIZE-1:0] fwdata,
58
+ // input int fdefault_value,
59
+ // input int frdata,
60
+ // input int frst);
61
+ //
62
+ // addr = faddr[ASIZE-1:0];
63
+ // // fwdata = wdata;
64
+ // rdata = frdata[DSIZE-1:0];
65
+ // rst = frst[0];
66
+ //
67
+ // default_value = fdefault_value[DSIZE-1:0];
68
+ //
69
+ // return wdata;
70
+ //
71
+ // endfunction:SET_REG
72
+
73
+
74
+ endinterface:common_configure_reg_interface
75
+
76
+ module CFG_REG #(
77
+ parameter DSIZE = 32
78
+ )(
79
+ common_configure_reg_interface.slaver cfg_inf,
80
+ input int addr,
81
+ output[DSIZE-1:0] wdata,
82
+ input [DSIZE-1:0] default_value,
83
+ input [DSIZE-1:0] rdata,
84
+ input logic rst
85
+ );
86
+
87
+ assign cfg_inf.addr = addr[cfg_inf.ASIZE-1:0];
88
+ assign wdata = cfg_inf.wdata[DSIZE-1:0];
89
+ assign cfg_inf.default_value = default_value[cfg_inf.DSIZE-1:0];
90
+ assign cfg_inf.rdata[DSIZE-1:0] = rdata;
91
+ assign cfg_inf.rst = rst;
92
+ assign cfg_inf.interrupt_enable = 1'b0;
93
+ assign cfg_inf.interrupt_trigger = 1'b0;
94
+ endmodule:CFG_REG
95
+
96
+ // module CFG_REG_A1 #(
97
+ // parameter DSIZE = 1
98
+ // )(
99
+ // common_configure_reg_interface.slaver cfg_inf,
100
+ // input int addr,
101
+ // output [DSIZE-1:0] wdata,
102
+ // input [DSIZE-1:0] default_value,
103
+ // input [DSIZE-1:0] rdata,
104
+ // input rst
105
+ // );
106
+ //
107
+ // assign cfg_inf.addr = addr[cfg_inf.ASIZE-1:0];
108
+ // assign wdata = cfg_inf.wdata;
109
+ // assign cfg_inf.default_value = default_value[cfg_inf.DSIZE-1:0];
110
+ // assign cfg_inf.rdata = rdata[cfg_inf.DSIZE-1:0];
111
+ // assign cfg_inf.rst = rst[0];
112
+ // assign cfg_inf.interrupt_enable = 1'b0;
113
+ // assign cfg_inf.interrupt_trigger = 1'b0;
114
+ // endmodule:CFG_REG_A1
115
+
116
+ module CFG_REG_INTR (
117
+ common_configure_reg_interface.slaver cfg_inf,
118
+ input int addr,
119
+ output int wdata,
120
+ input int default_value,
121
+ input int rdata,
122
+ input int rst,
123
+ input logic interrupt_trigger
124
+ );
125
+
126
+ assign cfg_inf.addr = addr[cfg_inf.ASIZE-1:0];
127
+ assign wdata = cfg_inf.wdata;
128
+ assign cfg_inf.default_value = default_value[cfg_inf.DSIZE-1:0];
129
+ assign cfg_inf.rdata = rdata[cfg_inf.DSIZE-1:0];
130
+ assign cfg_inf.rst = rst[0];
131
+ assign cfg_inf.interrupt_enable = 1'b1;
132
+ assign cfg_inf.interrupt_trigger = interrupt_trigger;
133
+
134
+ endmodule:CFG_REG_INTR
135
+
136
+ module general_reg (
137
+ common_configure_reg_interface.slaver cfg_inf,
138
+ input int addr,
139
+ output int data,
140
+ input int default_value
141
+ );
142
+
143
+ CFG_REG CFG_REG_INST(
144
+ /* common_configure_reg_interface.slaver */ .cfg_inf (cfg_inf ),
145
+ /* input int */ .addr (addr ),
146
+ /* output [cfg_inf.DSIZE-1:0] */ .wdata (data ),
147
+ /* input int */ .default_value (default_value),
148
+ /* input int */ .rdata (data ),
149
+ /* input int */ .rst (0 )
150
+ );
151
+
152
+ endmodule:general_reg
153
+
154
+ module general_reg_intr (
155
+ common_configure_reg_interface.slaver cfg_inf,
156
+ input int addr,
157
+ output int data,
158
+ input int default_value,
159
+ input interrupt_trigger
160
+ );
161
+
162
+ CFG_REG_INTR CFG_REG_INST(
163
+ /* common_configure_reg_interface.slaver */ .cfg_inf (cfg_inf ),
164
+ /* input int */ .addr (addr ),
165
+ /* output [cfg_inf.DSIZE-1:0] */ .wdata (data ),
166
+ /* input int */ .default_value (default_value),
167
+ /* input int */ .rdata (data ),
168
+ /* input int */ .rst ('0 ),
169
+ /* input */ .interrupt_trigger (interrupt_trigger )
170
+ );
171
+
172
+ endmodule:general_reg_intr
173
+
174
+ module general_only_read_reg #(
175
+ parameter DSIZE = 32
176
+ )(
177
+ common_configure_reg_interface.slaver cfg_inf,
178
+ input int addr,
179
+ input [DSIZE-1:0] rdata
180
+ );
181
+
182
+ CFG_REG #(DSIZE) CFG_REG_INST(
183
+ /* common_configure_reg_interface.slaver */ .cfg_inf (cfg_inf ),
184
+ /* input int */ .addr (addr ),
185
+ /* output nit */ .wdata ( ),
186
+ /* input int */ .default_value ('0 ),
187
+ /* input int */ .rdata (rdata ),
188
+ /* input int */ .rst ('0 )
189
+ );
190
+
191
+ endmodule:general_only_read_reg
192
+
193
+ module general_only_read_reg_intr (
194
+ common_configure_reg_interface.slaver cfg_inf,
195
+ input int addr,
196
+ input int rdata,
197
+ input interrupt_trigger
198
+ );
199
+
200
+ CFG_REG_INTR CFG_REG_INST(
201
+ /* common_configure_reg_interface.slaver */ .cfg_inf (cfg_inf ),
202
+ /* input int */ .addr (addr ),
203
+ /* output nit */ .wdata ( ),
204
+ /* input int */ .default_value ('0 ),
205
+ /* input int */ .rdata (rdata ),
206
+ /* input int */ .rst ('0 ),
207
+ /* input */ .interrupt_trigger (interrupt_trigger)
208
+ );
209
+
210
+ endmodule:general_only_read_reg_intr
211
+
212
+ module general_pulse(
213
+ common_configure_reg_interface.slaver cfg_inf,
214
+ input int addr,
215
+ output data
216
+ );
217
+
218
+ int wdata;
219
+ assign data = wdata[0];
220
+
221
+ CFG_REG CFG_REG_inst(
222
+ /* common_configure_reg_interface.slaver */ .cfg_inf (cfg_inf ),
223
+ /* input int */ .addr (addr ),
224
+ /* output int */ .wdata (wdata ),
225
+ /* input int */ .default_value ('0 ),
226
+ /* input int */ .rdata ('0 ),
227
+ /* input int */ .rst (data )
228
+ );
229
+
230
+ endmodule:general_pulse
data/lib/axi/AXI_Lite/common_configure_reg_interface/common_configure_reg_interface.sv.bak ADDED
@@ -0,0 +1,109 @@
1
+ /**********************************************
2
+ _______________________________________
3
+ ___________ Cook Darwin __________
4
+ _______________________________________
5
+ descript: 通用配置寄存器接口 用于配置模块寄存器
6
+ author : Cook.Darwin
7
+ Version: VERA.0.1 : 2017/11/24
8
+ creaded: 2017/1/9
9
+ madified:
10
+ ***********************************************/
11
+ interface common_configure_reg_interface #(
12
+ parameter ASIZE = 8,
13
+ parameter DSIZE = 32
14
+ )();
15
+
16
+ // logic [ASIZE-1:0] bus_addr;
17
+ logic [DSIZE-1:0] wdata;
18
+ logic [DSIZE-1:0] rdata;
19
+ logic [ASIZE-1:0] addr;
20
+ logic [DSIZE-1:0] default_value;
21
+ logic rst;
22
+
23
+ logic interrupt_enable;
24
+ logic interrupt_trigger;
25
+
26
+ assign interrupt_enable= 1'b0;
27
+ assign interrupt_trigger =1'b0;
28
+
29
+
30
+ modport master (
31
+ output wdata,
32
+ input rdata,
33
+ input addr,
34
+ input default_value,
35
+ input rst,
36
+ input interrupt_enable,
37
+ input interrupt_trigger
38
+ // import function logic[DSIZE-1:0] SET_REG(
39
+ // input int faddr,
40
+ // // output [cfg_inf.DSIZE-1:0] fwdata,
41
+ // input int fdefault_value,
42
+ // input int frdata,
43
+ // input int frst)
44
+ );
45
+
46
+ modport slaver (
47
+ input wdata,
48
+ output rdata,
49
+ output addr,
50
+ output default_value,
51
+ output rst,
52
+ input interrupt_enable,
53
+ input interrupt_trigger
54
+ );
55
+
56
+
57
+ endinterface:common_configure_reg_interface
58
+
59
+ module CFG_REG (
60
+ common_configure_reg_interface.slaver cfg_inf,
61
+ input int addr,
62
+ output int wdata,
63
+ input int default_value,
64
+ input int rdata,
65
+ input int rst
66
+ );
67
+
68
+ assign cfg_inf.addr = addr[cfg_inf.ASIZE-1:0];
69
+ assign wdata = cfg_inf.wdata;
70
+ assign cfg_inf.default_value = default_value[cfg_inf.DSIZE-1:0];
71
+ assign cfg_inf.rdata = rdata[cfg_inf.DSIZE-1:0];
72
+ assign cfg_inf.rst = rst[0];
73
+
74
+ endmodule:CFG_REG
75
+
76
+ module general_reg (
77
+ common_configure_reg_interface.slaver cfg_inf,
78
+ input int addr,
79
+ output int data,
80
+ input int default_value
81
+ );
82
+
83
+ CFG_REG CFG_REG_INST(
84
+ /* common_configure_reg_interface.slaver */ .cfg_inf (cfg_inf ),
85
+ /* input int */ .addr (addr ),
86
+ /* output [cfg_inf.DSIZE-1:0] */ .wdata (data ),
87
+ /* input int */ .default_value (default_value),
88
+ /* input int */ .rdata (data ),
89
+ /* input int */ .rst (0 )
90
+ );
91
+
92
+ endmodule:general_reg
93
+
94
+ module general_only_read_reg (
95
+ common_configure_reg_interface.slaver cfg_inf,
96
+ input int addr,
97
+ input int rdata
98
+ );
99
+
100
+ CFG_REG CFG_REG_INST(
101
+ /* common_configure_reg_interface.slaver */ .cfg_inf (cfg_inf ),
102
+ /* input int */ .addr (addr ),
103
+ /* output nit */ .wdata ( ),
104
+ /* input int */ .default_value (0 ),
105
+ /* input int */ .rdata (rdata ),
106
+ /* input int */ .rst (0 )
107
+ );
108
+
109
+ endmodule:general_only_read_reg
data/lib/axi/AXI_Lite/common_configure_reg_interface/jtag_to_axilite_wrapper.sv ADDED
@@ -0,0 +1,56 @@
1
+ /**********************************************
2
+ _______________________________________
3
+ ___________ Cook Darwin __________
4
+ _______________________________________
5
+ descript:
6
+ author : Cook.Darwin
7
+ Version: VERA.0.0
8
+ creaded: 2017/11/16
9
+ madified:
10
+ ***********************************************/
11
+ `timescale 1ns/1ps
12
+ (* axi_lite = "true" *)
13
+ module jtag_to_axilite_wrapper(
14
+ axi_lite_inf.master lite
15
+ );
16
+
17
+ import SystemPkg::*;
18
+ assign clock = lite.axi_aclk;
19
+ assign rst_n = lite.axi_aresetn;
20
+
21
+
22
+ generate
23
+ if(SIM=="FALSE" || SIM=="OFF")begin
24
+
25
+ assign lite.axi_arlock = 1'b0;
26
+ assign lite.axi_awlock = 1'b0;
27
+
28
+ jtag_axi_0 jtag_axi_0_inst(
29
+ /* input */ .aclk (clock ),
30
+ /* input */ .aresetn (/*rst_n*/1'b1 ),
31
+ /* output [31:0] */ .m_axi_awaddr (lite.axi_awaddr ),
32
+ /* output [2:0] */ .m_axi_awprot (/*lite.axi_awprot*/ ),
33
+ /* output */ .m_axi_awvalid (lite.axi_awvalid ),
34
+ /* input */ .m_axi_awready (lite.axi_awready ),
35
+ /* output [31:0] */ .m_axi_wdata (lite.axi_wdata ),
36
+ /* output [3:0] */ .m_axi_wstrb (/*lite.axi_wstrb */ ),
37
+ /* output */ .m_axi_wvalid (lite.axi_wvalid ),
38
+ /* input */ .m_axi_wready (lite.axi_wready ),
39
+ /* input [1:0] */ .m_axi_bresp (lite.axi_bresp ),
40
+ /* input */ .m_axi_bvalid (lite.axi_bvalid ),
41
+ /* output */ .m_axi_bready (lite.axi_bready ),
42
+ /* output [31:0] */ .m_axi_araddr (lite.axi_araddr ),
43
+ /* output [2:0] */ .m_axi_arprot (/*lite.axi_arprot */ ),
44
+ /* output */ .m_axi_arvalid (lite.axi_arvalid ),
45
+ /* input */ .m_axi_arready (lite.axi_arready ),
46
+ /* input [31:0] */ .m_axi_rdata (lite.axi_rdata ),
47
+ /* input [1:0] */ .m_axi_rresp (/*lite.axi_rresp */'0 ),
48
+ /* input */ .m_axi_rvalid (lite.axi_rvalid ),
49
+ /* output */ .m_axi_rready (lite.axi_rready )
50
+ );
51
+ end else
52
+ sim_jtag_debug jtag_axi_0_inst(
53
+ /* axi_lite_inf.master */ .lite (lite )
54
+ );
55
+ endgenerate
56
+ endmodule
data/lib/axi/AXI_Lite/gen_axi_lite_ctrl.sv ADDED
@@ -0,0 +1,515 @@
1
+ /**********************************************
2
+ _______________________________________
3
+ ___________ Cook Darwin __________
4
+ _______________________________________
5
+ descript:
6
+ author : Cook.Darwin
7
+ Version: VERA.0.0
8
+ creaded: 2017/1/11
9
+ madified:
10
+ ***********************************************/
11
+ `timescale 1ns/1ps
12
+ interface Lite_Addr_Data_CMD #(
13
+ parameter ASIZE = 8,
14
+ parameter DSIZE = 32
15
+ )();
16
+
17
+ // `include "E:/work/xilinx_exp/digilent_aritx_ethernet_1205/RTL/data_interface/cfg_reg_define.svh"
18
+
19
+ parameter bit WRITE = 1,
20
+ READ = 0;
21
+
22
+ logic [ASIZE-1:0] addr;
23
+ logic [DSIZE-1:0] wdata;
24
+ logic [DSIZE-1:0] rdata;
25
+ logic wr_rd_type;
26
+ logic wait_intrq;
27
+ logic intrq;
28
+
29
+ logic keep_read;
30
+ logic [DSIZE-1:0] meet_rdata;
31
+ logic [DSIZE-1:0] meet_keep;
32
+ logic en_keep;
33
+
34
+ modport master (
35
+ output addr,
36
+ output wdata,
37
+ input rdata,
38
+ output wr_rd_type,
39
+ output wait_intrq,
40
+ output intrq,
41
+ output keep_read,
42
+ output meet_rdata,
43
+ output meet_keep,
44
+ output en_keep,
45
+ import function bit WriteCode(),
46
+ function bit ReadCode(),
47
+ function bit IfWrite(),
48
+ function bit IfRead()
49
+ );
50
+
51
+ modport slaver (
52
+ input addr,
53
+ input wdata,
54
+ output rdata,
55
+ input wr_rd_type,
56
+ input wait_intrq,
57
+ input intrq,
58
+ input keep_read,
59
+ input meet_rdata,
60
+ input meet_keep,
61
+ input en_keep,
62
+ import function bit WriteCode(),
63
+ function bit ReadCode(),
64
+ function bit IfWrite(),
65
+ function bit IfRead()
66
+ );
67
+
68
+ function bit WriteCode();
69
+ return WRITE;
70
+ endfunction:WriteCode
71
+
72
+
73
+ function bit ReadCode();
74
+ return READ;
75
+ endfunction:ReadCode
76
+
77
+ function bit IfWrite();
78
+ return wr_rd_type == WRITE;
79
+ endfunction:IfWrite
80
+
81
+ function bit IfRead();
82
+ return wr_rd_type == READ;
83
+ endfunction:IfRead
84
+
85
+ endinterface:Lite_Addr_Data_CMD
86
+
87
+ module gen_axi_lite_ctrl #(
88
+ parameter NUM = 32
89
+ )(
90
+ input from_up_trigger,
91
+ output logic to_domn_trigger,
92
+ axi_lite_inf.master lite,
93
+ Lite_Addr_Data_CMD.slaver addrdatac [NUM-1:0],
94
+ output logic [lite.DSIZE-1:0] lite_rdata
95
+ );
96
+
97
+ genvar KK;
98
+
99
+ logic[lite.ASIZE-1:0] addr [NUM-1:0];
100
+ logic[lite.DSIZE-1:0] wdata[NUM-1:0];
101
+ logic[lite.DSIZE-1:0] rdata[NUM-1:0];
102
+
103
+ logic[NUM-1:0] wr_rd_type;
104
+ logic[NUM-1:0] wait_intrq;
105
+ logic[NUM-1:0] intrq;
106
+
107
+ logic[NUM-1:0] keep_read;
108
+ logic[lite.DSIZE-1:0] meet_rdata[NUM-1:0];
109
+ logic[lite.DSIZE-1:0] meet_keep[NUM-1:0];
110
+ logic[NUM-1:0] en_keep;
111
+
112
+ generate
113
+ for(KK=0;KK<NUM;KK++)begin
114
+ assign addr[KK] = addrdatac[KK].addr;
115
+ assign wdata[KK] = addrdatac[KK].wdata;
116
+ assign addrdatac[KK].rdata = rdata[KK];
117
+ assign wr_rd_type[KK] = addrdatac[KK].wr_rd_type;
118
+ assign wait_intrq[KK] = addrdatac[KK].wait_intrq;
119
+ assign intrq[KK] = addrdatac[KK].intrq;
120
+ assign keep_read[KK] = addrdatac[KK].keep_read;
121
+ assign meet_rdata[KK] = addrdatac[KK].meet_rdata;
122
+ assign meet_keep[KK] = addrdatac[KK].meet_keep;
123
+ assign en_keep[KK] = addrdatac[KK].en_keep;
124
+ end
125
+ endgenerate
126
+
127
+ wire clock,rst_n;
128
+
129
+ assign clock = lite.axi_aclk;
130
+ assign rst_n = lite.axi_aresetn;
131
+
132
+ localparam NSIZE = (NUM+2) <= 2 ? 1 :
133
+ (NUM+2) <= 4 ? 2 :
134
+ (NUM+2) <= 8 ? 3 :
135
+ (NUM+2) <= 16 ? 4 :
136
+ (NUM+2) <= 32 ? 5 :
137
+ (NUM+2) <= 64 ? 6 :
138
+ (NUM+2) <= 128 ? 7 :
139
+ (NUM+2) <= 256 ? 8 : 16;
140
+
141
+ logic [NSIZE-1:0] state;
142
+
143
+ //--->> RECORD INTRQ <<---------------------------
144
+ logic rst_recd_wr_rd_ok;
145
+ logic recd_wr_rd_ok;
146
+ logic wr_rd_ok;
147
+
148
+ always@(posedge clock,negedge rst_n)
149
+ if(~rst_n) recd_wr_rd_ok <= 1'b0;
150
+ else begin
151
+ if(rst_recd_wr_rd_ok)
152
+ recd_wr_rd_ok <= 1'b0;
153
+ else if(wr_rd_ok)
154
+ recd_wr_rd_ok <= 1'b1;
155
+ else recd_wr_rd_ok <= recd_wr_rd_ok;
156
+ end
157
+ //---<< RECORD INTRQ >>---------------------------
158
+
159
+ always@(posedge clock)
160
+ if(~rst_n) state <= {NSIZE{1'b0}};
161
+ else begin
162
+ if(from_up_trigger && state=={NSIZE{1'b0}})
163
+ state <= 1;
164
+ else begin
165
+ if(state == (NUM+1) )
166
+ state <= {NSIZE{1'b0}} ;
167
+ else if(wr_rd_ok)
168
+ state <= state + (!wait_intrq[state-1]);
169
+ else if(recd_wr_rd_ok && wait_intrq[state-1])
170
+ state <= state + intrq[state-1];
171
+ else state <= state ;
172
+ end
173
+ end
174
+
175
+
176
+ logic wr_ok;
177
+ logic wr_data_ok,wr_addr_ok;
178
+
179
+ logic rd_ok;
180
+ logic rd_addr_ok;
181
+
182
+ always@(posedge clock,negedge rst_n)
183
+ if(~rst_n) wr_ok <= 1'b0;
184
+ else wr_ok <= ( (lite.axi_awready && lite.axi_awvalid) || wr_addr_ok ) && ((lite.axi_wready && lite.axi_wvalid) || wr_data_ok) && (lite.axi_bready && lite.axi_bvalid);
185
+
186
+ always@(posedge clock,negedge rst_n)
187
+ if(~rst_n) rd_ok <= 1'b0;
188
+ else begin
189
+ if(en_keep[state-1])
190
+ rd_ok <= ( (lite.axi_arready && lite.axi_arvalid) || rd_addr_ok ) && (lite.axi_rready && lite.axi_rvalid) && (!keep_read[state-1] || (lite.axi_rdata & meet_keep[state-1])==(meet_rdata[state-1] & meet_keep[state-1]));
191
+ else
192
+ rd_ok <= ( (lite.axi_arready && lite.axi_arvalid) || rd_addr_ok ) && (lite.axi_rready && lite.axi_rvalid) && (!keep_read[state-1] || lite.axi_rdata == meet_rdata[state-1] );
193
+ end
194
+
195
+ assign wr_rd_ok = wr_ok | rd_ok;
196
+ //--->> FLAG <<----------------------------
197
+ logic flag;
198
+ logic [NSIZE-1:0] old_state;
199
+
200
+ always@(posedge clock,negedge rst_n)
201
+ if(~rst_n) old_state <= {NSIZE{1'b0}};
202
+ else old_state <= state;
203
+
204
+ always@(posedge clock,negedge rst_n)
205
+ if(~rst_n) flag <= 1'b0;
206
+ else flag <= state != old_state && state != (NUM+1);
207
+
208
+ assign rst_recd_wr_rd_ok = flag;
209
+ //---<< FLAG >>----------------------------
210
+ //--->> CTRL <<-----------------------------------
211
+ always@(posedge clock,negedge rst_n)
212
+ if(~rst_n) wr_data_ok <= 1'b0;
213
+ else begin
214
+ // if(flag)
215
+ // wr_data_ok <= 1'b0;
216
+ // else
217
+ if(~wr_data_ok)begin
218
+ if(lite.axi_wready && lite.axi_wvalid)
219
+ wr_data_ok <= 1'b1;
220
+ else wr_data_ok <= 1'b0;
221
+ end else begin
222
+ if(lite.axi_bready && lite.axi_bvalid)
223
+ wr_data_ok <= 1'b0;
224
+ else wr_data_ok <= 1'b1;
225
+ end
226
+ end
227
+
228
+ always@(posedge clock,negedge rst_n)
229
+ if(~rst_n) wr_addr_ok <= 1'b0;
230
+ else begin
231
+ // if(flag)
232
+ // wr_addr_ok <= 1'b0;
233
+ // else
234
+ if(~wr_addr_ok)begin
235
+ if(lite.axi_awready && lite.axi_awvalid)
236
+ wr_addr_ok <= 1'b1;
237
+ else wr_addr_ok <= 1'b0;
238
+ end else begin
239
+ if(lite.axi_bready && lite.axi_bvalid)
240
+ wr_addr_ok <= 1'b0;
241
+ else wr_addr_ok <= 1'b1;
242
+ end
243
+ end
244
+
245
+ always@(posedge clock,negedge rst_n)
246
+ if(~rst_n) rd_addr_ok <= 1'b0;
247
+ else begin
248
+ if(flag)
249
+ rd_addr_ok <= 1'b0;
250
+ else if(~rd_addr_ok)begin
251
+ if(lite.axi_arready && lite.axi_arvalid)
252
+ rd_addr_ok <= 1'b1;
253
+ else rd_addr_ok <= 1'b0;
254
+ end else begin
255
+ if(lite.axi_rvalid && lite.axi_rready)
256
+ rd_addr_ok <= 1'b0;
257
+ else rd_addr_ok <= 1'b1;
258
+ end
259
+ end
260
+ //---<< CTRL >>-----------------------------------
261
+ //--->> ADDR WR <<-------------------------
262
+ always@(posedge clock,negedge rst_n)
263
+ if(~rst_n) lite.axi_awvalid <= 1'b0;
264
+ else begin
265
+ if(state > 0 && state < NUM+1)begin
266
+ if(flag)
267
+ lite.axi_awvalid <= wr_rd_type[state-1]==addrdatac[0].WRITE ;
268
+ else if(lite.axi_awvalid && lite.axi_awready)
269
+ lite.axi_awvalid <= 1'b0;
270
+ else lite.axi_awvalid <= lite.axi_awvalid;
271
+ end else lite.axi_awvalid <= 1'b0;
272
+ end
273
+
274
+ always@(posedge clock,negedge rst_n)
275
+ if(~rst_n) lite.axi_awaddr <= {lite.ASIZE{1'b0}};
276
+ else begin
277
+ if(state > 0 && state < NUM+1)begin
278
+ if(wr_rd_type[state-1]==addrdatac[0].WRITE)
279
+ lite.axi_awaddr <= addr[state-1];
280
+ else lite.axi_awaddr <= lite.axi_awaddr;
281
+ end else lite.axi_awaddr <= lite.axi_awaddr;
282
+ end
283
+ //---<< ADDR WR >>-------------------------
284
+ //--->> DATA WR <<-------------------------
285
+ always@(posedge clock,negedge rst_n)
286
+ if(~rst_n) lite.axi_wvalid <= 1'b0;
287
+ else begin
288
+ if(state > 0 && state < NUM+1)begin
289
+ if(flag)
290
+ lite.axi_wvalid <= wr_rd_type[state-1]==addrdatac[0].WRITE ;
291
+ else if(lite.axi_wvalid && lite.axi_wready)
292
+ lite.axi_wvalid <= 1'b0;
293
+ else lite.axi_wvalid <= lite.axi_wvalid;
294
+ end else lite.axi_wvalid <= 1'b0;
295
+ end
296
+
297
+ always@(posedge clock,negedge rst_n)
298
+ if(~rst_n) lite.axi_wdata <= {lite.DSIZE{1'b0}};
299
+ else begin
300
+ if(state > 0 && state < NUM+1)begin
301
+ if(wr_rd_type[state-1]==addrdatac[0].WRITE)
302
+ lite.axi_wdata <= wdata[state-1];
303
+ else lite.axi_wdata <= lite.axi_wdata;
304
+ end else lite.axi_wdata <= lite.axi_wdata;
305
+ end
306
+ //---<< DATA WR >>-------------------------
307
+ //--->> RESP WR <<-------------------------
308
+ always@(posedge clock,negedge rst_n)
309
+ if(~rst_n) lite.axi_bready <= 1'b0;
310
+ else begin
311
+ if(state > 0 && state < NUM+1)begin
312
+ if(flag)
313
+ lite.axi_bready <= wr_rd_type[state-1]==addrdatac[0].WRITE ;
314
+ else if(lite.axi_bready && lite.axi_bvalid)
315
+ lite.axi_bready <= 1'b0;
316
+ else lite.axi_bready <= lite.axi_bready;
317
+ end else lite.axi_bready <= 1'b0;
318
+ end
319
+ //---<< RESP WR >>-------------------------
320
+ //--->> ADDR RD <<-------------------------
321
+ logic resend_rd;
322
+
323
+ always@(posedge clock,negedge rst_n)
324
+ if(~rst_n) resend_rd <= 1'b0;
325
+ else begin
326
+ if(keep_read[state-1])begin
327
+ if(en_keep[state-1])
328
+ resend_rd <= ( rd_addr_ok ) && (lite.axi_rready && lite.axi_rvalid && (lite.axi_rdata & meet_keep[state-1]) != (meet_rdata[state-1] & meet_keep[state-1]));
329
+ else
330
+ resend_rd <= ( rd_addr_ok ) && (lite.axi_rready && lite.axi_rvalid && lite.axi_rdata != meet_rdata[state-1]);
331
+ end
332
+ else resend_rd <= 1'b0;
333
+ end
334
+
335
+ always@(posedge clock,negedge rst_n)
336
+ if(~rst_n) lite.axi_arvalid <= 1'b0;
337
+ else begin
338
+ if(state > 0 && state < NUM+1)begin
339
+ if(flag || resend_rd)
340
+ lite.axi_arvalid <= wr_rd_type[state-1]==addrdatac[0].READ ;
341
+ else if(lite.axi_arvalid && lite.axi_arready)
342
+ lite.axi_arvalid <= 1'b0;
343
+ else lite.axi_arvalid <= lite.axi_arvalid;
344
+ end else lite.axi_arvalid <= 1'b0;
345
+ end
346
+ //
347
+ always@(posedge clock,negedge rst_n)
348
+ if(~rst_n) lite.axi_araddr <= {lite.ASIZE{1'b0}};
349
+ else begin
350
+ if(state > 0 && state < NUM+1)begin
351
+ if(wr_rd_type[state-1]==addrdatac[0].READ)
352
+ lite.axi_araddr <= addr[state-1];
353
+ else lite.axi_araddr <= lite.axi_araddr;
354
+ end else lite.axi_araddr <= lite.axi_araddr;
355
+ end
356
+ //---<< ADDR RD >>-------------------------
357
+ //--->> DATA RD <<-------------------------
358
+ always@(posedge clock,negedge rst_n)
359
+ if(~rst_n) lite.axi_rready <= 1'b0;
360
+ else begin
361
+ if(state > 0 && state < NUM+1)begin
362
+ if(flag || resend_rd)
363
+ lite.axi_rready <= wr_rd_type[state-1]==addrdatac[0].READ ;
364
+ else if(lite.axi_rready && lite.axi_rvalid)
365
+ lite.axi_rready <= 1'b0;
366
+ else lite.axi_rready <= lite.axi_rready;
367
+ end else lite.axi_rready <= 1'b0;
368
+ end
369
+ //
370
+ always@(posedge clock,negedge rst_n)
371
+ if(~rst_n) ;
372
+ else begin
373
+ if(state > 0 && state < NUM+1)begin
374
+ if(wr_rd_type[state-1]==addrdatac[0].READ)
375
+ rdata[state-1] <= (lite.axi_rready && lite.axi_rvalid)? lite.axi_rdata : rdata[state-1];
376
+ else rdata[state-1] <= rdata[state-1];
377
+ end else rdata[state-1] <= rdata[state-1];
378
+ end
379
+ //---<< DARA RD >>-------------------------
380
+ always@(posedge clock,negedge rst_n)
381
+ if(~rst_n) to_domn_trigger <= 1'b0;
382
+ else to_domn_trigger <= state == NUM+1;
383
+
384
+ //--->> common rdata <<-------------------
385
+ always@(posedge clock,negedge rst_n)
386
+ if(~rst_n) lite_rdata <= {lite.DSIZE{1'b0}};
387
+ else lite_rdata <= (lite.axi_rready && lite.axi_rvalid)? lite.axi_rdata : lite_rdata;
388
+ //---<< common rdata >>-------------------
389
+ endmodule:gen_axi_lite_ctrl
390
+
391
+ module Lite_Addr_Data_List (
392
+ Lite_Addr_Data_CMD.master addrdatac,
393
+ input int addr,
394
+ input int wdata,
395
+ output int rdata,
396
+ input int wr_rd_type,
397
+ input int wait_intrq,
398
+ input int intrq,
399
+ input int keep_read,
400
+ input int meet_rdata
401
+ );
402
+
403
+ assign addrdatac.addr = addr[addrdatac.ASIZE-1:0];
404
+ assign addrdatac.wdata = wdata[addrdatac.DSIZE-1:0];
405
+ assign addrdatac.wr_rd_type = wr_rd_type[0];
406
+ assign addrdatac.wait_intrq = wait_intrq[0];
407
+ assign addrdatac.intrq = intrq[0];
408
+ assign addrdatac.keep_read = keep_read[0];
409
+ assign addrdatac.meet_rdata = meet_rdata[addrdatac.DSIZE-1:0];
410
+ assign addrdatac.meet_keep = '1;
411
+ assign addrdatac.en_keep = 1'b0;
412
+ assign rdata = addrdatac.rdata;
413
+
414
+ endmodule:Lite_Addr_Data_List
415
+
416
+ module Lite_Addr_Data_WR(
417
+ Lite_Addr_Data_CMD.master addrdatac,
418
+ input int addr,
419
+ input int wdata
420
+ );
421
+
422
+ Lite_Addr_Data_List Lite_Addr_Data_List_inst(
423
+ /* Lite_Addr_Data_CMD.master */ .addrdatac (addrdatac ),
424
+ /* input int */ .addr (addr ),
425
+ /* input int */ .wdata (wdata ),
426
+ /* output int */ .rdata ( ),
427
+ /* input int */ .wr_rd_type ({31'd0,addrdatac.WRITE} ),
428
+ /* input int */ .wait_intrq ( 0),
429
+ /* input int */ .intrq ( 0),
430
+ /* input int */ .keep_read ( 0),
431
+ /* input int */ .meet_rdata ( 0)
432
+ );
433
+
434
+ endmodule:Lite_Addr_Data_WR
435
+
436
+
437
+ module Lite_Addr_Data_WR_IRQ(
438
+ Lite_Addr_Data_CMD.master addrdatac,
439
+ input int addr,
440
+ input int wdata,
441
+ input intrq
442
+ );
443
+
444
+ Lite_Addr_Data_List Lite_Addr_Data_List_inst(
445
+ /* Lite_Addr_Data_CMD.master */ .addrdatac (addrdatac ),
446
+ /* input int */ .addr (addr ),
447
+ /* input int */ .wdata (wdata ),
448
+ /* output int */ .rdata ( ),
449
+ /* input int */ .wr_rd_type ({31'd0,addrdatac.WRITE} ),
450
+ /* input int */ .wait_intrq ( 1),
451
+ /* input int */ .intrq ({31'd0,intrq}),
452
+ /* input int */ .keep_read ( 0),
453
+ /* input int */ .meet_rdata ( 0)
454
+ );
455
+
456
+ endmodule:Lite_Addr_Data_WR_IRQ
457
+
458
+ module Lite_Addr_Data_RD(
459
+ Lite_Addr_Data_CMD.master addrdatac,
460
+ input int addr,
461
+ output int rdata
462
+ );
463
+
464
+ Lite_Addr_Data_List Lite_Addr_Data_List_inst(
465
+ /* Lite_Addr_Data_CMD.master */ .addrdatac (addrdatac ),
466
+ /* input int */ .addr (addr ),
467
+ /* input int */ .wdata (0 ),
468
+ /* output int */ .rdata (rdata ),
469
+ /* input int */ .wr_rd_type ({31'd0,addrdatac.READ} ),
470
+ /* input int */ .wait_intrq ( 0),
471
+ /* input int */ .intrq ( 0),
472
+ /* input int */ .keep_read ( 0),
473
+ /* input int */ .meet_rdata ( 0)
474
+ );
475
+
476
+ endmodule:Lite_Addr_Data_RD
477
+
478
+ module Lite_Addr_Data_RD_MEET(
479
+ Lite_Addr_Data_CMD.master addrdatac,
480
+ input int addr,
481
+ input int meet_rdata
482
+ );
483
+
484
+ Lite_Addr_Data_List Lite_Addr_Data_List_inst(
485
+ /* Lite_Addr_Data_CMD.master */ .addrdatac (addrdatac ),
486
+ /* input int */ .addr (addr ),
487
+ /* input int */ .wdata (0 ),
488
+ /* output int */ .rdata ( ),
489
+ /* input int */ .wr_rd_type ({31'd0,addrdatac.READ} ),
490
+ /* input int */ .wait_intrq ( 0),
491
+ /* input int */ .intrq ( 0),
492
+ /* input int */ .keep_read ( 1),
493
+ /* input int */ .meet_rdata (meet_rdata )
494
+ );
495
+
496
+ endmodule:Lite_Addr_Data_RD_MEET
497
+
498
+ module Lite_Addr_Data_RD_S(
499
+ Lite_Addr_Data_CMD.master addrdatac,
500
+ input int addr
501
+ );
502
+
503
+ Lite_Addr_Data_List Lite_Addr_Data_List_inst(
504
+ /* Lite_Addr_Data_CMD.master */ .addrdatac (addrdatac ),
505
+ /* input int */ .addr (addr ),
506
+ /* input int */ .wdata (0 ),
507
+ /* output int */ .rdata ( ),
508
+ /* input int */ .wr_rd_type ({31'd0,addrdatac.READ} ),
509
+ /* input int */ .wait_intrq ( 0),
510
+ /* input int */ .intrq ( 0),
511
+ /* input int */ .keep_read ( 0),
512
+ /* input int */ .meet_rdata ( 0)
513
+ );
514
+
515
+ endmodule:Lite_Addr_Data_RD_S