axi_tdl 0.0.2
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- checksums.yaml +7 -0
- data/.gitignore +8 -0
- data/CODE_OF_CONDUCT.md +74 -0
- data/Gemfile +6 -0
- data/Gemfile.lock +43 -0
- data/LICENSE +504 -0
- data/README.md +311 -0
- data/Rakefile +18 -0
- data/axi_tdl.gemspec +43 -0
- data/bin/console +14 -0
- data/bin/setup +8 -0
- data/lib/.rspec +1 -0
- data/lib/axi/AXI4/axi4_combin_wr_rd_batch.sv +59 -0
- data/lib/axi/AXI4/axi4_direct.sv +137 -0
- data/lib/axi/AXI4/axi4_direct_A1.sv +229 -0
- data/lib/axi/AXI4/axi4_direct_B1.sv +74 -0
- data/lib/axi/AXI4/axi4_direct_verb.sv +79 -0
- data/lib/axi/AXI4/axi4_direct_verc.sv +146 -0
- data/lib/axi/AXI4/axi4_dpram_cache.rb +106 -0
- data/lib/axi/AXI4/axi4_dpram_cache.sv +112 -0
- data/lib/axi/AXI4/axi4_long_to_axi4_wide.sv +85 -0
- data/lib/axi/AXI4/axi4_long_to_axi4_wide_A1.sv +96 -0
- data/lib/axi/AXI4/axi4_long_to_axi4_wide_track.sv +118 -0
- data/lib/axi/AXI4/axi4_long_to_axi4_wide_verb.sv +131 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_pipe.sv +44 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_pipe_verb.sv +45 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_rd_pipe.sv +111 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_rd_pipe_verb.sv +113 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_wr_pipe.sv +142 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_wr_pipe_verb.sv +146 -0
- data/lib/axi/AXI4/axi4_rd_auxiliary_batch_gen.sv +134 -0
- data/lib/axi/AXI4/axi4_rd_auxiliary_gen.sv +89 -0
- data/lib/axi/AXI4/axi4_rd_auxiliary_gen_A1.sv +109 -0
- data/lib/axi/AXI4/axi4_rd_burst_track.sv +164 -0
- data/lib/axi/AXI4/axi4_wr_aux_bind_data.sv +121 -0
- data/lib/axi/AXI4/axi4_wr_auxiliary_batch_gen.sv +140 -0
- data/lib/axi/AXI4/axi4_wr_auxiliary_gen.sv +102 -0
- data/lib/axi/AXI4/axi4_wr_auxiliary_gen_without_resp.sv +91 -0
- data/lib/axi/AXI4/axi4_wr_burst_track.sv +146 -0
- data/lib/axi/AXI4/axi_stream_add_addr_len.sv +50 -0
- data/lib/axi/AXI4/axi_stream_to_axi4_wr.sv +61 -0
- data/lib/axi/AXI4/axi_stream_to_axi4_wr_verb.sv.bak +123 -0
- data/lib/axi/AXI4/axis_to_axi4_wr.rb +149 -0
- data/lib/axi/AXI4/axis_to_axi4_wr.sv +141 -0
- data/lib/axi/AXI4/full_axi4_to_axis.sv +188 -0
- data/lib/axi/AXI4/full_axi4_to_axis_partition_wr_rd.sv +208 -0
- data/lib/axi/AXI4/id_record.sv +55 -0
- data/lib/axi/AXI4/idata_pool_axi4.sv +110 -0
- data/lib/axi/AXI4/interconnect/AXI4_interconnect_M2S.sv +291 -0
- data/lib/axi/AXI4/interconnect/axi4_mix_interconnect_M2S.sv +72 -0
- data/lib/axi/AXI4/interconnect/axi4_rd_interconnect_M2S.sv +148 -0
- data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S.sv +255 -0
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- data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S_A2.sv +281 -0
- data/lib/axi/AXI4/interconnect/axi4_wr_interconnect_M2S.sv +235 -0
- data/lib/axi/AXI4/interconnect/axi4_wr_interconnect_M2S_A1.sv +283 -0
- data/lib/axi/AXI4/interconnect/axi4_wr_mix_interconnect_M2S.sv +32 -0
- data/lib/axi/AXI4/long_axi4_to_wide_axi4.sv.bak +251 -0
- data/lib/axi/AXI4/odata_pool_axi4.sv +134 -0
- data/lib/axi/AXI4/odata_pool_axi4_A1.sv +165 -0
- data/lib/axi/AXI4/odata_pool_axi4_A2.sv +159 -0
- data/lib/axi/AXI4/odata_pool_axi4_A3.sv +183 -0
- data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo.sv +61 -0
- data/lib/axi/AXI4/packet_fifo/axi4_rd_packet_fifo.sv +282 -0
- data/lib/axi/AXI4/packet_fifo/axi4_wr_packet_fifo.sv +181 -0
- data/lib/axi/AXI4/packet_merge/axi4_merge.sv +60 -0
- data/lib/axi/AXI4/packet_merge/axi4_merge_rd.sv +279 -0
- data/lib/axi/AXI4/packet_merge/axi4_merge_wr.sv +267 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition.sv +36 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_OD.sv +66 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd.sv +211 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_OD.sv +322 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.rb +80 -0
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- data/lib/axi/AXI4/packet_partition/data_inf_partition.rb +293 -0
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- data/lib/axi/AXI4/width_convert/axi4_data_combin_aflag_pipe.sv +239 -0
- data/lib/axi/AXI4/width_convert/axi4_data_combin_aflag_pipe_A1.sv +204 -0
- data/lib/axi/AXI4/width_convert/axi4_data_convert.sv +312 -0
- data/lib/axi/AXI4/width_convert/axi4_data_convert_A1.sv +217 -0
- data/lib/axi/AXI4/width_convert/data_combin.sv +366 -0
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- data/lib/axi/AXI4/width_convert/data_destruct.sv +304 -0
- data/lib/axi/AXI4/width_convert/feed_check.sv +94 -0
- data/lib/axi/AXI4/width_convert/len_convert.sv.bak +61 -0
- data/lib/axi/AXI4/width_convert/odd_width_convert.sv +229 -0
- data/lib/axi/AXI4/width_convert/odd_width_convert_verb.sv +105 -0
- data/lib/axi/AXI4/width_convert/simple_data_pipe.sv +40 -0
- data/lib/axi/AXI4/width_convert/simple_data_pipe_slaver.sv +33 -0
- data/lib/axi/AXI4/width_convert/width_combin.sv +113 -0
- data/lib/axi/AXI4/width_convert/width_convert.sv +87 -0
- data/lib/axi/AXI4/width_convert/width_convert_verb.sv +249 -0
- data/lib/axi/AXI4/width_convert/width_destruct.sv +206 -0
- data/lib/axi/AXI4/width_convert/width_destruct_A1.sv +251 -0
- data/lib/axi/AXI_BFM/AXI_BFM_PKG.sv +1039 -0
- data/lib/axi/AXI_BFM/Data_C_BFM_PKG.sv +97 -0
- data/lib/axi/AXI_BFM/axi4_error_chk.sv +298 -0
- data/lib/axi/AXI_BFM/axi4_illegal_bfm_pkg.sv +607 -0
- data/lib/axi/AXI_BFM/axi_lite_master.sv +102 -0
- data/lib/axi/AXI_BFM/axi_lite_tb.sv +23 -0
- data/lib/axi/AXI_BFM/axi_master.sv +185 -0
- data/lib/axi/AXI_BFM/axi_mirror.sv +266 -0
- data/lib/axi/AXI_BFM/axi_mm_tb.sv +134 -0
- data/lib/axi/AXI_BFM/axi_slaver.sv.bak +340 -0
- data/lib/axi/AXI_BFM/axistreambfm.sv +117 -0
- data/lib/axi/AXI_Lite/axi4_to_lite.sv +36 -0
- data/lib/axi/AXI_Lite/axi_lite_configure.sv +356 -0
- data/lib/axi/AXI_Lite/axi_lite_configure_inf2.sv +365 -0
- data/lib/axi/AXI_Lite/axi_lite_configure_verb.sv.bck +370 -0
- data/lib/axi/AXI_Lite/axi_lite_interconnect_M2S.sv +437 -0
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- data/lib/axi/AXI_Lite/axi_lite_slaver_empty.sv +27 -0
- data/lib/axi/AXI_Lite/axil_direct.sv +52 -0
- data/lib/axi/AXI_Lite/common_configure_reg_interface/common_configure_reg_interface.sv +230 -0
- data/lib/axi/AXI_Lite/common_configure_reg_interface/common_configure_reg_interface.sv.bak +109 -0
- data/lib/axi/AXI_Lite/common_configure_reg_interface/jtag_to_axilite_wrapper.sv +56 -0
- data/lib/axi/AXI_Lite/gen_axi_lite_ctrl.sv +515 -0
- data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_C1.sv +369 -0
- data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_verb.sv +365 -0
- data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_verc.sv +401 -0
- data/lib/axi/AXI_Lite/wr_lite_to_axis.sv +141 -0
- data/lib/axi/AXI_Lite/wr_lite_to_axis.sv.bak +141 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S.sv +76 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_A1.sv +77 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_A2.sv +71 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_bind_tuser.sv +72 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_noaddr.sv +151 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_with_addr.sv +87 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_S2M.sv +65 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_auto.sv +50 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_with_info.sv +64 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_with_keep.sv.bak +64 -0
- data/lib/axi/AXI_stream/axi_stream_packet_fifo_with_info.sv.bak +49 -0
- data/lib/axi/AXI_stream/axi_stream_partition.sv +147 -0
- data/lib/axi/AXI_stream/axi_stream_partition_A1.sv +63 -0
- data/lib/axi/AXI_stream/axi_stream_planer.sv +51 -0
- data/lib/axi/AXI_stream/axi_stream_split_channel.rb +56 -0
- data/lib/axi/AXI_stream/axi_stream_split_channel.sv +149 -0
- data/lib/axi/AXI_stream/axi_streams_combin.sv +151 -0
- data/lib/axi/AXI_stream/axi_streams_combin_A1.sv +179 -0
- data/lib/axi/AXI_stream/axi_streams_scaler.sv +171 -0
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- data/lib/axi/AXI_stream/axis_append.sv +79 -0
- data/lib/axi/AXI_stream/axis_append_A1.sv +82 -0
- data/lib/axi/AXI_stream/axis_base_pipe.sv +184 -0
- data/lib/axi/AXI_stream/axis_combin_with_fifo.sv +69 -0
- data/lib/axi/AXI_stream/axis_connect_pipe.sv +86 -0
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- data/lib/axi/AXI_stream/axis_connect_pipe_left_shift.sv +64 -0
- data/lib/axi/AXI_stream/axis_connect_pipe_right_shift.sv +64 -0
- data/lib/axi/AXI_stream/axis_connect_pipe_right_shift_verb.sv +70 -0
- data/lib/axi/AXI_stream/axis_connect_pipe_with_info.sv +93 -0
- data/lib/axi/AXI_stream/axis_direct.sv +55 -0
- data/lib/axi/AXI_stream/axis_direct_A1.sv +81 -0
- data/lib/axi/AXI_stream/axis_filter.sv +38 -0
- data/lib/axi/AXI_stream/axis_full_to_data_c.sv +26 -0
- data/lib/axi/AXI_stream/axis_head_cut.sv +67 -0
- data/lib/axi/AXI_stream/axis_head_cut_verb.sv +60 -0
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- data/lib/axi/AXI_stream/axis_head_cut_verc.sv +245 -0
- data/lib/axi/AXI_stream/axis_inct_s2m_with_flag.sv +84 -0
- data/lib/axi/AXI_stream/axis_insert_copy.rb +59 -0
- data/lib/axi/AXI_stream/axis_insert_copy.sv +66 -0
- data/lib/axi/AXI_stream/axis_intc_M2S_with_addr_inf.sv +114 -0
- data/lib/axi/AXI_stream/axis_intc_S2M_with_addr_inf.sv +85 -0
- data/lib/axi/AXI_stream/axis_interconnect_S2M_pipe.sv +75 -0
- data/lib/axi/AXI_stream/axis_length_cut.sv +64 -0
- data/lib/axi/AXI_stream/axis_length_fill.sv +194 -0
- data/lib/axi/AXI_stream/axis_length_split.sv +86 -0
- data/lib/axi/AXI_stream/axis_length_split_with_addr.sv +127 -0
- data/lib/axi/AXI_stream/axis_length_split_writh_user.sv +87 -0
- data/lib/axi/AXI_stream/axis_link_trigger.sv +81 -0
- data/lib/axi/AXI_stream/axis_master_empty.sv +26 -0
- data/lib/axi/AXI_stream/axis_mirror_to_master.sv +126 -0
- data/lib/axi/AXI_stream/axis_mirrors.sv +60 -0
- data/lib/axi/AXI_stream/axis_orthogonal.sv +66 -0
- data/lib/axi/AXI_stream/axis_ram_buffer.sv +118 -0
- data/lib/axi/AXI_stream/axis_rom_contect.rb +97 -0
- data/lib/axi/AXI_stream/axis_rom_contect.sv +110 -0
- data/lib/axi/AXI_stream/axis_rom_contect_sim.rb +102 -0
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- data/lib/axi/AXI_stream/axis_slaver_empty.sv +22 -0
- data/lib/axi/AXI_stream/axis_slaver_pipe.sv +84 -0
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- data/lib/axi/AXI_stream/axis_split_channel_verb.rb +42 -0
- data/lib/axi/AXI_stream/axis_split_channel_verb.sv +62 -0
- data/lib/axi/AXI_stream/axis_to_axi4_or_lite.rb +127 -0
- data/lib/axi/AXI_stream/axis_to_axi4_or_lite.sv +153 -0
- data/lib/axi/AXI_stream/axis_to_data_inf.sv +34 -0
- data/lib/axi/AXI_stream/axis_to_lite_rd.sv +81 -0
- data/lib/axi/AXI_stream/axis_to_lite_wr.sv +71 -0
- data/lib/axi/AXI_stream/axis_uncompress.sv +147 -0
- data/lib/axi/AXI_stream/axis_uncompress_A1.sv +150 -0
- data/lib/axi/AXI_stream/axis_uncompress_verb.rb +32 -0
- data/lib/axi/AXI_stream/axis_uncompress_verb.sv +54 -0
- data/lib/axi/AXI_stream/axis_valve.sv +29 -0
- data/lib/axi/AXI_stream/axis_valve_with_pipe.sv +76 -0
- data/lib/axi/AXI_stream/axis_vector_master_empty.rb +11 -0
- data/lib/axi/AXI_stream/axis_vector_master_empty.sv +35 -0
- data/lib/axi/AXI_stream/axis_vector_slaver_empty.rb +11 -0
- data/lib/axi/AXI_stream/axis_vector_slaver_empty.sv +35 -0
- data/lib/axi/AXI_stream/check_stream_crc.sv +28 -0
- data/lib/axi/AXI_stream/data_c_to_axis_full.sv +23 -0
- data/lib/axi/AXI_stream/data_to_axis_inf.sv +103 -0
- data/lib/axi/AXI_stream/data_to_axis_inf_A1.sv +28 -0
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- data/lib/axi/AXI_stream/data_width/axis_width_combin_A1.sv +220 -0
- data/lib/axi/AXI_stream/data_width/axis_width_convert.sv +49 -0
- data/lib/axi/AXI_stream/data_width/axis_width_destruct.sv +82 -0
- data/lib/axi/AXI_stream/data_width/axis_width_destruct_A1.sv +86 -0
- data/lib/axi/AXI_stream/ex_status/axis_ex_status.sv +97 -0
- data/lib/axi/AXI_stream/gen_big_field_table.sv +170 -0
- data/lib/axi/AXI_stream/gen_common_frame_table.sv +382 -0
- data/lib/axi/AXI_stream/gen_common_frame_table_bind_tuser.sv +428 -0
- data/lib/axi/AXI_stream/gen_origin_axis.sv +116 -0
- data/lib/axi/AXI_stream/gen_origin_axis_A1.sv +129 -0
- data/lib/axi/AXI_stream/gen_origin_axis_A2.sv +162 -0
- data/lib/axi/AXI_stream/gen_simple_axis.sv +164 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_long_fifo.sv +132 -0
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- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo.sv +125 -0
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- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1E.sv +198 -0
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- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_B1.sv +82 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_mirror.sv +44 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_verb.sv +58 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_long_cache.sv +55 -0
- data/lib/axi/AXI_stream/stream_crc.sv +67 -0
- data/lib/axi/AXI_stream/vcs_axis_comptable.sv +73 -0
- data/lib/axi/LICENSE +504 -0
- data/lib/axi/ReadME.md +6 -0
- data/lib/axi/SIM/tb_axi4_partition_20201105.sv +115 -0
- data/lib/axi/SIM/tb_axis_bfm_0504.sv +61 -0
- data/lib/axi/SIM/tb_axis_partitiom_0929.sv +102 -0
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- data/lib/axi/SIM/tb_axis_to_axi4_0925.sv +107 -0
- data/lib/axi/SIM/tb_data_c_m2s_inf_20200114.sv +222 -0
- data/lib/axi/SIM/tb_data_c_m2s_inf_20201103.sv +245 -0
- data/lib/axi/SIM/tb_data_c_pipe_inf_20180417.sv +114 -0
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- data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_gen_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_gen_without_resp_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_wr_burst_track_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_wr_interconnect_M2S_A1_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_wr_interconnect_M2S_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_wr_mix_interconnect_M2S_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_wr_packet_fifo_sdl.rb +11 -0
- data/lib/tdl/SDL/axi4/axi4_wr_pipe_sdl.rb +9 -0
- data/lib/tdl/SDL/axi4/axi4_wr_pipe_verb_sdl.rb +9 -0
- data/lib/tdl/SDL/axi4/axi_stream_add_addr_len_sdl.rb +11 -0
- data/lib/tdl/SDL/axi4/axi_stream_to_axi4_wr_sdl.rb +9 -0
- data/lib/tdl/SDL/axi4/data_combin_sdl.rb +20 -0
- data/lib/tdl/SDL/axi4/data_destruct_sdl.rb +19 -0
- data/lib/tdl/SDL/axi4/feed_check_sdl.rb +18 -0
- data/lib/tdl/SDL/axi4/full_axi4_to_axis_partition_wr_rd_sdl.rb +11 -0
- data/lib/tdl/SDL/axi4/full_axi4_to_axis_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/id_record_sdl.rb +19 -0
- data/lib/tdl/SDL/axi4/idata_pool_axi4_sdl.rb +18 -0
- data/lib/tdl/SDL/axi4/odata_pool_axi4_A1_sdl.rb +13 -0
- data/lib/tdl/SDL/axi4/odata_pool_axi4_A2_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/odata_pool_axi4_sdl.rb +19 -0
- data/lib/tdl/SDL/axi4/odd_width_convert_sdl.rb +19 -0
- data/lib/tdl/SDL/axi4/odd_width_convert_verb_sdl.rb +19 -0
- data/lib/tdl/SDL/axi4/simple_data_pipe_sdl.rb +16 -0
- data/lib/tdl/SDL/axi4/simple_data_pipe_slaver_sdl.rb +16 -0
- data/lib/tdl/SDL/axi4/vcs_axi4_array_comptable.rb +9 -0
- data/lib/tdl/SDL/axi4/vcs_axi4_array_comptable_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/vcs_axi4_comptable.rb +8 -0
- data/lib/tdl/SDL/axi4/vcs_axi4_comptable_sdl.rb +9 -0
- data/lib/tdl/SDL/axi4/width_combin_sdl.rb +20 -0
- data/lib/tdl/SDL/axi4/width_convert_sdl.rb +20 -0
- data/lib/tdl/SDL/axi4/width_convert_verb_sdl.rb +20 -0
- data/lib/tdl/SDL/axi4/width_destruct_A1_sdl.rb +22 -0
- data/lib/tdl/SDL/axi4/width_destruct_sdl.rb +19 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_35bit_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_36_71bit_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_72_95bit_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_72_95bit_with_keep_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_96_143bit_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_B1_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_mirror_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_verb_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_A1_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_A2_sdl.rb +13 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_bind_tuser_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_noaddr_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_with_addr_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_S2M_auto_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_S2M_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axi_stream_long_cache_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axi_stream_long_fifo_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axi_stream_long_fifo_verb_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_B1E_sdl.rb +16 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_B1_sdl.rb +14 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_verb_sdl.rb +13 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_with_info_sdl.rb +13 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_long_fifo_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axi_stream_partition_A1_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axi_stream_partition_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axi_stream_wide_fifo_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axi_streams_combin_A1_sdl.rb +15 -0
- data/lib/tdl/SDL/axistream/axi_streams_combin_sdl.rb +16 -0
- data/lib/tdl/SDL/axistream/axi_streams_scaler_A1_sdl.rb +14 -0
- data/lib/tdl/SDL/axistream/axi_streams_scaler_sdl.rb +15 -0
- data/lib/tdl/SDL/axistream/axis_append_A1_sdl.rb +18 -0
- data/lib/tdl/SDL/axistream/axis_append_sdl.rb +17 -0
- data/lib/tdl/SDL/axistream/axis_base_pipe_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_combin_with_fifo_sdl.rb +14 -0
- data/lib/tdl/SDL/axistream/axis_connect_pipe_right_shift_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_connect_pipe_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_connect_pipe_with_info_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axis_direct_A1_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axis_direct_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_ex_status_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axis_filter_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_full_to_data_c_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_head_cut_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_inct_s2m_with_flag_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axis_intc_M2S_with_addr_inf_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axis_intc_S2M_with_addr_inf_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axis_interconnect_S2M_pipe_sdl.rb +15 -0
- data/lib/tdl/SDL/axistream/axis_length_cut_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_length_fill_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_length_split_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_length_split_with_addr_sdl.rb +13 -0
- data/lib/tdl/SDL/axistream/axis_length_split_writh_user_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_link_trigger_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axis_master_empty_sdl.rb +8 -0
- data/lib/tdl/SDL/axistream/axis_mirror_to_master_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_mirrors_sdl.rb +14 -0
- data/lib/tdl/SDL/axistream/axis_orthogonal_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_pkt_fifo_filter_keep_A1_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_pkt_fifo_filter_keep_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_ram_buffer_sdl.rb +13 -0
- data/lib/tdl/SDL/axistream/axis_slaver_empty_sdl.rb +8 -0
- data/lib/tdl/SDL/axistream/axis_slaver_pipe_A1_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_slaver_pipe_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_slaver_vector_empty_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_to_data_inf_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_to_lite_rd_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axis_to_lite_wr_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_uncompress_A1_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axis_uncompress_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axis_valve_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_valve_with_pipe_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axis_width_combin_A1_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_width_combin_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_width_convert_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_width_destruct_A1_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_width_destruct_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/check_stream_crc_sdl.rb +8 -0
- data/lib/tdl/SDL/axistream/data_c_to_axis_full_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/data_to_axis_inf_A1_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/data_to_axis_inf_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/gen_big_field_table_sdl.rb +14 -0
- data/lib/tdl/SDL/axistream/gen_common_frame_table_sdl.rb +60 -0
- data/lib/tdl/SDL/axistream/gen_origin_axis_A1_sdl.rb +13 -0
- data/lib/tdl/SDL/axistream/gen_origin_axis_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/gen_simple_axis_sdl.rb +13 -0
- data/lib/tdl/SDL/axistream/parse_big_field_table_A1_sdl.rb +17 -0
- data/lib/tdl/SDL/axistream/parse_big_field_table_A2_sdl.rb +17 -0
- data/lib/tdl/SDL/axistream/parse_big_field_table_sdl.rb +17 -0
- data/lib/tdl/SDL/axistream/stream_crc_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/vcs_axis_comptable.rb +16 -0
- data/lib/tdl/SDL/axistream/vcs_axis_comptable_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_bind_sdl.rb +10 -0
- data/lib/tdl/SDL/data_inf_c/data_c_cache_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_c_direct_mirror_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_c_direct_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_c_intc_M2S_force_robin_sdl.rb +10 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_force_vld_bind_data_sdl.rb +13 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_force_vld_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_A1_sdl.rb +10 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_right_shift_sdl.rb +13 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_C1_sdl.rb +14 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_C1_with_id_sdl.rb +16 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_sdl.rb +13 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_with_addr_sdl.rb +13 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_with_id_sdl.rb +15 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_latency_sdl.rb +10 -0
- data/lib/tdl/SDL/data_inf_c/data_c_scaler_A1_sdl.rb +16 -0
- data/lib/tdl/SDL/data_inf_c/data_c_scaler_sdl.rb +15 -0
- data/lib/tdl/SDL/data_inf_c/data_c_tmp_cache_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_condition_mirror_sdl.rb +13 -0
- data/lib/tdl/SDL/data_inf_c/data_condition_valve_sdl.rb +13 -0
- data/lib/tdl/SDL/data_inf_c/data_connect_pipe_inf_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_connect_pipe_sdl.rb +17 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_A2B_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_B2A_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_M2S_with_addr_and_id_sdl.rb +17 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_M2S_with_id_sdl.rb +15 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_A1_sdl.rb +13 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_sdl.rb +12 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_with_lazy_sdl.rb +15 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_interconnect_M2S_sdl.rb +12 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_pipe_condition_sdl.rb +10 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_A1.rb +12 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_A1_sdl.rb +14 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_sdl.rb +13 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_cross_clk_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_force_addr_with_id_sdl.rb +19 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_prio_sdl.rb +14 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_prio_with_id_sdl.rb +17 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_interconnect_M2S_noaddr_sdl.rb +14 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_interconnect_M2S_with_id_noaddr_sdl.rb +17 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_planer_A1_sdl.rb +15 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_planer_sdl.rb +14 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_ticktock_sdl.rb +18 -0
- data/lib/tdl/SDL/data_inf_c/data_intc_M2S_force_robin_sdl.rb +10 -0
- data/lib/tdl/SDL/data_inf_c/data_mirrors_sdl.rb +14 -0
- data/lib/tdl/SDL/data_inf_c/data_pair_map_A1_sdl.rb +16 -0
- data/lib/tdl/SDL/data_inf_c/data_pair_map_A2_sdl.rb +19 -0
- data/lib/tdl/SDL/data_inf_c/data_pair_map_sdl.rb +14 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_A1_sdl.rb +19 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_sdl.rb +17 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_verb_sdl.rb +16 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_A1_sdl.rb +19 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_sdl.rb +16 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_verb_sdl.rb +15 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_sdl.rb +23 -0
- data/lib/tdl/SDL/data_inf_c/data_streams_combin_A1_sdl.rb +20 -0
- data/lib/tdl/SDL/data_inf_c/data_streams_combin_sdl.rb +20 -0
- data/lib/tdl/SDL/data_inf_c/data_streams_scaler_sdl.rb +19 -0
- data/lib/tdl/SDL/data_inf_c/data_uncompress_sdl.rb +11 -0
- data/lib/tdl/SDL/data_inf_c/data_valve_sdl.rb +10 -0
- data/lib/tdl/SDL/data_inf_c/datainf_c_master_empty_sdl.rb +8 -0
- data/lib/tdl/SDL/data_inf_c/datainf_c_slaver_empty_sdl.rb +8 -0
- data/lib/tdl/SDL/data_inf_c/datainf_master_empty_sdl.rb +8 -0
- data/lib/tdl/SDL/data_inf_c/datainf_slaver_empty_sdl.rb +8 -0
- data/lib/tdl/SDL/data_inf_c/latency_sdl.rb +8 -0
- data/lib/tdl/SDL/data_inf_c/next_prio_sdl.rb +12 -0
- data/lib/tdl/SDL/data_inf_c/part_data_pair_map_sdl.rb +19 -0
- data/lib/tdl/SDL/data_inf_c/trigger_data_inf_c_A1_sdl.rb +11 -0
- data/lib/tdl/SDL/data_inf_c/trigger_data_inf_c_sdl.rb +11 -0
- data/lib/tdl/SDL/data_inf_c/trigger_ready_ctrl_sdl.rb +12 -0
- data/lib/tdl/SDL/data_inf_c/vcs_data_c_comptable.rb +8 -0
- data/lib/tdl/SDL/data_inf_c/vcs_data_c_comptable_sdl.rb +9 -0
- data/lib/tdl/SDL/fifo/common_fifo_sdl.rb +20 -0
- data/lib/tdl/SDL/fifo/common_stack_sdl.rb +14 -0
- data/lib/tdl/SDL/fifo/independent_clock_fifo_a1_sdl.rb +21 -0
- data/lib/tdl/SDL/fifo/independent_clock_fifo_sdl.rb +20 -0
- data/lib/tdl/SDL/fifo/independent_stack_sdl.rb +18 -0
- data/lib/tdl/SDL/path_lib.rb +6 -0
- data/lib/tdl/VideoInf/simple_video_gen.rb +46 -0
- data/lib/tdl/VideoInf/video_from_axi4.rb +108 -0
- data/lib/tdl/VideoInf/video_lib.rb +8 -0
- data/lib/tdl/VideoInf/video_stream_2_axi_stream.rb +67 -0
- data/lib/tdl/VideoInf/video_to_axi4.rb +75 -0
- data/lib/tdl/auto_script/auto_gen_tdl.rb +49 -0
- data/lib/tdl/auto_script/autogensdl.rb +289 -0
- data/lib/tdl/auto_script/autogentdl_a2.rb +452 -0
- data/lib/tdl/auto_script/import_hdl.rb +35 -0
- data/lib/tdl/auto_script/import_sdl.rb +26 -0
- data/lib/tdl/auto_script/test_autogensdl.rb +73 -0
- data/lib/tdl/auto_script/tmp.rb +6 -0
- data/lib/tdl/auto_script/tmp/hdl_test_sdl.rb +12 -0
- data/lib/tdl/axi4/axi4_combin_wr_rd_batch_auto.rb +79 -0
- data/lib/tdl/axi4/axi4_direct.rb +36 -0
- data/lib/tdl/axi4/axi4_direct_A1_auto.rb +137 -0
- data/lib/tdl/axi4/axi4_direct_auto.rb +79 -0
- data/lib/tdl/axi4/axi4_direct_verb_auto.rb +71 -0
- data/lib/tdl/axi4/axi4_interconnect_verb.rb +323 -0
- data/lib/tdl/axi4/axi4_lib.rb +9 -0
- data/lib/tdl/axi4/axi4_long_to_axi4_wide_A1_auto.rb +79 -0
- data/lib/tdl/axi4/axi4_long_to_axi4_wide_auto.rb +71 -0
- data/lib/tdl/axi4/axi4_long_to_axi4_wide_verb_auto.rb +86 -0
- data/lib/tdl/axi4/axi4_packet_fifo_auto.rb +155 -0
- data/lib/tdl/axi4/axi4_pipe_auto.rb +127 -0
- data/lib/tdl/axi4/axi4_pipe_verb_auto.rb +127 -0
- data/lib/tdl/axi4/axi4_rd_auxiliary_gen_auto.rb +71 -0
- data/lib/tdl/axi4/axi4_wr_auxiliary_gen_without_resp_auto.rb +78 -0
- data/lib/tdl/axi4/axis_to_axi4_wr_auto.rb +85 -0
- data/lib/tdl/axi4/bak/__axi4_wr_auxiliary_gen_without_resp.rb +175 -0
- data/lib/tdl/axi4/bak/axi4_combin_wr_rd_batch_auto.rb +153 -0
- data/lib/tdl/axi4/bak/axi4_data_convert.rb +74 -0
- data/lib/tdl/axi4/bak/axi4_direct_auto.rb +153 -0
- data/lib/tdl/axi4/bak/axi4_direct_verb_auto.rb +126 -0
- data/lib/tdl/axi4/bak/axi4_interconnect.rb.bak +91 -0
- data/lib/tdl/axi4/bak/axi4_long_to_axi4_wide_A1_auto.rb +153 -0
- data/lib/tdl/axi4/bak/axi4_long_to_axi4_wide_auto.rb +126 -0
- data/lib/tdl/axi4/bak/axi4_long_to_axi4_wide_verb_auto.rb +179 -0
- data/lib/tdl/axi4/bak/axi4_packet_fifo.rb.bak +75 -0
- data/lib/tdl/axi4/bak/axi4_packet_fifo_auto.rb +259 -0
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- data/lib/tdl/examples/11_test_unit/dve.tcl +64 -0
- data/lib/tdl/examples/11_test_unit/exp_test_unit.rb +58 -0
- data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +35 -0
- data/lib/tdl/examples/11_test_unit/exp_test_unit_constraints.xdc +25 -0
- data/lib/tdl/examples/11_test_unit/modules/sub_md0.rb +23 -0
- data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +41 -0
- data/lib/tdl/examples/11_test_unit/modules/sub_md1.rb +25 -0
- data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv +41 -0
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +28 -0
- data/lib/tdl/examples/11_test_unit/tu0.sv +38 -0
- data/lib/tdl/examples/11_test_unit/tu1.sv +28 -0
- data/lib/tdl/examples/1_define_module/example1.rb +39 -0
- data/lib/tdl/examples/1_define_module/exmple_md.sv +50 -0
- data/lib/tdl/examples/2_hdl_class/always_comb.rb +99 -0
- data/lib/tdl/examples/2_hdl_class/always_ff.rb +143 -0
- data/lib/tdl/examples/2_hdl_class/case.rb +93 -0
- data/lib/tdl/examples/2_hdl_class/foreach.rb +21 -0
- data/lib/tdl/examples/2_hdl_class/function.rb +34 -0
- data/lib/tdl/examples/2_hdl_class/generate.rb +62 -0
- data/lib/tdl/examples/2_hdl_class/module_def.rb +33 -0
- data/lib/tdl/examples/2_hdl_class/module_head_import_package.rb +36 -0
- data/lib/tdl/examples/2_hdl_class/module_instance_test.rb +13 -0
- data/lib/tdl/examples/2_hdl_class/package.rb +29 -0
- data/lib/tdl/examples/2_hdl_class/package2.rb +21 -0
- data/lib/tdl/examples/2_hdl_class/simple_assign.rb +39 -0
- data/lib/tdl/examples/2_hdl_class/state_case.rb +65 -0
- data/lib/tdl/examples/2_hdl_class/struct.rb +25 -0
- data/lib/tdl/examples/2_hdl_class/struct_function.rb +28 -0
- data/lib/tdl/examples/2_hdl_class/test_axi4_M2S.rb +16 -0
- data/lib/tdl/examples/2_hdl_class/test_initial_assert.rb +11 -0
- data/lib/tdl/examples/2_hdl_class/test_inst_sugar.rb +28 -0
- data/lib/tdl/examples/2_hdl_class/test_module_port.rb +47 -0
- data/lib/tdl/examples/2_hdl_class/test_module_var.rb +18 -0
- data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv +108 -0
- data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +35 -0
- data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv +105 -0
- data/lib/tdl/examples/2_hdl_class/tmp/head_pkg_module.sv +42 -0
- data/lib/tdl/examples/2_hdl_class/tmp/init_module.sv +110 -0
- data/lib/tdl/examples/2_hdl_class/tmp/module_instance_test.sv +31 -0
- data/lib/tdl/examples/2_hdl_class/tmp/port_module.sv +99 -0
- data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv +27 -0
- data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv +78 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_axi4_M2S.sv +30 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_foreach.sv +34 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_function.sv +52 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_initial_assert.sv +31 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_inst_sugar.sv +42 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +36 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_port.sv +33 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +35 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +38 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_package2.sv +36 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_struct.sv +38 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_struct_function.sv +44 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +27 -0
- data/lib/tdl/examples/2_hdl_class/tmp/text_generate.sv +54 -0
- data/lib/tdl/examples/2_hdl_class/vcs_string.rb +5 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/hdl_test.sv +13 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/main.rb +26 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/main_md.sv +42 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/sdl_md.sv +30 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/sdl_test.rb +9 -0
- data/lib/tdl/examples/4_generate/example.rb +38 -0
- data/lib/tdl/examples/4_generate/test_generate.sv +59 -0
- data/lib/tdl/examples/5_logic_combin/login_combin.rb +22 -0
- data/lib/tdl/examples/5_logic_combin/test_logic_combin.sv +36 -0
- data/lib/tdl/examples/6_module_with_interface/example.rb +48 -0
- data/lib/tdl/examples/6_module_with_interface/example_interface.sv +40 -0
- data/lib/tdl/examples/6_module_with_interface/inf_collect.rb +54 -0
- data/lib/tdl/examples/6_module_with_interface/inf_collect.sv +63 -0
- data/lib/tdl/examples/7_module_with_package/body_package.rb +3 -0
- data/lib/tdl/examples/7_module_with_package/body_package.sv +25 -0
- data/lib/tdl/examples/7_module_with_package/example_pkg.rb +20 -0
- data/lib/tdl/examples/7_module_with_package/example_pkg.sv +35 -0
- data/lib/tdl/examples/7_module_with_package/head_package.rb +8 -0
- data/lib/tdl/examples/7_module_with_package/head_package.sv +29 -0
- data/lib/tdl/examples/8_top_module/dve.tcl +64 -0
- data/lib/tdl/examples/8_top_module/example.rb +8 -0
- data/lib/tdl/examples/8_top_module/pins.yml +7 -0
- data/lib/tdl/examples/8_top_module/tb_test_top.sv +29 -0
- data/lib/tdl/examples/8_top_module/test_top.sv +28 -0
- data/lib/tdl/examples/8_top_module/test_top_constraints.xdc +37 -0
- data/lib/tdl/examples/9_itegration/A_itgt/a_test_md.sv +29 -0
- data/lib/tdl/examples/9_itegration/A_itgt/a_test_module.rb +6 -0
- data/lib/tdl/examples/9_itegration/A_itgt/itgt_module_a_block.rb +34 -0
- data/lib/tdl/examples/9_itegration/clock_manage/itgt_module_clock_manage.rb +33 -0
- data/lib/tdl/examples/9_itegration/clock_manage/simple_clock.rb +7 -0
- data/lib/tdl/examples/9_itegration/clock_manage/simple_clock.sv +29 -0
- data/lib/tdl/examples/9_itegration/dve.tcl +64 -0
- data/lib/tdl/examples/9_itegration/pins.yml +4 -0
- data/lib/tdl/examples/9_itegration/tb_test_top.sv +29 -0
- data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +29 -0
- data/lib/tdl/examples/9_itegration/test_top.sv +40 -0
- data/lib/tdl/examples/9_itegration/test_top_constraints.xdc +29 -0
- data/lib/tdl/examples/9_itegration/test_tttop.sv +40 -0
- data/lib/tdl/examples/9_itegration/test_tttop_constraints.xdc +29 -0
- data/lib/tdl/examples/9_itegration/top.rb +11 -0
- data/lib/tdl/examples/readme.md +31 -0
- data/lib/tdl/exlib/common_cfg_reg_inf.rb +139 -0
- data/lib/tdl/exlib/constraints.rb +286 -0
- data/lib/tdl/exlib/constraints_verb.rb +304 -0
- data/lib/tdl/exlib/dve_tcl.rb +162 -0
- data/lib/tdl/exlib/element_class_vars.rb +106 -0
- data/lib/tdl/exlib/global_param.rb +108 -0
- data/lib/tdl/exlib/integral_test/bak/integral_test.rb +206 -0
- data/lib/tdl/exlib/integral_test/clock_itest.rb +28 -0
- data/lib/tdl/exlib/integral_test/diff_clock_itest.rb +30 -0
- data/lib/tdl/exlib/integral_test/io_itest.rb +41 -0
- data/lib/tdl/exlib/integral_test/reset_itest.rb +31 -0
- data/lib/tdl/exlib/integral_test/simple_logic_itest.rb +19 -0
- data/lib/tdl/exlib/itegration.rb +307 -0
- data/lib/tdl/exlib/itegration_verb.rb +913 -0
- data/lib/tdl/exlib/parse_argv.rb +43 -0
- data/lib/tdl/exlib/sdlmodule_sim.bak.rb +375 -0
- data/lib/tdl/exlib/test_point.rb +287 -0
- data/lib/tdl/global_scan.rb +134 -0
- data/lib/tdl/rebuild_ele/axi4.rb +141 -0
- data/lib/tdl/rebuild_ele/axi_lite.rb +56 -0
- data/lib/tdl/rebuild_ele/axi_stream.rb +121 -0
- data/lib/tdl/rebuild_ele/cm_ram_inf.sv +105 -0
- data/lib/tdl/rebuild_ele/cm_ram_inf_define.rb +44 -0
- data/lib/tdl/rebuild_ele/data_inf.rb +27 -0
- data/lib/tdl/rebuild_ele/data_inf_c.rb +83 -0
- data/lib/tdl/rebuild_ele/ele_base.rb +822 -0
- data/lib/tdl/rebuild_ele/readme.md +1 -0
- data/lib/tdl/sdlimplement/resource.yml +154 -0
- data/lib/tdl/sdlimplement/sdl_impl_module.rb +391 -0
- data/lib/tdl/sdlimplement/sdl_impl_param.rb +26 -0
- data/lib/tdl/sdlimplement/test.rb +64 -0
- data/lib/tdl/sdlmodule/bak/sdlmodule_varible_ex.rb +120 -0
- data/lib/tdl/sdlmodule/generator_block_module.rb +84 -0
- data/lib/tdl/sdlmodule/sdlmodule.rb +407 -0
- data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb +333 -0
- data/lib/tdl/sdlmodule/sdlmodule_draw.rb +272 -0
- data/lib/tdl/sdlmodule/sdlmodule_head_logo.txt +10 -0
- data/lib/tdl/sdlmodule/sdlmodule_instance.rb +623 -0
- data/lib/tdl/sdlmodule/sdlmodule_port_define.rb +374 -0
- data/lib/tdl/sdlmodule/sdlmodule_varible.rb +160 -0
- data/lib/tdl/sdlmodule/sdlmodule_vcs_comptable.rb +140 -0
- data/lib/tdl/sdlmodule/techbench_module.rb +14 -0
- data/lib/tdl/sdlmodule/test_unit_module.rb +138 -0
- data/lib/tdl/sdlmodule/top_module.rb +543 -0
- data/lib/tdl/tdl.rb +265 -0
- data/lib/tdl/tdlerror/tdlerror.rb +8 -0
- data/lib/tdl/testunit/test_all.rb +4 -0
- data/lib/tdl/testunit/test_array_chain.rb +89 -0
- data/lib/tdl/testunit/test_tmp.rb +47 -0
- metadata +1301 -0
@@ -0,0 +1,24 @@
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class Integer
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def method_missing(method,arg=nil)
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if method.to_s =~ /^s?[h|d]\d+$/i || method.to_s =~ /^s?[b](0|1|_)+$/i || method.to_s =~ /^s?[h][\d]?[\d|a-f]+$/i
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if self.nonzero?
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return "#{self.to_s}'#{method}".to_nq
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else
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return "'#{method}".to_nq
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end
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end
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super
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end
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# define_method("")
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def A
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if self.zero?
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return "'0".to_nq
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else
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return "~('0)".to_nq
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end
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end
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end
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"""
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DefArrayChain:
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- DefLogicArrayChain:
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- ClockDefLogicArrayChain
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- ResetDefLogicArrayChain
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- DefDataInf_ArrayChain:
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- PortDefDataInf_ArrayChain
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- DefDataInf_C_ArrayChain:
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- DefAxiStream_ArrayChain
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- PortDefAxiStream_ArrayChain:
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-
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- PortDefDataInf_C_ArrayChain:
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- DefAxiLite_ArrayChain:
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- PortDefAxiLite_ArrayChain
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- PortDefAxi4_ArrayChain
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"""
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module TdlSpace
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module PortDef
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PORT_SUB_TYPE = [:master,:slaver,:mirror,:out_mirror,:master_wr,:slaver_wr,:master_rd,:slaver_rd,:master_rd_aux,:mirror_rd,:mirror_wr,:master_wr_aux,:master_wr_aux_no_resp]
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PORT_SUB_TYPE.each do |e|
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define_method(e) do |args=[]|
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@sub_type = e
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# @has_args = args
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args.each do |key,value|
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# send(key,value)
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self.instance_variable_set("@#{key}",value)
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end
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return self
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end
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end
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def [](*a)
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new_c = super
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new_c.instance_variable_set("@sub_type",@sub_type)
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return new_c
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end
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end
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# class PortDefAxiStream_ArrayChain < DefAxiStream_ArrayChain
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# include PortDef
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# def -(name)
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# yname = to_inp(name)
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# @dsize = NqString.new("#{yname.to_s}.DSIZE") unless @dsize
|
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# a = ::AxiStream.new(name:yname,dsize:@dsize,port:@sub_type.to_s,dimension:@chain,freqM:freqM,belong_to_module: @belong_to_module)
|
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# # @belong_to_module.add_to_new_module("@port_axisinfs",a)
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# StringBandItegration.add_method_to_itgt(name,a)
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# a
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# end
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# end
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# class PortDefDataInf_ArrayChain < DefDataInf_ArrayChain
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# include PortDef
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# def -(name)
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# yname = to_inp(name)
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# @dsize = NqString.new("#{yname.to_s}.DSIZE") unless @dsize
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# # a = super(name)
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# a = DataInf.new(name:yname,dsize: @dsize,port: @sub_type.to_s,dimension:@chain ,belong_to_module: @belong_to_module)
|
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# # @belong_to_module.add_to_new_module("@port_datainfs",a)
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# StringBandItegration.add_method_to_itgt(name,a)
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# a
|
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# end
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# end
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# class PortDefDataInf_C_ArrayChain < DefDataInf_C_ArrayChain
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# include PortDef
|
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# def -(name)
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# yname = to_inp(name)
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# @dsize = NqString.new("#{yname.to_s}.DSIZE") unless @dsize
|
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# a = DataInf_C.new(name:yname,dsize:@dsize,port: @sub_type,dimension:@chain,freqM:freqM,belong_to_module: @belong_to_module)
|
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# # @belong_to_module.add_to_new_module("@port_datainf_c_s",a)
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# StringBandItegration.add_method_to_itgt(name,a)
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# a
|
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# end
|
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# end
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# class PortDefAxiLite_ArrayChain < DefAxiLite_ArrayChain
|
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# include PortDef
|
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# def -(name)
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# yname = to_inp(name)
|
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|
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# # @dsize = NqString.new("#{name.to_s}.DSIZE") unless @dsize
|
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# a = AxiLite.new(name:yname,clock:clock,reset:reset,dsize:dsize,asize:asize,mode:AxiLite::BOTH,port: @sub_type,freqM:freqM,belong_to_module: @belong_to_module)
|
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# # @belong_to_module.add_to_new_module("@port_axilinfs",a)
|
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# StringBandItegration.add_method_to_itgt(name,a)
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# a
|
98
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# end
|
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# end
|
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|
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# class PortDefAxi4_ArrayChain < DefAxi4_ArrayChain
|
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# include PortDef
|
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# def -(name)
|
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# yname = to_inp(name)
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# @dsize = NqString.new("#{yname.to_s}.DSIZE") unless @dsize
|
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# @idsize = NqString.new("#{yname.to_s}.IDSIZE") unless @idsize
|
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# @asize = NqString.new("#{yname.to_s}.ASIZE") unless @asize
|
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# @lsize = NqString.new("#{yname.to_s}.LSIZE") unless @lsize
|
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# @clock = NqString.new("#{yname.to_s}.axi_aclk") unless @clock
|
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# @reset = NqString.new("#{yname.to_s}.axi_aresetn") unless @reset
|
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# # @freqM = NqString.new("#{name.to_s}.FreqM") unless @freqM
|
113
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|
114
|
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# a = Axi4.new(name:yname,dsize:dsize,idsize:idsize,asize:asize,lsize:lsize,port:@sub_type,mode:mode,dimension:@chain,freqM:freqM,addr_step: addr_step,belong_to_module: @belong_to_module)
|
115
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+
|
116
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# if a.port.eql?(:master_wr) || a.port.eql?(:slaver_wr)
|
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# a.mode = Axi4::ONLY_WRITE
|
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# elsif a.port.eql?(:master_rd) || a.port.eql?(:slaver_rd)
|
119
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# a.mode = Axi4::ONLY_READ
|
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# else
|
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# a.mode = Axi4::BOTH
|
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# end
|
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# # @belong_to_module.add_to_new_module("@port_axi4infs",a)
|
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# StringBandItegration.add_method_to_itgt(name,a)
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# a
|
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# end
|
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# end
|
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class DefPortArrayChain
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attr_accessor :belong_to_module
|
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def initialize(belong_to_module)
|
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@belong_to_module = belong_to_module
|
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end
|
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# def axis
|
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# return PortDefAxiStream_ArrayChain.new(belong_to_module: self.belong_to_module)
|
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# end
|
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|
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# alias_method :axi_stream_inf,:axis
|
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# def axi4
|
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# return PortDefAxi4_ArrayChain.new(belong_to_module: self.belong_to_module)
|
146
|
+
# end
|
147
|
+
|
148
|
+
# def data
|
149
|
+
# return PortDefDataInf_ArrayChain.new(belong_to_module: self.belong_to_module)
|
150
|
+
# end
|
151
|
+
|
152
|
+
# alias_method :data_inf,:data
|
153
|
+
|
154
|
+
# def data_c
|
155
|
+
# return PortDefDataInf_C_ArrayChain.new(belong_to_module: self.belong_to_module)
|
156
|
+
# end
|
157
|
+
|
158
|
+
# alias_method :data_inf_c,:data_c
|
159
|
+
|
160
|
+
# def axilite
|
161
|
+
# return PortDefAxiLite_ArrayChain.new(belong_to_module: self.belong_to_module)
|
162
|
+
# end
|
163
|
+
|
164
|
+
end
|
165
|
+
|
166
|
+
class ClockDefLogicArrayChain < DefLogicArrayChain
|
167
|
+
attr_accessor :freqM
|
168
|
+
def -(name)
|
169
|
+
name = to_inp(name)
|
170
|
+
|
171
|
+
belong_to_module.Def.clock(name:name,freqM:@freqM || 100,dsize:@dsize || 1)
|
172
|
+
end
|
173
|
+
end
|
174
|
+
|
175
|
+
class ResetDefLogicArrayChain < DefLogicArrayChain
|
176
|
+
attr_accessor :active
|
177
|
+
def -(name)
|
178
|
+
name = to_inp(name)
|
179
|
+
|
180
|
+
belong_to_module.Def.reset(name:name,active: @active || "low",dsize: @dsize || 1)
|
181
|
+
end
|
182
|
+
end
|
183
|
+
|
184
|
+
class DefLogicArrayChain
|
185
|
+
def clock(*args)
|
186
|
+
if args.any?
|
187
|
+
if args[0].is_a? Hash
|
188
|
+
freqM = args[0][:freqM]
|
189
|
+
else
|
190
|
+
freqM = args[0]
|
191
|
+
end
|
192
|
+
else
|
193
|
+
freqM = nil
|
194
|
+
end
|
195
|
+
|
196
|
+
a = ClockDefLogicArrayChain.new(@belong_to_module)
|
197
|
+
a.freqM = freqM
|
198
|
+
|
199
|
+
return a
|
200
|
+
end
|
201
|
+
|
202
|
+
def reset(*args)
|
203
|
+
|
204
|
+
if args.any?
|
205
|
+
if args[0].is_a? Hash
|
206
|
+
active = args[0][:active]
|
207
|
+
else
|
208
|
+
active = args[0]
|
209
|
+
end
|
210
|
+
else
|
211
|
+
active = nil
|
212
|
+
end
|
213
|
+
|
214
|
+
a = ResetDefLogicArrayChain.new(@belong_to_module)
|
215
|
+
a.active = active
|
216
|
+
|
217
|
+
return a
|
218
|
+
|
219
|
+
end
|
220
|
+
end
|
221
|
+
end
|
222
|
+
|
223
|
+
class SdlModule
|
224
|
+
## 端口定义
|
225
|
+
def port
|
226
|
+
|
227
|
+
# return ClassHDL::PortDefChain.new(self)
|
228
|
+
return TdlSpace::DefPortArrayChain.new(self)
|
229
|
+
end
|
230
|
+
|
231
|
+
end
|
@@ -0,0 +1,114 @@
|
|
1
|
+
module ClassHDL
|
2
|
+
|
3
|
+
class BlockFOREACH < BlockELSE
|
4
|
+
attr_accessor :flag
|
5
|
+
def instance(as_type= :cond)
|
6
|
+
|
7
|
+
head_str = "foreach(#{cond.to_s}[#{flag}])begin"
|
8
|
+
|
9
|
+
sub_str = []
|
10
|
+
opertor_chains.each do |oc|
|
11
|
+
unless oc.is_a? BlockIF
|
12
|
+
unless oc.slaver
|
13
|
+
sub_str.push " #{oc.instance(as_type)};"
|
14
|
+
end
|
15
|
+
else
|
16
|
+
sub_str.push( oc.instance(as_type).gsub(/^./){ |m| " #{m}"} )
|
17
|
+
end
|
18
|
+
end
|
19
|
+
|
20
|
+
return "#{head_str}\n#{sub_str.join("\n")}\nend"
|
21
|
+
|
22
|
+
end
|
23
|
+
end
|
24
|
+
|
25
|
+
class BlockFOR < BlockELSE
|
26
|
+
attr_accessor :flag,:var,:start,:stop,:step,:var_type
|
27
|
+
def instance(as_type= :cond)
|
28
|
+
|
29
|
+
unless var
|
30
|
+
head_str = "for(#{var_type} #{flag}=#{start};#{flag}<#{stop};#{flag}=#{flag}+#{step})begin"
|
31
|
+
else
|
32
|
+
head_str = "for(#{var}=#{start};#{flag}<#{stop};#{flag}=#{flag}+#{step})begin"
|
33
|
+
end
|
34
|
+
|
35
|
+
sub_str = []
|
36
|
+
opertor_chains.each do |oc|
|
37
|
+
unless oc.is_a? BlockIF
|
38
|
+
unless oc.slaver
|
39
|
+
sub_str.push " #{oc.instance(as_type)};"
|
40
|
+
end
|
41
|
+
else
|
42
|
+
sub_str.push( oc.instance(as_type).gsub(/^./){ |m| " #{m}"} )
|
43
|
+
end
|
44
|
+
end
|
45
|
+
|
46
|
+
return "#{head_str}\n#{sub_str.join("\n")}\nend"
|
47
|
+
|
48
|
+
end
|
49
|
+
end
|
50
|
+
end
|
51
|
+
|
52
|
+
class SdlModule
|
53
|
+
@@__foreach_index_cnt__ = 0
|
54
|
+
def FOREACH(cond,&block)
|
55
|
+
ClassHDL::AssignDefOpertor.with_normal_opertor do
|
56
|
+
@@__foreach_index_cnt__ += 1
|
57
|
+
end
|
58
|
+
new_op = ClassHDL::BlockFOREACH.new
|
59
|
+
|
60
|
+
ClassHDL::AssignDefOpertor.with_new_opertor do
|
61
|
+
ClassHDL::AssignDefOpertor.with_new_assign_block(new_op) do |ab|
|
62
|
+
if cond.is_a? ClassHDL::OpertorChain
|
63
|
+
cond.slaver = true
|
64
|
+
end
|
65
|
+
ab.cond = cond
|
66
|
+
ab.flag = "i#{@@__foreach_index_cnt__}".to_nq
|
67
|
+
block.call(ab.flag)
|
68
|
+
|
69
|
+
end
|
70
|
+
end
|
71
|
+
|
72
|
+
ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(new_op)
|
73
|
+
ClassHDL::AssignDefOpertor.with_normal_opertor do
|
74
|
+
@@__foreach_index_cnt__ -= 1
|
75
|
+
end
|
76
|
+
return new_op
|
77
|
+
end
|
78
|
+
|
79
|
+
@@__for_index_cnt__ = 0
|
80
|
+
def FOR(var: nil, start: 0, stop: 8, step: 1,&block)
|
81
|
+
ClassHDL::AssignDefOpertor.with_normal_opertor do
|
82
|
+
@@__for_index_cnt__ += 1
|
83
|
+
end
|
84
|
+
new_op = ClassHDL::BlockFOR.new
|
85
|
+
|
86
|
+
ClassHDL::AssignDefOpertor.with_new_opertor do
|
87
|
+
ClassHDL::AssignDefOpertor.with_new_assign_block(new_op) do |ab|
|
88
|
+
# if cond.is_a? ClassHDL::OpertorChain
|
89
|
+
# cond.slaver = true
|
90
|
+
# end
|
91
|
+
# ab.cond = cond
|
92
|
+
ab.var = var
|
93
|
+
ab.start = start
|
94
|
+
ab.stop = stop
|
95
|
+
ab.step = step
|
96
|
+
ab.flag = var || "gvar_cc_#{@@__for_index_cnt__}".to_nq
|
97
|
+
block.call(ab.flag)
|
98
|
+
|
99
|
+
end
|
100
|
+
end
|
101
|
+
|
102
|
+
if ClassHDL::AssignDefOpertor.curr_assign_block.is_a?(ClassHDL::GenerateBlock)
|
103
|
+
new_op.var_type = "genvar"
|
104
|
+
else
|
105
|
+
new_op.var_type = "integer"
|
106
|
+
end
|
107
|
+
|
108
|
+
ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(new_op)
|
109
|
+
ClassHDL::AssignDefOpertor.with_normal_opertor do
|
110
|
+
@@__for_index_cnt__ -= 1
|
111
|
+
end
|
112
|
+
return new_op
|
113
|
+
end
|
114
|
+
end
|
@@ -0,0 +1,277 @@
|
|
1
|
+
module ClassHDL
|
2
|
+
|
3
|
+
class HDLFunctionIvoke
|
4
|
+
include AssignDefOpertor
|
5
|
+
|
6
|
+
def initialize(func_inst,*fargvs)
|
7
|
+
@fargvs = fargvs
|
8
|
+
@func_inst = func_inst
|
9
|
+
inst_strcut_method()
|
10
|
+
end
|
11
|
+
## 例化 struct 方法调用
|
12
|
+
def inst_strcut_method
|
13
|
+
if @func_inst.return_type.is_a? StructMeta
|
14
|
+
@func_inst.return_type.struct_slots.each do |e|
|
15
|
+
self.define_singleton_method(e.name) do
|
16
|
+
TdlSpace::ArrayChain.new("#{@func_inst.name}.#{e.name}".to_nq)
|
17
|
+
end
|
18
|
+
end
|
19
|
+
end
|
20
|
+
end
|
21
|
+
|
22
|
+
def ivoked
|
23
|
+
str = @fargvs.map do |e|
|
24
|
+
if e.is_a? OpertorChain
|
25
|
+
e.slaver = true
|
26
|
+
end
|
27
|
+
|
28
|
+
if e.instance_of? String
|
29
|
+
"\"#{e}\""
|
30
|
+
else
|
31
|
+
e.to_s
|
32
|
+
end
|
33
|
+
end.join(",")
|
34
|
+
|
35
|
+
return "#{@func_inst.name}(#{str})".to_nq
|
36
|
+
end
|
37
|
+
|
38
|
+
# def <=(oc)
|
39
|
+
|
40
|
+
# end
|
41
|
+
|
42
|
+
def to_s
|
43
|
+
if @func_inst.open_ivoke
|
44
|
+
ivoked
|
45
|
+
else
|
46
|
+
@func_inst.name.to_s.to_nq
|
47
|
+
end
|
48
|
+
end
|
49
|
+
|
50
|
+
# def self_ioved
|
51
|
+
|
52
|
+
# end
|
53
|
+
end
|
54
|
+
|
55
|
+
|
56
|
+
class HDLFunction
|
57
|
+
attr_accessor :opertor_chains,:name
|
58
|
+
attr_accessor :open_ivoke
|
59
|
+
attr_reader :return_type
|
60
|
+
|
61
|
+
def initialize(name,return_type,*argvs)
|
62
|
+
@opertor_chains = []
|
63
|
+
@name = name
|
64
|
+
@argvs = argvs
|
65
|
+
@return_type = return_type
|
66
|
+
end
|
67
|
+
|
68
|
+
def inst_port
|
69
|
+
return @argvs.map{|e| "#{e.inst_port[0]} #{e.inst_port[1]}" }.join(',')
|
70
|
+
end
|
71
|
+
|
72
|
+
def instance
|
73
|
+
str = []
|
74
|
+
if @return_type
|
75
|
+
if @return_type.is_a? EnumStruct
|
76
|
+
str.push "function #{@return_type.typedef_name} #{@name}(#{inst_port}); "
|
77
|
+
elsif @return_type.is_a? StructMeta
|
78
|
+
str.push "function #{@return_type.name} #{@name}(#{inst_port}); "
|
79
|
+
else
|
80
|
+
str.push "function #{@return_type.to_s} #{@name}(#{inst_port}); "
|
81
|
+
end
|
82
|
+
else
|
83
|
+
str.push "function #{@name}(#{inst_port}); "
|
84
|
+
end
|
85
|
+
|
86
|
+
opertor_chains.each do |op|
|
87
|
+
unless op.is_a? OpertorChain
|
88
|
+
str.push op.instance(:assign).gsub(/^./){ |m| " #{m}"}
|
89
|
+
else
|
90
|
+
unless op.slaver
|
91
|
+
rel_str = ClassHDL.compact_op_ch(op.instance(:assign))
|
92
|
+
str.push " #{rel_str};"
|
93
|
+
end
|
94
|
+
end
|
95
|
+
|
96
|
+
end
|
97
|
+
str.push "endfunction:#{@name}\n"
|
98
|
+
str.join("\n")
|
99
|
+
end
|
100
|
+
|
101
|
+
def ivoked(*fargvs)
|
102
|
+
str = fargvs.map do |e|
|
103
|
+
if e.is_a? OpertorChain
|
104
|
+
e.slaver = true
|
105
|
+
end
|
106
|
+
|
107
|
+
if e.instance_of? String
|
108
|
+
"\"#{e}\""
|
109
|
+
else
|
110
|
+
e.to_s
|
111
|
+
end
|
112
|
+
end.join(",")
|
113
|
+
|
114
|
+
return "#{@name}(#{str})".to_nq
|
115
|
+
end
|
116
|
+
end
|
117
|
+
|
118
|
+
def self.Function(sdl_m,name,return_type,*argvs,&block)
|
119
|
+
define_func_block_method(sdl_m,*argvs)
|
120
|
+
func_inst = ClassHDL::HDLFunction.new(name,return_type,*argvs)
|
121
|
+
## 给 sdl module 定义函数方法
|
122
|
+
sdl_m.define_singleton_method(name) do |*fargvs|
|
123
|
+
# new_op = OpertorChain.new
|
124
|
+
# new_op.tree.push([func_inst.ivoked(*fargvs)])
|
125
|
+
# new_op.slaver= true
|
126
|
+
# AssignDefOpertor.curr_assign_block.opertor_chains.push(new_op)
|
127
|
+
# new_op
|
128
|
+
fargvs.each do |e|
|
129
|
+
if e.is_a? OpertorChain
|
130
|
+
e.slaver = true
|
131
|
+
end
|
132
|
+
end
|
133
|
+
|
134
|
+
HDLFunctionIvoke.new(func_inst,*fargvs)
|
135
|
+
end
|
136
|
+
|
137
|
+
ClassHDL::AssignDefOpertor.with_new_assign_block(func_inst) do |ab|
|
138
|
+
|
139
|
+
AssignDefOpertor.with_rollback_opertors(:old) do
|
140
|
+
argvs.each do |e|
|
141
|
+
|
142
|
+
end
|
143
|
+
end
|
144
|
+
AssignDefOpertor.with_rollback_opertors(:new,&block)
|
145
|
+
# return ClassHDL::AssignDefOpertor.curr_assign_block
|
146
|
+
AssignDefOpertor.with_rollback_opertors(:old) do
|
147
|
+
sdl_m.Logic_draw.push ab.instance
|
148
|
+
end
|
149
|
+
end
|
150
|
+
remove_func_block_method(sdl_m,*argvs)
|
151
|
+
func_inst.open_ivoke = true
|
152
|
+
end
|
153
|
+
|
154
|
+
class DefFunction
|
155
|
+
attr_accessor :return_type
|
156
|
+
def initialize(sdlm,return_type=nil)
|
157
|
+
@return_type = return_type
|
158
|
+
@sdlm = sdlm
|
159
|
+
end
|
160
|
+
|
161
|
+
def method_missing(method,*argvs,&block)
|
162
|
+
ClassHDL::Function(@sdlm,method,return_type,*argvs,&block)
|
163
|
+
ClassHDL.enable_SdlModule_port
|
164
|
+
end
|
165
|
+
end
|
166
|
+
|
167
|
+
## redefine sdlmodule input output
|
168
|
+
|
169
|
+
def self.disable_SdlModule_port
|
170
|
+
symbs = [:Input,:Output,:Inout]
|
171
|
+
symbs.each do |symb|
|
172
|
+
SdlModule.class_eval do
|
173
|
+
alias_method "_function_bak_#{symb}__",symb
|
174
|
+
end
|
175
|
+
end
|
176
|
+
end
|
177
|
+
|
178
|
+
def self.enable_SdlModule_port
|
179
|
+
symbs = [:Input,:Output,:Inout]
|
180
|
+
symbs.each do |symb|
|
181
|
+
SdlModule.class_eval do
|
182
|
+
alias_method symb,"_function_bak_#{symb}__"
|
183
|
+
end
|
184
|
+
end
|
185
|
+
end
|
186
|
+
|
187
|
+
def self.new_def_SdlModule_port
|
188
|
+
SdlModule.class_eval do
|
189
|
+
def Input(name,dsize:1,dimension:[],pin:[],iostd:[],pin_prop:nil)
|
190
|
+
port_name_chk(name)
|
191
|
+
# pin,iostd = parse_pin_prop(pin_prop) if pin_prop
|
192
|
+
# RedefOpertor.with_normal_operators do
|
193
|
+
ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
|
194
|
+
tmp = Logic.new(name:name,dsize:dsize,port:"input",dimension:dimension)
|
195
|
+
# add_to_new_module("@port_logics",tmp)
|
196
|
+
# add_method_to_itgt(name,tmp)
|
197
|
+
tmp
|
198
|
+
end
|
199
|
+
end
|
200
|
+
|
201
|
+
def Output(name,dsize:1,dimension:[],pin:[],iostd:[],pin_prop:nil)
|
202
|
+
port_name_chk(name)
|
203
|
+
# pin,iostd = parse_pin_prop(pin_prop) if pin_prop
|
204
|
+
# RedefOpertor.with_normal_operators do
|
205
|
+
ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
|
206
|
+
tmp = Logic.new(name:name,dsize:dsize,port:"output logic",dimension:dimension)
|
207
|
+
# add_to_new_module("@port_logics",tmp)
|
208
|
+
|
209
|
+
if block_given?
|
210
|
+
yield(tmp)
|
211
|
+
end
|
212
|
+
# define_method(name) do
|
213
|
+
# add_method_to_itgt(name,tmp)
|
214
|
+
tmp
|
215
|
+
end
|
216
|
+
end
|
217
|
+
|
218
|
+
def Inout(name,dsize:1,dimension:[],pin:[],iostd:[],pin_prop:nil)
|
219
|
+
port_name_chk(name)
|
220
|
+
# pin,iostd = parse_pin_prop(pin_prop) if pin_prop
|
221
|
+
# RedefOpertor.with_normal_operators do
|
222
|
+
ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
|
223
|
+
tmp = Logic.new(name:name,dsize:dsize,port:"inout",dimension:dimension)
|
224
|
+
# add_to_new_module("@port_logics",tmp)
|
225
|
+
|
226
|
+
if block_given?
|
227
|
+
yield(tmp)
|
228
|
+
end
|
229
|
+
# define_method(name) do
|
230
|
+
# add_method_to_itgt(name,tmp)
|
231
|
+
tmp
|
232
|
+
end
|
233
|
+
end
|
234
|
+
end
|
235
|
+
end
|
236
|
+
|
237
|
+
def self.with_disable_SdlModule_port(&block)
|
238
|
+
disable_SdlModule_port
|
239
|
+
new_def_SdlModule_port
|
240
|
+
rel = block.call
|
241
|
+
enable_SdlModule_port
|
242
|
+
rel
|
243
|
+
end
|
244
|
+
## 为 function 块内定义 argv 方法
|
245
|
+
def self.define_func_block_method(sdlm,*argv)
|
246
|
+
argv.each do |e|
|
247
|
+
sdlm.define_singleton_method(e.name) do
|
248
|
+
e
|
249
|
+
end
|
250
|
+
end
|
251
|
+
end
|
252
|
+
|
253
|
+
def self.remove_func_block_method(sdlm,*argv)
|
254
|
+
argv.each do |e|
|
255
|
+
# sdlm.define_singleton_method(e.name) do
|
256
|
+
# method_missing(e.name)
|
257
|
+
# end
|
258
|
+
sdlm.instance_eval("undef #{e.name}")
|
259
|
+
end
|
260
|
+
end
|
261
|
+
end
|
262
|
+
|
263
|
+
|
264
|
+
|
265
|
+
class SdlModule
|
266
|
+
|
267
|
+
# def _core_function(name,*argvs,&block)
|
268
|
+
# ClassHDL::Function(self,name,*argvs,&block)
|
269
|
+
# end
|
270
|
+
|
271
|
+
def function(return_type=nil)
|
272
|
+
ClassHDL.disable_SdlModule_port
|
273
|
+
ClassHDL.new_def_SdlModule_port
|
274
|
+
return ClassHDL::DefFunction.new(self,return_type)
|
275
|
+
end
|
276
|
+
|
277
|
+
end
|