axi_tdl 0.0.2

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Files changed (1189) hide show
  1. checksums.yaml +7 -0
  2. data/.gitignore +8 -0
  3. data/CODE_OF_CONDUCT.md +74 -0
  4. data/Gemfile +6 -0
  5. data/Gemfile.lock +43 -0
  6. data/LICENSE +504 -0
  7. data/README.md +311 -0
  8. data/Rakefile +18 -0
  9. data/axi_tdl.gemspec +43 -0
  10. data/bin/console +14 -0
  11. data/bin/setup +8 -0
  12. data/lib/.rspec +1 -0
  13. data/lib/axi/AXI4/axi4_combin_wr_rd_batch.sv +59 -0
  14. data/lib/axi/AXI4/axi4_direct.sv +137 -0
  15. data/lib/axi/AXI4/axi4_direct_A1.sv +229 -0
  16. data/lib/axi/AXI4/axi4_direct_B1.sv +74 -0
  17. data/lib/axi/AXI4/axi4_direct_verb.sv +79 -0
  18. data/lib/axi/AXI4/axi4_direct_verc.sv +146 -0
  19. data/lib/axi/AXI4/axi4_dpram_cache.rb +106 -0
  20. data/lib/axi/AXI4/axi4_dpram_cache.sv +112 -0
  21. data/lib/axi/AXI4/axi4_long_to_axi4_wide.sv +85 -0
  22. data/lib/axi/AXI4/axi4_long_to_axi4_wide_A1.sv +96 -0
  23. data/lib/axi/AXI4/axi4_long_to_axi4_wide_track.sv +118 -0
  24. data/lib/axi/AXI4/axi4_long_to_axi4_wide_verb.sv +131 -0
  25. data/lib/axi/AXI4/axi4_pipe/axi4_pipe.sv +44 -0
  26. data/lib/axi/AXI4/axi4_pipe/axi4_pipe_verb.sv +45 -0
  27. data/lib/axi/AXI4/axi4_pipe/axi4_rd_pipe.sv +111 -0
  28. data/lib/axi/AXI4/axi4_pipe/axi4_rd_pipe_verb.sv +113 -0
  29. data/lib/axi/AXI4/axi4_pipe/axi4_wr_pipe.sv +142 -0
  30. data/lib/axi/AXI4/axi4_pipe/axi4_wr_pipe_verb.sv +146 -0
  31. data/lib/axi/AXI4/axi4_rd_auxiliary_batch_gen.sv +134 -0
  32. data/lib/axi/AXI4/axi4_rd_auxiliary_gen.sv +89 -0
  33. data/lib/axi/AXI4/axi4_rd_auxiliary_gen_A1.sv +109 -0
  34. data/lib/axi/AXI4/axi4_rd_burst_track.sv +164 -0
  35. data/lib/axi/AXI4/axi4_wr_aux_bind_data.sv +121 -0
  36. data/lib/axi/AXI4/axi4_wr_auxiliary_batch_gen.sv +140 -0
  37. data/lib/axi/AXI4/axi4_wr_auxiliary_gen.sv +102 -0
  38. data/lib/axi/AXI4/axi4_wr_auxiliary_gen_without_resp.sv +91 -0
  39. data/lib/axi/AXI4/axi4_wr_burst_track.sv +146 -0
  40. data/lib/axi/AXI4/axi_stream_add_addr_len.sv +50 -0
  41. data/lib/axi/AXI4/axi_stream_to_axi4_wr.sv +61 -0
  42. data/lib/axi/AXI4/axi_stream_to_axi4_wr_verb.sv.bak +123 -0
  43. data/lib/axi/AXI4/axis_to_axi4_wr.rb +149 -0
  44. data/lib/axi/AXI4/axis_to_axi4_wr.sv +141 -0
  45. data/lib/axi/AXI4/full_axi4_to_axis.sv +188 -0
  46. data/lib/axi/AXI4/full_axi4_to_axis_partition_wr_rd.sv +208 -0
  47. data/lib/axi/AXI4/id_record.sv +55 -0
  48. data/lib/axi/AXI4/idata_pool_axi4.sv +110 -0
  49. data/lib/axi/AXI4/interconnect/AXI4_interconnect_M2S.sv +291 -0
  50. data/lib/axi/AXI4/interconnect/axi4_mix_interconnect_M2S.sv +72 -0
  51. data/lib/axi/AXI4/interconnect/axi4_rd_interconnect_M2S.sv +148 -0
  52. data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S.sv +255 -0
  53. data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S.sv.bak +255 -0
  54. data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S_A1.sv +286 -0
  55. data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S_A2.sv +281 -0
  56. data/lib/axi/AXI4/interconnect/axi4_wr_interconnect_M2S.sv +235 -0
  57. data/lib/axi/AXI4/interconnect/axi4_wr_interconnect_M2S_A1.sv +283 -0
  58. data/lib/axi/AXI4/interconnect/axi4_wr_mix_interconnect_M2S.sv +32 -0
  59. data/lib/axi/AXI4/long_axi4_to_wide_axi4.sv.bak +251 -0
  60. data/lib/axi/AXI4/odata_pool_axi4.sv +134 -0
  61. data/lib/axi/AXI4/odata_pool_axi4_A1.sv +165 -0
  62. data/lib/axi/AXI4/odata_pool_axi4_A2.sv +159 -0
  63. data/lib/axi/AXI4/odata_pool_axi4_A3.sv +183 -0
  64. data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo.sv +61 -0
  65. data/lib/axi/AXI4/packet_fifo/axi4_rd_packet_fifo.sv +282 -0
  66. data/lib/axi/AXI4/packet_fifo/axi4_wr_packet_fifo.sv +181 -0
  67. data/lib/axi/AXI4/packet_merge/axi4_merge.sv +60 -0
  68. data/lib/axi/AXI4/packet_merge/axi4_merge_rd.sv +279 -0
  69. data/lib/axi/AXI4/packet_merge/axi4_merge_wr.sv +267 -0
  70. data/lib/axi/AXI4/packet_partition/axi4_partition.sv +36 -0
  71. data/lib/axi/AXI4/packet_partition/axi4_partition_OD.sv +66 -0
  72. data/lib/axi/AXI4/packet_partition/axi4_partition_rd.sv +211 -0
  73. data/lib/axi/AXI4/packet_partition/axi4_partition_rd_OD.sv +322 -0
  74. data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.rb +80 -0
  75. data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +93 -0
  76. data/lib/axi/AXI4/packet_partition/axi4_partition_wr.sv +239 -0
  77. data/lib/axi/AXI4/packet_partition/axi4_partition_wr_OD.sv +302 -0
  78. data/lib/axi/AXI4/packet_partition/data_inf_partition.rb +293 -0
  79. data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +307 -0
  80. data/lib/axi/AXI4/vcs_axi4_array_comptable.sv +35 -0
  81. data/lib/axi/AXI4/vcs_axi4_comptable.sv +330 -0
  82. data/lib/axi/AXI4/wide_axis_to_axi4_wr.rb +149 -0
  83. data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +140 -0
  84. data/lib/axi/AXI4/width_convert/axi4_data_combin_aflag_pipe.sv +239 -0
  85. data/lib/axi/AXI4/width_convert/axi4_data_combin_aflag_pipe_A1.sv +204 -0
  86. data/lib/axi/AXI4/width_convert/axi4_data_convert.sv +312 -0
  87. data/lib/axi/AXI4/width_convert/axi4_data_convert_A1.sv +217 -0
  88. data/lib/axi/AXI4/width_convert/data_combin.sv +366 -0
  89. data/lib/axi/AXI4/width_convert/data_combin.sv.bak +290 -0
  90. data/lib/axi/AXI4/width_convert/data_destruct.sv +304 -0
  91. data/lib/axi/AXI4/width_convert/feed_check.sv +94 -0
  92. data/lib/axi/AXI4/width_convert/len_convert.sv.bak +61 -0
  93. data/lib/axi/AXI4/width_convert/odd_width_convert.sv +229 -0
  94. data/lib/axi/AXI4/width_convert/odd_width_convert_verb.sv +105 -0
  95. data/lib/axi/AXI4/width_convert/simple_data_pipe.sv +40 -0
  96. data/lib/axi/AXI4/width_convert/simple_data_pipe_slaver.sv +33 -0
  97. data/lib/axi/AXI4/width_convert/width_combin.sv +113 -0
  98. data/lib/axi/AXI4/width_convert/width_convert.sv +87 -0
  99. data/lib/axi/AXI4/width_convert/width_convert_verb.sv +249 -0
  100. data/lib/axi/AXI4/width_convert/width_destruct.sv +206 -0
  101. data/lib/axi/AXI4/width_convert/width_destruct_A1.sv +251 -0
  102. data/lib/axi/AXI_BFM/AXI_BFM_PKG.sv +1039 -0
  103. data/lib/axi/AXI_BFM/Data_C_BFM_PKG.sv +97 -0
  104. data/lib/axi/AXI_BFM/axi4_error_chk.sv +298 -0
  105. data/lib/axi/AXI_BFM/axi4_illegal_bfm_pkg.sv +607 -0
  106. data/lib/axi/AXI_BFM/axi_lite_master.sv +102 -0
  107. data/lib/axi/AXI_BFM/axi_lite_tb.sv +23 -0
  108. data/lib/axi/AXI_BFM/axi_master.sv +185 -0
  109. data/lib/axi/AXI_BFM/axi_mirror.sv +266 -0
  110. data/lib/axi/AXI_BFM/axi_mm_tb.sv +134 -0
  111. data/lib/axi/AXI_BFM/axi_slaver.sv.bak +340 -0
  112. data/lib/axi/AXI_BFM/axistreambfm.sv +117 -0
  113. data/lib/axi/AXI_Lite/axi4_to_lite.sv +36 -0
  114. data/lib/axi/AXI_Lite/axi_lite_configure.sv +356 -0
  115. data/lib/axi/AXI_Lite/axi_lite_configure_inf2.sv +365 -0
  116. data/lib/axi/AXI_Lite/axi_lite_configure_verb.sv.bck +370 -0
  117. data/lib/axi/AXI_Lite/axi_lite_interconnect_M2S.sv +437 -0
  118. data/lib/axi/AXI_Lite/axi_lite_interconnect_S2M.sv +359 -0
  119. data/lib/axi/AXI_Lite/axi_lite_interconnect_S2M.sv.bak +359 -0
  120. data/lib/axi/AXI_Lite/axi_lite_master_empty.sv +30 -0
  121. data/lib/axi/AXI_Lite/axi_lite_slaver_empty.sv +27 -0
  122. data/lib/axi/AXI_Lite/axil_direct.sv +52 -0
  123. data/lib/axi/AXI_Lite/common_configure_reg_interface/common_configure_reg_interface.sv +230 -0
  124. data/lib/axi/AXI_Lite/common_configure_reg_interface/common_configure_reg_interface.sv.bak +109 -0
  125. data/lib/axi/AXI_Lite/common_configure_reg_interface/jtag_to_axilite_wrapper.sv +56 -0
  126. data/lib/axi/AXI_Lite/gen_axi_lite_ctrl.sv +515 -0
  127. data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_C1.sv +369 -0
  128. data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_verb.sv +365 -0
  129. data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_verc.sv +401 -0
  130. data/lib/axi/AXI_Lite/wr_lite_to_axis.sv +141 -0
  131. data/lib/axi/AXI_Lite/wr_lite_to_axis.sv.bak +141 -0
  132. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S.sv +76 -0
  133. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_A1.sv +77 -0
  134. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_A2.sv +71 -0
  135. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_bind_tuser.sv +72 -0
  136. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_noaddr.sv +151 -0
  137. data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_with_addr.sv +87 -0
  138. data/lib/axi/AXI_stream/axi_stream_interconnect_S2M.sv +65 -0
  139. data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_auto.sv +50 -0
  140. data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_with_info.sv +64 -0
  141. data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_with_keep.sv.bak +64 -0
  142. data/lib/axi/AXI_stream/axi_stream_packet_fifo_with_info.sv.bak +49 -0
  143. data/lib/axi/AXI_stream/axi_stream_partition.sv +147 -0
  144. data/lib/axi/AXI_stream/axi_stream_partition_A1.sv +63 -0
  145. data/lib/axi/AXI_stream/axi_stream_planer.sv +51 -0
  146. data/lib/axi/AXI_stream/axi_stream_split_channel.rb +56 -0
  147. data/lib/axi/AXI_stream/axi_stream_split_channel.sv +149 -0
  148. data/lib/axi/AXI_stream/axi_streams_combin.sv +151 -0
  149. data/lib/axi/AXI_stream/axi_streams_combin_A1.sv +179 -0
  150. data/lib/axi/AXI_stream/axi_streams_scaler.sv +171 -0
  151. data/lib/axi/AXI_stream/axi_streams_scaler_A1.sv +179 -0
  152. data/lib/axi/AXI_stream/axis_append.sv +79 -0
  153. data/lib/axi/AXI_stream/axis_append_A1.sv +82 -0
  154. data/lib/axi/AXI_stream/axis_base_pipe.sv +184 -0
  155. data/lib/axi/AXI_stream/axis_combin_with_fifo.sv +69 -0
  156. data/lib/axi/AXI_stream/axis_connect_pipe.sv +86 -0
  157. data/lib/axi/AXI_stream/axis_connect_pipe_A1.sv.bak +170 -0
  158. data/lib/axi/AXI_stream/axis_connect_pipe_left_shift.sv +64 -0
  159. data/lib/axi/AXI_stream/axis_connect_pipe_right_shift.sv +64 -0
  160. data/lib/axi/AXI_stream/axis_connect_pipe_right_shift_verb.sv +70 -0
  161. data/lib/axi/AXI_stream/axis_connect_pipe_with_info.sv +93 -0
  162. data/lib/axi/AXI_stream/axis_direct.sv +55 -0
  163. data/lib/axi/AXI_stream/axis_direct_A1.sv +81 -0
  164. data/lib/axi/AXI_stream/axis_filter.sv +38 -0
  165. data/lib/axi/AXI_stream/axis_full_to_data_c.sv +26 -0
  166. data/lib/axi/AXI_stream/axis_head_cut.sv +67 -0
  167. data/lib/axi/AXI_stream/axis_head_cut_verb.sv +60 -0
  168. data/lib/axi/AXI_stream/axis_head_cut_verc.rb +175 -0
  169. data/lib/axi/AXI_stream/axis_head_cut_verc.sv +245 -0
  170. data/lib/axi/AXI_stream/axis_inct_s2m_with_flag.sv +84 -0
  171. data/lib/axi/AXI_stream/axis_insert_copy.rb +59 -0
  172. data/lib/axi/AXI_stream/axis_insert_copy.sv +66 -0
  173. data/lib/axi/AXI_stream/axis_intc_M2S_with_addr_inf.sv +114 -0
  174. data/lib/axi/AXI_stream/axis_intc_S2M_with_addr_inf.sv +85 -0
  175. data/lib/axi/AXI_stream/axis_interconnect_S2M_pipe.sv +75 -0
  176. data/lib/axi/AXI_stream/axis_length_cut.sv +64 -0
  177. data/lib/axi/AXI_stream/axis_length_fill.sv +194 -0
  178. data/lib/axi/AXI_stream/axis_length_split.sv +86 -0
  179. data/lib/axi/AXI_stream/axis_length_split_with_addr.sv +127 -0
  180. data/lib/axi/AXI_stream/axis_length_split_writh_user.sv +87 -0
  181. data/lib/axi/AXI_stream/axis_link_trigger.sv +81 -0
  182. data/lib/axi/AXI_stream/axis_master_empty.sv +26 -0
  183. data/lib/axi/AXI_stream/axis_mirror_to_master.sv +126 -0
  184. data/lib/axi/AXI_stream/axis_mirrors.sv +60 -0
  185. data/lib/axi/AXI_stream/axis_orthogonal.sv +66 -0
  186. data/lib/axi/AXI_stream/axis_ram_buffer.sv +118 -0
  187. data/lib/axi/AXI_stream/axis_rom_contect.rb +97 -0
  188. data/lib/axi/AXI_stream/axis_rom_contect.sv +110 -0
  189. data/lib/axi/AXI_stream/axis_rom_contect_sim.rb +102 -0
  190. data/lib/axi/AXI_stream/axis_rom_contect_sim.sv +113 -0
  191. data/lib/axi/AXI_stream/axis_slaver_empty.sv +22 -0
  192. data/lib/axi/AXI_stream/axis_slaver_pipe.sv +84 -0
  193. data/lib/axi/AXI_stream/axis_slaver_pipe_A1.sv +54 -0
  194. data/lib/axi/AXI_stream/axis_slaver_vector_empty.sv +27 -0
  195. data/lib/axi/AXI_stream/axis_split_channel_verb.rb +42 -0
  196. data/lib/axi/AXI_stream/axis_split_channel_verb.sv +62 -0
  197. data/lib/axi/AXI_stream/axis_to_axi4_or_lite.rb +127 -0
  198. data/lib/axi/AXI_stream/axis_to_axi4_or_lite.sv +153 -0
  199. data/lib/axi/AXI_stream/axis_to_data_inf.sv +34 -0
  200. data/lib/axi/AXI_stream/axis_to_lite_rd.sv +81 -0
  201. data/lib/axi/AXI_stream/axis_to_lite_wr.sv +71 -0
  202. data/lib/axi/AXI_stream/axis_uncompress.sv +147 -0
  203. data/lib/axi/AXI_stream/axis_uncompress_A1.sv +150 -0
  204. data/lib/axi/AXI_stream/axis_uncompress_verb.rb +32 -0
  205. data/lib/axi/AXI_stream/axis_uncompress_verb.sv +54 -0
  206. data/lib/axi/AXI_stream/axis_valve.sv +29 -0
  207. data/lib/axi/AXI_stream/axis_valve_with_pipe.sv +76 -0
  208. data/lib/axi/AXI_stream/axis_vector_master_empty.rb +11 -0
  209. data/lib/axi/AXI_stream/axis_vector_master_empty.sv +35 -0
  210. data/lib/axi/AXI_stream/axis_vector_slaver_empty.rb +11 -0
  211. data/lib/axi/AXI_stream/axis_vector_slaver_empty.sv +35 -0
  212. data/lib/axi/AXI_stream/check_stream_crc.sv +28 -0
  213. data/lib/axi/AXI_stream/data_c_to_axis_full.sv +23 -0
  214. data/lib/axi/AXI_stream/data_to_axis_inf.sv +103 -0
  215. data/lib/axi/AXI_stream/data_to_axis_inf_A1.sv +28 -0
  216. data/lib/axi/AXI_stream/data_width/axis_width_combin.sv +204 -0
  217. data/lib/axi/AXI_stream/data_width/axis_width_combin_A1.sv +220 -0
  218. data/lib/axi/AXI_stream/data_width/axis_width_convert.sv +49 -0
  219. data/lib/axi/AXI_stream/data_width/axis_width_destruct.sv +82 -0
  220. data/lib/axi/AXI_stream/data_width/axis_width_destruct_A1.sv +86 -0
  221. data/lib/axi/AXI_stream/ex_status/axis_ex_status.sv +97 -0
  222. data/lib/axi/AXI_stream/gen_big_field_table.sv +170 -0
  223. data/lib/axi/AXI_stream/gen_common_frame_table.sv +382 -0
  224. data/lib/axi/AXI_stream/gen_common_frame_table_bind_tuser.sv +428 -0
  225. data/lib/axi/AXI_stream/gen_origin_axis.sv +116 -0
  226. data/lib/axi/AXI_stream/gen_origin_axis_A1.sv +129 -0
  227. data/lib/axi/AXI_stream/gen_origin_axis_A2.sv +162 -0
  228. data/lib/axi/AXI_stream/gen_simple_axis.sv +164 -0
  229. data/lib/axi/AXI_stream/packet_fifo/axi_stream_long_fifo.sv +132 -0
  230. data/lib/axi/AXI_stream/packet_fifo/axi_stream_long_fifo_verb.sv +140 -0
  231. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo.sv +125 -0
  232. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1.sv +142 -0
  233. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1E.sv +198 -0
  234. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_verb.sv +120 -0
  235. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_with_info.sv +49 -0
  236. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_long_fifo.sv +197 -0
  237. data/lib/axi/AXI_stream/packet_fifo/axi_stream_wide_fifo.sv +141 -0
  238. data/lib/axi/AXI_stream/packet_fifo/axis_pkt_fifo_filter_keep.sv +164 -0
  239. data/lib/axi/AXI_stream/packet_fifo/axis_pkt_fifo_filter_keep_A1.sv +166 -0
  240. data/lib/axi/AXI_stream/parse_big_field_table.sv +164 -0
  241. data/lib/axi/AXI_stream/parse_big_field_table_A1.sv +162 -0
  242. data/lib/axi/AXI_stream/parse_big_field_table_A2.sv +165 -0
  243. data/lib/axi/AXI_stream/parse_big_field_table_verb.sv +118 -0
  244. data/lib/axi/AXI_stream/parse_common_frame_table.sv +202 -0
  245. data/lib/axi/AXI_stream/parse_common_frame_table_A1.sv +521 -0
  246. data/lib/axi/AXI_stream/parse_common_frame_table_A2.sv +561 -0
  247. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache.sv +46 -0
  248. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_35bit.sv +122 -0
  249. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_36_71bit.sv +71 -0
  250. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_72_95bit.sv +96 -0
  251. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_72_95bit_with_keep.sv +99 -0
  252. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_96_143bit.sv +119 -0
  253. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_A1.sv +49 -0
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  255. data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_mirror.sv +44 -0
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  257. data/lib/axi/AXI_stream/stream_cache/axi_stream_long_cache.sv +55 -0
  258. data/lib/axi/AXI_stream/stream_crc.sv +67 -0
  259. data/lib/axi/AXI_stream/vcs_axis_comptable.sv +73 -0
  260. data/lib/axi/LICENSE +504 -0
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  263. data/lib/axi/SIM/tb_axis_bfm_0504.sv +61 -0
  264. data/lib/axi/SIM/tb_axis_partitiom_0929.sv +102 -0
  265. data/lib/axi/SIM/tb_axis_s2m_pipe_1023.sv +163 -0
  266. data/lib/axi/SIM/tb_axis_to_axi4_0925.sv +107 -0
  267. data/lib/axi/SIM/tb_data_c_m2s_inf_20200114.sv +222 -0
  268. data/lib/axi/SIM/tb_data_c_m2s_inf_20201103.sv +245 -0
  269. data/lib/axi/SIM/tb_data_c_pipe_inf_20180417.sv +114 -0
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  275. data/lib/axi/axi4_to_xilinx_ddr_native/ddr3_ip_native_to_axi4.sv +194 -0
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  283. data/lib/axi/cfg.yml +15 -0
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  285. data/lib/axi/common/common_ram_sim_wrapper.rb +66 -0
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  287. data/lib/axi/common/common_ram_wrapper.rb +71 -0
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  289. data/lib/axi/common/data_c_interface_dram.rb +90 -0
  290. data/lib/axi/common/data_c_interface_dram.sv +106 -0
  291. data/lib/axi/common/mem_format.coe +60 -0
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  311. data/lib/axi/data_interface/data_inf_c/data_c_pipe_force_vld_bind_data.sv +81 -0
  312. data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf.sv +130 -0
  313. data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf_A1.sv +135 -0
  314. data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf_left_shift.sv +158 -0
  315. data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf_right_shift.sv +155 -0
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  319. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_best_last.sv +319 -0
  320. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_best_robin.sv +293 -0
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  322. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_robin_with_id.sv +46 -0
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  324. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_verc_with_addr.sv +226 -0
  325. data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_verc_with_id.sv +54 -0
  326. data/lib/axi/data_interface/data_inf_c/data_c_pipe_latency.sv +68 -0
  327. data/lib/axi/data_interface/data_inf_c/data_c_scaler.sv +326 -0
  328. data/lib/axi/data_interface/data_inf_c/data_c_scaler_A1.sv +333 -0
  329. data/lib/axi/data_interface/data_inf_c/data_c_tmp_cache.sv +44 -0
  330. data/lib/axi/data_interface/data_inf_c/data_condition_mirror.sv +64 -0
  331. data/lib/axi/data_interface/data_inf_c/data_condition_valve.sv +53 -0
  332. data/lib/axi/data_interface/data_inf_c/data_connect_pipe_inf.sv +73 -0
  333. data/lib/axi/data_interface/data_inf_c/data_inf_c_M2S_with_addr_and_id.sv +66 -0
  334. data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_M2S_with_id.sv +67 -0
  335. data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_S2M.sv +70 -0
  336. data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_S2M_A1.sv +72 -0
  337. data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_S2M_with_lazy.sv +49 -0
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  339. data/lib/axi/data_interface/data_inf_c/data_inf_c_pipe_condition.sv +33 -0
  340. data/lib/axi/data_interface/data_inf_c/data_inf_c_planer.sv +50 -0
  341. data/lib/axi/data_interface/data_inf_c/data_inf_c_planer_A1.sv +53 -0
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  347. data/lib/axi/data_interface/data_inf_c/next_prio.sv +42 -0
  348. data/lib/axi/data_interface/data_inf_c/trigger_data_inf_c.sv +51 -0
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  354. data/lib/axi/data_interface/data_inf_intc_M2S_prio.sv +152 -0
  355. data/lib/axi/data_interface/data_inf_intc_M2S_prio_with_id.sv +55 -0
  356. data/lib/axi/data_interface/data_inf_interconnect_M2S_noaddr.sv +136 -0
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  358. data/lib/axi/data_interface/data_inf_planer.sv +59 -0
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  382. data/lib/axi/data_interface/datainf_slaver_empty.sv +22 -0
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  384. data/lib/axi/interface_define/axi_aux_inf.sv +206 -0
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  423. data/lib/axi/platform_ip/fifo_73_96bit.sv +102 -0
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  468. data/lib/axi/top/tb_data_intc_S2M_0807.sv +168 -0
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  482. data/lib/tdl/Logic/logic_operator.rb.bak +128 -0
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  486. data/lib/tdl/ReadMe.md +295 -0
  487. data/lib/tdl/SDL/axi4/AXI4_interconnect_M2S_sdl.rb +10 -0
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  498. data/lib/tdl/SDL/axi4/axi4_long_to_axi4_wide_A1_sdl.rb +10 -0
  499. data/lib/tdl/SDL/axi4/axi4_long_to_axi4_wide_sdl.rb +9 -0
  500. data/lib/tdl/SDL/axi4/axi4_long_to_axi4_wide_track_sdl.rb +9 -0
  501. data/lib/tdl/SDL/axi4/axi4_long_to_axi4_wide_verb_sdl.rb +11 -0
  502. data/lib/tdl/SDL/axi4/axi4_merge_rd_sdl.rb +10 -0
  503. data/lib/tdl/SDL/axi4/axi4_merge_sdl.rb +10 -0
  504. data/lib/tdl/SDL/axi4/axi4_merge_wr_sdl.rb +10 -0
  505. data/lib/tdl/SDL/axi4/axi4_mix_interconnect_M2S_sdl.rb +10 -0
  506. data/lib/tdl/SDL/axi4/axi4_packet_fifo_sdl.rb +12 -0
  507. data/lib/tdl/SDL/axi4/axi4_partition_OD_sdl.rb +11 -0
  508. data/lib/tdl/SDL/axi4/axi4_partition_rd_OD_sdl.rb +10 -0
  509. data/lib/tdl/SDL/axi4/axi4_partition_rd_sdl.rb +11 -0
  510. data/lib/tdl/SDL/axi4/axi4_partition_sdl.rb +11 -0
  511. data/lib/tdl/SDL/axi4/axi4_partition_wr_OD_sdl.rb +10 -0
  512. data/lib/tdl/SDL/axi4/axi4_partition_wr_sdl.rb +11 -0
  513. data/lib/tdl/SDL/axi4/axi4_pipe_sdl.rb +9 -0
  514. data/lib/tdl/SDL/axi4/axi4_pipe_verb_sdl.rb +9 -0
  515. data/lib/tdl/SDL/axi4/axi4_rd_auxiliary_batch_gen_sdl.rb +11 -0
  516. data/lib/tdl/SDL/axi4/axi4_rd_auxiliary_gen_A1_sdl.rb +9 -0
  517. data/lib/tdl/SDL/axi4/axi4_rd_auxiliary_gen_sdl.rb +9 -0
  518. data/lib/tdl/SDL/axi4/axi4_rd_burst_track_sdl.rb +10 -0
  519. data/lib/tdl/SDL/axi4/axi4_rd_interconnect_M2S_sdl.rb +10 -0
  520. data/lib/tdl/SDL/axi4/axi4_rd_mix_interconnect_M2S_A1_sdl.rb +10 -0
  521. data/lib/tdl/SDL/axi4/axi4_rd_mix_interconnect_M2S_A2_sdl.rb +10 -0
  522. data/lib/tdl/SDL/axi4/axi4_rd_mix_interconnect_M2S_sdl.rb +10 -0
  523. data/lib/tdl/SDL/axi4/axi4_rd_packet_fifo_sdl.rb +11 -0
  524. data/lib/tdl/SDL/axi4/axi4_rd_pipe_sdl.rb +9 -0
  525. data/lib/tdl/SDL/axi4/axi4_rd_pipe_verb_sdl.rb +9 -0
  526. data/lib/tdl/SDL/axi4/axi4_wr_aux_bind_data_sdl.rb +9 -0
  527. data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_batch_gen_sdl.rb +11 -0
  528. data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_gen_sdl.rb +10 -0
  529. data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_gen_without_resp_sdl.rb +10 -0
  530. data/lib/tdl/SDL/axi4/axi4_wr_burst_track_sdl.rb +10 -0
  531. data/lib/tdl/SDL/axi4/axi4_wr_interconnect_M2S_A1_sdl.rb +10 -0
  532. data/lib/tdl/SDL/axi4/axi4_wr_interconnect_M2S_sdl.rb +10 -0
  533. data/lib/tdl/SDL/axi4/axi4_wr_mix_interconnect_M2S_sdl.rb +10 -0
  534. data/lib/tdl/SDL/axi4/axi4_wr_packet_fifo_sdl.rb +11 -0
  535. data/lib/tdl/SDL/axi4/axi4_wr_pipe_sdl.rb +9 -0
  536. data/lib/tdl/SDL/axi4/axi4_wr_pipe_verb_sdl.rb +9 -0
  537. data/lib/tdl/SDL/axi4/axi_stream_add_addr_len_sdl.rb +11 -0
  538. data/lib/tdl/SDL/axi4/axi_stream_to_axi4_wr_sdl.rb +9 -0
  539. data/lib/tdl/SDL/axi4/data_combin_sdl.rb +20 -0
  540. data/lib/tdl/SDL/axi4/data_destruct_sdl.rb +19 -0
  541. data/lib/tdl/SDL/axi4/feed_check_sdl.rb +18 -0
  542. data/lib/tdl/SDL/axi4/full_axi4_to_axis_partition_wr_rd_sdl.rb +11 -0
  543. data/lib/tdl/SDL/axi4/full_axi4_to_axis_sdl.rb +10 -0
  544. data/lib/tdl/SDL/axi4/id_record_sdl.rb +19 -0
  545. data/lib/tdl/SDL/axi4/idata_pool_axi4_sdl.rb +18 -0
  546. data/lib/tdl/SDL/axi4/odata_pool_axi4_A1_sdl.rb +13 -0
  547. data/lib/tdl/SDL/axi4/odata_pool_axi4_A2_sdl.rb +10 -0
  548. data/lib/tdl/SDL/axi4/odata_pool_axi4_sdl.rb +19 -0
  549. data/lib/tdl/SDL/axi4/odd_width_convert_sdl.rb +19 -0
  550. data/lib/tdl/SDL/axi4/odd_width_convert_verb_sdl.rb +19 -0
  551. data/lib/tdl/SDL/axi4/simple_data_pipe_sdl.rb +16 -0
  552. data/lib/tdl/SDL/axi4/simple_data_pipe_slaver_sdl.rb +16 -0
  553. data/lib/tdl/SDL/axi4/vcs_axi4_array_comptable.rb +9 -0
  554. data/lib/tdl/SDL/axi4/vcs_axi4_array_comptable_sdl.rb +10 -0
  555. data/lib/tdl/SDL/axi4/vcs_axi4_comptable.rb +8 -0
  556. data/lib/tdl/SDL/axi4/vcs_axi4_comptable_sdl.rb +9 -0
  557. data/lib/tdl/SDL/axi4/width_combin_sdl.rb +20 -0
  558. data/lib/tdl/SDL/axi4/width_convert_sdl.rb +20 -0
  559. data/lib/tdl/SDL/axi4/width_convert_verb_sdl.rb +20 -0
  560. data/lib/tdl/SDL/axi4/width_destruct_A1_sdl.rb +22 -0
  561. data/lib/tdl/SDL/axi4/width_destruct_sdl.rb +19 -0
  562. data/lib/tdl/SDL/axistream/axi_stream_cache_35bit_sdl.rb +9 -0
  563. data/lib/tdl/SDL/axistream/axi_stream_cache_36_71bit_sdl.rb +9 -0
  564. data/lib/tdl/SDL/axistream/axi_stream_cache_72_95bit_sdl.rb +9 -0
  565. data/lib/tdl/SDL/axistream/axi_stream_cache_72_95bit_with_keep_sdl.rb +9 -0
  566. data/lib/tdl/SDL/axistream/axi_stream_cache_96_143bit_sdl.rb +9 -0
  567. data/lib/tdl/SDL/axistream/axi_stream_cache_B1_sdl.rb +9 -0
  568. data/lib/tdl/SDL/axistream/axi_stream_cache_mirror_sdl.rb +9 -0
  569. data/lib/tdl/SDL/axistream/axi_stream_cache_sdl.rb +9 -0
  570. data/lib/tdl/SDL/axistream/axi_stream_cache_verb_sdl.rb +9 -0
  571. data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_A1_sdl.rb +11 -0
  572. data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_A2_sdl.rb +13 -0
  573. data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_bind_tuser_sdl.rb +11 -0
  574. data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_noaddr_sdl.rb +11 -0
  575. data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_sdl.rb +12 -0
  576. data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_with_addr_sdl.rb +12 -0
  577. data/lib/tdl/SDL/axistream/axi_stream_interconnect_S2M_auto_sdl.rb +11 -0
  578. data/lib/tdl/SDL/axistream/axi_stream_interconnect_S2M_sdl.rb +12 -0
  579. data/lib/tdl/SDL/axistream/axi_stream_long_cache_sdl.rb +10 -0
  580. data/lib/tdl/SDL/axistream/axi_stream_long_fifo_sdl.rb +11 -0
  581. data/lib/tdl/SDL/axistream/axi_stream_long_fifo_verb_sdl.rb +11 -0
  582. data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_B1E_sdl.rb +16 -0
  583. data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_B1_sdl.rb +14 -0
  584. data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_sdl.rb +10 -0
  585. data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_verb_sdl.rb +13 -0
  586. data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_with_info_sdl.rb +13 -0
  587. data/lib/tdl/SDL/axistream/axi_stream_packet_long_fifo_sdl.rb +11 -0
  588. data/lib/tdl/SDL/axistream/axi_stream_partition_A1_sdl.rb +11 -0
  589. data/lib/tdl/SDL/axistream/axi_stream_partition_sdl.rb +12 -0
  590. data/lib/tdl/SDL/axistream/axi_stream_wide_fifo_sdl.rb +10 -0
  591. data/lib/tdl/SDL/axistream/axi_streams_combin_A1_sdl.rb +15 -0
  592. data/lib/tdl/SDL/axistream/axi_streams_combin_sdl.rb +16 -0
  593. data/lib/tdl/SDL/axistream/axi_streams_scaler_A1_sdl.rb +14 -0
  594. data/lib/tdl/SDL/axistream/axi_streams_scaler_sdl.rb +15 -0
  595. data/lib/tdl/SDL/axistream/axis_append_A1_sdl.rb +18 -0
  596. data/lib/tdl/SDL/axistream/axis_append_sdl.rb +17 -0
  597. data/lib/tdl/SDL/axistream/axis_base_pipe_sdl.rb +10 -0
  598. data/lib/tdl/SDL/axistream/axis_combin_with_fifo_sdl.rb +14 -0
  599. data/lib/tdl/SDL/axistream/axis_connect_pipe_right_shift_sdl.rb +10 -0
  600. data/lib/tdl/SDL/axistream/axis_connect_pipe_sdl.rb +9 -0
  601. data/lib/tdl/SDL/axistream/axis_connect_pipe_with_info_sdl.rb +12 -0
  602. data/lib/tdl/SDL/axistream/axis_direct_A1_sdl.rb +11 -0
  603. data/lib/tdl/SDL/axistream/axis_direct_sdl.rb +9 -0
  604. data/lib/tdl/SDL/axistream/axis_ex_status_sdl.rb +12 -0
  605. data/lib/tdl/SDL/axistream/axis_filter_sdl.rb +10 -0
  606. data/lib/tdl/SDL/axistream/axis_full_to_data_c_sdl.rb +9 -0
  607. data/lib/tdl/SDL/axistream/axis_head_cut_sdl.rb +10 -0
  608. data/lib/tdl/SDL/axistream/axis_inct_s2m_with_flag_sdl.rb +11 -0
  609. data/lib/tdl/SDL/axistream/axis_intc_M2S_with_addr_inf_sdl.rb +11 -0
  610. data/lib/tdl/SDL/axistream/axis_intc_S2M_with_addr_inf_sdl.rb +12 -0
  611. data/lib/tdl/SDL/axistream/axis_interconnect_S2M_pipe_sdl.rb +15 -0
  612. data/lib/tdl/SDL/axistream/axis_length_cut_sdl.rb +10 -0
  613. data/lib/tdl/SDL/axistream/axis_length_fill_sdl.rb +10 -0
  614. data/lib/tdl/SDL/axistream/axis_length_split_sdl.rb +10 -0
  615. data/lib/tdl/SDL/axistream/axis_length_split_with_addr_sdl.rb +13 -0
  616. data/lib/tdl/SDL/axistream/axis_length_split_writh_user_sdl.rb +10 -0
  617. data/lib/tdl/SDL/axistream/axis_link_trigger_sdl.rb +12 -0
  618. data/lib/tdl/SDL/axistream/axis_master_empty_sdl.rb +8 -0
  619. data/lib/tdl/SDL/axistream/axis_mirror_to_master_sdl.rb +10 -0
  620. data/lib/tdl/SDL/axistream/axis_mirrors_sdl.rb +14 -0
  621. data/lib/tdl/SDL/axistream/axis_orthogonal_sdl.rb +10 -0
  622. data/lib/tdl/SDL/axistream/axis_pkt_fifo_filter_keep_A1_sdl.rb +10 -0
  623. data/lib/tdl/SDL/axistream/axis_pkt_fifo_filter_keep_sdl.rb +10 -0
  624. data/lib/tdl/SDL/axistream/axis_ram_buffer_sdl.rb +13 -0
  625. data/lib/tdl/SDL/axistream/axis_slaver_empty_sdl.rb +8 -0
  626. data/lib/tdl/SDL/axistream/axis_slaver_pipe_A1_sdl.rb +10 -0
  627. data/lib/tdl/SDL/axistream/axis_slaver_pipe_sdl.rb +9 -0
  628. data/lib/tdl/SDL/axistream/axis_slaver_vector_empty_sdl.rb +9 -0
  629. data/lib/tdl/SDL/axistream/axis_to_data_inf_sdl.rb +10 -0
  630. data/lib/tdl/SDL/axistream/axis_to_lite_rd_sdl.rb +11 -0
  631. data/lib/tdl/SDL/axistream/axis_to_lite_wr_sdl.rb +10 -0
  632. data/lib/tdl/SDL/axistream/axis_uncompress_A1_sdl.rb +12 -0
  633. data/lib/tdl/SDL/axistream/axis_uncompress_sdl.rb +11 -0
  634. data/lib/tdl/SDL/axistream/axis_valve_sdl.rb +10 -0
  635. data/lib/tdl/SDL/axistream/axis_valve_with_pipe_sdl.rb +11 -0
  636. data/lib/tdl/SDL/axistream/axis_width_combin_A1_sdl.rb +9 -0
  637. data/lib/tdl/SDL/axistream/axis_width_combin_sdl.rb +9 -0
  638. data/lib/tdl/SDL/axistream/axis_width_convert_sdl.rb +9 -0
  639. data/lib/tdl/SDL/axistream/axis_width_destruct_A1_sdl.rb +9 -0
  640. data/lib/tdl/SDL/axistream/axis_width_destruct_sdl.rb +9 -0
  641. data/lib/tdl/SDL/axistream/check_stream_crc_sdl.rb +8 -0
  642. data/lib/tdl/SDL/axistream/data_c_to_axis_full_sdl.rb +9 -0
  643. data/lib/tdl/SDL/axistream/data_to_axis_inf_A1_sdl.rb +10 -0
  644. data/lib/tdl/SDL/axistream/data_to_axis_inf_sdl.rb +11 -0
  645. data/lib/tdl/SDL/axistream/gen_big_field_table_sdl.rb +14 -0
  646. data/lib/tdl/SDL/axistream/gen_common_frame_table_sdl.rb +60 -0
  647. data/lib/tdl/SDL/axistream/gen_origin_axis_A1_sdl.rb +13 -0
  648. data/lib/tdl/SDL/axistream/gen_origin_axis_sdl.rb +12 -0
  649. data/lib/tdl/SDL/axistream/gen_simple_axis_sdl.rb +13 -0
  650. data/lib/tdl/SDL/axistream/parse_big_field_table_A1_sdl.rb +17 -0
  651. data/lib/tdl/SDL/axistream/parse_big_field_table_A2_sdl.rb +17 -0
  652. data/lib/tdl/SDL/axistream/parse_big_field_table_sdl.rb +17 -0
  653. data/lib/tdl/SDL/axistream/stream_crc_sdl.rb +9 -0
  654. data/lib/tdl/SDL/axistream/vcs_axis_comptable.rb +16 -0
  655. data/lib/tdl/SDL/axistream/vcs_axis_comptable_sdl.rb +9 -0
  656. data/lib/tdl/SDL/data_inf_c/data_bind_sdl.rb +10 -0
  657. data/lib/tdl/SDL/data_inf_c/data_c_cache_sdl.rb +9 -0
  658. data/lib/tdl/SDL/data_inf_c/data_c_direct_mirror_sdl.rb +9 -0
  659. data/lib/tdl/SDL/data_inf_c/data_c_direct_sdl.rb +9 -0
  660. data/lib/tdl/SDL/data_inf_c/data_c_intc_M2S_force_robin_sdl.rb +10 -0
  661. data/lib/tdl/SDL/data_inf_c/data_c_pipe_force_vld_bind_data_sdl.rb +13 -0
  662. data/lib/tdl/SDL/data_inf_c/data_c_pipe_force_vld_sdl.rb +9 -0
  663. data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_A1_sdl.rb +10 -0
  664. data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_right_shift_sdl.rb +13 -0
  665. data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_sdl.rb +9 -0
  666. data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_C1_sdl.rb +14 -0
  667. data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_C1_with_id_sdl.rb +16 -0
  668. data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_sdl.rb +13 -0
  669. data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_with_addr_sdl.rb +13 -0
  670. data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_with_id_sdl.rb +15 -0
  671. data/lib/tdl/SDL/data_inf_c/data_c_pipe_latency_sdl.rb +10 -0
  672. data/lib/tdl/SDL/data_inf_c/data_c_scaler_A1_sdl.rb +16 -0
  673. data/lib/tdl/SDL/data_inf_c/data_c_scaler_sdl.rb +15 -0
  674. data/lib/tdl/SDL/data_inf_c/data_c_tmp_cache_sdl.rb +9 -0
  675. data/lib/tdl/SDL/data_inf_c/data_condition_mirror_sdl.rb +13 -0
  676. data/lib/tdl/SDL/data_inf_c/data_condition_valve_sdl.rb +13 -0
  677. data/lib/tdl/SDL/data_inf_c/data_connect_pipe_inf_sdl.rb +9 -0
  678. data/lib/tdl/SDL/data_inf_c/data_connect_pipe_sdl.rb +17 -0
  679. data/lib/tdl/SDL/data_inf_c/data_inf_A2B_sdl.rb +9 -0
  680. data/lib/tdl/SDL/data_inf_c/data_inf_B2A_sdl.rb +9 -0
  681. data/lib/tdl/SDL/data_inf_c/data_inf_c_M2S_with_addr_and_id_sdl.rb +17 -0
  682. data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_M2S_with_id_sdl.rb +15 -0
  683. data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_A1_sdl.rb +13 -0
  684. data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_sdl.rb +12 -0
  685. data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_with_lazy_sdl.rb +15 -0
  686. data/lib/tdl/SDL/data_inf_c/data_inf_c_interconnect_M2S_sdl.rb +12 -0
  687. data/lib/tdl/SDL/data_inf_c/data_inf_c_pipe_condition_sdl.rb +10 -0
  688. data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_A1.rb +12 -0
  689. data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_A1_sdl.rb +14 -0
  690. data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_sdl.rb +13 -0
  691. data/lib/tdl/SDL/data_inf_c/data_inf_cross_clk_sdl.rb +9 -0
  692. data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_force_addr_with_id_sdl.rb +19 -0
  693. data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_prio_sdl.rb +14 -0
  694. data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_prio_with_id_sdl.rb +17 -0
  695. data/lib/tdl/SDL/data_inf_c/data_inf_interconnect_M2S_noaddr_sdl.rb +14 -0
  696. data/lib/tdl/SDL/data_inf_c/data_inf_interconnect_M2S_with_id_noaddr_sdl.rb +17 -0
  697. data/lib/tdl/SDL/data_inf_c/data_inf_planer_A1_sdl.rb +15 -0
  698. data/lib/tdl/SDL/data_inf_c/data_inf_planer_sdl.rb +14 -0
  699. data/lib/tdl/SDL/data_inf_c/data_inf_ticktock_sdl.rb +18 -0
  700. data/lib/tdl/SDL/data_inf_c/data_intc_M2S_force_robin_sdl.rb +10 -0
  701. data/lib/tdl/SDL/data_inf_c/data_mirrors_sdl.rb +14 -0
  702. data/lib/tdl/SDL/data_inf_c/data_pair_map_A1_sdl.rb +16 -0
  703. data/lib/tdl/SDL/data_inf_c/data_pair_map_A2_sdl.rb +19 -0
  704. data/lib/tdl/SDL/data_inf_c/data_pair_map_sdl.rb +14 -0
  705. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_A1_sdl.rb +19 -0
  706. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_sdl.rb +17 -0
  707. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_verb_sdl.rb +16 -0
  708. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_A1_sdl.rb +19 -0
  709. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_sdl.rb +16 -0
  710. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_verb_sdl.rb +15 -0
  711. data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_sdl.rb +23 -0
  712. data/lib/tdl/SDL/data_inf_c/data_streams_combin_A1_sdl.rb +20 -0
  713. data/lib/tdl/SDL/data_inf_c/data_streams_combin_sdl.rb +20 -0
  714. data/lib/tdl/SDL/data_inf_c/data_streams_scaler_sdl.rb +19 -0
  715. data/lib/tdl/SDL/data_inf_c/data_uncompress_sdl.rb +11 -0
  716. data/lib/tdl/SDL/data_inf_c/data_valve_sdl.rb +10 -0
  717. data/lib/tdl/SDL/data_inf_c/datainf_c_master_empty_sdl.rb +8 -0
  718. data/lib/tdl/SDL/data_inf_c/datainf_c_slaver_empty_sdl.rb +8 -0
  719. data/lib/tdl/SDL/data_inf_c/datainf_master_empty_sdl.rb +8 -0
  720. data/lib/tdl/SDL/data_inf_c/datainf_slaver_empty_sdl.rb +8 -0
  721. data/lib/tdl/SDL/data_inf_c/latency_sdl.rb +8 -0
  722. data/lib/tdl/SDL/data_inf_c/next_prio_sdl.rb +12 -0
  723. data/lib/tdl/SDL/data_inf_c/part_data_pair_map_sdl.rb +19 -0
  724. data/lib/tdl/SDL/data_inf_c/trigger_data_inf_c_A1_sdl.rb +11 -0
  725. data/lib/tdl/SDL/data_inf_c/trigger_data_inf_c_sdl.rb +11 -0
  726. data/lib/tdl/SDL/data_inf_c/trigger_ready_ctrl_sdl.rb +12 -0
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  967. data/lib/tdl/class_hdl/hdl_module_def.rb +447 -0
  968. data/lib/tdl/class_hdl/hdl_package.rb +150 -0
  969. data/lib/tdl/class_hdl/hdl_parameter.rb +73 -0
  970. data/lib/tdl/class_hdl/hdl_random.rb +31 -0
  971. data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +653 -0
  972. data/lib/tdl/class_hdl/hdl_struct.rb +209 -0
  973. data/lib/tdl/class_hdl/hdl_verify.rb +136 -0
  974. data/lib/tdl/data_inf/_data_mirrors.rb +92 -0
  975. data/lib/tdl/data_inf/bak/_data_mirrors.rb +273 -0
  976. data/lib/tdl/data_inf/bak/common_fifo_auto.rb +279 -0
  977. data/lib/tdl/data_inf/bak/data_bind_auto.rb +128 -0
  978. data/lib/tdl/data_inf/bak/data_c_direct_auto.rb +138 -0
  979. data/lib/tdl/data_inf/bak/data_c_direct_mirror_auto.rb +138 -0
  980. data/lib/tdl/data_inf/bak/data_c_tmp_cache_auto.rb +138 -0
  981. data/lib/tdl/data_inf/bak/data_condition_mirror_auto.rb +216 -0
  982. data/lib/tdl/data_inf/bak/data_condition_valve_auto.rb +215 -0
  983. data/lib/tdl/data_inf/bak/data_connect_pipe.rb +80 -0
  984. data/lib/tdl/data_inf/bak/data_connect_pipe_inf_auto.rb +138 -0
  985. data/lib/tdl/data_inf/bak/data_inf_c_interconnect.rb +86 -0
  986. data/lib/tdl/data_inf/bak/data_inf_c_pipe_condition_auto.rb +157 -0
  987. data/lib/tdl/data_inf/bak/data_inf_cross_clk.rb +60 -0
  988. data/lib/tdl/data_inf/bak/data_inf_interconnect.rb +144 -0
  989. data/lib/tdl/data_inf/bak/data_inf_planer.rb +78 -0
  990. data/lib/tdl/data_inf/bak/data_inf_ticktack.rb +80 -0
  991. data/lib/tdl/data_inf/bak/data_inf_ticktock_auto.rb +0 -0
  992. data/lib/tdl/data_inf/bak/data_mirrors_auto.rb +234 -0
  993. data/lib/tdl/data_inf/bak/data_mirrors_verb.sv_auto.rb +234 -0
  994. data/lib/tdl/data_inf/bak/data_uncompress_auto.rb +177 -0
  995. data/lib/tdl/data_inf/bak/data_valve_auto.rb +127 -0
  996. data/lib/tdl/data_inf/bak/datainf_c_master_empty_auto.rb +95 -0
  997. data/lib/tdl/data_inf/bak/datainf_c_slaver_empty_auto.rb +88 -0
  998. data/lib/tdl/data_inf/bak/datainf_master_empty_auto.rb +95 -0
  999. data/lib/tdl/data_inf/bak/datainf_slaver_empty_auto.rb +88 -0
  1000. data/lib/tdl/data_inf/bak/independent_clock_fifo_auto.rb +298 -0
  1001. data/lib/tdl/data_inf/bak/part_data_pair_map_auto.rb +306 -0
  1002. data/lib/tdl/data_inf/common_fifo_auto.rb +141 -0
  1003. data/lib/tdl/data_inf/data_bind_auto.rb +79 -0
  1004. data/lib/tdl/data_inf/data_c_cache_auto.rb +135 -0
  1005. data/lib/tdl/data_inf/data_c_direct_auto.rb +127 -0
  1006. data/lib/tdl/data_inf/data_c_direct_mirror_auto.rb +127 -0
  1007. data/lib/tdl/data_inf/data_c_interconnect.rb +97 -0
  1008. data/lib/tdl/data_inf/data_c_pipe_force_vld_auto.rb +127 -0
  1009. data/lib/tdl/data_inf/data_c_pipe_inf_auto.rb +127 -0
  1010. data/lib/tdl/data_inf/data_c_pipe_intc_M2S_verc_auto.rb +123 -0
  1011. data/lib/tdl/data_inf/data_c_tmp_cache_auto.rb +127 -0
  1012. data/lib/tdl/data_inf/data_condition_mirror_auto.rb +165 -0
  1013. data/lib/tdl/data_inf/data_condition_valve_auto.rb +164 -0
  1014. data/lib/tdl/data_inf/data_connect_pipe_inf_auto.rb +127 -0
  1015. data/lib/tdl/data_inf/data_inf_c_pipe_condition_auto.rb +136 -0
  1016. data/lib/tdl/data_inf/data_mirrors_auto.rb +173 -0
  1017. data/lib/tdl/data_inf/data_mirrors_verb.sv_auto.rb +173 -0
  1018. data/lib/tdl/data_inf/data_uncompress_auto.rb +146 -0
  1019. data/lib/tdl/data_inf/data_valve_auto.rb +104 -0
  1020. data/lib/tdl/data_inf/datainf_c_master_empty_auto.rb +85 -0
  1021. data/lib/tdl/data_inf/datainf_c_slaver_empty_auto.rb +68 -0
  1022. data/lib/tdl/data_inf/datainf_master_empty_auto.rb +85 -0
  1023. data/lib/tdl/data_inf/datainf_slaver_empty_auto.rb +68 -0
  1024. data/lib/tdl/data_inf/independent_clock_fifo_auto.rb +141 -0
  1025. data/lib/tdl/data_inf/part_data_pair_map_auto.rb +149 -0
  1026. data/lib/tdl/data_inf/path_lib.rb +18 -0
  1027. data/lib/tdl/elements/Reset.rb +153 -0
  1028. data/lib/tdl/elements/axi4.rb +642 -0
  1029. data/lib/tdl/elements/axi_lite.rb +246 -0
  1030. data/lib/tdl/elements/axi_stream.rb +674 -0
  1031. data/lib/tdl/elements/clock.rb +193 -0
  1032. data/lib/tdl/elements/common_configure_reg.rb +135 -0
  1033. data/lib/tdl/elements/data_inf.rb +660 -0
  1034. data/lib/tdl/elements/logic.rb +356 -0
  1035. data/lib/tdl/elements/mail_box.rb +64 -0
  1036. data/lib/tdl/elements/originclass.rb +689 -0
  1037. data/lib/tdl/elements/parameter.rb +318 -0
  1038. data/lib/tdl/elements/track_inf.rb +163 -0
  1039. data/lib/tdl/elements/videoinf.rb +224 -0
  1040. data/lib/tdl/examples/10_random/exp_random.rb +13 -0
  1041. data/lib/tdl/examples/10_random/exp_random.sv +36 -0
  1042. data/lib/tdl/examples/11_test_unit/dve.tcl +64 -0
  1043. data/lib/tdl/examples/11_test_unit/exp_test_unit.rb +58 -0
  1044. data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +35 -0
  1045. data/lib/tdl/examples/11_test_unit/exp_test_unit_constraints.xdc +25 -0
  1046. data/lib/tdl/examples/11_test_unit/modules/sub_md0.rb +23 -0
  1047. data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +41 -0
  1048. data/lib/tdl/examples/11_test_unit/modules/sub_md1.rb +25 -0
  1049. data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv +41 -0
  1050. data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +28 -0
  1051. data/lib/tdl/examples/11_test_unit/tu0.sv +38 -0
  1052. data/lib/tdl/examples/11_test_unit/tu1.sv +28 -0
  1053. data/lib/tdl/examples/1_define_module/example1.rb +39 -0
  1054. data/lib/tdl/examples/1_define_module/exmple_md.sv +50 -0
  1055. data/lib/tdl/examples/2_hdl_class/always_comb.rb +99 -0
  1056. data/lib/tdl/examples/2_hdl_class/always_ff.rb +143 -0
  1057. data/lib/tdl/examples/2_hdl_class/case.rb +93 -0
  1058. data/lib/tdl/examples/2_hdl_class/foreach.rb +21 -0
  1059. data/lib/tdl/examples/2_hdl_class/function.rb +34 -0
  1060. data/lib/tdl/examples/2_hdl_class/generate.rb +62 -0
  1061. data/lib/tdl/examples/2_hdl_class/module_def.rb +33 -0
  1062. data/lib/tdl/examples/2_hdl_class/module_head_import_package.rb +36 -0
  1063. data/lib/tdl/examples/2_hdl_class/module_instance_test.rb +13 -0
  1064. data/lib/tdl/examples/2_hdl_class/package.rb +29 -0
  1065. data/lib/tdl/examples/2_hdl_class/package2.rb +21 -0
  1066. data/lib/tdl/examples/2_hdl_class/simple_assign.rb +39 -0
  1067. data/lib/tdl/examples/2_hdl_class/state_case.rb +65 -0
  1068. data/lib/tdl/examples/2_hdl_class/struct.rb +25 -0
  1069. data/lib/tdl/examples/2_hdl_class/struct_function.rb +28 -0
  1070. data/lib/tdl/examples/2_hdl_class/test_axi4_M2S.rb +16 -0
  1071. data/lib/tdl/examples/2_hdl_class/test_initial_assert.rb +11 -0
  1072. data/lib/tdl/examples/2_hdl_class/test_inst_sugar.rb +28 -0
  1073. data/lib/tdl/examples/2_hdl_class/test_module_port.rb +47 -0
  1074. data/lib/tdl/examples/2_hdl_class/test_module_var.rb +18 -0
  1075. data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv +108 -0
  1076. data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +35 -0
  1077. data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv +105 -0
  1078. data/lib/tdl/examples/2_hdl_class/tmp/head_pkg_module.sv +42 -0
  1079. data/lib/tdl/examples/2_hdl_class/tmp/init_module.sv +110 -0
  1080. data/lib/tdl/examples/2_hdl_class/tmp/module_instance_test.sv +31 -0
  1081. data/lib/tdl/examples/2_hdl_class/tmp/port_module.sv +99 -0
  1082. data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv +27 -0
  1083. data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv +78 -0
  1084. data/lib/tdl/examples/2_hdl_class/tmp/test_axi4_M2S.sv +30 -0
  1085. data/lib/tdl/examples/2_hdl_class/tmp/test_foreach.sv +34 -0
  1086. data/lib/tdl/examples/2_hdl_class/tmp/test_function.sv +52 -0
  1087. data/lib/tdl/examples/2_hdl_class/tmp/test_initial_assert.sv +31 -0
  1088. data/lib/tdl/examples/2_hdl_class/tmp/test_inst_sugar.sv +42 -0
  1089. data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +36 -0
  1090. data/lib/tdl/examples/2_hdl_class/tmp/test_module_port.sv +33 -0
  1091. data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +35 -0
  1092. data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +38 -0
  1093. data/lib/tdl/examples/2_hdl_class/tmp/test_package2.sv +36 -0
  1094. data/lib/tdl/examples/2_hdl_class/tmp/test_struct.sv +38 -0
  1095. data/lib/tdl/examples/2_hdl_class/tmp/test_struct_function.sv +44 -0
  1096. data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +27 -0
  1097. data/lib/tdl/examples/2_hdl_class/tmp/text_generate.sv +54 -0
  1098. data/lib/tdl/examples/2_hdl_class/vcs_string.rb +5 -0
  1099. data/lib/tdl/examples/3_hdl_sdl_instance/hdl_test.sv +13 -0
  1100. data/lib/tdl/examples/3_hdl_sdl_instance/main.rb +26 -0
  1101. data/lib/tdl/examples/3_hdl_sdl_instance/main_md.sv +42 -0
  1102. data/lib/tdl/examples/3_hdl_sdl_instance/sdl_md.sv +30 -0
  1103. data/lib/tdl/examples/3_hdl_sdl_instance/sdl_test.rb +9 -0
  1104. data/lib/tdl/examples/4_generate/example.rb +38 -0
  1105. data/lib/tdl/examples/4_generate/test_generate.sv +59 -0
  1106. data/lib/tdl/examples/5_logic_combin/login_combin.rb +22 -0
  1107. data/lib/tdl/examples/5_logic_combin/test_logic_combin.sv +36 -0
  1108. data/lib/tdl/examples/6_module_with_interface/example.rb +48 -0
  1109. data/lib/tdl/examples/6_module_with_interface/example_interface.sv +40 -0
  1110. data/lib/tdl/examples/6_module_with_interface/inf_collect.rb +54 -0
  1111. data/lib/tdl/examples/6_module_with_interface/inf_collect.sv +63 -0
  1112. data/lib/tdl/examples/7_module_with_package/body_package.rb +3 -0
  1113. data/lib/tdl/examples/7_module_with_package/body_package.sv +25 -0
  1114. data/lib/tdl/examples/7_module_with_package/example_pkg.rb +20 -0
  1115. data/lib/tdl/examples/7_module_with_package/example_pkg.sv +35 -0
  1116. data/lib/tdl/examples/7_module_with_package/head_package.rb +8 -0
  1117. data/lib/tdl/examples/7_module_with_package/head_package.sv +29 -0
  1118. data/lib/tdl/examples/8_top_module/dve.tcl +64 -0
  1119. data/lib/tdl/examples/8_top_module/example.rb +8 -0
  1120. data/lib/tdl/examples/8_top_module/pins.yml +7 -0
  1121. data/lib/tdl/examples/8_top_module/tb_test_top.sv +29 -0
  1122. data/lib/tdl/examples/8_top_module/test_top.sv +28 -0
  1123. data/lib/tdl/examples/8_top_module/test_top_constraints.xdc +37 -0
  1124. data/lib/tdl/examples/9_itegration/A_itgt/a_test_md.sv +29 -0
  1125. data/lib/tdl/examples/9_itegration/A_itgt/a_test_module.rb +6 -0
  1126. data/lib/tdl/examples/9_itegration/A_itgt/itgt_module_a_block.rb +34 -0
  1127. data/lib/tdl/examples/9_itegration/clock_manage/itgt_module_clock_manage.rb +33 -0
  1128. data/lib/tdl/examples/9_itegration/clock_manage/simple_clock.rb +7 -0
  1129. data/lib/tdl/examples/9_itegration/clock_manage/simple_clock.sv +29 -0
  1130. data/lib/tdl/examples/9_itegration/dve.tcl +64 -0
  1131. data/lib/tdl/examples/9_itegration/pins.yml +4 -0
  1132. data/lib/tdl/examples/9_itegration/tb_test_top.sv +29 -0
  1133. data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +29 -0
  1134. data/lib/tdl/examples/9_itegration/test_top.sv +40 -0
  1135. data/lib/tdl/examples/9_itegration/test_top_constraints.xdc +29 -0
  1136. data/lib/tdl/examples/9_itegration/test_tttop.sv +40 -0
  1137. data/lib/tdl/examples/9_itegration/test_tttop_constraints.xdc +29 -0
  1138. data/lib/tdl/examples/9_itegration/top.rb +11 -0
  1139. data/lib/tdl/examples/readme.md +31 -0
  1140. data/lib/tdl/exlib/common_cfg_reg_inf.rb +139 -0
  1141. data/lib/tdl/exlib/constraints.rb +286 -0
  1142. data/lib/tdl/exlib/constraints_verb.rb +304 -0
  1143. data/lib/tdl/exlib/dve_tcl.rb +162 -0
  1144. data/lib/tdl/exlib/element_class_vars.rb +106 -0
  1145. data/lib/tdl/exlib/global_param.rb +108 -0
  1146. data/lib/tdl/exlib/integral_test/bak/integral_test.rb +206 -0
  1147. data/lib/tdl/exlib/integral_test/clock_itest.rb +28 -0
  1148. data/lib/tdl/exlib/integral_test/diff_clock_itest.rb +30 -0
  1149. data/lib/tdl/exlib/integral_test/io_itest.rb +41 -0
  1150. data/lib/tdl/exlib/integral_test/reset_itest.rb +31 -0
  1151. data/lib/tdl/exlib/integral_test/simple_logic_itest.rb +19 -0
  1152. data/lib/tdl/exlib/itegration.rb +307 -0
  1153. data/lib/tdl/exlib/itegration_verb.rb +913 -0
  1154. data/lib/tdl/exlib/parse_argv.rb +43 -0
  1155. data/lib/tdl/exlib/sdlmodule_sim.bak.rb +375 -0
  1156. data/lib/tdl/exlib/test_point.rb +287 -0
  1157. data/lib/tdl/global_scan.rb +134 -0
  1158. data/lib/tdl/rebuild_ele/axi4.rb +141 -0
  1159. data/lib/tdl/rebuild_ele/axi_lite.rb +56 -0
  1160. data/lib/tdl/rebuild_ele/axi_stream.rb +121 -0
  1161. data/lib/tdl/rebuild_ele/cm_ram_inf.sv +105 -0
  1162. data/lib/tdl/rebuild_ele/cm_ram_inf_define.rb +44 -0
  1163. data/lib/tdl/rebuild_ele/data_inf.rb +27 -0
  1164. data/lib/tdl/rebuild_ele/data_inf_c.rb +83 -0
  1165. data/lib/tdl/rebuild_ele/ele_base.rb +822 -0
  1166. data/lib/tdl/rebuild_ele/readme.md +1 -0
  1167. data/lib/tdl/sdlimplement/resource.yml +154 -0
  1168. data/lib/tdl/sdlimplement/sdl_impl_module.rb +391 -0
  1169. data/lib/tdl/sdlimplement/sdl_impl_param.rb +26 -0
  1170. data/lib/tdl/sdlimplement/test.rb +64 -0
  1171. data/lib/tdl/sdlmodule/bak/sdlmodule_varible_ex.rb +120 -0
  1172. data/lib/tdl/sdlmodule/generator_block_module.rb +84 -0
  1173. data/lib/tdl/sdlmodule/sdlmodule.rb +407 -0
  1174. data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb +333 -0
  1175. data/lib/tdl/sdlmodule/sdlmodule_draw.rb +272 -0
  1176. data/lib/tdl/sdlmodule/sdlmodule_head_logo.txt +10 -0
  1177. data/lib/tdl/sdlmodule/sdlmodule_instance.rb +623 -0
  1178. data/lib/tdl/sdlmodule/sdlmodule_port_define.rb +374 -0
  1179. data/lib/tdl/sdlmodule/sdlmodule_varible.rb +160 -0
  1180. data/lib/tdl/sdlmodule/sdlmodule_vcs_comptable.rb +140 -0
  1181. data/lib/tdl/sdlmodule/techbench_module.rb +14 -0
  1182. data/lib/tdl/sdlmodule/test_unit_module.rb +138 -0
  1183. data/lib/tdl/sdlmodule/top_module.rb +543 -0
  1184. data/lib/tdl/tdl.rb +265 -0
  1185. data/lib/tdl/tdlerror/tdlerror.rb +8 -0
  1186. data/lib/tdl/testunit/test_all.rb +4 -0
  1187. data/lib/tdl/testunit/test_array_chain.rb +89 -0
  1188. data/lib/tdl/testunit/test_tmp.rb +47 -0
  1189. metadata +1301 -0
data/lib/tdl/elements/axi_lite.rb ADDED
@@ -0,0 +1,246 @@
1
+ # require_relative "./tdlerror"
2
+ # require_relative "./clock"
3
+ # require_relative "./Reset"
4
+ # require_relative "./logic"
5
+ # require_relative "./basefunc"
6
+ # require_relative "./axi_stream/axi_stream_lib"
7
+
8
+ class AxiLite < CLKInfElm
9
+ extend BaseFunc
10
+ include BaseModule
11
+ MACRO = '..\..\axi\macro\axil_macro.sv'
12
+ BOTH = "BOTH"
13
+ ONLY_READ = "ONLY_READ"
14
+ ONLY_WRITE = "ONLY_WRITE"
15
+
16
+ attr_accessor :id,:name,:dsize,:asize,:mode,:ghost,:port
17
+
18
+ def initialize(name:"axi_lite",clock:nil,reset:nil,dsize:8,asize:8,mode:BOTH,port:false,freqM:nil)
19
+ name_legal?(name)
20
+ super(clock:clock,reset:reset,freqM:freqM)
21
+ @inf_name = "axi_lite_inf"
22
+ @name = name
23
+ @dsize = dsize
24
+ @asize = asize
25
+ @mode = mode
26
+ @port = port
27
+
28
+ # @id = GlobalParam.CurrTdlModule.BindEleClassVars.AxiLite.id
29
+ # @correlation_proc = ""
30
+ # if @port
31
+ # GlobalParam.CurrTdlModule.BindEleClassVars.AxiLite.ports << self
32
+ # else
33
+ # GlobalParam.CurrTdlModule.BindEleClassVars.AxiLite.inst_stack << method(:inst).to_proc
34
+ # end
35
+ # @interconnect_up_streams = []
36
+ # GlobalParam.CurrTdlModule.BindEleClassVars.AxiLite.draw_stack << method(:draw).to_proc
37
+ end
38
+
39
+ # def signal
40
+ # if @port
41
+ # @name.to_s
42
+ # else
43
+ # "lite_#{@name}_#{@id}_inf"
44
+ # end
45
+ # end
46
+
47
+ def inst
48
+ return "" if @ghost
49
+ large_name_len(@mode,@clock,@reset)
50
+ "
51
+ #{@inf_name} #(
52
+ .ASIZE (#{align_signal(asize)}),
53
+ .DSIZE (#{align_signal(dsize)}),
54
+ .FreqM (#{freq_align_signal})
55
+ )#{signal}(
56
+ .axi_aclk (#{align_signal(@clock,false)}),
57
+ .axi_aresetn (#{align_signal(@reset.low_signal,false)})
58
+ );
59
+ "
60
+ end
61
+
62
+ # def self.inst
63
+ # GlobalParam.CurrTdlModule.BindEleClassVars.AxiLite.inst_stack.map { |e| e.call }.join("")
64
+ # end
65
+ #
66
+ # def self.draw
67
+ # str = ""
68
+ # GlobalParam.CurrTdlModule.BindEleClassVars.AxiLite.draw_stack.each do |e|
69
+ # str += e.call
70
+ # end
71
+ # return str
72
+ # end
73
+
74
+ def draw
75
+ super
76
+ return '' if @interconnect_up_streams.empty? && @correlation_proc.empty?
77
+ head_str = "\n//-------->>>> #{signal} <<<<----------------\n"
78
+ end_str = "\n//========<<<< #{signal} >>>>================\n"
79
+ unless @interconnect_up_streams.empty?
80
+ @correlation_proc += interconnect_draw
81
+ end
82
+ return head_str+@correlation_proc+end_str
83
+ end
84
+
85
+ def copy(name:@name.to_s,clock:@clock,reset:@reset,dsize:@dsize,asize:@asize,freqM:nil)
86
+ _freqM = use_which_freq_when_copy(clock,freqM)
87
+ append_name = name_copy(name)
88
+ new_obj = AxiLite.new(name:append_name,clock:clock,reset:reset,dsize:dsize,asize:asize,freqM:_freqM)
89
+ return new_obj
90
+ end
91
+
92
+ # def self.clear
93
+ # @@id = 1
94
+ # @@inst_stack = []
95
+ # @@ports = []
96
+ # # @@draw_stack = [NC.method(:draw).to_proc]
97
+ # @@draw_stack = []
98
+ # # NC.instance_variable_set("@correlation_proc","")
99
+ # @@nc = AxiLite.new(name:"implicit",dsize:1,clock:Clock.NC,reset:Reset.NC)
100
+ # BaseElm.recfg_nc(@@nc)
101
+ # end
102
+
103
+ # NC = AxiLite.new(name:"implicit",dsize:1,clock:Clock::NC,reset:Reset::NC)
104
+ # NC.instance_variable_set("@_id",0)
105
+
106
+ # def NC.signal
107
+ # id = NC.instance_variable_get("@_id")
108
+ # NC.instance_variable_set("@_id",id+1).to_s
109
+ # end
110
+
111
+ # @@nc = AxiLite.new(name:"implicit",dsize:1,clock:Clock.NC,reset:Reset.NC)
112
+ # @@nc.instance_variable_set("@_id",0)
113
+
114
+ # def self.NC
115
+ # GlobalParam.CurrTdlModule.BindEleClassVars.AxiLite.nc
116
+ # end
117
+
118
+ # def @@nc.signal
119
+ # id = @@nc.instance_variable_get("@_id")
120
+ # @@nc.instance_variable_set("@_id",id+1).to_s
121
+ # end
122
+
123
+ def self.nc_create
124
+ AxiLite.new(name:"implicit",dsize:1,clock:Clock.NC,reset:Reset.NC)
125
+ end
126
+
127
+ ### parse text for autogen method and constant ###
128
+
129
+ Synth_REP = Regexp.union(/\(\*\s+axi_lite\s*=\s*"true"\s+\*\)/,/\(\*\s+lite\s*=\s*"true"\s+\*\)/)
130
+
131
+ def self.parse_ports(port_array=nil)
132
+ rep = /(?<up_down>\(\*\s+(?<ud_name>axil_up|axil_down)\s*=\s*"true"\s+\*\))?\s*(axi_lite_inf\.)(?<modport>master|slaver|master_rd|slaver_rd|master_wr|slaver_wr)\s+(?<name>\w+)\s*(?<vector>\[.*?\])?/m
133
+ up_stream_rep = /axil_up/
134
+
135
+ super(port_array,rep,"axi_lite_inf",up_stream_rep) do |h|
136
+ h[:type] = AxiLite
137
+ yield h
138
+ end
139
+ end
140
+
141
+
142
+
143
+ end
144
+
145
+
146
+ class AxiLite ## signals in interface
147
+
148
+ def __inf_signal__(name)
149
+ raise TdlError.new("\nARRAY Don't have '#{name}'\n") unless @dimension.empty?
150
+ # puts "--------------"
151
+ # puts $new_m.instance_variable_get("@port_axisinfs")
152
+ # puts "============="
153
+ NqString.new(signal.concat ".#{name}")
154
+ # signal.concat ".#{name}"
155
+ end
156
+
157
+ INTERFACE_S_SIGNALS = %W{
158
+ axi_aclk
159
+ axi_aresetn
160
+ axi_awsize
161
+ axi_awvalid
162
+ axi_awready
163
+ axi_arsize
164
+ axi_arvalid
165
+ axi_arready
166
+ axi_bready
167
+ axi_bresp
168
+ axi_bvalid
169
+ axi_wvalid
170
+ axi_wready
171
+ axi_rready
172
+ axi_rvalid
173
+ DSIZE
174
+ ASIZE
175
+ MODE
176
+ FreqM
177
+ }
178
+ array_signals = AxiLite::INTERFACE_S_SIGNALS
179
+
180
+ array_signals.each do |item|
181
+ define_method(item) do
182
+ __inf_signal__(item)
183
+ end
184
+ end
185
+
186
+ # def vld_rdy
187
+ # axis_tvalid.concat(" && ").concat(axis_tready)
188
+ # end
189
+ #
190
+ # def vld_rdy_last
191
+ # axis_tvalid.concat(" && ").concat(axis_tready).concat(" && ").concat(axis_tlast)
192
+ # end
193
+
194
+ def _axi_data(name,h=nil,l=nil)
195
+ raise TdlError.new("\nARRAY Don't have '#{name}'") unless @dimension.empty?
196
+
197
+ if h.is_a? Range
198
+ l = h.to_a.min
199
+ h = h.to_a.max
200
+ end
201
+
202
+ if h
203
+ if l
204
+ sqr = "[#{h.to_s}:#{l.to_s}]"
205
+ else
206
+ sqr = "[#{h.to_s}]"
207
+ end
208
+ else
209
+ sqr = ""
210
+ end
211
+ signal.concat(".#{name}").concat(sqr)
212
+ end
213
+
214
+ INTERFACE_VECTOR_SIGNALS = %W{
215
+ axi_awaddr
216
+ axi_araddr
217
+ axi_wdata
218
+ axi_rdata
219
+ }
220
+
221
+ array_data_signals = INTERFACE_VECTOR_SIGNALS
222
+
223
+ array_data_signals.each do |item|
224
+ define_method(item) do
225
+ _axi_data(item)
226
+ end
227
+ end
228
+
229
+
230
+ end
231
+
232
+ class AxiLite # add empty
233
+ def self.leave_empty(curr_type: :master,dsize:8,asize:32,clock:Clock.NC,reset:Reset.NC)
234
+ nc = AxiLite.new(name:"empty",clock:clock,reset:reset,dsize:dsize,asize:asize,mode:BOTH,port:false)
235
+
236
+ if curr_type.to_sym == :slaver
237
+ self.axi_lite_master_empty(lite:nc)
238
+ elsif curr_type.to_sym == :master
239
+ self.axi_lite_slaver_empty(lite:nc)
240
+ else
241
+ raise TdlError.new("\n\n Axi Lite don't has this type << #{type} >> \n\n")
242
+ end
243
+
244
+ return nc
245
+ end
246
+ end
data/lib/tdl/elements/axi_stream.rb ADDED
@@ -0,0 +1,674 @@
1
+ # require_relative "./tdlerror"
2
+ # require_relative "./clock"
3
+ # require_relative "./Reset"
4
+ # require_relative "./logic"
5
+ # require_relative "./basefunc"
6
+ # require_relative "./axi_stream/axi_stream_lib"
7
+
8
+ class AxiStream < CLKInfElm
9
+ extend BaseFunc
10
+ include BaseModule
11
+
12
+ attr_accessor :id,:name,:dsize,:ghost
13
+ attr_accessor :port
14
+ def initialize(name:"test_axis",clock:nil,reset:nil,dsize:nil,port:false,dimension:[],freqM:nil)
15
+ name_legal?(name)
16
+ super(dimension:dimension,clock:clock,reset:reset,freqM:freqM)
17
+ @name = name.to_s
18
+ # @id = GlobalParam.CurrTdlModule.BindEleClassVars.AxiStream.id
19
+
20
+ @port = port
21
+ # raise TdlError.new("AXI STREAM CLOCK ERROR >>#{clock.class}<<") unless clock.is_a? Clock
22
+ # raise TdlError.new("AXI STREAM RESET ERROR") unless reset.is_a? Reset
23
+ # raise TdlError.new("AXI STREAM DATA ERROR") unless dsize.is_a? Fixnum
24
+
25
+ @dsize = dsize
26
+
27
+ unless port
28
+ @dsize = dsize
29
+ @clock = clock
30
+ @reset = reset
31
+ else
32
+ if dimension.empty?
33
+ @dsize = "#{name.to_s}.DSIZE".to_nq unless dsize
34
+ @clock = "#{name.to_s}.aclk".to_nq unless clock
35
+ @reset = "#{name.to_s}.aresetn".to_nq unless reset
36
+ else
37
+ @dsize = "#{name.to_s}[0].DSIZE".to_nq unless dsize
38
+ @clock = "#{name.to_s}[0].aclk".to_nq unless clock
39
+ @reset = "#{name.to_s}[0].aresetn".to_nq unless reset
40
+ end
41
+ end
42
+ # add_dsize_func
43
+ # @correlation_proc = ""
44
+ # @up_streams = []
45
+ # if @port
46
+ # GlobalParam.CurrTdlModule.BindEleClassVars.AxiStream.ports << self
47
+ # else
48
+ # GlobalParam.CurrTdlModule.BindEleClassVars.AxiStream.inst_stack << method(:inst).to_proc
49
+ # end
50
+ # @interconnect_up_streams = []
51
+
52
+ # GlobalParam.CurrTdlModule.BindEleClassVars.AxiStream.draw_stack << method(:draw).to_proc
53
+ end
54
+
55
+ # def signal(index=nil)
56
+ # square_str = super(index)
57
+ # if @port
58
+ # String.new(@name.to_s).concat square_str
59
+ # else
60
+ # unless @nc
61
+ # String.new("axis_#{@name}_id#{@id}#{square_str}")
62
+ # else
63
+ # String.new("nc_axis_#{@name}_id#{@id}#{square_str}")
64
+ # end
65
+ # end
66
+ # end
67
+
68
+ def inst
69
+ return "" if @ghost
70
+ if @reset.is_a? SignalElm
71
+ if @reset.active.casecmp("LOW") == 0
72
+ "axi_stream_inf #(.DSIZE(#{dsize}),.FreqM(#{intf_def_freqM})) #{signal}#{array_inst} (.aclk(#{compact_signal(@clock)}),.aresetn(#{@reset.signal}),.aclken(1'b1));"
73
+ else
74
+ "axi_stream_inf #(.DSIZE(#{dsize}),.FreqM(#{intf_def_freqM})) #{signal}#{array_inst} (.aclk(#{compact_signal(@clock)}),.aresetn(!#{@reset.signal}),.aclken(1'b1));"
75
+ end
76
+ else
77
+ "axi_stream_inf #(.DSIZE(#{dsize}),.FreqM(#{intf_def_freqM})) #{signal}#{array_inst} (.aclk(#{compact_signal(@clock)}),.aresetn(#{compact_signal(@reset)}),.aclken(1'b1));"
78
+ end
79
+ end
80
+
81
+ def port_length
82
+ ("axi_stream_inf." + @port.to_s + " ").length
83
+ end
84
+
85
+ def inst_port
86
+
87
+ # if @port
88
+ # ("axi_stream_inf." + @port.to_s + " " + " "*sub_len + @name.to_s + array_inst)
89
+ # end
90
+
91
+ return ["axi_stream_inf." + @port.to_s,@name.to_s,array_inst]
92
+ end
93
+
94
+
95
+ # def copy(name:@name,clock:"#{signal(0)}.aclk",reset:"#{signal(0)}.aresetn",dsize:"#{signal(0)}.DSIZE")
96
+ def copy(name:@name.to_s,clock:@clock,reset:@reset,dsize:@dsize,freqM:nil,dimension:[])
97
+ append_name = name_copy(name)
98
+ _freqM = use_which_freq_when_copy(clock,freqM)
99
+ a = belong_to_module.Def.axi_stream(name:append_name,clock:clock,reset:reset,dsize:dsize,freqM:_freqM,dimension:dimension)
100
+ a
101
+ end
102
+
103
+ def inherited(name:@name.to_s,clock: nil,reset: nil,dsize: nil,freqM: nil,dimension:[])
104
+ a = nil
105
+ ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
106
+ append_name = name_copy(name)
107
+ _freqM = use_which_freq_when_copy(clock,freqM)
108
+ a = belong_to_module.Def.axi_stream(
109
+ name:append_name,
110
+ clock: clock || self.aclk,
111
+ reset: reset || self.aresetn,
112
+ dsize: dsize || self.DSIZE,
113
+ freqM: _freqM,
114
+ dimension: dimension)
115
+ end
116
+ a
117
+ end
118
+
119
+ def branch(name:@name,clock:@clock,reset:@reset,dsize:@dsize,freqM:nil)
120
+ a = copy(name:name,clock:clock,reset:reset,dsize:dsize,freqM:freqM)
121
+ self << a
122
+ return a
123
+ end
124
+
125
+ def self.string_copy_inf(strs,belong_to_module)
126
+ @@_str_cp_id ||= 0
127
+ a = belong_to_module.Def.axi_stream(name:"string_copy_axis_#{@@_str_cp_id}",clock:"#{strs}.aclk",reset:"#{strs}.aresetn",dsize:"#{strs}.dsize")
128
+ @@_str_cp_id += 1
129
+ a
130
+ end
131
+
132
+ def gen_origin_draw
133
+ ""
134
+ end
135
+
136
+ def self.master_empty(*ms)
137
+ ms.each do |e|
138
+ # puts e
139
+ self.axis_master_empty(master:e)
140
+ end
141
+ end
142
+
143
+ def self.slaver_empty(*ss)
144
+ ss.each do |e|
145
+ self.axis_slaver_empty(slaver:e)
146
+ end
147
+ end
148
+
149
+ ## ---- new --------------
150
+
151
+ def self.leave_slaver_empty(*ms)
152
+ ms.each do |e|
153
+ # puts e
154
+ self.axis_master_empty(master:e)
155
+ end
156
+ end
157
+
158
+ def self.leave_master_empty(*ss)
159
+ ss.each do |e|
160
+ self.axis_slaver_empty(slaver:e)
161
+ end
162
+ end
163
+ ## =======================
164
+ def self.leave_empty(curr_type: :master,dsize:8,clock:"",reset:"",belong_to_module:nil)
165
+ nc = belong_to_module.Def.axi_stream(name:"empty_#{belong_to_module.AxiStream_NC.signal}",dsize:dsize,clock:clock,reset:reset)
166
+ # puts belong_to_module.module_name
167
+ if curr_type.to_sym == :slaver
168
+ self.axis_master_empty(master:nc)
169
+ elsif curr_type.to_sym == :master
170
+ self.axis_slaver_empty(slaver:nc)
171
+ else
172
+ raise TdlError.new("\n\n Axi Stream don't has this type << #{type} >> \n\n")
173
+ end
174
+
175
+ return nc
176
+ end
177
+
178
+
179
+ ### parse text for autogen method and constant ###
180
+
181
+ Synth_REP = /\(\*\s+axi_stream\s*=\s*"true"\s+\*\)/
182
+
183
+ def self.parse_ports(port_array=nil)
184
+ rep = /(?<up_down>\(\*\s+(?<ud_name>axis_up|axis_down|up_stream|down_stream)\s*=\s*"true"\s+\*\))?\s*(axi_stream_inf\.)(?<modport>master|slaver|mirror|out_mirror)\s+(?<name>\w+)\s*(?<vector>\[.*?\])?/m
185
+ up_stream_rep = Regexp.union(/axis_up/,/up_stream/)
186
+
187
+ super(port_array,rep,"axi_stream_inf",up_stream_rep) do |h|
188
+ h[:type] = AxiStream
189
+ # puts h
190
+ yield h
191
+ end
192
+ end
193
+
194
+ ## ----- Design Ref -------------------------
195
+
196
+ def last(latency:0)
197
+ lat = %Q{
198
+ //----->> #{signal} LAST DELAY <<------------------
199
+ logic #{signal}_last_Q;
200
+
201
+ latency #(
202
+ .LAT (#{latency}),
203
+ .DSIZE (1)
204
+ )#{signal}_last_lat(
205
+ #{signal}.aclk,
206
+ #{signal}.aresetn,
207
+ (#{signal}.axis_tvalid && #{signal}.axis_tready && #{signal}.axis_tlast),
208
+ #{signal}_last_Q
209
+ );
210
+ //-----<< #{signal} LAST DELAY >>------------------
211
+ }
212
+
213
+ if latency > 0
214
+ # GlobalParam.CurrTdlModule.BindEleClassVars.AxiStream.pre_inst << lambda { lat }
215
+ belong_to_module.AxiStream_draw << lat
216
+ return "#{signal}_last_Q"
217
+ else
218
+ return "(#{signal}.axis_tvalid && #{signal}.axis_tready && #{signal}.axis_tlast)"
219
+ end
220
+ end
221
+ end
222
+
223
+
224
+ class AxiStream # add []
225
+
226
+
227
+ def seq(start,lr) #lr must larger than zero, START : START+lr-1
228
+ RedefOpertor.with_old_operators do
229
+ @__seq_start_ ||= 1024
230
+ @__seq_end_ ||= 0
231
+ @__seq_start_ = start if @__seq_start_ > start
232
+ @__seq_end_ = (start+lr) if (@__seq_end_ < (start+lr))
233
+
234
+ unless @_sub_sel_value
235
+ ## dsize < 0 [0:X-1]
236
+ if @dsize.is_a? Numeric
237
+ @_sub_sel_value = belong_to_module.Def.logic(name:"#{signal(square:false)}_seq_value",dsize: -@dsize*(@__seq_end_-@__seq_start_),msb_high:false,port: :origin)
238
+ @_full_sub_sel_value = belong_to_module.Def.logic(name:"#{signal(square:false)}_full_seq_value",dsize: -@dsize*(@__seq_end_-0),msb_high:false,port: :origin)
239
+ else
240
+ @_sub_sel_value = belong_to_module.Def.logic(name:"#{signal(square:false)}_seq_value",dsize: "#{@dsize}*#{(@__seq_end_-@__seq_start_)}",msb_high:false,port: :origin)
241
+ @_full_sub_sel_value = belong_to_module.Def.logic(name:"#{signal(square:false)}_full_seq_value",dsize: "#{@dsize}*#{(@__seq_end_-0)}",msb_high:false,port: :origin)
242
+ @_sub_sel_value.force_nege_index(true)
243
+ @_full_sub_sel_value.force_nege_index(true)
244
+ end
245
+ else
246
+ if @dsize.is_a? Numeric
247
+ @_sub_sel_value.dsize = -@dsize*(@__seq_end_-@__seq_start_)
248
+ @_full_sub_sel_value.dsize = -@dsize*(@__seq_end_-0)
249
+ else
250
+ @_sub_sel_value.dsize = "#{@dsize}*#{(@__seq_end_-@__seq_start_)}"
251
+ @_full_sub_sel_value.dsize = "#{@dsize}*#{(@__seq_end_-0)}"
252
+ end
253
+ end
254
+
255
+ belong_to_module.AxiStream_pre_inst_stack << Proc.new do
256
+ if @dsize.is_a? Numeric
257
+ belong_to_module.Assign do
258
+ @_full_sub_sel_value[@__seq_start_*@dsize,@__seq_end_*@dsize-1] <= @_sub_sel_value
259
+ end
260
+ else
261
+ belong_to_module.Assign do
262
+ "#{@_full_sub_sel_value.signal(square:false)}[#{@__seq_start_}*#{self.DSIZE}:#{@__seq_end_}*#{self.DSIZE}-1]".to_nq <= @_sub_sel_value
263
+ end
264
+ end
265
+ ""
266
+ end
267
+
268
+ @_sub_sel_out_vld ||= belong_to_module.Def.logic(name:"#{signal(square:false)}_seq_vld",dsize:1,port: :origin)
269
+
270
+ # unless seq_vld()
271
+ self.define_singleton_method(:seq_vld) do
272
+ @_sub_sel_out_vld
273
+ end
274
+ # end
275
+
276
+ unless @_seq_call_
277
+ @_p_cm_tb_m = copy(name:"cm_tb_m_#{@name}")
278
+
279
+ self.define_singleton_method(:seq_tail_stream) do
280
+ @_called_seq_tail_stream = true
281
+ @_p_cm_tb_m
282
+ end
283
+
284
+ self.define_singleton_method(:seq_vld_rdy_last) do
285
+ @_p_cm_tb_m.vld_rdy_last
286
+ end
287
+ @_vcs_self_cpt_ = self.vcs_comptable(origin: 'slaver',to: 'mirror')
288
+ @_seq_call_ = lambda {
289
+
290
+ if @__seq_start_ == 0
291
+ enable = "1'b1"
292
+ else
293
+ enable = "(#{signal}.axis_tcnt >= #{@__seq_start_})"
294
+ end
295
+
296
+ AxiStream.parse_big_field_table_a2(
297
+ dsize: @dsize,
298
+ field_len:@__seq_end_ - @__seq_start_ ,
299
+ try_parse:"OFF",
300
+ enable:enable,
301
+ value:@_sub_sel_value.signal(square:false),
302
+ out_valid:@_sub_sel_out_vld,
303
+ cm_tb_s:self,
304
+ cm_tb_m:@_p_cm_tb_m,
305
+ cm_mirror: @_vcs_self_cpt_,
306
+ belong_to_module:belong_to_module
307
+ )
308
+ AxiStream.slaver_empty(@_p_cm_tb_m) unless @_called_seq_tail_stream
309
+ }
310
+ belong_to_module.AxiStream_pre_inst_stack << @_seq_call_
311
+ end
312
+
313
+ end
314
+ if @dsize.is_a? Numeric
315
+ return @_full_sub_sel_value[start*@dsize,(start+lr)*@dsize-1]
316
+ else
317
+ return "#{@_full_sub_sel_value.signal(square:false)}[#{start}*#{self.DSIZE}:#{(start+lr)}*#{self.DSIZE}-1]".to_nq
318
+ end
319
+ end
320
+
321
+ def mirror_seq(start,lr) #lr must larger than zero, START : START+lr-1
322
+ RedefOpertor.with_old_operators do
323
+ @__mirror_seq_start_ ||= 1024
324
+ @__mirror_seq_end_ ||= 0
325
+ @__mirror_seq_start_ = start if @__mirror_seq_start_ > start
326
+ @__mirror_seq_end_ = (start+lr) if (@__mirror_seq_end_ < (start+lr))
327
+
328
+ unless @_sub_mirror_seq_value
329
+ @_sub_mirror_seq_value = belong_to_module.Def.logic(name:"#{signal(square:false)}_seq_value",dsize: -@dsize*(@__mirror_seq_end_-@__mirror_seq_start_),msb_high:false,port: :origin)
330
+ end
331
+
332
+ @_sub_mirror_seq_value.dsize = -@dsize*(@__mirror_seq_end_-@__mirror_seq_start_)
333
+
334
+ if @__mirror_seq_start_ > 0
335
+ # @_sub_mirror_seq_value.send(:define_singleton_method,:inst) do
336
+ @_sub_mirror_seq_value.instance_variable_set("@__mirror_seq_start_",@__mirror_seq_start_*@dsize)
337
+ @_sub_mirror_seq_value.instance_variable_set("@__signal_name_",signal(square:false)+"_seq_value")
338
+ @_sub_mirror_seq_value.define_singleton_method(:inst) do
339
+ # puts @__mirror_seq_start_,@dsize
340
+ "logic [#{@__mirror_seq_start_}:#{(@dsize.abs-1)+@__mirror_seq_start_}] #{@__signal_name_};\n"
341
+ end
342
+ end
343
+
344
+ unless @_sub_mirror_seq_out_vld
345
+ @_sub_mirror_seq_out_vld = belong_to_module.Def.logic(name:"#{signal(square:false)}_seq_vld",dsize:1,port: :origin)
346
+ end
347
+
348
+ unless @_mirror_seq_call_
349
+ @_mirror_seq_call_ = lambda {
350
+
351
+ if @__mirror_seq_start_ == 0
352
+ enable = "1'b1"
353
+ else
354
+ enable = "(#{signal}.axis_tcnt >= #{@__mirror_seq_start_})"
355
+ end
356
+
357
+ @_mirror_p_cm_tb_m = copy(name:"cm_tb_m")
358
+
359
+ AxiStream.parse_big_field_table_a2(
360
+ dsize: @dsize,
361
+ field_len:@__mirror_seq_end_ - @__mirror_seq_start_ ,
362
+ try_parse:"ON",
363
+ enable:enable,
364
+ value:@_sub_mirror_seq_value.signal(square:false),
365
+ out_valid:@_sub_mirror_seq_out_vld,
366
+ cm_tb_s:self,
367
+ cm_tb_m:@_mirror_p_cm_tb_m,
368
+ cm_mirror:self)
369
+ }
370
+ # Tdl.module_stack << @_mirror_seq_call_
371
+ belong_to_module.AxiStream_pre_inst_stack << @_mirror_seq_call_
372
+ end
373
+
374
+ end
375
+
376
+ return "#{@_sub_mirror_seq_value[start*@dsize,(start+lr)*@dsize-1]}"
377
+ end
378
+
379
+ private
380
+ def square_inst
381
+ # value = Logic.new(name:"value",dsize:@dsize*@_p_cut)
382
+ # out_valid = Logic.new(name:"out_valid",dsize:1)
383
+ # puts @@inst_stack.length.to_s+"pre"
384
+ # cm_tb_s = copy(name:"cm_tb_s")
385
+ # cm_tb_s = AxiStream.new(name:"-----",dsize:8,clock:Clock::NC,reset:Reset::NC)
386
+ # puts cm_tb_s.inst
387
+ # puts cm_tb_m.inst
388
+ # puts @@inst_stack.length.to_s+"post"
389
+ if @_p_min == 0
390
+ enable = "1'b1"
391
+ else
392
+ enable = "(#{signal}.axis_tcnt >= #{@_p_min})"
393
+ end
394
+ # cm_mirror = self.copy()
395
+ AxiStream.parse_big_field_table(field_len:@_p_cut,try_parse:@_p_try_parse,enable:enable,value:@_sub_sel_value.signal(square:false),out_valid:@_sub_sel_out_vld,cm_tb_s:self,cm_tb_m:@_p_cm_tb_m,cm_mirror:self)
396
+ @_p_square.map { |e| e.call }.join("\n") + "\n"
397
+ end
398
+
399
+ public
400
+
401
+ def mirror_to(axis)
402
+ a = "\n//--->> #{signal} MIRROR <<-----------------------\n"
403
+ a +="assign #{axis.signal}.axis_tvalid = #{signal}.axis_tvalid;\n"
404
+ a +="assign #{axis.signal}.axis_tdata = #{signal}.axis_tdata ;\n"
405
+ a +="assign #{axis.signal}.axis_tlast = #{signal}.axis_tlast ;\n"
406
+ a +="assign #{axis.signal}.axis_tready = #{signal}.axis_tready;\n"
407
+
408
+ a +="assign #{axis.signal}.axis_tuser = #{signal}.axis_tuser;\n"
409
+ a +="assign #{axis.signal}.axis_tkeep = #{signal}.axis_tkeep;\n"
410
+ a += "//---<< #{signal} MIRROR >>-----------------------\n"
411
+
412
+ # GlobalParam.CurrTdlModule.BindEleClassVars.AxiStream.draw_stack << lambda{ a }
413
+ belong_to_module.AxiStream_draw << a
414
+ ""
415
+ end
416
+
417
+ end
418
+
419
+ class AxiStream # + * / =
420
+
421
+ def +(other_stream)
422
+ raise TdlError.new("#{other_stream} is not a AxiStream") unless other_stream.is_a? AxiStream
423
+ master_stream = self.copy(name:"#{name}_scaler_m00")
424
+ # AxiStream.axi_streams_scaler(mode:"HEAD",cut_or_combin_body:"OFF",dsize:@dsize,new_body_len:"16'hFFFF",head_inf:self,body_inf:other_stream,end_inf:self.copy(name:"tmp"),m00:master_stream)
425
+ AxiStream.axi_streams_scaler_a1(mode:"HEAD",cut_or_combin_body:"OFF",new_body_len:"16'hFFFF",head_inf:self,body_inf:other_stream,end_inf:self.copy(name:"tmp"),m00:master_stream)
426
+ return master_stream
427
+ end
428
+
429
+ def *(num)
430
+ raise TdlError.new("#{num} is not a Integer") unless num.is_a? Integer
431
+ div_mul(num,"*")
432
+ end
433
+
434
+ def /(num)
435
+ raise TdlError.new("#{num} is not a Integer") unless num.is_a? Integer
436
+ div_mul(num,"/")
437
+ end
438
+
439
+ def |(down_stream) # pipe
440
+ raise TdlError.new("#{down_stream} is not a AxiStream") unless down_stream.is_a? AxiStream
441
+ raise TdlError.new("PIPE '|' axi stream dsize dont eql !!! \n") if down_stream.dsize != @dsize
442
+ AxiStream.axis_connect_pipe(dsize:@dsize,up_stream:self,down_stream:down_stream)
443
+ return down_stream
444
+ end
445
+
446
+ def %(plength)
447
+ raise TdlError.new("#{plength} is not a Integer") unless plength.is_a? Integer
448
+
449
+ down_stream = self.copy(name:"partition")
450
+ AxiStream.axi_stream_partition(valve:"1'b1",partition_len:plength,req_new_len:"",up_stream:self,down_stream:down_stream)
451
+
452
+ return down_stream
453
+ end
454
+
455
+ # def _=(up_stream)
456
+ # raise TdlError.new("#{up_stream} is not a AxiStream") unless up_stream.is_a? AxiStream
457
+ #
458
+ # AxiStream.axis_direct(up_stream:up_stream,down_stream:self)
459
+ #
460
+ # return self
461
+ # end
462
+
463
+
464
+
465
+ private
466
+
467
+ def div_mul(num,m="*")
468
+ # raise TdlError.new("#{num} is not a Fixnum") unless num.is_a? Integer
469
+
470
+ stream = self.copy(name:"width_convert",dsize:(m=="*"? @dsize*num : @dsize/num) )
471
+
472
+ str = %Q{
473
+ width_convert #(
474
+ .ISIZE (#{@dsize}),
475
+ .OSIZE (#{@dsize}#{m}#{num} )
476
+ )#{signal}_width_convert_inst(
477
+ /* input */ .clock (#{signal}.aclk ),
478
+ /* input */ .rst_n (#{signal}.aresetn ),
479
+ /* input [ISIZE-1:0] */ .wr_data (#{signal}.axis_tdata ),
480
+ /* input */ .wr_vld (#{signal}.axis_tvalid ),
481
+ /* output logic */ .wr_ready (#{signal}.axis_tready ),
482
+ /* input */ .wr_last (#{signal}.axis_tlast ),
483
+ /* input */ .wr_align_last (1'b0 ), //can be leave 1'b0
484
+ /* output logic[OSIZE-1:0] */ .rd_data (#{stream}.axis_tdata ),
485
+ /* output logic */ .rd_vld (#{stream}.axis_tvalid ),
486
+ /* input */ .rd_ready (#{stream}.axis_tready ),
487
+ /* output */ .rd_last (#{stream}.axis_tlast )
488
+ );
489
+ }
490
+
491
+ # GlobalParam.CurrTdlModule.BindEleClassVars.AxiStream.pre_inst << lambda { str }
492
+ belong_to_module.AxiStream_draw << str
493
+
494
+ return stream
495
+ end
496
+
497
+ end
498
+
499
+ class AxiStream
500
+ # alias_method :direct,:axis_direct
501
+ # @@pre_inst << lambda {
502
+ # alias_method :direct,:axis_direct
503
+ # return ""
504
+ # }
505
+
506
+ def direct(slaver:"slaver",master:"master",up_stream:nil,down_stream:nil)
507
+ axis_direct(slaver:slaver,master:master,up_stream:up_stream,down_stream:down_stream)
508
+ end
509
+
510
+ def self.direct(slaver:"slaver",master:"master",up_stream:nil,down_stream:nil,belong_to_module:nil)
511
+ self.axis_direct(slaver:slaver,master:master,up_stream:up_stream,down_stream:down_stream,belong_to_module:belong_to_module)
512
+ end
513
+
514
+ end
515
+
516
+ class AxiStream ## signals in interface
517
+
518
+ def __inf_signal__(name)
519
+ raise TdlError.new("\nARRAY Don't have '#{name}'\n") unless @dimension.empty?
520
+ # puts "--------------"
521
+ # puts $new_m.instance_variable_get("@port_axisinfs")
522
+ # puts "============="
523
+ NqString.new(signal.concat ".#{name}")
524
+ # signal.concat ".#{name}"
525
+ end
526
+
527
+ array_signals = %W{axis_tvalid axis_tready axis_tlast axis_tcnt axis_tuser axis_tkeep DSIZE KSIZE}
528
+
529
+ def aclk(n=0)
530
+ if @clock.is_a? Clock
531
+ @clock
532
+ else
533
+ if dimension.empty?
534
+ NqString.new(signal.concat ".aclk")
535
+ else
536
+ NqString.new(signal(n).concat ".aclk")
537
+ end
538
+ end
539
+ end
540
+
541
+ def aresetn(n=0)
542
+ if @reset.is_a? Reset
543
+ @reset
544
+ else
545
+ if dimension.empty?
546
+ NqString.new(signal.concat ".aresetn")
547
+ else
548
+ NqString.new(signal(n).concat ".aresetn")
549
+ end
550
+ end
551
+ end
552
+
553
+ array_signals.each do |item|
554
+ define_method(item) do
555
+ __inf_signal__(item)
556
+ end
557
+ end
558
+
559
+ def vld_rdy
560
+ axis_tvalid.concat(" && ").concat(axis_tready)
561
+ end
562
+
563
+ def vld_rdy_last
564
+ axis_tvalid.concat(" && ").concat(axis_tready).concat(" && ").concat(axis_tlast)
565
+ end
566
+
567
+ def axis_tdata(h=nil,l=nil)
568
+ raise TdlError.new("\nARRAY Don't have 'axis_tdata'") unless @dimension.empty?
569
+
570
+ if h.is_a? Range
571
+ l = h.to_a.min
572
+ h = h.to_a.max
573
+ end
574
+
575
+ if h
576
+ if l
577
+ sqr = "[#{h.to_s}:#{l.to_s}]"
578
+ else
579
+ sqr = "[#{h.to_s}]"
580
+ end
581
+ else
582
+ sqr = ""
583
+ end
584
+ NqString.new(signal.concat(".axis_tdata").concat(sqr))
585
+ end
586
+ end
587
+
588
+ class AxiStream
589
+
590
+ def self.aclk(obj)
591
+ if(obj.is_a? AxiStream)
592
+ obj.aclk
593
+ elsif obj.is_a? String
594
+ NqString.new(obj.concat ".aclk")
595
+ end
596
+ end
597
+
598
+ def self.aresetn(obj)
599
+ if(obj.is_a? AxiStream)
600
+ obj.aresetn
601
+ elsif obj.is_a? String
602
+ NqString.new(obj.concat ".aresetn")
603
+ end
604
+ end
605
+
606
+ class << self
607
+ array_signals = %W{ axis_tvalid axis_tready axis_tlast axis_tcnt axis_tuser axis_tkeep DSIZE KSIZE FreqM}
608
+ array_signals.each do |item|
609
+ define_method(item) do |obj|
610
+ if(obj.is_a? AxiStream)
611
+ obj.send(item)
612
+ elsif obj.is_a? String
613
+ NqString.new(obj.concat ".#{item}")
614
+ end
615
+ end
616
+ end
617
+ end
618
+
619
+ def self.copy(obj)
620
+ if obj.is_a? AxiStream
621
+ obj.copy
622
+ elsif obj.is_a? String
623
+ AxiStream.new(name:"copy_#{obj}",clock:AxiStream.aclk(obj),reset:AxiStream.aresetn(obj),dsize:AxiStream.DSIZE(obj))
624
+ end
625
+ end
626
+
627
+ end
628
+
629
+ ## 添加 兼容 VCS 的 方法
630
+
631
+ class AxiStream
632
+
633
+ def vcs_comptable(origin: 'master',to: 'slaver')
634
+
635
+ if belong_to_module.respond_to? "#{@name}_#{origin}_to_#{to}"
636
+ return belong_to_module.send("#{@name}_#{origin}_to_#{to}").name.to_nq
637
+ end
638
+ ''' 返回字符串'''
639
+ # idm = belong_to_module.instance_variable_get("@_include_define_macro_")
640
+ # unless idm
641
+ # unless belong_to_module.ex_up_code
642
+ # belong_to_module.ex_up_code = '`include "define_macro.sv"'+"\n"
643
+ # else
644
+ # belong_to_module.ex_up_code += "`include \"define_macro.sv\"\n"
645
+ # end
646
+ # belong_to_module.instance_variable_set("@_include_define_macro_",true)
647
+ # end
648
+
649
+ # str = "\n`VCS_AXIS_CPT(#{@name},#{origin},#{to})\n"
650
+ # belong_to_module.AxiStream_draw << str
651
+ # @_vcs_cpt_ = "`#{@name}_vcs_cpt".to_nq
652
+ # return @_vcs_cpt_
653
+ belong_to_module.instance_exec(self,origin,to) do |origin_inf,origin_modport,to_modport|
654
+ Instance(:vcs_axis_comptable,"vcs_axis_comptable_#{origin_inf.name}_#{origin_modport}_#{to_modport}_inst") do |h|
655
+ h[:ORIGIN] = origin_modport
656
+ h[:TO] = to_modport
657
+ h[:origin] = origin_inf
658
+ h[:to] = origin_inf.copy(name: "#{origin_inf.name}_#{origin_modport}_to_#{to_modport}")
659
+ end
660
+ end
661
+
662
+ return belong_to_module.send("#{@name}_#{origin}_to_#{to}").name.to_nq
663
+ end
664
+ end
665
+
666
+ ## add clock_reset_taps
667
+ class AxiStream
668
+
669
+ def clock_reset_taps(def_clock_name,def_reset_name)
670
+
671
+ super(def_clock_name,def_reset_name,self.aclk,self.aresetn)
672
+ end
673
+
674
+ end