axi_tdl 0.0.2
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- checksums.yaml +7 -0
- data/.gitignore +8 -0
- data/CODE_OF_CONDUCT.md +74 -0
- data/Gemfile +6 -0
- data/Gemfile.lock +43 -0
- data/LICENSE +504 -0
- data/README.md +311 -0
- data/Rakefile +18 -0
- data/axi_tdl.gemspec +43 -0
- data/bin/console +14 -0
- data/bin/setup +8 -0
- data/lib/.rspec +1 -0
- data/lib/axi/AXI4/axi4_combin_wr_rd_batch.sv +59 -0
- data/lib/axi/AXI4/axi4_direct.sv +137 -0
- data/lib/axi/AXI4/axi4_direct_A1.sv +229 -0
- data/lib/axi/AXI4/axi4_direct_B1.sv +74 -0
- data/lib/axi/AXI4/axi4_direct_verb.sv +79 -0
- data/lib/axi/AXI4/axi4_direct_verc.sv +146 -0
- data/lib/axi/AXI4/axi4_dpram_cache.rb +106 -0
- data/lib/axi/AXI4/axi4_dpram_cache.sv +112 -0
- data/lib/axi/AXI4/axi4_long_to_axi4_wide.sv +85 -0
- data/lib/axi/AXI4/axi4_long_to_axi4_wide_A1.sv +96 -0
- data/lib/axi/AXI4/axi4_long_to_axi4_wide_track.sv +118 -0
- data/lib/axi/AXI4/axi4_long_to_axi4_wide_verb.sv +131 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_pipe.sv +44 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_pipe_verb.sv +45 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_rd_pipe.sv +111 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_rd_pipe_verb.sv +113 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_wr_pipe.sv +142 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_wr_pipe_verb.sv +146 -0
- data/lib/axi/AXI4/axi4_rd_auxiliary_batch_gen.sv +134 -0
- data/lib/axi/AXI4/axi4_rd_auxiliary_gen.sv +89 -0
- data/lib/axi/AXI4/axi4_rd_auxiliary_gen_A1.sv +109 -0
- data/lib/axi/AXI4/axi4_rd_burst_track.sv +164 -0
- data/lib/axi/AXI4/axi4_wr_aux_bind_data.sv +121 -0
- data/lib/axi/AXI4/axi4_wr_auxiliary_batch_gen.sv +140 -0
- data/lib/axi/AXI4/axi4_wr_auxiliary_gen.sv +102 -0
- data/lib/axi/AXI4/axi4_wr_auxiliary_gen_without_resp.sv +91 -0
- data/lib/axi/AXI4/axi4_wr_burst_track.sv +146 -0
- data/lib/axi/AXI4/axi_stream_add_addr_len.sv +50 -0
- data/lib/axi/AXI4/axi_stream_to_axi4_wr.sv +61 -0
- data/lib/axi/AXI4/axi_stream_to_axi4_wr_verb.sv.bak +123 -0
- data/lib/axi/AXI4/axis_to_axi4_wr.rb +149 -0
- data/lib/axi/AXI4/axis_to_axi4_wr.sv +141 -0
- data/lib/axi/AXI4/full_axi4_to_axis.sv +188 -0
- data/lib/axi/AXI4/full_axi4_to_axis_partition_wr_rd.sv +208 -0
- data/lib/axi/AXI4/id_record.sv +55 -0
- data/lib/axi/AXI4/idata_pool_axi4.sv +110 -0
- data/lib/axi/AXI4/interconnect/AXI4_interconnect_M2S.sv +291 -0
- data/lib/axi/AXI4/interconnect/axi4_mix_interconnect_M2S.sv +72 -0
- data/lib/axi/AXI4/interconnect/axi4_rd_interconnect_M2S.sv +148 -0
- data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S.sv +255 -0
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- data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S_A2.sv +281 -0
- data/lib/axi/AXI4/interconnect/axi4_wr_interconnect_M2S.sv +235 -0
- data/lib/axi/AXI4/interconnect/axi4_wr_interconnect_M2S_A1.sv +283 -0
- data/lib/axi/AXI4/interconnect/axi4_wr_mix_interconnect_M2S.sv +32 -0
- data/lib/axi/AXI4/long_axi4_to_wide_axi4.sv.bak +251 -0
- data/lib/axi/AXI4/odata_pool_axi4.sv +134 -0
- data/lib/axi/AXI4/odata_pool_axi4_A1.sv +165 -0
- data/lib/axi/AXI4/odata_pool_axi4_A2.sv +159 -0
- data/lib/axi/AXI4/odata_pool_axi4_A3.sv +183 -0
- data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo.sv +61 -0
- data/lib/axi/AXI4/packet_fifo/axi4_rd_packet_fifo.sv +282 -0
- data/lib/axi/AXI4/packet_fifo/axi4_wr_packet_fifo.sv +181 -0
- data/lib/axi/AXI4/packet_merge/axi4_merge.sv +60 -0
- data/lib/axi/AXI4/packet_merge/axi4_merge_rd.sv +279 -0
- data/lib/axi/AXI4/packet_merge/axi4_merge_wr.sv +267 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition.sv +36 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_OD.sv +66 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd.sv +211 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_OD.sv +322 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.rb +80 -0
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- data/lib/axi/AXI4/packet_partition/data_inf_partition.rb +293 -0
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- data/lib/axi/AXI4/width_convert/axi4_data_combin_aflag_pipe.sv +239 -0
- data/lib/axi/AXI4/width_convert/axi4_data_combin_aflag_pipe_A1.sv +204 -0
- data/lib/axi/AXI4/width_convert/axi4_data_convert.sv +312 -0
- data/lib/axi/AXI4/width_convert/axi4_data_convert_A1.sv +217 -0
- data/lib/axi/AXI4/width_convert/data_combin.sv +366 -0
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- data/lib/axi/AXI4/width_convert/data_destruct.sv +304 -0
- data/lib/axi/AXI4/width_convert/feed_check.sv +94 -0
- data/lib/axi/AXI4/width_convert/len_convert.sv.bak +61 -0
- data/lib/axi/AXI4/width_convert/odd_width_convert.sv +229 -0
- data/lib/axi/AXI4/width_convert/odd_width_convert_verb.sv +105 -0
- data/lib/axi/AXI4/width_convert/simple_data_pipe.sv +40 -0
- data/lib/axi/AXI4/width_convert/simple_data_pipe_slaver.sv +33 -0
- data/lib/axi/AXI4/width_convert/width_combin.sv +113 -0
- data/lib/axi/AXI4/width_convert/width_convert.sv +87 -0
- data/lib/axi/AXI4/width_convert/width_convert_verb.sv +249 -0
- data/lib/axi/AXI4/width_convert/width_destruct.sv +206 -0
- data/lib/axi/AXI4/width_convert/width_destruct_A1.sv +251 -0
- data/lib/axi/AXI_BFM/AXI_BFM_PKG.sv +1039 -0
- data/lib/axi/AXI_BFM/Data_C_BFM_PKG.sv +97 -0
- data/lib/axi/AXI_BFM/axi4_error_chk.sv +298 -0
- data/lib/axi/AXI_BFM/axi4_illegal_bfm_pkg.sv +607 -0
- data/lib/axi/AXI_BFM/axi_lite_master.sv +102 -0
- data/lib/axi/AXI_BFM/axi_lite_tb.sv +23 -0
- data/lib/axi/AXI_BFM/axi_master.sv +185 -0
- data/lib/axi/AXI_BFM/axi_mirror.sv +266 -0
- data/lib/axi/AXI_BFM/axi_mm_tb.sv +134 -0
- data/lib/axi/AXI_BFM/axi_slaver.sv.bak +340 -0
- data/lib/axi/AXI_BFM/axistreambfm.sv +117 -0
- data/lib/axi/AXI_Lite/axi4_to_lite.sv +36 -0
- data/lib/axi/AXI_Lite/axi_lite_configure.sv +356 -0
- data/lib/axi/AXI_Lite/axi_lite_configure_inf2.sv +365 -0
- data/lib/axi/AXI_Lite/axi_lite_configure_verb.sv.bck +370 -0
- data/lib/axi/AXI_Lite/axi_lite_interconnect_M2S.sv +437 -0
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- data/lib/axi/AXI_Lite/axi_lite_slaver_empty.sv +27 -0
- data/lib/axi/AXI_Lite/axil_direct.sv +52 -0
- data/lib/axi/AXI_Lite/common_configure_reg_interface/common_configure_reg_interface.sv +230 -0
- data/lib/axi/AXI_Lite/common_configure_reg_interface/common_configure_reg_interface.sv.bak +109 -0
- data/lib/axi/AXI_Lite/common_configure_reg_interface/jtag_to_axilite_wrapper.sv +56 -0
- data/lib/axi/AXI_Lite/gen_axi_lite_ctrl.sv +515 -0
- data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_C1.sv +369 -0
- data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_verb.sv +365 -0
- data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_verc.sv +401 -0
- data/lib/axi/AXI_Lite/wr_lite_to_axis.sv +141 -0
- data/lib/axi/AXI_Lite/wr_lite_to_axis.sv.bak +141 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S.sv +76 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_A1.sv +77 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_A2.sv +71 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_bind_tuser.sv +72 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_noaddr.sv +151 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_with_addr.sv +87 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_S2M.sv +65 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_auto.sv +50 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_with_info.sv +64 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_with_keep.sv.bak +64 -0
- data/lib/axi/AXI_stream/axi_stream_packet_fifo_with_info.sv.bak +49 -0
- data/lib/axi/AXI_stream/axi_stream_partition.sv +147 -0
- data/lib/axi/AXI_stream/axi_stream_partition_A1.sv +63 -0
- data/lib/axi/AXI_stream/axi_stream_planer.sv +51 -0
- data/lib/axi/AXI_stream/axi_stream_split_channel.rb +56 -0
- data/lib/axi/AXI_stream/axi_stream_split_channel.sv +149 -0
- data/lib/axi/AXI_stream/axi_streams_combin.sv +151 -0
- data/lib/axi/AXI_stream/axi_streams_combin_A1.sv +179 -0
- data/lib/axi/AXI_stream/axi_streams_scaler.sv +171 -0
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- data/lib/axi/AXI_stream/axis_append.sv +79 -0
- data/lib/axi/AXI_stream/axis_append_A1.sv +82 -0
- data/lib/axi/AXI_stream/axis_base_pipe.sv +184 -0
- data/lib/axi/AXI_stream/axis_combin_with_fifo.sv +69 -0
- data/lib/axi/AXI_stream/axis_connect_pipe.sv +86 -0
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- data/lib/axi/AXI_stream/axis_connect_pipe_left_shift.sv +64 -0
- data/lib/axi/AXI_stream/axis_connect_pipe_right_shift.sv +64 -0
- data/lib/axi/AXI_stream/axis_connect_pipe_right_shift_verb.sv +70 -0
- data/lib/axi/AXI_stream/axis_connect_pipe_with_info.sv +93 -0
- data/lib/axi/AXI_stream/axis_direct.sv +55 -0
- data/lib/axi/AXI_stream/axis_direct_A1.sv +81 -0
- data/lib/axi/AXI_stream/axis_filter.sv +38 -0
- data/lib/axi/AXI_stream/axis_full_to_data_c.sv +26 -0
- data/lib/axi/AXI_stream/axis_head_cut.sv +67 -0
- data/lib/axi/AXI_stream/axis_head_cut_verb.sv +60 -0
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- data/lib/axi/AXI_stream/axis_head_cut_verc.sv +245 -0
- data/lib/axi/AXI_stream/axis_inct_s2m_with_flag.sv +84 -0
- data/lib/axi/AXI_stream/axis_insert_copy.rb +59 -0
- data/lib/axi/AXI_stream/axis_insert_copy.sv +66 -0
- data/lib/axi/AXI_stream/axis_intc_M2S_with_addr_inf.sv +114 -0
- data/lib/axi/AXI_stream/axis_intc_S2M_with_addr_inf.sv +85 -0
- data/lib/axi/AXI_stream/axis_interconnect_S2M_pipe.sv +75 -0
- data/lib/axi/AXI_stream/axis_length_cut.sv +64 -0
- data/lib/axi/AXI_stream/axis_length_fill.sv +194 -0
- data/lib/axi/AXI_stream/axis_length_split.sv +86 -0
- data/lib/axi/AXI_stream/axis_length_split_with_addr.sv +127 -0
- data/lib/axi/AXI_stream/axis_length_split_writh_user.sv +87 -0
- data/lib/axi/AXI_stream/axis_link_trigger.sv +81 -0
- data/lib/axi/AXI_stream/axis_master_empty.sv +26 -0
- data/lib/axi/AXI_stream/axis_mirror_to_master.sv +126 -0
- data/lib/axi/AXI_stream/axis_mirrors.sv +60 -0
- data/lib/axi/AXI_stream/axis_orthogonal.sv +66 -0
- data/lib/axi/AXI_stream/axis_ram_buffer.sv +118 -0
- data/lib/axi/AXI_stream/axis_rom_contect.rb +97 -0
- data/lib/axi/AXI_stream/axis_rom_contect.sv +110 -0
- data/lib/axi/AXI_stream/axis_rom_contect_sim.rb +102 -0
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- data/lib/axi/AXI_stream/axis_slaver_empty.sv +22 -0
- data/lib/axi/AXI_stream/axis_slaver_pipe.sv +84 -0
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- data/lib/axi/AXI_stream/axis_split_channel_verb.rb +42 -0
- data/lib/axi/AXI_stream/axis_split_channel_verb.sv +62 -0
- data/lib/axi/AXI_stream/axis_to_axi4_or_lite.rb +127 -0
- data/lib/axi/AXI_stream/axis_to_axi4_or_lite.sv +153 -0
- data/lib/axi/AXI_stream/axis_to_data_inf.sv +34 -0
- data/lib/axi/AXI_stream/axis_to_lite_rd.sv +81 -0
- data/lib/axi/AXI_stream/axis_to_lite_wr.sv +71 -0
- data/lib/axi/AXI_stream/axis_uncompress.sv +147 -0
- data/lib/axi/AXI_stream/axis_uncompress_A1.sv +150 -0
- data/lib/axi/AXI_stream/axis_uncompress_verb.rb +32 -0
- data/lib/axi/AXI_stream/axis_uncompress_verb.sv +54 -0
- data/lib/axi/AXI_stream/axis_valve.sv +29 -0
- data/lib/axi/AXI_stream/axis_valve_with_pipe.sv +76 -0
- data/lib/axi/AXI_stream/axis_vector_master_empty.rb +11 -0
- data/lib/axi/AXI_stream/axis_vector_master_empty.sv +35 -0
- data/lib/axi/AXI_stream/axis_vector_slaver_empty.rb +11 -0
- data/lib/axi/AXI_stream/axis_vector_slaver_empty.sv +35 -0
- data/lib/axi/AXI_stream/check_stream_crc.sv +28 -0
- data/lib/axi/AXI_stream/data_c_to_axis_full.sv +23 -0
- data/lib/axi/AXI_stream/data_to_axis_inf.sv +103 -0
- data/lib/axi/AXI_stream/data_to_axis_inf_A1.sv +28 -0
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- data/lib/axi/AXI_stream/data_width/axis_width_combin_A1.sv +220 -0
- data/lib/axi/AXI_stream/data_width/axis_width_convert.sv +49 -0
- data/lib/axi/AXI_stream/data_width/axis_width_destruct.sv +82 -0
- data/lib/axi/AXI_stream/data_width/axis_width_destruct_A1.sv +86 -0
- data/lib/axi/AXI_stream/ex_status/axis_ex_status.sv +97 -0
- data/lib/axi/AXI_stream/gen_big_field_table.sv +170 -0
- data/lib/axi/AXI_stream/gen_common_frame_table.sv +382 -0
- data/lib/axi/AXI_stream/gen_common_frame_table_bind_tuser.sv +428 -0
- data/lib/axi/AXI_stream/gen_origin_axis.sv +116 -0
- data/lib/axi/AXI_stream/gen_origin_axis_A1.sv +129 -0
- data/lib/axi/AXI_stream/gen_origin_axis_A2.sv +162 -0
- data/lib/axi/AXI_stream/gen_simple_axis.sv +164 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_long_fifo.sv +132 -0
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- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo.sv +125 -0
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- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1E.sv +198 -0
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- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_B1.sv +82 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_mirror.sv +44 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_verb.sv +58 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_long_cache.sv +55 -0
- data/lib/axi/AXI_stream/stream_crc.sv +67 -0
- data/lib/axi/AXI_stream/vcs_axis_comptable.sv +73 -0
- data/lib/axi/LICENSE +504 -0
- data/lib/axi/ReadME.md +6 -0
- data/lib/axi/SIM/tb_axi4_partition_20201105.sv +115 -0
- data/lib/axi/SIM/tb_axis_bfm_0504.sv +61 -0
- data/lib/axi/SIM/tb_axis_partitiom_0929.sv +102 -0
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- data/lib/axi/SIM/tb_axis_to_axi4_0925.sv +107 -0
- data/lib/axi/SIM/tb_data_c_m2s_inf_20200114.sv +222 -0
- data/lib/axi/SIM/tb_data_c_m2s_inf_20201103.sv +245 -0
- data/lib/axi/SIM/tb_data_c_pipe_inf_20180417.sv +114 -0
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- data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_gen_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_gen_without_resp_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_wr_burst_track_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_wr_interconnect_M2S_A1_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_wr_interconnect_M2S_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_wr_mix_interconnect_M2S_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/axi4_wr_packet_fifo_sdl.rb +11 -0
- data/lib/tdl/SDL/axi4/axi4_wr_pipe_sdl.rb +9 -0
- data/lib/tdl/SDL/axi4/axi4_wr_pipe_verb_sdl.rb +9 -0
- data/lib/tdl/SDL/axi4/axi_stream_add_addr_len_sdl.rb +11 -0
- data/lib/tdl/SDL/axi4/axi_stream_to_axi4_wr_sdl.rb +9 -0
- data/lib/tdl/SDL/axi4/data_combin_sdl.rb +20 -0
- data/lib/tdl/SDL/axi4/data_destruct_sdl.rb +19 -0
- data/lib/tdl/SDL/axi4/feed_check_sdl.rb +18 -0
- data/lib/tdl/SDL/axi4/full_axi4_to_axis_partition_wr_rd_sdl.rb +11 -0
- data/lib/tdl/SDL/axi4/full_axi4_to_axis_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/id_record_sdl.rb +19 -0
- data/lib/tdl/SDL/axi4/idata_pool_axi4_sdl.rb +18 -0
- data/lib/tdl/SDL/axi4/odata_pool_axi4_A1_sdl.rb +13 -0
- data/lib/tdl/SDL/axi4/odata_pool_axi4_A2_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/odata_pool_axi4_sdl.rb +19 -0
- data/lib/tdl/SDL/axi4/odd_width_convert_sdl.rb +19 -0
- data/lib/tdl/SDL/axi4/odd_width_convert_verb_sdl.rb +19 -0
- data/lib/tdl/SDL/axi4/simple_data_pipe_sdl.rb +16 -0
- data/lib/tdl/SDL/axi4/simple_data_pipe_slaver_sdl.rb +16 -0
- data/lib/tdl/SDL/axi4/vcs_axi4_array_comptable.rb +9 -0
- data/lib/tdl/SDL/axi4/vcs_axi4_array_comptable_sdl.rb +10 -0
- data/lib/tdl/SDL/axi4/vcs_axi4_comptable.rb +8 -0
- data/lib/tdl/SDL/axi4/vcs_axi4_comptable_sdl.rb +9 -0
- data/lib/tdl/SDL/axi4/width_combin_sdl.rb +20 -0
- data/lib/tdl/SDL/axi4/width_convert_sdl.rb +20 -0
- data/lib/tdl/SDL/axi4/width_convert_verb_sdl.rb +20 -0
- data/lib/tdl/SDL/axi4/width_destruct_A1_sdl.rb +22 -0
- data/lib/tdl/SDL/axi4/width_destruct_sdl.rb +19 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_35bit_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_36_71bit_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_72_95bit_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_72_95bit_with_keep_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_96_143bit_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_B1_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_mirror_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_verb_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_A1_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_A2_sdl.rb +13 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_bind_tuser_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_noaddr_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_with_addr_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_S2M_auto_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_S2M_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axi_stream_long_cache_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axi_stream_long_fifo_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axi_stream_long_fifo_verb_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_B1E_sdl.rb +16 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_B1_sdl.rb +14 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_verb_sdl.rb +13 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_with_info_sdl.rb +13 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_long_fifo_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axi_stream_partition_A1_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axi_stream_partition_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axi_stream_wide_fifo_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axi_streams_combin_A1_sdl.rb +15 -0
- data/lib/tdl/SDL/axistream/axi_streams_combin_sdl.rb +16 -0
- data/lib/tdl/SDL/axistream/axi_streams_scaler_A1_sdl.rb +14 -0
- data/lib/tdl/SDL/axistream/axi_streams_scaler_sdl.rb +15 -0
- data/lib/tdl/SDL/axistream/axis_append_A1_sdl.rb +18 -0
- data/lib/tdl/SDL/axistream/axis_append_sdl.rb +17 -0
- data/lib/tdl/SDL/axistream/axis_base_pipe_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_combin_with_fifo_sdl.rb +14 -0
- data/lib/tdl/SDL/axistream/axis_connect_pipe_right_shift_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_connect_pipe_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_connect_pipe_with_info_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axis_direct_A1_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axis_direct_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_ex_status_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axis_filter_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_full_to_data_c_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_head_cut_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_inct_s2m_with_flag_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axis_intc_M2S_with_addr_inf_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axis_intc_S2M_with_addr_inf_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axis_interconnect_S2M_pipe_sdl.rb +15 -0
- data/lib/tdl/SDL/axistream/axis_length_cut_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_length_fill_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_length_split_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_length_split_with_addr_sdl.rb +13 -0
- data/lib/tdl/SDL/axistream/axis_length_split_writh_user_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_link_trigger_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axis_master_empty_sdl.rb +8 -0
- data/lib/tdl/SDL/axistream/axis_mirror_to_master_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_mirrors_sdl.rb +14 -0
- data/lib/tdl/SDL/axistream/axis_orthogonal_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_pkt_fifo_filter_keep_A1_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_pkt_fifo_filter_keep_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_ram_buffer_sdl.rb +13 -0
- data/lib/tdl/SDL/axistream/axis_slaver_empty_sdl.rb +8 -0
- data/lib/tdl/SDL/axistream/axis_slaver_pipe_A1_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_slaver_pipe_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_slaver_vector_empty_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_to_data_inf_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_to_lite_rd_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axis_to_lite_wr_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_uncompress_A1_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/axis_uncompress_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axis_valve_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/axis_valve_with_pipe_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/axis_width_combin_A1_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_width_combin_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_width_convert_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_width_destruct_A1_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/axis_width_destruct_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/check_stream_crc_sdl.rb +8 -0
- data/lib/tdl/SDL/axistream/data_c_to_axis_full_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/data_to_axis_inf_A1_sdl.rb +10 -0
- data/lib/tdl/SDL/axistream/data_to_axis_inf_sdl.rb +11 -0
- data/lib/tdl/SDL/axistream/gen_big_field_table_sdl.rb +14 -0
- data/lib/tdl/SDL/axistream/gen_common_frame_table_sdl.rb +60 -0
- data/lib/tdl/SDL/axistream/gen_origin_axis_A1_sdl.rb +13 -0
- data/lib/tdl/SDL/axistream/gen_origin_axis_sdl.rb +12 -0
- data/lib/tdl/SDL/axistream/gen_simple_axis_sdl.rb +13 -0
- data/lib/tdl/SDL/axistream/parse_big_field_table_A1_sdl.rb +17 -0
- data/lib/tdl/SDL/axistream/parse_big_field_table_A2_sdl.rb +17 -0
- data/lib/tdl/SDL/axistream/parse_big_field_table_sdl.rb +17 -0
- data/lib/tdl/SDL/axistream/stream_crc_sdl.rb +9 -0
- data/lib/tdl/SDL/axistream/vcs_axis_comptable.rb +16 -0
- data/lib/tdl/SDL/axistream/vcs_axis_comptable_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_bind_sdl.rb +10 -0
- data/lib/tdl/SDL/data_inf_c/data_c_cache_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_c_direct_mirror_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_c_direct_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_c_intc_M2S_force_robin_sdl.rb +10 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_force_vld_bind_data_sdl.rb +13 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_force_vld_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_A1_sdl.rb +10 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_right_shift_sdl.rb +13 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_C1_sdl.rb +14 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_C1_with_id_sdl.rb +16 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_sdl.rb +13 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_with_addr_sdl.rb +13 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_with_id_sdl.rb +15 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_latency_sdl.rb +10 -0
- data/lib/tdl/SDL/data_inf_c/data_c_scaler_A1_sdl.rb +16 -0
- data/lib/tdl/SDL/data_inf_c/data_c_scaler_sdl.rb +15 -0
- data/lib/tdl/SDL/data_inf_c/data_c_tmp_cache_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_condition_mirror_sdl.rb +13 -0
- data/lib/tdl/SDL/data_inf_c/data_condition_valve_sdl.rb +13 -0
- data/lib/tdl/SDL/data_inf_c/data_connect_pipe_inf_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_connect_pipe_sdl.rb +17 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_A2B_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_B2A_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_M2S_with_addr_and_id_sdl.rb +17 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_M2S_with_id_sdl.rb +15 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_A1_sdl.rb +13 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_sdl.rb +12 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_with_lazy_sdl.rb +15 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_interconnect_M2S_sdl.rb +12 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_pipe_condition_sdl.rb +10 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_A1.rb +12 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_A1_sdl.rb +14 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_sdl.rb +13 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_cross_clk_sdl.rb +9 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_force_addr_with_id_sdl.rb +19 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_prio_sdl.rb +14 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_prio_with_id_sdl.rb +17 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_interconnect_M2S_noaddr_sdl.rb +14 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_interconnect_M2S_with_id_noaddr_sdl.rb +17 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_planer_A1_sdl.rb +15 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_planer_sdl.rb +14 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_ticktock_sdl.rb +18 -0
- data/lib/tdl/SDL/data_inf_c/data_intc_M2S_force_robin_sdl.rb +10 -0
- data/lib/tdl/SDL/data_inf_c/data_mirrors_sdl.rb +14 -0
- data/lib/tdl/SDL/data_inf_c/data_pair_map_A1_sdl.rb +16 -0
- data/lib/tdl/SDL/data_inf_c/data_pair_map_A2_sdl.rb +19 -0
- data/lib/tdl/SDL/data_inf_c/data_pair_map_sdl.rb +14 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_A1_sdl.rb +19 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_sdl.rb +17 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_verb_sdl.rb +16 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_A1_sdl.rb +19 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_sdl.rb +16 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_verb_sdl.rb +15 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_sdl.rb +23 -0
- data/lib/tdl/SDL/data_inf_c/data_streams_combin_A1_sdl.rb +20 -0
- data/lib/tdl/SDL/data_inf_c/data_streams_combin_sdl.rb +20 -0
- data/lib/tdl/SDL/data_inf_c/data_streams_scaler_sdl.rb +19 -0
- data/lib/tdl/SDL/data_inf_c/data_uncompress_sdl.rb +11 -0
- data/lib/tdl/SDL/data_inf_c/data_valve_sdl.rb +10 -0
- data/lib/tdl/SDL/data_inf_c/datainf_c_master_empty_sdl.rb +8 -0
- data/lib/tdl/SDL/data_inf_c/datainf_c_slaver_empty_sdl.rb +8 -0
- data/lib/tdl/SDL/data_inf_c/datainf_master_empty_sdl.rb +8 -0
- data/lib/tdl/SDL/data_inf_c/datainf_slaver_empty_sdl.rb +8 -0
- data/lib/tdl/SDL/data_inf_c/latency_sdl.rb +8 -0
- data/lib/tdl/SDL/data_inf_c/next_prio_sdl.rb +12 -0
- data/lib/tdl/SDL/data_inf_c/part_data_pair_map_sdl.rb +19 -0
- data/lib/tdl/SDL/data_inf_c/trigger_data_inf_c_A1_sdl.rb +11 -0
- data/lib/tdl/SDL/data_inf_c/trigger_data_inf_c_sdl.rb +11 -0
- data/lib/tdl/SDL/data_inf_c/trigger_ready_ctrl_sdl.rb +12 -0
- data/lib/tdl/SDL/data_inf_c/vcs_data_c_comptable.rb +8 -0
- data/lib/tdl/SDL/data_inf_c/vcs_data_c_comptable_sdl.rb +9 -0
- data/lib/tdl/SDL/fifo/common_fifo_sdl.rb +20 -0
- data/lib/tdl/SDL/fifo/common_stack_sdl.rb +14 -0
- data/lib/tdl/SDL/fifo/independent_clock_fifo_a1_sdl.rb +21 -0
- data/lib/tdl/SDL/fifo/independent_clock_fifo_sdl.rb +20 -0
- data/lib/tdl/SDL/fifo/independent_stack_sdl.rb +18 -0
- data/lib/tdl/SDL/path_lib.rb +6 -0
- data/lib/tdl/VideoInf/simple_video_gen.rb +46 -0
- data/lib/tdl/VideoInf/video_from_axi4.rb +108 -0
- data/lib/tdl/VideoInf/video_lib.rb +8 -0
- data/lib/tdl/VideoInf/video_stream_2_axi_stream.rb +67 -0
- data/lib/tdl/VideoInf/video_to_axi4.rb +75 -0
- data/lib/tdl/auto_script/auto_gen_tdl.rb +49 -0
- data/lib/tdl/auto_script/autogensdl.rb +289 -0
- data/lib/tdl/auto_script/autogentdl_a2.rb +452 -0
- data/lib/tdl/auto_script/import_hdl.rb +35 -0
- data/lib/tdl/auto_script/import_sdl.rb +26 -0
- data/lib/tdl/auto_script/test_autogensdl.rb +73 -0
- data/lib/tdl/auto_script/tmp.rb +6 -0
- data/lib/tdl/auto_script/tmp/hdl_test_sdl.rb +12 -0
- data/lib/tdl/axi4/axi4_combin_wr_rd_batch_auto.rb +79 -0
- data/lib/tdl/axi4/axi4_direct.rb +36 -0
- data/lib/tdl/axi4/axi4_direct_A1_auto.rb +137 -0
- data/lib/tdl/axi4/axi4_direct_auto.rb +79 -0
- data/lib/tdl/axi4/axi4_direct_verb_auto.rb +71 -0
- data/lib/tdl/axi4/axi4_interconnect_verb.rb +323 -0
- data/lib/tdl/axi4/axi4_lib.rb +9 -0
- data/lib/tdl/axi4/axi4_long_to_axi4_wide_A1_auto.rb +79 -0
- data/lib/tdl/axi4/axi4_long_to_axi4_wide_auto.rb +71 -0
- data/lib/tdl/axi4/axi4_long_to_axi4_wide_verb_auto.rb +86 -0
- data/lib/tdl/axi4/axi4_packet_fifo_auto.rb +155 -0
- data/lib/tdl/axi4/axi4_pipe_auto.rb +127 -0
- data/lib/tdl/axi4/axi4_pipe_verb_auto.rb +127 -0
- data/lib/tdl/axi4/axi4_rd_auxiliary_gen_auto.rb +71 -0
- data/lib/tdl/axi4/axi4_wr_auxiliary_gen_without_resp_auto.rb +78 -0
- data/lib/tdl/axi4/axis_to_axi4_wr_auto.rb +85 -0
- data/lib/tdl/axi4/bak/__axi4_wr_auxiliary_gen_without_resp.rb +175 -0
- data/lib/tdl/axi4/bak/axi4_combin_wr_rd_batch_auto.rb +153 -0
- data/lib/tdl/axi4/bak/axi4_data_convert.rb +74 -0
- data/lib/tdl/axi4/bak/axi4_direct_auto.rb +153 -0
- data/lib/tdl/axi4/bak/axi4_direct_verb_auto.rb +126 -0
- data/lib/tdl/axi4/bak/axi4_interconnect.rb.bak +91 -0
- data/lib/tdl/axi4/bak/axi4_long_to_axi4_wide_A1_auto.rb +153 -0
- data/lib/tdl/axi4/bak/axi4_long_to_axi4_wide_auto.rb +126 -0
- data/lib/tdl/axi4/bak/axi4_long_to_axi4_wide_verb_auto.rb +179 -0
- data/lib/tdl/axi4/bak/axi4_packet_fifo.rb.bak +75 -0
- data/lib/tdl/axi4/bak/axi4_packet_fifo_auto.rb +259 -0
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- data/lib/tdl/examples/11_test_unit/dve.tcl +64 -0
- data/lib/tdl/examples/11_test_unit/exp_test_unit.rb +58 -0
- data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +35 -0
- data/lib/tdl/examples/11_test_unit/exp_test_unit_constraints.xdc +25 -0
- data/lib/tdl/examples/11_test_unit/modules/sub_md0.rb +23 -0
- data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +41 -0
- data/lib/tdl/examples/11_test_unit/modules/sub_md1.rb +25 -0
- data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv +41 -0
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +28 -0
- data/lib/tdl/examples/11_test_unit/tu0.sv +38 -0
- data/lib/tdl/examples/11_test_unit/tu1.sv +28 -0
- data/lib/tdl/examples/1_define_module/example1.rb +39 -0
- data/lib/tdl/examples/1_define_module/exmple_md.sv +50 -0
- data/lib/tdl/examples/2_hdl_class/always_comb.rb +99 -0
- data/lib/tdl/examples/2_hdl_class/always_ff.rb +143 -0
- data/lib/tdl/examples/2_hdl_class/case.rb +93 -0
- data/lib/tdl/examples/2_hdl_class/foreach.rb +21 -0
- data/lib/tdl/examples/2_hdl_class/function.rb +34 -0
- data/lib/tdl/examples/2_hdl_class/generate.rb +62 -0
- data/lib/tdl/examples/2_hdl_class/module_def.rb +33 -0
- data/lib/tdl/examples/2_hdl_class/module_head_import_package.rb +36 -0
- data/lib/tdl/examples/2_hdl_class/module_instance_test.rb +13 -0
- data/lib/tdl/examples/2_hdl_class/package.rb +29 -0
- data/lib/tdl/examples/2_hdl_class/package2.rb +21 -0
- data/lib/tdl/examples/2_hdl_class/simple_assign.rb +39 -0
- data/lib/tdl/examples/2_hdl_class/state_case.rb +65 -0
- data/lib/tdl/examples/2_hdl_class/struct.rb +25 -0
- data/lib/tdl/examples/2_hdl_class/struct_function.rb +28 -0
- data/lib/tdl/examples/2_hdl_class/test_axi4_M2S.rb +16 -0
- data/lib/tdl/examples/2_hdl_class/test_initial_assert.rb +11 -0
- data/lib/tdl/examples/2_hdl_class/test_inst_sugar.rb +28 -0
- data/lib/tdl/examples/2_hdl_class/test_module_port.rb +47 -0
- data/lib/tdl/examples/2_hdl_class/test_module_var.rb +18 -0
- data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv +108 -0
- data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +35 -0
- data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv +105 -0
- data/lib/tdl/examples/2_hdl_class/tmp/head_pkg_module.sv +42 -0
- data/lib/tdl/examples/2_hdl_class/tmp/init_module.sv +110 -0
- data/lib/tdl/examples/2_hdl_class/tmp/module_instance_test.sv +31 -0
- data/lib/tdl/examples/2_hdl_class/tmp/port_module.sv +99 -0
- data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv +27 -0
- data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv +78 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_axi4_M2S.sv +30 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_foreach.sv +34 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_function.sv +52 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_initial_assert.sv +31 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_inst_sugar.sv +42 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +36 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_port.sv +33 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +35 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +38 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_package2.sv +36 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_struct.sv +38 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_struct_function.sv +44 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +27 -0
- data/lib/tdl/examples/2_hdl_class/tmp/text_generate.sv +54 -0
- data/lib/tdl/examples/2_hdl_class/vcs_string.rb +5 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/hdl_test.sv +13 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/main.rb +26 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/main_md.sv +42 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/sdl_md.sv +30 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/sdl_test.rb +9 -0
- data/lib/tdl/examples/4_generate/example.rb +38 -0
- data/lib/tdl/examples/4_generate/test_generate.sv +59 -0
- data/lib/tdl/examples/5_logic_combin/login_combin.rb +22 -0
- data/lib/tdl/examples/5_logic_combin/test_logic_combin.sv +36 -0
- data/lib/tdl/examples/6_module_with_interface/example.rb +48 -0
- data/lib/tdl/examples/6_module_with_interface/example_interface.sv +40 -0
- data/lib/tdl/examples/6_module_with_interface/inf_collect.rb +54 -0
- data/lib/tdl/examples/6_module_with_interface/inf_collect.sv +63 -0
- data/lib/tdl/examples/7_module_with_package/body_package.rb +3 -0
- data/lib/tdl/examples/7_module_with_package/body_package.sv +25 -0
- data/lib/tdl/examples/7_module_with_package/example_pkg.rb +20 -0
- data/lib/tdl/examples/7_module_with_package/example_pkg.sv +35 -0
- data/lib/tdl/examples/7_module_with_package/head_package.rb +8 -0
- data/lib/tdl/examples/7_module_with_package/head_package.sv +29 -0
- data/lib/tdl/examples/8_top_module/dve.tcl +64 -0
- data/lib/tdl/examples/8_top_module/example.rb +8 -0
- data/lib/tdl/examples/8_top_module/pins.yml +7 -0
- data/lib/tdl/examples/8_top_module/tb_test_top.sv +29 -0
- data/lib/tdl/examples/8_top_module/test_top.sv +28 -0
- data/lib/tdl/examples/8_top_module/test_top_constraints.xdc +37 -0
- data/lib/tdl/examples/9_itegration/A_itgt/a_test_md.sv +29 -0
- data/lib/tdl/examples/9_itegration/A_itgt/a_test_module.rb +6 -0
- data/lib/tdl/examples/9_itegration/A_itgt/itgt_module_a_block.rb +34 -0
- data/lib/tdl/examples/9_itegration/clock_manage/itgt_module_clock_manage.rb +33 -0
- data/lib/tdl/examples/9_itegration/clock_manage/simple_clock.rb +7 -0
- data/lib/tdl/examples/9_itegration/clock_manage/simple_clock.sv +29 -0
- data/lib/tdl/examples/9_itegration/dve.tcl +64 -0
- data/lib/tdl/examples/9_itegration/pins.yml +4 -0
- data/lib/tdl/examples/9_itegration/tb_test_top.sv +29 -0
- data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +29 -0
- data/lib/tdl/examples/9_itegration/test_top.sv +40 -0
- data/lib/tdl/examples/9_itegration/test_top_constraints.xdc +29 -0
- data/lib/tdl/examples/9_itegration/test_tttop.sv +40 -0
- data/lib/tdl/examples/9_itegration/test_tttop_constraints.xdc +29 -0
- data/lib/tdl/examples/9_itegration/top.rb +11 -0
- data/lib/tdl/examples/readme.md +31 -0
- data/lib/tdl/exlib/common_cfg_reg_inf.rb +139 -0
- data/lib/tdl/exlib/constraints.rb +286 -0
- data/lib/tdl/exlib/constraints_verb.rb +304 -0
- data/lib/tdl/exlib/dve_tcl.rb +162 -0
- data/lib/tdl/exlib/element_class_vars.rb +106 -0
- data/lib/tdl/exlib/global_param.rb +108 -0
- data/lib/tdl/exlib/integral_test/bak/integral_test.rb +206 -0
- data/lib/tdl/exlib/integral_test/clock_itest.rb +28 -0
- data/lib/tdl/exlib/integral_test/diff_clock_itest.rb +30 -0
- data/lib/tdl/exlib/integral_test/io_itest.rb +41 -0
- data/lib/tdl/exlib/integral_test/reset_itest.rb +31 -0
- data/lib/tdl/exlib/integral_test/simple_logic_itest.rb +19 -0
- data/lib/tdl/exlib/itegration.rb +307 -0
- data/lib/tdl/exlib/itegration_verb.rb +913 -0
- data/lib/tdl/exlib/parse_argv.rb +43 -0
- data/lib/tdl/exlib/sdlmodule_sim.bak.rb +375 -0
- data/lib/tdl/exlib/test_point.rb +287 -0
- data/lib/tdl/global_scan.rb +134 -0
- data/lib/tdl/rebuild_ele/axi4.rb +141 -0
- data/lib/tdl/rebuild_ele/axi_lite.rb +56 -0
- data/lib/tdl/rebuild_ele/axi_stream.rb +121 -0
- data/lib/tdl/rebuild_ele/cm_ram_inf.sv +105 -0
- data/lib/tdl/rebuild_ele/cm_ram_inf_define.rb +44 -0
- data/lib/tdl/rebuild_ele/data_inf.rb +27 -0
- data/lib/tdl/rebuild_ele/data_inf_c.rb +83 -0
- data/lib/tdl/rebuild_ele/ele_base.rb +822 -0
- data/lib/tdl/rebuild_ele/readme.md +1 -0
- data/lib/tdl/sdlimplement/resource.yml +154 -0
- data/lib/tdl/sdlimplement/sdl_impl_module.rb +391 -0
- data/lib/tdl/sdlimplement/sdl_impl_param.rb +26 -0
- data/lib/tdl/sdlimplement/test.rb +64 -0
- data/lib/tdl/sdlmodule/bak/sdlmodule_varible_ex.rb +120 -0
- data/lib/tdl/sdlmodule/generator_block_module.rb +84 -0
- data/lib/tdl/sdlmodule/sdlmodule.rb +407 -0
- data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb +333 -0
- data/lib/tdl/sdlmodule/sdlmodule_draw.rb +272 -0
- data/lib/tdl/sdlmodule/sdlmodule_head_logo.txt +10 -0
- data/lib/tdl/sdlmodule/sdlmodule_instance.rb +623 -0
- data/lib/tdl/sdlmodule/sdlmodule_port_define.rb +374 -0
- data/lib/tdl/sdlmodule/sdlmodule_varible.rb +160 -0
- data/lib/tdl/sdlmodule/sdlmodule_vcs_comptable.rb +140 -0
- data/lib/tdl/sdlmodule/techbench_module.rb +14 -0
- data/lib/tdl/sdlmodule/test_unit_module.rb +138 -0
- data/lib/tdl/sdlmodule/top_module.rb +543 -0
- data/lib/tdl/tdl.rb +265 -0
- data/lib/tdl/tdlerror/tdlerror.rb +8 -0
- data/lib/tdl/testunit/test_all.rb +4 -0
- data/lib/tdl/testunit/test_array_chain.rb +89 -0
- data/lib/tdl/testunit/test_tmp.rb +47 -0
- metadata +1301 -0
@@ -0,0 +1,150 @@
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module ClassHDL
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class SdlPackage < SdlModule
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def macro_def
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''
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end
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def build_params(ex_str="")
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"Draw Parameters of sv module"
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str = []
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max_len = 0
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@port_params.each do |k,v|
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if v.port_length > max_len
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max_len = v.port_length;
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end
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end
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@port_params.each do |k,v|
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str << v.inst_port(max_len-v.port_length)+";"
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end
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unless ex_str.empty?
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head_tap = '//------>> EX PARAMETER <<-------------------'+"\n"
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end_tap = "\n//------<< EX PARAMETER >>-------------------"+"\n"
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else
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head_tap = ""
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end_tap = ""
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end
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if str.empty?
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if ex_str.empty?
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return ""
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else
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# ex_str.gsub!(/,\s*$/m,"")
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return head_tap + ex_str + end_tap
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end
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else
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# if (ex_str !~ /,\s*$/m)
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# ex_str = ex_str + ",\n" unless ex_str.empty?
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# end
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head_tap + ex_str + end_tap + str.join("\n")
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end
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end
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def build_module(ex_param: "",ex_port: "",ex_up_code: "",ex_down_code: "")
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# Tdl.Puts pagination(module_name)
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Tdl.Build_SdlModule_Puts(module_name)
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ex_param = ex_param.to_s unless ex_param
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ex_port = ex_port.to_s unless ex_port
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ex_up_code = ex_up_code.to_s unless ex_up_code
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ex_down_code = ex_down_code.to_s unless ex_down_code
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# gen_auto_method # auto generate class method for interface
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# draw = Tdl.inst + Tdl.draw
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instance_draw_str = instance_draw # It must run before vars_define_inst,because some signals define when inst
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vars_exec_inst_str = vars_exec_inst # It must run before vars_define_inst,because some signals define when vars exec
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post_str = post_inst_stack_call()
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unless post_str.strip.empty?
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post_str = pagination("ROOT REF") + post_str
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end
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draw = pagination("define") + vars_define_inst + pagination("instance") + instance_draw_str + pagination("expression") + vars_exec_inst_str + post_str
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unless ex_up_code.empty?
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ex_up_code = "\n//------>> EX CODE <<-------------------\n" + ex_up_code + "//------<< EX CODE >>-------------------\n"
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end
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unless ex_down_code.empty?
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ex_down_code = "//------>> EX CODE <<-------------------\n" + ex_down_code + "//------<< EX CODE >>-------------------\n"
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end
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# str = module_head+"module #{@module_name}" + build_params(ex_param) + build_ports(ex_port) + ex_up_code + gen_lite_str() + draw + ex_down_code + "\nendmodule\n"
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# unless GlobalParam.sim
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module_name_str = @module_name
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# else
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# module_name_str = @module_name+"_sim"
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# end
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str = module_head+"package #{module_name_str};\n" + build_params(ex_param) + ex_up_code + draw + ex_down_code + "\nendpackage:#{module_name_str}\n" + add_sub_module_file_paths
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create_vivado_tcl if @create_tcl
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create_constraints_file if @create_sdc
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return str
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end
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end
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# class ReqPakcgeLine
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# def initialize(sdlm)
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# @sdlm
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# end
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# def method_missing(method,*arg,&block)
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# _var = @sdlm.instance_variable_get("@_import_packages_")
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# @sdlm.instance_variable_set("@_import_packages_",[]) unless _var
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# end
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# end
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end
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class TdlPackage
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# return ClassHDL::AnonyModule.new
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def self.method_missing(method,*args,&block)
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sdlm = ClassHDL::SdlPackage.new(name: method,out_sv_path: args[0])
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sdlm.instance_exec(&block)
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sdlm.gen_sv_module
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end
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end
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class SdlModule
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def require_package(tdl_package_str,ex_code=true)
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# puts tdl_package
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if SdlModule.exist_module?(tdl_package_str) && SdlModule.call_module(tdl_package_str).instance_of?(ClassHDL::SdlPackage)
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tdl_package = SdlModule.call_module(tdl_package_str)
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@_import_packages_ ||= []
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@_import_packages_ << tdl_package
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if ex_code
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self.ex_up_code ||= ''
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self.ex_up_code += "import #{tdl_package.module_name}::*;\n"
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end
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else
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raise TdlError.new("Dont have packge #{tdl_package_str}")
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end
|
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define_singleton_method(tdl_package_str) do
|
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SdlModule.call_module(tdl_package_str)
|
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end
|
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|
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## 替换掉 package 里面 DefStruct 指向的 sdlmodule
|
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metac = tdl_package.instance_variable_get("@_struct_meta_collect_") || []
|
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metac.each do |e|
|
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e.sdlm = self
|
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end
|
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end
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end
|
@@ -0,0 +1,73 @@
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2
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module HDLClass
|
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class ImplicitInstParam
|
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attr_accessor :local,:vcs_string
|
5
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def initialize(sdlm)
|
6
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@sdlm = sdlm
|
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@type = nil
|
8
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+
end
|
9
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def [](num)
|
11
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@type = "[#{num}-1:0]"
|
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self
|
13
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end
|
14
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|
15
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def real
|
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@type = 'real'
|
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return self
|
18
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end
|
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|
20
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def int
|
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@type = 'int'
|
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return self
|
23
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+
end
|
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|
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# def -(name)
|
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# @sdlm.Parameter(name,value=0,type:nil,show:true)
|
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# end
|
28
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|
29
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def method_missing(name,*args,&block)
|
30
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if name !~ /\w+/
|
31
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raise TdlError.new("cont define parameter name #{name}")
|
32
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+
end
|
33
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+
if args.any?
|
34
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+
unless local
|
35
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+
relp = @sdlm.Parameter(name,args[0],type:@type,show:true)
|
36
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+
else
|
37
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+
relp = @sdlm.Def.parameter(name: name,value: args[0],local:true,type:@type)
|
38
|
+
end
|
39
|
+
if vcs_string
|
40
|
+
relp.vcs_string = vcs_string
|
41
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+
end
|
42
|
+
relp
|
43
|
+
else
|
44
|
+
@sdlm.public_send(name)
|
45
|
+
end
|
46
|
+
end
|
47
|
+
end
|
48
|
+
end
|
49
|
+
|
50
|
+
class SdlModule
|
51
|
+
|
52
|
+
|
53
|
+
def parameter
|
54
|
+
return HDLClass::ImplicitInstParam.new(self)
|
55
|
+
end
|
56
|
+
|
57
|
+
alias_method :param,:parameter
|
58
|
+
|
59
|
+
def localparam
|
60
|
+
a = HDLClass::ImplicitInstParam.new(self)
|
61
|
+
a.local = true
|
62
|
+
return a
|
63
|
+
end
|
64
|
+
|
65
|
+
def vcs_string(total=64,local=false)
|
66
|
+
a = HDLClass::ImplicitInstParam.new(self)
|
67
|
+
self.macro_add_vcs
|
68
|
+
a.vcs_string = total
|
69
|
+
a.local = local
|
70
|
+
return a
|
71
|
+
end
|
72
|
+
|
73
|
+
end
|
@@ -0,0 +1,31 @@
|
|
1
|
+
module ClassHDL
|
2
|
+
|
3
|
+
module RandomNum
|
4
|
+
def precent_true
|
5
|
+
return "($urandom_range(0,99) <= #{self.to_s})".to_nq
|
6
|
+
end
|
7
|
+
|
8
|
+
def precent_false
|
9
|
+
return "($urandom_range(1,100) > #{self.to_s})".to_nq
|
10
|
+
end
|
11
|
+
end
|
12
|
+
|
13
|
+
end
|
14
|
+
|
15
|
+
class SdlModule
|
16
|
+
def urandom_range(a,b)
|
17
|
+
return "$urandom_range(#{a},#{b})".to_nq
|
18
|
+
end
|
19
|
+
end
|
20
|
+
|
21
|
+
class Numeric
|
22
|
+
include ClassHDL::RandomNum
|
23
|
+
end
|
24
|
+
|
25
|
+
class Parameter
|
26
|
+
include ClassHDL::RandomNum
|
27
|
+
end
|
28
|
+
|
29
|
+
class Logic
|
30
|
+
include ClassHDL::RandomNum
|
31
|
+
end
|
@@ -0,0 +1,653 @@
|
|
1
|
+
"""
|
2
|
+
Block{
|
3
|
+
Block{
|
4
|
+
OpertorChain
|
5
|
+
OpertorChain
|
6
|
+
}
|
7
|
+
OpertorChain
|
8
|
+
OpertorChain
|
9
|
+
}
|
10
|
+
"""
|
11
|
+
|
12
|
+
## 在/logic/redefine_operator.rb 里引用
|
13
|
+
module ClassHDL
|
14
|
+
|
15
|
+
class GlobalVar
|
16
|
+
@@curr_assign_block
|
17
|
+
@@AssignDefOpertor_included_class = []
|
18
|
+
|
19
|
+
def self.ass_defp_class
|
20
|
+
@@AssignDefOpertor_included_class
|
21
|
+
end
|
22
|
+
end
|
23
|
+
end
|
24
|
+
## 直接简单赋值 block语句
|
25
|
+
## ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new(["$error(\"#{argv_str}\")"]))
|
26
|
+
|
27
|
+
## 解析赋值
|
28
|
+
## ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new([x,x])
|
29
|
+
module ClassHDL
|
30
|
+
OP_SYMBOLS = %w{+ - * / % > < >= <= == != << | & ^}
|
31
|
+
|
32
|
+
def self.compact_op_ch(str)
|
33
|
+
if str =~ /^(?<head>[\w\.\[\]\:]+\s*)(?<eq><?=\s*)\((?<body>.+)\)$/
|
34
|
+
rel_str = $~[:head] + $~[:eq] + $~[:body]
|
35
|
+
else
|
36
|
+
rel_str = str
|
37
|
+
end
|
38
|
+
end
|
39
|
+
|
40
|
+
class OpertorChain
|
41
|
+
attr_accessor :slaver,:tree,:instance_add_brackets
|
42
|
+
|
43
|
+
def initialize(arg=nil)
|
44
|
+
@tree = [] #[[inst0,symb0],[inst1,symb1],[other_chain,symb2],[other_chain,symb3]]
|
45
|
+
# self <symb0> inst0 <symb1> inst1 <symb2> ( other_chain ) <symb3> ( other_chain )
|
46
|
+
if arg
|
47
|
+
@tree << arg
|
48
|
+
end
|
49
|
+
end
|
50
|
+
|
51
|
+
ClassHDL::OP_SYMBOLS.each do |os|
|
52
|
+
|
53
|
+
define_method(os) do |b|
|
54
|
+
# puts "OpertorChain #{os} #{b} #{b.class}"
|
55
|
+
if b.is_a? OpertorChain
|
56
|
+
b.slaver = true
|
57
|
+
end
|
58
|
+
# 计算生成新的OpertorChain 是 self 也需要抛弃
|
59
|
+
self.slaver = true
|
60
|
+
# return self
|
61
|
+
new_op = OpertorChain.new
|
62
|
+
new_op.tree = new_op.tree + self.tree
|
63
|
+
new_op.tree.push [b,os]
|
64
|
+
|
65
|
+
if ClassHDL::AssignDefOpertor.curr_assign_block
|
66
|
+
ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(new_op)
|
67
|
+
end
|
68
|
+
|
69
|
+
new_op
|
70
|
+
end
|
71
|
+
|
72
|
+
end
|
73
|
+
|
74
|
+
def simple_op?
|
75
|
+
## 判断是不是简单的运算 如 X > 0 ,x & y
|
76
|
+
##[[tmp0[0]], ["FALSE", "&"], [#<ClassHDL::OpertorChain:0x00005557046de088 @tree=[[a_inf.valid], ["1'b0", "|"]], @slaver=true>, "&"]]
|
77
|
+
##[[a_inf.valid], ["1'b0", "|"]
|
78
|
+
rel = false
|
79
|
+
AssignDefOpertor.with_rollback_opertors(:old) do
|
80
|
+
if tree.size==2 && tree[0].size==1 && !(tree[0][0].is_a?(ClassHDL::OpertorChain)) && !(tree[1][0].is_a?(ClassHDL::OpertorChain))
|
81
|
+
rel = true
|
82
|
+
else
|
83
|
+
rel = false
|
84
|
+
end
|
85
|
+
end
|
86
|
+
return rel
|
87
|
+
end
|
88
|
+
|
89
|
+
define_method("~") do
|
90
|
+
# self.nege = true
|
91
|
+
# return self
|
92
|
+
self.slaver = true
|
93
|
+
new_op = OpertorChain.new(["~(#{self.instance})".to_nq])
|
94
|
+
end
|
95
|
+
|
96
|
+
def brackets
|
97
|
+
self.slaver = true
|
98
|
+
new_op = OpertorChain.new(["(#{self.instance})".to_nq])
|
99
|
+
end
|
100
|
+
|
101
|
+
def clog2
|
102
|
+
self.slaver = true
|
103
|
+
new_op = OpertorChain.new(["$clog2(#{self.instance})".to_nq])
|
104
|
+
end
|
105
|
+
|
106
|
+
def self.define_op_flag(ruby_op,hdl_op)
|
107
|
+
define_method(ruby_op) do |b|
|
108
|
+
if b.is_a? OpertorChain
|
109
|
+
b.slaver = true
|
110
|
+
unless b.simple_op?
|
111
|
+
b.instance_add_brackets = true
|
112
|
+
end
|
113
|
+
end
|
114
|
+
# 计算生成新的OpertorChain 是 self 也需要抛弃
|
115
|
+
self.slaver = true
|
116
|
+
# return self
|
117
|
+
new_op = OpertorChain.new
|
118
|
+
new_op.tree = new_op.tree + self.tree
|
119
|
+
new_op.tree.push [b,hdl_op]
|
120
|
+
|
121
|
+
if ClassHDL::AssignDefOpertor.curr_assign_block
|
122
|
+
ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(new_op)
|
123
|
+
end
|
124
|
+
new_op
|
125
|
+
end
|
126
|
+
end
|
127
|
+
|
128
|
+
define_op_flag("or","||")
|
129
|
+
define_op_flag("and","&&")
|
130
|
+
|
131
|
+
|
132
|
+
def to_s
|
133
|
+
instance(type=:cond)
|
134
|
+
end
|
135
|
+
|
136
|
+
def instance(type=:assign)
|
137
|
+
AssignDefOpertor.with_rollback_opertors(:old) do
|
138
|
+
str = ''
|
139
|
+
# both_symb_used = false
|
140
|
+
cnt = 0
|
141
|
+
@tree.each do |node|
|
142
|
+
if cnt==1
|
143
|
+
if node[1].to_s=="<="
|
144
|
+
if type==:always_ff || type==:cond
|
145
|
+
sb = " <= "
|
146
|
+
else
|
147
|
+
sb = " = "
|
148
|
+
end
|
149
|
+
else
|
150
|
+
sb = "#{node[1].to_s}"
|
151
|
+
end
|
152
|
+
else
|
153
|
+
sb = "#{node[1].to_s} "
|
154
|
+
end
|
155
|
+
|
156
|
+
unless node[0].is_a? OpertorChain
|
157
|
+
## 判断是不是属于 Var <= "String" 形式
|
158
|
+
if (@tree.length == 2) && node[0].instance_of?(String) && !@slaver
|
159
|
+
str += (sb + '"' + node[0].to_s + '"')
|
160
|
+
elsif node[0].instance_of?(String)
|
161
|
+
# "如果是字符串 则原始输出"
|
162
|
+
str += (sb + '"' + node[0].to_s + '"')
|
163
|
+
else
|
164
|
+
str += (sb + node[0].to_s)
|
165
|
+
end
|
166
|
+
else
|
167
|
+
node[0].slaver = true
|
168
|
+
# puts "--------"
|
169
|
+
# p node[0].tree
|
170
|
+
# puts "========"
|
171
|
+
# if node[0].tree.length>2 && ["&","|","<",">"].include?(node[0].tree[1][1])
|
172
|
+
|
173
|
+
# else
|
174
|
+
if sb =~/(\||&){2,2}/
|
175
|
+
str += " #{sb}#{node[0].instance(:slaver).to_s}"
|
176
|
+
else
|
177
|
+
str += "#{sb}(#{node[0].instance(:slaver).to_s})"
|
178
|
+
end
|
179
|
+
# end
|
180
|
+
# str += "#{sb}(#{"Node"})"
|
181
|
+
end
|
182
|
+
cnt += 1
|
183
|
+
end
|
184
|
+
|
185
|
+
## 修饰
|
186
|
+
|
187
|
+
# if nege
|
188
|
+
# str = "~(#{str})"
|
189
|
+
# else
|
190
|
+
# str
|
191
|
+
# end
|
192
|
+
if instance_add_brackets
|
193
|
+
"(#{str})"
|
194
|
+
else
|
195
|
+
str
|
196
|
+
end
|
197
|
+
end
|
198
|
+
end
|
199
|
+
end
|
200
|
+
end
|
201
|
+
|
202
|
+
module ClassHDL
|
203
|
+
|
204
|
+
module AssignDefOpertor
|
205
|
+
@@included_class = []
|
206
|
+
@@curr_assign_block = HDLAssignBlock.new ##HDLAssignBlock ##HDLAlwaysCombBlock
|
207
|
+
@@curr_assign_block_stack = [HDLAssignBlock.new ]
|
208
|
+
@@curr_opertor_stack = [:old]
|
209
|
+
|
210
|
+
def self.curr_opertor_stack
|
211
|
+
@@curr_opertor_stack
|
212
|
+
end
|
213
|
+
|
214
|
+
def self.curr_assign_block
|
215
|
+
@@curr_assign_block
|
216
|
+
end
|
217
|
+
|
218
|
+
def self.curr_assign_block=(b)
|
219
|
+
unless b
|
220
|
+
raise TdlError.new('Assign Block cant be nil')
|
221
|
+
end
|
222
|
+
@@curr_assign_block = b
|
223
|
+
end
|
224
|
+
|
225
|
+
def self.curr_assign_block_stack
|
226
|
+
@@curr_assign_block_stack
|
227
|
+
end
|
228
|
+
|
229
|
+
def self.with_new_assign_block(na,&block)
|
230
|
+
unless na
|
231
|
+
raise TdlError.new('Assign Block cant be nil')
|
232
|
+
end
|
233
|
+
@@curr_assign_block = na
|
234
|
+
@@curr_assign_block_stack.push(na)
|
235
|
+
rels = yield(na)
|
236
|
+
|
237
|
+
@@curr_assign_block_stack.pop
|
238
|
+
@@curr_assign_block = @@curr_assign_block_stack.last
|
239
|
+
rels
|
240
|
+
end
|
241
|
+
|
242
|
+
# OP_SYMBOLS = %w{+ - * / % > < >= <= == != << | &}
|
243
|
+
OP_SYMBOLS = ClassHDL::OP_SYMBOLS
|
244
|
+
|
245
|
+
def self.included(mod)
|
246
|
+
@@included_class.push mod
|
247
|
+
mod.extend self
|
248
|
+
init_op_methods(mod)
|
249
|
+
end
|
250
|
+
|
251
|
+
def self.init_op_methods(aclass)
|
252
|
+
|
253
|
+
# if aclass.methods.include? :inst
|
254
|
+
# class_inst = aclass.nc_create
|
255
|
+
# else
|
256
|
+
# class_inst = aclass.new
|
257
|
+
# end
|
258
|
+
|
259
|
+
aclass.class_eval do
|
260
|
+
|
261
|
+
def operation_tow(symb,b)
|
262
|
+
# puts "aclass #{symb} #{b.class}"
|
263
|
+
if b.is_a? OpertorChain
|
264
|
+
b.slaver = true
|
265
|
+
end
|
266
|
+
new_op = OpertorChain.new
|
267
|
+
new_op.tree.push([self])
|
268
|
+
new_op.tree.push([b,symb])
|
269
|
+
if @@curr_assign_block
|
270
|
+
@@curr_assign_block.opertor_chains.push(new_op)
|
271
|
+
else
|
272
|
+
raise TdlError.new("operation_tow[#{symb}] <#{b}> Error: curr_assign_block is nil ")
|
273
|
+
end
|
274
|
+
return new_op
|
275
|
+
end
|
276
|
+
|
277
|
+
|
278
|
+
ClassHDL::OP_SYMBOLS.each do |symb|
|
279
|
+
# if class_inst.respond_to?(symb)
|
280
|
+
if self.instance_methods.include?(symb.to_sym)
|
281
|
+
alias_method "_old_#{symb}__",symb
|
282
|
+
else
|
283
|
+
define_method("_old_#{symb}__") do |b|
|
284
|
+
operation_tow(symb,b)
|
285
|
+
end
|
286
|
+
end
|
287
|
+
|
288
|
+
## define new
|
289
|
+
|
290
|
+
define_method("_new_#{symb}__") do |b|
|
291
|
+
operation_tow(symb,b)
|
292
|
+
end
|
293
|
+
end
|
294
|
+
|
295
|
+
## 定义片选
|
296
|
+
def new_slice_cc(*a)
|
297
|
+
if a.size == 1
|
298
|
+
if a[0].is_a? Range
|
299
|
+
"#{self}[#{a[0].first}:#{a[1].last}]".to_nq
|
300
|
+
else
|
301
|
+
"#{self}[#{a[0]}]".to_nq
|
302
|
+
end
|
303
|
+
else
|
304
|
+
"#{self}[#{a[0]}:#{a[1]}]".to_nq
|
305
|
+
end
|
306
|
+
end
|
307
|
+
|
308
|
+
if self.instance_methods.include?("[]".to_sym)
|
309
|
+
alias_method "_old_slice_","[]"
|
310
|
+
else
|
311
|
+
alias_method "_old_slice_","new_slice_cc"
|
312
|
+
end
|
313
|
+
end
|
314
|
+
end
|
315
|
+
|
316
|
+
def self.use_new_yield_opertors
|
317
|
+
# NqString.class_exec do
|
318
|
+
# define_method("+") do |a|
|
319
|
+
# "+++++"
|
320
|
+
# end
|
321
|
+
# end
|
322
|
+
@@included_class.each do |oc|
|
323
|
+
oc.class_eval do
|
324
|
+
ClassHDL::OP_SYMBOLS.each do |symb|
|
325
|
+
# if symb.eql? "<="
|
326
|
+
# alias_method symb,:_assign_small_and_eq
|
327
|
+
# # define_method(symb,instance_method(:_assign_small_and_eq))
|
328
|
+
# else
|
329
|
+
# alias_method symb,"_new_#{symb}__"
|
330
|
+
# # define_method(symb,instance_method("_new_#{symb}__"))
|
331
|
+
# end
|
332
|
+
alias_method symb,"_new_#{symb}__"
|
333
|
+
# define_method(symb,instance_method("_new_#{symb}__"))
|
334
|
+
## 测试用
|
335
|
+
# define_method(symb) do |a|
|
336
|
+
# "+++++++"
|
337
|
+
# end
|
338
|
+
|
339
|
+
end
|
340
|
+
end
|
341
|
+
end
|
342
|
+
end
|
343
|
+
|
344
|
+
def self.use_old_cond_opertors
|
345
|
+
ClassHDL::OP_SYMBOLS.each do |symb|
|
346
|
+
@@included_class.each do |oc|
|
347
|
+
oc.class_eval do
|
348
|
+
alias_method symb,"_old_#{symb}__"
|
349
|
+
# define_method(symb,instance_method("_old_#{symb}__"))
|
350
|
+
end
|
351
|
+
end
|
352
|
+
end
|
353
|
+
end
|
354
|
+
|
355
|
+
def self.with_rollback_opertors(use_op,&block)
|
356
|
+
|
357
|
+
case(use_op)
|
358
|
+
when :new
|
359
|
+
rels = with_new_opertor(&block)
|
360
|
+
when :old
|
361
|
+
rels = with_normal_opertor(&block)
|
362
|
+
else
|
363
|
+
|
364
|
+
end
|
365
|
+
|
366
|
+
case(@@curr_opertor_stack.last)
|
367
|
+
when :new
|
368
|
+
use_new_yield_opertors
|
369
|
+
when :old
|
370
|
+
use_old_cond_opertors
|
371
|
+
else
|
372
|
+
use_old_cond_opertors
|
373
|
+
end
|
374
|
+
|
375
|
+
rels
|
376
|
+
end
|
377
|
+
|
378
|
+
def self.with_new_opertor(&block)
|
379
|
+
use_new_yield_opertors
|
380
|
+
@@curr_opertor_stack.push :new
|
381
|
+
rels = yield
|
382
|
+
@@curr_opertor_stack.pop
|
383
|
+
rels
|
384
|
+
end
|
385
|
+
|
386
|
+
def self.with_normal_opertor(&block)
|
387
|
+
use_old_cond_opertors
|
388
|
+
@@curr_opertor_stack.push :old
|
389
|
+
rels = yield
|
390
|
+
@@curr_opertor_stack.pop
|
391
|
+
rels
|
392
|
+
end
|
393
|
+
|
394
|
+
## 类方法
|
395
|
+
|
396
|
+
end
|
397
|
+
end
|
398
|
+
|
399
|
+
class SdlModule
|
400
|
+
def rubyOP(&block)
|
401
|
+
ClassHDL::AssignDefOpertor.with_rollback_opertors(:old,&block )
|
402
|
+
end
|
403
|
+
end
|
404
|
+
|
405
|
+
class String
|
406
|
+
include ClassHDL::AssignDefOpertor
|
407
|
+
|
408
|
+
end
|
409
|
+
|
410
|
+
class NqString
|
411
|
+
include ClassHDL::AssignDefOpertor
|
412
|
+
|
413
|
+
def [](a,b=nil)
|
414
|
+
if a.is_a? ClassHDL::OpertorChain
|
415
|
+
a.slaver = true
|
416
|
+
arel = a.instance(:slaver)
|
417
|
+
else
|
418
|
+
arel = a
|
419
|
+
end
|
420
|
+
|
421
|
+
if b.is_a? ClassHDL::OpertorChain
|
422
|
+
b.slaver = true
|
423
|
+
brel = b.instance(:slaver)
|
424
|
+
else
|
425
|
+
brel = b
|
426
|
+
end
|
427
|
+
|
428
|
+
unless b
|
429
|
+
if a.is_a? Range
|
430
|
+
af = a.first
|
431
|
+
al = a.last
|
432
|
+
return "#{self}[#{af}:#{al}]".to_nq
|
433
|
+
end
|
434
|
+
|
435
|
+
|
436
|
+
return "#{self}[#{arel}]".to_nq
|
437
|
+
else
|
438
|
+
return "#{self}[#{arel}:#{brel}]".to_nq
|
439
|
+
end
|
440
|
+
end
|
441
|
+
end
|
442
|
+
|
443
|
+
|
444
|
+
class BaseElm
|
445
|
+
## 重覆盖掉
|
446
|
+
def signal(index=nil)
|
447
|
+
ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
|
448
|
+
with_new_align(0) do
|
449
|
+
unless index
|
450
|
+
NqString.new(@name.to_s)
|
451
|
+
else
|
452
|
+
unless index.is_a? String
|
453
|
+
NqString.new("#{@name.to_s}[#{align_signal(index)}]")
|
454
|
+
else
|
455
|
+
NqString.new("#{@name.to_s}[#{index.strip}]")
|
456
|
+
end
|
457
|
+
end
|
458
|
+
end
|
459
|
+
end
|
460
|
+
end
|
461
|
+
|
462
|
+
private
|
463
|
+
## ArrayChain 相关
|
464
|
+
def self.define_arraychain_tail_method(name,width=1,rv=false,&block)
|
465
|
+
self.define_method(name) do
|
466
|
+
ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
|
467
|
+
if @dimension.empty?
|
468
|
+
NqString.new(signal.concat ".#{name}")
|
469
|
+
else
|
470
|
+
@_array_chain_hash_ ||= {}
|
471
|
+
unless @_array_chain_hash_[name.to_s]
|
472
|
+
if width.is_a? Proc
|
473
|
+
r_width = width.call(self)
|
474
|
+
else
|
475
|
+
r_width = width
|
476
|
+
end
|
477
|
+
rel = generate_inf_to_signals(name.to_s,width=r_width,rv=rv)
|
478
|
+
|
479
|
+
@_array_chain_hash_[name.to_s] = rel
|
480
|
+
end
|
481
|
+
TdlSpace::ArrayChain.new(@_array_chain_hash_[name.to_s],[])
|
482
|
+
end
|
483
|
+
end
|
484
|
+
end
|
485
|
+
end
|
486
|
+
|
487
|
+
end
|
488
|
+
|
489
|
+
class InfElm
|
490
|
+
## 重覆盖掉
|
491
|
+
def signal(index=nil) #array interface
|
492
|
+
# large_name_len("")
|
493
|
+
ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
|
494
|
+
with_new_align(0) do
|
495
|
+
if @dimension.any? && index
|
496
|
+
if index.is_a? String
|
497
|
+
sq = "[#{index}]"
|
498
|
+
NqString.new("#{@name}#{sq}")
|
499
|
+
# NqString.new("#{@name}")
|
500
|
+
else
|
501
|
+
NqString.new("#{@name}[#{align_signal(index)}]")
|
502
|
+
end
|
503
|
+
else
|
504
|
+
NqString.new("#{@name}")
|
505
|
+
end
|
506
|
+
end
|
507
|
+
end
|
508
|
+
end
|
509
|
+
end
|
510
|
+
|
511
|
+
class SignalElm
|
512
|
+
define_method("!") do # 定义取反
|
513
|
+
ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
|
514
|
+
NqString.new("!#{signal}")
|
515
|
+
end
|
516
|
+
end
|
517
|
+
|
518
|
+
define_method("~") do # 定义取反
|
519
|
+
ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
|
520
|
+
NqString.new("~#{signal}")
|
521
|
+
end
|
522
|
+
end
|
523
|
+
end
|
524
|
+
|
525
|
+
module TdlSpace
|
526
|
+
class ArrayChain
|
527
|
+
def [](a,b=false)
|
528
|
+
if a.is_a? Range
|
529
|
+
b = a.last
|
530
|
+
a = a.first
|
531
|
+
end
|
532
|
+
|
533
|
+
if a.is_a? ClassHDL::OpertorChain
|
534
|
+
a.slaver = true
|
535
|
+
end
|
536
|
+
|
537
|
+
if b.is_a? ClassHDL::OpertorChain
|
538
|
+
b.slaver = true
|
539
|
+
end
|
540
|
+
|
541
|
+
if @end_slice
|
542
|
+
raise TdlError.new("数组下标已经被用片选[#{@end_slice[0]},#{@end_slice[1]}]终结")
|
543
|
+
end
|
544
|
+
ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
|
545
|
+
unless b
|
546
|
+
ArrayChain.new(obj,chain+[a])
|
547
|
+
else
|
548
|
+
# ArrayChain.new(&obj,chain,[a,b])
|
549
|
+
@end_slice = [a,b]
|
550
|
+
self
|
551
|
+
end
|
552
|
+
end
|
553
|
+
end
|
554
|
+
|
555
|
+
def to_s
|
556
|
+
ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
|
557
|
+
str = ""
|
558
|
+
xstr = false
|
559
|
+
chain.each do |e|
|
560
|
+
unless e.is_a? ArrayChainSignalMethod
|
561
|
+
str += "[#{e.to_s}]"
|
562
|
+
else
|
563
|
+
if (e.name.to_s == "vld_rdy" || e.name.to_s == "vld_rdy_last") && ( obj.is_a?(AxiStream) || obj.is_a?(DataInf_C) )
|
564
|
+
xstr = obj.public_send("array_chain_#{e.name.to_s}_inst",obj.to_s + chain[0, chain.size-1].map{|x| "[#{x}]"}.join(''))
|
565
|
+
else
|
566
|
+
str += ".#{e.name.to_s}"
|
567
|
+
end
|
568
|
+
end
|
569
|
+
end
|
570
|
+
if @end_slice
|
571
|
+
str += "[#{@end_slice[0]}:#{@end_slice[1]}]"
|
572
|
+
end
|
573
|
+
|
574
|
+
xstr || "#{obj.to_s}#{str}"
|
575
|
+
|
576
|
+
end
|
577
|
+
end
|
578
|
+
|
579
|
+
def ~
|
580
|
+
ArrayChain.new("~#{self.to_s}")
|
581
|
+
end
|
582
|
+
end
|
583
|
+
end
|
584
|
+
|
585
|
+
class Logic
|
586
|
+
include ClassHDL::AssignDefOpertor
|
587
|
+
end
|
588
|
+
|
589
|
+
class Clock
|
590
|
+
include ClassHDL::AssignDefOpertor
|
591
|
+
end
|
592
|
+
|
593
|
+
class Reset
|
594
|
+
include ClassHDL::AssignDefOpertor
|
595
|
+
end
|
596
|
+
|
597
|
+
class Numeric
|
598
|
+
include ClassHDL::AssignDefOpertor
|
599
|
+
end
|
600
|
+
|
601
|
+
class Integer
|
602
|
+
include ClassHDL::AssignDefOpertor
|
603
|
+
end
|
604
|
+
|
605
|
+
module TdlSpace
|
606
|
+
module DefOpertor
|
607
|
+
|
608
|
+
OP_SYMBOLS = %w{+ - * / % > < >= <= == != << | &}
|
609
|
+
|
610
|
+
|
611
|
+
OP_SYMBOLS.each do |e|
|
612
|
+
define_method(e) do |b|
|
613
|
+
if b.is_a? Proc
|
614
|
+
ll = lambda { ("(".concat(self.to_s).concat(" #{e} #{b.call})")).to_nq }
|
615
|
+
ll
|
616
|
+
else
|
617
|
+
("(".concat(self.to_s).concat(" #{e} #{b.to_s})").to_nq)
|
618
|
+
end
|
619
|
+
end
|
620
|
+
end
|
621
|
+
|
622
|
+
end
|
623
|
+
end
|
624
|
+
|
625
|
+
module TdlSpace
|
626
|
+
class ArrayChain
|
627
|
+
include TdlSpace::DefOpertor
|
628
|
+
include ClassHDL::AssignDefOpertor
|
629
|
+
end
|
630
|
+
end
|
631
|
+
|
632
|
+
module ClassHDL
|
633
|
+
class StructVar
|
634
|
+
include ClassHDL::AssignDefOpertor
|
635
|
+
end
|
636
|
+
end
|
637
|
+
|
638
|
+
# ele_array = ([Parameter] | SignalElm.subclass | InfElm.subclass | CLKInfElm.subclass | [MailBox,BfmStream])
|
639
|
+
|
640
|
+
# ele_array.each do |e|
|
641
|
+
# if e.instance_methods.include? :to_s
|
642
|
+
# e.class_eval do
|
643
|
+
# alias_method "_old_to_s",:to_s
|
644
|
+
# define_method(:new_to_s) do |*args|
|
645
|
+
# ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
|
646
|
+
# send("_old_to_s",*args)
|
647
|
+
# end
|
648
|
+
# end
|
649
|
+
# alias_method :to_s,:new_to_s
|
650
|
+
# end
|
651
|
+
# end
|
652
|
+
# end
|
653
|
+
|