wasmtime 20.0.2 → 21.0.1
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- checksums.yaml +4 -4
- data/Cargo.lock +129 -124
- data/ext/Cargo.toml +8 -6
- data/ext/cargo-vendor/cobs-0.2.3/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cobs-0.2.3/Cargo.toml +39 -0
- data/ext/cargo-vendor/cobs-0.2.3/LICENSE-APACHE +202 -0
- data/ext/cargo-vendor/cobs-0.2.3/LICENSE-MIT +19 -0
- data/ext/cargo-vendor/cobs-0.2.3/README.md +23 -0
- data/ext/cargo-vendor/cobs-0.2.3/src/dec.rs +360 -0
- data/ext/cargo-vendor/cobs-0.2.3/src/enc.rs +216 -0
- data/ext/cargo-vendor/cobs-0.2.3/src/lib.rs +14 -0
- data/ext/cargo-vendor/cobs-0.2.3/tests/test.rs +265 -0
- data/ext/cargo-vendor/cranelift-bforest-0.108.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-bforest-0.108.1/Cargo.toml +40 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/Cargo.toml +189 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/build.rs +266 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/alias_analysis.rs +403 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/context.rs +395 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/ctxhash.rs +167 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/egraph/elaborate.rs +835 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/egraph.rs +839 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/incremental_cache.rs +256 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/ir/instructions.rs +1020 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/aarch64/abi.rs +1580 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/aarch64/inst/args.rs +721 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/aarch64/inst/emit.rs +3846 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/aarch64/inst/emit_tests.rs +7902 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/aarch64/inst/imms.rs +1213 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/aarch64/inst/mod.rs +3094 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/aarch64/inst/regs.rs +288 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/aarch64/inst.isle +4225 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/aarch64/lower/isle.rs +810 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/aarch64/pcc.rs +568 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/mod.rs +449 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/riscv64/abi.rs +1051 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/riscv64/inst/args.rs +1938 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/riscv64/inst/emit.rs +2681 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/riscv64/inst/emit_tests.rs +2197 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/riscv64/inst/mod.rs +1975 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/riscv64/inst/regs.rs +168 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/riscv64/inst/vector.rs +1144 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/riscv64/inst.isle +2969 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/riscv64/lower/isle.rs +625 -0
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- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/s390x/abi.rs +1037 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/s390x/inst/args.rs +314 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/s390x/inst/emit.rs +3646 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/s390x/inst/imms.rs +202 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/s390x/inst/mod.rs +3421 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/s390x/inst/regs.rs +180 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/x64/abi.rs +1410 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/x64/inst/args.rs +2256 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/x64/inst/emit.rs +4311 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/x64/inst/emit_tests.rs +5171 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/x64/inst/mod.rs +2838 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/x64/inst/regs.rs +276 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/x64/inst.isle +5294 -0
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- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/x64/lower.rs +337 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/x64/pcc.rs +1014 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/lib.rs +106 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/machinst/abi.rs +2506 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/machinst/blockorder.rs +465 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/machinst/isle.rs +903 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/machinst/lower.rs +1432 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/machinst/mod.rs +555 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/machinst/reg.rs +522 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/machinst/valueregs.rs +138 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/machinst/vcode.rs +1741 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/nan_canonicalization.rs +130 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/opts/arithmetic.isle +240 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/opts/icmp.isle +215 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/ranges.rs +131 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/remove_constant_phis.rs +419 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/scoped_hash_map.rs +310 -0
- data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/settings.rs +590 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.108.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.108.1/Cargo.toml +35 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.108.1/src/gen_inst.rs +1278 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.108.1/src/gen_isle.rs +519 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.108.1/src/gen_settings.rs +508 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.108.1/src/gen_types.rs +75 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.108.1/src/isa/riscv64.rs +168 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.108.1/src/isa/x86.rs +414 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.108.1/src/isle.rs +126 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.108.1/src/lib.rs +98 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.108.1/src/shared/settings.rs +348 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.108.1/src/srcgen.rs +464 -0
- data/ext/cargo-vendor/cranelift-codegen-shared-0.108.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-shared-0.108.1/Cargo.toml +22 -0
- data/ext/cargo-vendor/cranelift-control-0.108.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-control-0.108.1/Cargo.toml +30 -0
- data/ext/cargo-vendor/cranelift-entity-0.108.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-entity-0.108.1/Cargo.toml +52 -0
- data/ext/cargo-vendor/cranelift-entity-0.108.1/src/lib.rs +381 -0
- data/ext/cargo-vendor/cranelift-frontend-0.108.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-frontend-0.108.1/Cargo.toml +67 -0
- data/ext/cargo-vendor/cranelift-frontend-0.108.1/src/switch.rs +696 -0
- data/ext/cargo-vendor/cranelift-isle-0.108.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-isle-0.108.1/Cargo.toml +46 -0
- data/ext/cargo-vendor/cranelift-isle-0.108.1/src/codegen.rs +886 -0
- data/ext/cargo-vendor/cranelift-isle-0.108.1/src/disjointsets.rs +169 -0
- data/ext/cargo-vendor/cranelift-isle-0.108.1/src/lib.rs +33 -0
- data/ext/cargo-vendor/cranelift-isle-0.108.1/src/sema.rs +2492 -0
- data/ext/cargo-vendor/cranelift-isle-0.108.1/src/serialize.rs +846 -0
- data/ext/cargo-vendor/cranelift-isle-0.108.1/src/stablemapset.rs +79 -0
- data/ext/cargo-vendor/cranelift-isle-0.108.1/src/trie_again.rs +684 -0
- data/ext/cargo-vendor/cranelift-native-0.108.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-native-0.108.1/Cargo.toml +43 -0
- data/ext/cargo-vendor/cranelift-wasm-0.108.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-wasm-0.108.1/Cargo.toml +109 -0
- data/ext/cargo-vendor/cranelift-wasm-0.108.1/src/code_translator.rs +3687 -0
- data/ext/cargo-vendor/cranelift-wasm-0.108.1/src/environ/dummy.rs +906 -0
- data/ext/cargo-vendor/cranelift-wasm-0.108.1/src/environ/spec.rs +945 -0
- data/ext/cargo-vendor/cranelift-wasm-0.108.1/src/sections_translator.rs +389 -0
- data/ext/cargo-vendor/deterministic-wasi-ctx-0.1.22/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/deterministic-wasi-ctx-0.1.22/Cargo.toml +48 -0
- data/ext/cargo-vendor/embedded-io-0.4.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/embedded-io-0.4.0/CHANGELOG.md +28 -0
- data/ext/cargo-vendor/embedded-io-0.4.0/Cargo.toml +73 -0
- data/ext/cargo-vendor/embedded-io-0.4.0/LICENSE-APACHE +201 -0
- data/ext/cargo-vendor/embedded-io-0.4.0/LICENSE-MIT +25 -0
- data/ext/cargo-vendor/embedded-io-0.4.0/README.md +33 -0
- data/ext/cargo-vendor/embedded-io-0.4.0/ci.sh +21 -0
- data/ext/cargo-vendor/embedded-io-0.4.0/rust-toolchain.toml +3 -0
- data/ext/cargo-vendor/embedded-io-0.4.0/src/adapters/futures_io.rs +65 -0
- data/ext/cargo-vendor/embedded-io-0.4.0/src/adapters/mod.rs +40 -0
- data/ext/cargo-vendor/embedded-io-0.4.0/src/adapters/std_io.rs +107 -0
- data/ext/cargo-vendor/embedded-io-0.4.0/src/adapters/tokio.rs +108 -0
- data/ext/cargo-vendor/embedded-io-0.4.0/src/asynch.rs +230 -0
- data/ext/cargo-vendor/embedded-io-0.4.0/src/blocking.rs +309 -0
- data/ext/cargo-vendor/embedded-io-0.4.0/src/fmt.rs +228 -0
- data/ext/cargo-vendor/embedded-io-0.4.0/src/lib.rs +125 -0
- data/ext/cargo-vendor/libm-0.2.8/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/libm-0.2.8/CHANGELOG.md +123 -0
- data/ext/cargo-vendor/libm-0.2.8/CONTRIBUTING.md +95 -0
- data/ext/cargo-vendor/libm-0.2.8/Cargo.toml +45 -0
- data/ext/cargo-vendor/libm-0.2.8/LICENSE-APACHE +201 -0
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- data/ext/cargo-vendor/libm-0.2.8/README.md +51 -0
- data/ext/cargo-vendor/libm-0.2.8/build.rs +463 -0
- data/ext/cargo-vendor/libm-0.2.8/src/lib.rs +59 -0
- data/ext/cargo-vendor/libm-0.2.8/src/libm_helper.rs +171 -0
- data/ext/cargo-vendor/libm-0.2.8/src/math/acos.rs +112 -0
- data/ext/cargo-vendor/libm-0.2.8/src/math/acosf.rs +79 -0
- data/ext/cargo-vendor/libm-0.2.8/src/math/acosh.rs +27 -0
- data/ext/cargo-vendor/libm-0.2.8/src/math/acoshf.rs +26 -0
- data/ext/cargo-vendor/libm-0.2.8/src/math/asin.rs +119 -0
- data/ext/cargo-vendor/libm-0.2.8/src/math/asinf.rs +72 -0
- data/ext/cargo-vendor/libm-0.2.8/src/math/asinh.rs +40 -0
- data/ext/cargo-vendor/libm-0.2.8/src/math/asinhf.rs +39 -0
- data/ext/cargo-vendor/libm-0.2.8/src/math/atan.rs +184 -0
- data/ext/cargo-vendor/libm-0.2.8/src/math/atan2.rs +126 -0
- data/ext/cargo-vendor/libm-0.2.8/src/math/atan2f.rs +91 -0
- data/ext/cargo-vendor/libm-0.2.8/src/math/atanf.rs +112 -0
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- data/ext/cargo-vendor/libm-0.2.8/src/math/atanhf.rs +37 -0
- data/ext/cargo-vendor/libm-0.2.8/src/math/cbrt.rs +113 -0
- data/ext/cargo-vendor/libm-0.2.8/src/math/cbrtf.rs +75 -0
- data/ext/cargo-vendor/libm-0.2.8/src/math/ceil.rs +82 -0
- data/ext/cargo-vendor/libm-0.2.8/src/math/ceilf.rs +65 -0
- data/ext/cargo-vendor/libm-0.2.8/src/math/copysign.rs +12 -0
- data/ext/cargo-vendor/libm-0.2.8/src/math/copysignf.rs +12 -0
- data/ext/cargo-vendor/libm-0.2.8/src/math/cos.rs +73 -0
- data/ext/cargo-vendor/libm-0.2.8/src/math/cosf.rs +83 -0
- data/ext/cargo-vendor/libm-0.2.8/src/math/cosh.rs +38 -0
- data/ext/cargo-vendor/libm-0.2.8/src/math/coshf.rs +38 -0
- data/ext/cargo-vendor/libm-0.2.8/src/math/erf.rs +318 -0
- data/ext/cargo-vendor/libm-0.2.8/src/math/erff.rs +230 -0
- data/ext/cargo-vendor/libm-0.2.8/src/math/exp.rs +154 -0
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- data/ext/cargo-vendor/libm-0.2.8/src/math/exp2.rs +394 -0
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- data/ext/cargo-vendor/libm-0.2.8/src/math/expo2.rs +14 -0
- data/ext/cargo-vendor/libm-0.2.8/src/math/fabs.rs +41 -0
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- data/ext/cargo-vendor/libm-0.2.8/src/math/fdim.rs +22 -0
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- /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/wasi.wit +0 -0
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- /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/world-diamond.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/world-diamond.wit.json +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/world-iface-no-collide.wit +0 -0
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- /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/world-implicit-import1.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/world-implicit-import1.wit.json +0 -0
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//! This module implements lowering (instruction selection) from Cranelift IR
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//! to machine instructions with virtual registers. This is *almost* the final
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//! machine code, except for register allocation.
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// TODO: separate the IR-query core of `Lower` from the lowering logic built on
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// top of it, e.g. the side-effect/coloring analysis and the scan support.
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use crate::entity::SecondaryMap;
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use crate::inst_predicates::{has_lowering_side_effect, is_constant_64bit};
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use crate::ir::pcc::{Fact, FactContext, PccError, PccResult};
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use crate::ir::{
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ArgumentPurpose, Block, Constant, ConstantData, DataFlowGraph, ExternalName, Function,
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GlobalValue, GlobalValueData, Immediate, Inst, InstructionData, MemFlags, RelSourceLoc, Type,
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Value, ValueDef, ValueLabelAssignments, ValueLabelStart,
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};
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use crate::machinst::{
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writable_value_regs, BlockIndex, BlockLoweringOrder, Callee, InsnIndex, LoweredBlock,
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MachLabel, Reg, SigSet, VCode, VCodeBuilder, VCodeConstant, VCodeConstantData, VCodeConstants,
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VCodeInst, ValueRegs, Writable,
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};
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use crate::settings::Flags;
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use crate::{trace, CodegenResult};
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use alloc::vec::Vec;
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use cranelift_control::ControlPlane;
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use rustc_hash::{FxHashMap, FxHashSet};
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use smallvec::{smallvec, SmallVec};
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use std::fmt::Debug;
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use super::{VCodeBuildDirection, VRegAllocator};
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/// A vector of ValueRegs, used to represent the outputs of an instruction.
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pub type InstOutput = SmallVec<[ValueRegs<Reg>; 2]>;
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/// An "instruction color" partitions CLIF instructions by side-effecting ops.
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/// All instructions with the same "color" are guaranteed not to be separated by
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/// any side-effecting op (for this purpose, loads are also considered
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/// side-effecting, to avoid subtle questions w.r.t. the memory model), and
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/// furthermore, it is guaranteed that for any two instructions A and B such
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/// that color(A) == color(B), either A dominates B and B postdominates A, or
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/// vice-versa. (For now, in practice, only ops in the same basic block can ever
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/// have the same color, trivially providing the second condition.) Intuitively,
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/// this means that the ops of the same color must always execute "together", as
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/// part of one atomic contiguous section of the dynamic execution trace, and
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/// they can be freely permuted (modulo true dataflow dependencies) without
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/// affecting program behavior.
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#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
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struct InstColor(u32);
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impl InstColor {
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fn new(n: u32) -> InstColor {
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InstColor(n)
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}
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/// Get an arbitrary index representing this color. The index is unique
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/// *within a single function compilation*, but indices may be reused across
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/// functions.
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pub fn get(self) -> u32 {
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self.0
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}
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}
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/// A representation of all of the ways in which a value is available, aside
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/// from as a direct register.
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///
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/// - An instruction, if it would be allowed to occur at the current location
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/// instead (see [Lower::get_input_as_source_or_const()] for more details).
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///
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/// - A constant, if the value is known to be a constant.
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#[derive(Clone, Copy, Debug)]
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pub struct NonRegInput {
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/// An instruction produces this value (as the given output), and its
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/// computation (and side-effect if applicable) could occur at the
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/// current instruction's location instead.
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///
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/// If this instruction's operation is merged into the current instruction,
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/// the backend must call [Lower::sink_inst()].
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///
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/// This enum indicates whether this use of the source instruction
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/// is unique or not.
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pub inst: InputSourceInst,
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/// The value is a known constant.
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pub constant: Option<u64>,
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}
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/// When examining an input to an instruction, this enum provides one
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/// of several options: there is or isn't a single instruction (that
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/// we can see and merge with) that produces that input's value, and
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/// we are or aren't the single user of that instruction.
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#[derive(Clone, Copy, Debug)]
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pub enum InputSourceInst {
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/// The input in question is the single, unique use of the given
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/// instruction and output index, and it can be sunk to the
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/// location of this input.
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UniqueUse(Inst, usize),
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/// The input in question is one of multiple uses of the given
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/// instruction. It can still be sunk to the location of this
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/// input.
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Use(Inst, usize),
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/// We cannot determine which instruction produced the input, or
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/// it is one of several instructions (e.g., due to a control-flow
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/// merge and blockparam), or the source instruction cannot be
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/// allowed to sink to the current location due to side-effects.
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None,
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}
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impl InputSourceInst {
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/// Get the instruction and output index for this source, whether
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/// we are its single or one of many users.
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pub fn as_inst(&self) -> Option<(Inst, usize)> {
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match self {
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&InputSourceInst::UniqueUse(inst, output_idx)
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| &InputSourceInst::Use(inst, output_idx) => Some((inst, output_idx)),
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&InputSourceInst::None => None,
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}
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}
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}
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/// A machine backend.
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pub trait LowerBackend {
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/// The machine instruction type.
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type MInst: VCodeInst;
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/// Lower a single instruction.
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///
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/// For a branch, this function should not generate the actual branch
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/// instruction. However, it must force any values it needs for the branch
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/// edge (block-param actuals) into registers, because the actual branch
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/// generation (`lower_branch()`) happens *after* any possible merged
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/// out-edge.
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///
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/// Returns `None` if no lowering for the instruction was found.
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fn lower(&self, ctx: &mut Lower<Self::MInst>, inst: Inst) -> Option<InstOutput>;
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/// Lower a block-terminating group of branches (which together can be seen
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/// as one N-way branch), given a vcode MachLabel for each target.
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///
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/// Returns `None` if no lowering for the branch was found.
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fn lower_branch(
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&self,
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ctx: &mut Lower<Self::MInst>,
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inst: Inst,
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targets: &[MachLabel],
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) -> Option<()>;
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/// A bit of a hack: give a fixed register that always holds the result of a
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/// `get_pinned_reg` instruction, if known. This allows elision of moves
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/// into the associated vreg, instead using the real reg directly.
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fn maybe_pinned_reg(&self) -> Option<Reg> {
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None
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}
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/// The type of state carried between `check_fact` invocations.
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type FactFlowState: Default + Clone + Debug;
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/// Check any facts about an instruction, given VCode with facts
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/// on VRegs. Takes mutable `VCode` so that it can propagate some
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/// kinds of facts automatically.
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fn check_fact(
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&self,
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_ctx: &FactContext<'_>,
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_vcode: &mut VCode<Self::MInst>,
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_inst: InsnIndex,
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_state: &mut Self::FactFlowState,
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) -> PccResult<()> {
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Err(PccError::UnimplementedBackend)
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}
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}
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/// Machine-independent lowering driver / machine-instruction container. Maintains a correspondence
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/// from original Inst to MachInsts.
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pub struct Lower<'func, I: VCodeInst> {
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/// The function to lower.
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f: &'func Function,
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/// Lowered machine instructions.
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vcode: VCodeBuilder<I>,
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/// VReg allocation context, given to the vcode field at build time to finalize the vcode.
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vregs: VRegAllocator<I>,
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/// Mapping from `Value` (SSA value in IR) to virtual register.
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value_regs: SecondaryMap<Value, ValueRegs<Reg>>,
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/// sret registers, if needed.
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sret_reg: Option<ValueRegs<Reg>>,
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/// Instruction colors at block exits. From this map, we can recover all
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/// instruction colors by scanning backward from the block end and
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/// decrementing on any color-changing (side-effecting) instruction.
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block_end_colors: SecondaryMap<Block, InstColor>,
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/// Instruction colors at side-effecting ops. This is the *entry* color,
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/// i.e., the version of global state that exists before an instruction
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/// executes. For each side-effecting instruction, the *exit* color is its
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/// entry color plus one.
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side_effect_inst_entry_colors: FxHashMap<Inst, InstColor>,
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/// Current color as we scan during lowering. While we are lowering an
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/// instruction, this is equal to the color *at entry to* the instruction.
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cur_scan_entry_color: Option<InstColor>,
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/// Current instruction as we scan during lowering.
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cur_inst: Option<Inst>,
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/// Instruction constant values, if known.
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inst_constants: FxHashMap<Inst, u64>,
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/// Use-counts per SSA value, as counted in the input IR. These
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/// are "coarsened", in the abstract-interpretation sense: we only
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/// care about "0, 1, many" states, as this is all we need and
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/// this lets us do an efficient fixpoint analysis.
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///
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/// See doc comment on `ValueUseState` for more details.
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value_ir_uses: SecondaryMap<Value, ValueUseState>,
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/// Actual uses of each SSA value so far, incremented while lowering.
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value_lowered_uses: SecondaryMap<Value, u32>,
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/// Effectful instructions that have been sunk; they are not codegen'd at
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/// their original locations.
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inst_sunk: FxHashSet<Inst>,
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/// Instructions collected for the CLIF inst in progress, in forward order.
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ir_insts: Vec<I>,
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/// The register to use for GetPinnedReg, if any, on this architecture.
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pinned_reg: Option<Reg>,
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/// Compilation flags.
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flags: Flags,
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}
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/// How is a value used in the IR?
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///
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/// This can be seen as a coarsening of an integer count. We only need
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/// distinct states for zero, one, or many.
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///
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/// This analysis deserves further explanation. The basic idea is that
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/// we want to allow instruction lowering to know whether a value that
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/// an instruction references is *only* referenced by that one use, or
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/// by others as well. This is necessary to know when we might want to
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/// move a side-effect: we cannot, for example, duplicate a load, so
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/// we cannot let instruction lowering match a load as part of a
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/// subpattern and potentially incorporate it.
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///
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/// Note that a lot of subtlety comes into play once we have
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/// *indirect* uses. The classical example of this in our development
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/// history was the x86 compare instruction, which is incorporated
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/// into flags users (e.g. `selectif`, `trueif`, branches) and can
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/// subsequently incorporate loads, or at least we would like it
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/// to. However, danger awaits: the compare might be the only user of
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/// a load, so we might think we can just move the load (and nothing
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/// is duplicated -- success!), except that the compare itself is
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/// codegen'd in multiple places, where it is incorporated as a
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/// subpattern itself.
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///
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/// So we really want a notion of "unique all the way along the
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/// matching path". Rust's `&T` and `&mut T` offer a partial analogy
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/// to the semantics that we want here: we want to know when we've
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/// matched a unique use of an instruction, and that instruction's
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/// unique use of another instruction, etc, just as `&mut T` can only
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/// be obtained by going through a chain of `&mut T`. If one has a
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/// `&T` to a struct containing `&mut T` (one of several uses of an
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/// instruction that itself has a unique use of an instruction), one
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/// can only get a `&T` (one can only get a "I am one of several users
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/// of this instruction" result).
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///
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/// We could track these paths, either dynamically as one "looks up the operand
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/// tree" or precomputed. But the former requires state and means that the
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/// `Lower` API carries that state implicitly, which we'd like to avoid if we
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/// can. And the latter implies O(n^2) storage: it is an all-pairs property (is
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/// inst `i` unique from the point of view of `j`).
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///
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/// To make matters even a little more complex still, a value that is
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/// not uniquely used when initially viewing the IR can *become*
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/// uniquely used, at least as a root allowing further unique uses of
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/// e.g. loads to merge, if no other instruction actually merges
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/// it. To be more concrete, if we have `v1 := load; v2 := op v1; v3
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/// := op v2; v4 := op v2` then `v2` is non-uniquely used, so from the
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/// point of view of lowering `v4` or `v3`, we cannot merge the load
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/// at `v1`. But if we decide just to use the assigned register for
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/// `v2` at both `v3` and `v4`, then we only actually codegen `v2`
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/// once, so it *is* a unique root at that point and we *can* merge
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/// the load.
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///
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/// Note also that the color scheme is not sufficient to give us this
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/// information, for various reasons: reasoning about side-effects
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/// does not tell us about potential duplication of uses through pure
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/// ops.
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///
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/// To keep things simple and avoid error-prone lowering APIs that
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+
/// would extract more information about whether instruction merging
|
292
|
+
/// happens or not (we don't have that info now, and it would be
|
293
|
+
/// difficult to refactor to get it and make that refactor 100%
|
294
|
+
/// correct), we give up on the above "can become unique if not
|
295
|
+
/// actually merged" point. Instead, we compute a
|
296
|
+
/// transitive-uniqueness. That is what this enum represents.
|
297
|
+
///
|
298
|
+
/// To define it plainly: a value is `Unused` if no references exist
|
299
|
+
/// to it; `Once` if only one other op refers to it, *and* that other
|
300
|
+
/// op is `Unused` or `Once`; and `Multiple` otherwise. In other
|
301
|
+
/// words, `Multiple` is contagious: even if an op's result value is
|
302
|
+
/// directly used only once in the CLIF, that value is `Multiple` if
|
303
|
+
/// the op that uses it is itself used multiple times (hence could be
|
304
|
+
/// codegen'd multiple times). In brief, this analysis tells us
|
305
|
+
/// whether, if every op merged all of its operand tree, a given op
|
306
|
+
/// could be codegen'd in more than one place.
|
307
|
+
///
|
308
|
+
/// To compute this, we first consider direct uses. At this point
|
309
|
+
/// `Unused` answers are correct, `Multiple` answers are correct, but
|
310
|
+
/// some `Once`s may change to `Multiple`s. Then we propagate
|
311
|
+
/// `Multiple` transitively using a workqueue/fixpoint algorithm.
|
312
|
+
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
|
313
|
+
enum ValueUseState {
|
314
|
+
/// Not used at all.
|
315
|
+
Unused,
|
316
|
+
/// Used exactly once.
|
317
|
+
Once,
|
318
|
+
/// Used multiple times.
|
319
|
+
Multiple,
|
320
|
+
}
|
321
|
+
|
322
|
+
impl ValueUseState {
|
323
|
+
/// Add one use.
|
324
|
+
fn inc(&mut self) {
|
325
|
+
let new = match self {
|
326
|
+
Self::Unused => Self::Once,
|
327
|
+
Self::Once | Self::Multiple => Self::Multiple,
|
328
|
+
};
|
329
|
+
*self = new;
|
330
|
+
}
|
331
|
+
}
|
332
|
+
|
333
|
+
/// Notion of "relocation distance". This gives an estimate of how far away a symbol will be from a
|
334
|
+
/// reference.
|
335
|
+
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
|
336
|
+
pub enum RelocDistance {
|
337
|
+
/// Target of relocation is "nearby". The threshold for this is fuzzy but should be interpreted
|
338
|
+
/// as approximately "within the compiled output of one module"; e.g., within AArch64's +/-
|
339
|
+
/// 128MB offset. If unsure, use `Far` instead.
|
340
|
+
Near,
|
341
|
+
/// Target of relocation could be anywhere in the address space.
|
342
|
+
Far,
|
343
|
+
}
|
344
|
+
|
345
|
+
impl<'func, I: VCodeInst> Lower<'func, I> {
|
346
|
+
/// Prepare a new lowering context for the given IR function.
|
347
|
+
pub fn new(
|
348
|
+
f: &'func Function,
|
349
|
+
abi: Callee<I::ABIMachineSpec>,
|
350
|
+
emit_info: I::Info,
|
351
|
+
block_order: BlockLoweringOrder,
|
352
|
+
sigs: SigSet,
|
353
|
+
flags: Flags,
|
354
|
+
) -> CodegenResult<Self> {
|
355
|
+
let constants = VCodeConstants::with_capacity(f.dfg.constants.len());
|
356
|
+
let vcode = VCodeBuilder::new(
|
357
|
+
sigs,
|
358
|
+
abi,
|
359
|
+
emit_info,
|
360
|
+
block_order,
|
361
|
+
constants,
|
362
|
+
VCodeBuildDirection::Backward,
|
363
|
+
);
|
364
|
+
|
365
|
+
// We usually need two VRegs per instruction result, plus extras for
|
366
|
+
// various temporaries, but two per Value is a good starting point.
|
367
|
+
let mut vregs = VRegAllocator::with_capacity(f.dfg.num_values() * 2);
|
368
|
+
|
369
|
+
let mut value_regs = SecondaryMap::with_default(ValueRegs::invalid());
|
370
|
+
|
371
|
+
// Assign a vreg to each block param and each inst result.
|
372
|
+
for bb in f.layout.blocks() {
|
373
|
+
for ¶m in f.dfg.block_params(bb) {
|
374
|
+
let ty = f.dfg.value_type(param);
|
375
|
+
if value_regs[param].is_invalid() {
|
376
|
+
let regs = vregs.alloc_with_maybe_fact(ty, f.dfg.facts[param].clone())?;
|
377
|
+
value_regs[param] = regs;
|
378
|
+
trace!("bb {} param {}: regs {:?}", bb, param, regs);
|
379
|
+
}
|
380
|
+
}
|
381
|
+
for inst in f.layout.block_insts(bb) {
|
382
|
+
for &result in f.dfg.inst_results(inst) {
|
383
|
+
let ty = f.dfg.value_type(result);
|
384
|
+
if value_regs[result].is_invalid() && !ty.is_invalid() {
|
385
|
+
let regs = vregs.alloc_with_maybe_fact(ty, f.dfg.facts[result].clone())?;
|
386
|
+
value_regs[result] = regs;
|
387
|
+
trace!(
|
388
|
+
"bb {} inst {} ({:?}): result {} regs {:?}",
|
389
|
+
bb,
|
390
|
+
inst,
|
391
|
+
f.dfg.insts[inst],
|
392
|
+
result,
|
393
|
+
regs,
|
394
|
+
);
|
395
|
+
}
|
396
|
+
}
|
397
|
+
}
|
398
|
+
}
|
399
|
+
|
400
|
+
// Find the sret register, if it's used.
|
401
|
+
let mut sret_param = None;
|
402
|
+
for ret in vcode.abi().signature().returns.iter() {
|
403
|
+
if ret.purpose == ArgumentPurpose::StructReturn {
|
404
|
+
let entry_bb = f.stencil.layout.entry_block().unwrap();
|
405
|
+
for (¶m, sig_param) in f
|
406
|
+
.dfg
|
407
|
+
.block_params(entry_bb)
|
408
|
+
.iter()
|
409
|
+
.zip(vcode.abi().signature().params.iter())
|
410
|
+
{
|
411
|
+
if sig_param.purpose == ArgumentPurpose::StructReturn {
|
412
|
+
assert!(sret_param.is_none());
|
413
|
+
sret_param = Some(param);
|
414
|
+
}
|
415
|
+
}
|
416
|
+
|
417
|
+
assert!(sret_param.is_some());
|
418
|
+
}
|
419
|
+
}
|
420
|
+
|
421
|
+
let sret_reg = sret_param.map(|param| {
|
422
|
+
let regs = value_regs[param];
|
423
|
+
assert!(regs.len() == 1);
|
424
|
+
regs
|
425
|
+
});
|
426
|
+
|
427
|
+
// Compute instruction colors, find constant instructions, and find instructions with
|
428
|
+
// side-effects, in one combined pass.
|
429
|
+
let mut cur_color = 0;
|
430
|
+
let mut block_end_colors = SecondaryMap::with_default(InstColor::new(0));
|
431
|
+
let mut side_effect_inst_entry_colors = FxHashMap::default();
|
432
|
+
let mut inst_constants = FxHashMap::default();
|
433
|
+
for bb in f.layout.blocks() {
|
434
|
+
cur_color += 1;
|
435
|
+
for inst in f.layout.block_insts(bb) {
|
436
|
+
let side_effect = has_lowering_side_effect(f, inst);
|
437
|
+
|
438
|
+
trace!("bb {} inst {} has color {}", bb, inst, cur_color);
|
439
|
+
if side_effect {
|
440
|
+
side_effect_inst_entry_colors.insert(inst, InstColor::new(cur_color));
|
441
|
+
trace!(" -> side-effecting; incrementing color for next inst");
|
442
|
+
cur_color += 1;
|
443
|
+
}
|
444
|
+
|
445
|
+
// Determine if this is a constant; if so, add to the table.
|
446
|
+
if let Some(c) = is_constant_64bit(f, inst) {
|
447
|
+
trace!(" -> constant: {}", c);
|
448
|
+
inst_constants.insert(inst, c);
|
449
|
+
}
|
450
|
+
}
|
451
|
+
|
452
|
+
block_end_colors[bb] = InstColor::new(cur_color);
|
453
|
+
}
|
454
|
+
|
455
|
+
let value_ir_uses = Self::compute_use_states(f, sret_param);
|
456
|
+
|
457
|
+
Ok(Lower {
|
458
|
+
f,
|
459
|
+
vcode,
|
460
|
+
vregs,
|
461
|
+
value_regs,
|
462
|
+
sret_reg,
|
463
|
+
block_end_colors,
|
464
|
+
side_effect_inst_entry_colors,
|
465
|
+
inst_constants,
|
466
|
+
value_ir_uses,
|
467
|
+
value_lowered_uses: SecondaryMap::default(),
|
468
|
+
inst_sunk: FxHashSet::default(),
|
469
|
+
cur_scan_entry_color: None,
|
470
|
+
cur_inst: None,
|
471
|
+
ir_insts: vec![],
|
472
|
+
pinned_reg: None,
|
473
|
+
flags,
|
474
|
+
})
|
475
|
+
}
|
476
|
+
|
477
|
+
pub fn sigs(&self) -> &SigSet {
|
478
|
+
self.vcode.sigs()
|
479
|
+
}
|
480
|
+
|
481
|
+
pub fn sigs_mut(&mut self) -> &mut SigSet {
|
482
|
+
self.vcode.sigs_mut()
|
483
|
+
}
|
484
|
+
|
485
|
+
/// Pre-analysis: compute `value_ir_uses`. See comment on
|
486
|
+
/// `ValueUseState` for a description of what this analysis
|
487
|
+
/// computes.
|
488
|
+
fn compute_use_states<'a>(
|
489
|
+
f: &'a Function,
|
490
|
+
sret_param: Option<Value>,
|
491
|
+
) -> SecondaryMap<Value, ValueUseState> {
|
492
|
+
// We perform the analysis without recursion, so we don't
|
493
|
+
// overflow the stack on long chains of ops in the input.
|
494
|
+
//
|
495
|
+
// This is sort of a hybrid of a "shallow use-count" pass and
|
496
|
+
// a DFS. We iterate over all instructions and mark their args
|
497
|
+
// as used. However when we increment a use-count to
|
498
|
+
// "Multiple" we push its args onto the stack and do a DFS,
|
499
|
+
// immediately marking the whole dependency tree as
|
500
|
+
// Multiple. Doing both (shallow use-counting over all insts,
|
501
|
+
// and deep Multiple propagation) lets us trim both
|
502
|
+
// traversals, stopping recursion when a node is already at
|
503
|
+
// the appropriate state.
|
504
|
+
//
|
505
|
+
// In particular, note that the *coarsening* into {Unused,
|
506
|
+
// Once, Multiple} is part of what makes this pass more
|
507
|
+
// efficient than a full indirect-use-counting pass.
|
508
|
+
|
509
|
+
let mut value_ir_uses = SecondaryMap::with_default(ValueUseState::Unused);
|
510
|
+
|
511
|
+
if let Some(sret_param) = sret_param {
|
512
|
+
// There's an implicit use of the struct-return parameter in each
|
513
|
+
// copy of the function epilogue, which we count here.
|
514
|
+
value_ir_uses[sret_param] = ValueUseState::Multiple;
|
515
|
+
}
|
516
|
+
|
517
|
+
// Stack of iterators over Values as we do DFS to mark
|
518
|
+
// Multiple-state subtrees. The iterator type is whatever is
|
519
|
+
// returned by `uses` below.
|
520
|
+
let mut stack: SmallVec<[_; 16]> = smallvec![];
|
521
|
+
|
522
|
+
// Find the args for the inst corresponding to the given value.
|
523
|
+
let uses = |value| {
|
524
|
+
trace!(" -> pushing args for {} onto stack", value);
|
525
|
+
if let ValueDef::Result(src_inst, _) = f.dfg.value_def(value) {
|
526
|
+
Some(f.dfg.inst_values(src_inst))
|
527
|
+
} else {
|
528
|
+
None
|
529
|
+
}
|
530
|
+
};
|
531
|
+
|
532
|
+
// Do a DFS through `value_ir_uses` to mark a subtree as
|
533
|
+
// Multiple.
|
534
|
+
for inst in f
|
535
|
+
.layout
|
536
|
+
.blocks()
|
537
|
+
.flat_map(|block| f.layout.block_insts(block))
|
538
|
+
{
|
539
|
+
// If this inst produces multiple values, we must mark all
|
540
|
+
// of its args as Multiple, because otherwise two uses
|
541
|
+
// could come in as Once on our two different results.
|
542
|
+
let force_multiple = f.dfg.inst_results(inst).len() > 1;
|
543
|
+
|
544
|
+
// Iterate over all values used by all instructions, noting an
|
545
|
+
// additional use on each operand.
|
546
|
+
for arg in f.dfg.inst_values(inst) {
|
547
|
+
let arg = f.dfg.resolve_aliases(arg);
|
548
|
+
let old = value_ir_uses[arg];
|
549
|
+
if force_multiple {
|
550
|
+
trace!(
|
551
|
+
"forcing arg {} to Multiple because of multiple results of user inst",
|
552
|
+
arg
|
553
|
+
);
|
554
|
+
value_ir_uses[arg] = ValueUseState::Multiple;
|
555
|
+
} else {
|
556
|
+
value_ir_uses[arg].inc();
|
557
|
+
}
|
558
|
+
let new = value_ir_uses[arg];
|
559
|
+
trace!("arg {} used, old state {:?}, new {:?}", arg, old, new);
|
560
|
+
|
561
|
+
// On transition to Multiple, do DFS.
|
562
|
+
if old == ValueUseState::Multiple || new != ValueUseState::Multiple {
|
563
|
+
continue;
|
564
|
+
}
|
565
|
+
if let Some(iter) = uses(arg) {
|
566
|
+
stack.push(iter);
|
567
|
+
}
|
568
|
+
while let Some(iter) = stack.last_mut() {
|
569
|
+
if let Some(value) = iter.next() {
|
570
|
+
let value = f.dfg.resolve_aliases(value);
|
571
|
+
trace!(" -> DFS reaches {}", value);
|
572
|
+
if value_ir_uses[value] == ValueUseState::Multiple {
|
573
|
+
// Truncate DFS here: no need to go further,
|
574
|
+
// as whole subtree must already be Multiple.
|
575
|
+
// With debug asserts, check one level of
|
576
|
+
// that invariant at least.
|
577
|
+
debug_assert!(uses(value).into_iter().flatten().all(|arg| {
|
578
|
+
let arg = f.dfg.resolve_aliases(arg);
|
579
|
+
value_ir_uses[arg] == ValueUseState::Multiple
|
580
|
+
}));
|
581
|
+
continue;
|
582
|
+
}
|
583
|
+
value_ir_uses[value] = ValueUseState::Multiple;
|
584
|
+
trace!(" -> became Multiple");
|
585
|
+
if let Some(iter) = uses(value) {
|
586
|
+
stack.push(iter);
|
587
|
+
}
|
588
|
+
} else {
|
589
|
+
// Empty iterator, discard.
|
590
|
+
stack.pop();
|
591
|
+
}
|
592
|
+
}
|
593
|
+
}
|
594
|
+
}
|
595
|
+
|
596
|
+
value_ir_uses
|
597
|
+
}
|
598
|
+
|
599
|
+
fn gen_arg_setup(&mut self) {
|
600
|
+
if let Some(entry_bb) = self.f.layout.entry_block() {
|
601
|
+
trace!(
|
602
|
+
"gen_arg_setup: entry BB {} args are:\n{:?}",
|
603
|
+
entry_bb,
|
604
|
+
self.f.dfg.block_params(entry_bb)
|
605
|
+
);
|
606
|
+
|
607
|
+
for (i, param) in self.f.dfg.block_params(entry_bb).iter().enumerate() {
|
608
|
+
if self.value_ir_uses[*param] == ValueUseState::Unused {
|
609
|
+
continue;
|
610
|
+
}
|
611
|
+
let regs = writable_value_regs(self.value_regs[*param]);
|
612
|
+
for insn in self
|
613
|
+
.vcode
|
614
|
+
.vcode
|
615
|
+
.abi
|
616
|
+
.gen_copy_arg_to_regs(&self.vcode.vcode.sigs, i, regs, &mut self.vregs)
|
617
|
+
.into_iter()
|
618
|
+
{
|
619
|
+
self.emit(insn);
|
620
|
+
}
|
621
|
+
}
|
622
|
+
if let Some(insn) = self
|
623
|
+
.vcode
|
624
|
+
.vcode
|
625
|
+
.abi
|
626
|
+
.gen_retval_area_setup(&self.vcode.vcode.sigs, &mut self.vregs)
|
627
|
+
{
|
628
|
+
self.emit(insn);
|
629
|
+
}
|
630
|
+
|
631
|
+
// The `args` instruction below must come first. Finish
|
632
|
+
// the current "IR inst" (with a default source location,
|
633
|
+
// as for other special instructions inserted during
|
634
|
+
// lowering) and continue the scan backward.
|
635
|
+
self.finish_ir_inst(Default::default());
|
636
|
+
|
637
|
+
if let Some(insn) = self.vcode.vcode.abi.take_args() {
|
638
|
+
self.emit(insn);
|
639
|
+
}
|
640
|
+
}
|
641
|
+
}
|
642
|
+
|
643
|
+
/// Generate the return instruction.
|
644
|
+
pub fn gen_return(&mut self, rets: Vec<ValueRegs<Reg>>) {
|
645
|
+
let mut out_rets = vec![];
|
646
|
+
|
647
|
+
let mut rets = rets.into_iter();
|
648
|
+
for (i, ret) in self
|
649
|
+
.abi()
|
650
|
+
.signature()
|
651
|
+
.returns
|
652
|
+
.clone()
|
653
|
+
.into_iter()
|
654
|
+
.enumerate()
|
655
|
+
{
|
656
|
+
let regs = if ret.purpose == ArgumentPurpose::StructReturn {
|
657
|
+
self.sret_reg.unwrap().clone()
|
658
|
+
} else {
|
659
|
+
rets.next().unwrap()
|
660
|
+
};
|
661
|
+
|
662
|
+
let (regs, insns) = self.vcode.abi().gen_copy_regs_to_retval(
|
663
|
+
self.vcode.sigs(),
|
664
|
+
i,
|
665
|
+
regs,
|
666
|
+
&mut self.vregs,
|
667
|
+
);
|
668
|
+
out_rets.extend(regs);
|
669
|
+
for insn in insns {
|
670
|
+
self.emit(insn);
|
671
|
+
}
|
672
|
+
}
|
673
|
+
|
674
|
+
// Hack: generate a virtual instruction that uses vmctx in
|
675
|
+
// order to keep it alive for the duration of the function,
|
676
|
+
// for the benefit of debuginfo.
|
677
|
+
if self.f.dfg.values_labels.is_some() {
|
678
|
+
if let Some(vmctx_val) = self.f.special_param(ArgumentPurpose::VMContext) {
|
679
|
+
if self.value_ir_uses[vmctx_val] != ValueUseState::Unused {
|
680
|
+
let vmctx_reg = self.value_regs[vmctx_val].only_reg().unwrap();
|
681
|
+
self.emit(I::gen_dummy_use(vmctx_reg));
|
682
|
+
}
|
683
|
+
}
|
684
|
+
}
|
685
|
+
|
686
|
+
let inst = self.abi().gen_rets(out_rets);
|
687
|
+
self.emit(inst);
|
688
|
+
}
|
689
|
+
|
690
|
+
/// Has this instruction been sunk to a use-site (i.e., away from its
|
691
|
+
/// original location)?
|
692
|
+
fn is_inst_sunk(&self, inst: Inst) -> bool {
|
693
|
+
self.inst_sunk.contains(&inst)
|
694
|
+
}
|
695
|
+
|
696
|
+
// Is any result of this instruction needed?
|
697
|
+
fn is_any_inst_result_needed(&self, inst: Inst) -> bool {
|
698
|
+
self.f
|
699
|
+
.dfg
|
700
|
+
.inst_results(inst)
|
701
|
+
.iter()
|
702
|
+
.any(|&result| self.value_lowered_uses[result] > 0)
|
703
|
+
}
|
704
|
+
|
705
|
+
fn lower_clif_block<B: LowerBackend<MInst = I>>(
|
706
|
+
&mut self,
|
707
|
+
backend: &B,
|
708
|
+
block: Block,
|
709
|
+
ctrl_plane: &mut ControlPlane,
|
710
|
+
) -> CodegenResult<()> {
|
711
|
+
self.cur_scan_entry_color = Some(self.block_end_colors[block]);
|
712
|
+
// Lowering loop:
|
713
|
+
// - For each non-branch instruction, in reverse order:
|
714
|
+
// - If side-effecting (load, store, branch/call/return,
|
715
|
+
// possible trap), or if used outside of this block, or if
|
716
|
+
// demanded by another inst, then lower.
|
717
|
+
//
|
718
|
+
// That's it! Lowering of side-effecting ops will force all *needed*
|
719
|
+
// (live) non-side-effecting ops to be lowered at the right places, via
|
720
|
+
// the `use_input_reg()` callback on the `Lower` (that's us). That's
|
721
|
+
// because `use_input_reg()` sets the eager/demand bit for any insts
|
722
|
+
// whose result registers are used.
|
723
|
+
//
|
724
|
+
// We set the VCodeBuilder to "backward" mode, so we emit
|
725
|
+
// blocks in reverse order wrt the BlockIndex sequence, and
|
726
|
+
// emit instructions in reverse order within blocks. Because
|
727
|
+
// the machine backend calls `ctx.emit()` in forward order, we
|
728
|
+
// collect per-IR-inst lowered instructions in `ir_insts`,
|
729
|
+
// then reverse these and append to the VCode at the end of
|
730
|
+
// each IR instruction.
|
731
|
+
for inst in self.f.layout.block_insts(block).rev() {
|
732
|
+
let data = &self.f.dfg.insts[inst];
|
733
|
+
let has_side_effect = has_lowering_side_effect(self.f, inst);
|
734
|
+
// If inst has been sunk to another location, skip it.
|
735
|
+
if self.is_inst_sunk(inst) {
|
736
|
+
continue;
|
737
|
+
}
|
738
|
+
// Are any outputs used at least once?
|
739
|
+
let value_needed = self.is_any_inst_result_needed(inst);
|
740
|
+
trace!(
|
741
|
+
"lower_clif_block: block {} inst {} ({:?}) is_branch {} side_effect {} value_needed {}",
|
742
|
+
block,
|
743
|
+
inst,
|
744
|
+
data,
|
745
|
+
data.opcode().is_branch(),
|
746
|
+
has_side_effect,
|
747
|
+
value_needed,
|
748
|
+
);
|
749
|
+
|
750
|
+
// Update scan state to color prior to this inst (as we are scanning
|
751
|
+
// backward).
|
752
|
+
self.cur_inst = Some(inst);
|
753
|
+
if has_side_effect {
|
754
|
+
let entry_color = *self
|
755
|
+
.side_effect_inst_entry_colors
|
756
|
+
.get(&inst)
|
757
|
+
.expect("every side-effecting inst should have a color-map entry");
|
758
|
+
self.cur_scan_entry_color = Some(entry_color);
|
759
|
+
}
|
760
|
+
|
761
|
+
// Skip lowering branches; these are handled separately
|
762
|
+
// (see `lower_clif_branches()` below).
|
763
|
+
if self.f.dfg.insts[inst].opcode().is_branch() {
|
764
|
+
continue;
|
765
|
+
}
|
766
|
+
|
767
|
+
// Normal instruction: codegen if the instruction is side-effecting
|
768
|
+
// or any of its outputs is used.
|
769
|
+
if has_side_effect || value_needed {
|
770
|
+
trace!("lowering: inst {}: {:?}", inst, self.f.dfg.insts[inst]);
|
771
|
+
let temp_regs = backend.lower(self, inst).unwrap_or_else(|| {
|
772
|
+
let ty = if self.num_outputs(inst) > 0 {
|
773
|
+
Some(self.output_ty(inst, 0))
|
774
|
+
} else {
|
775
|
+
None
|
776
|
+
};
|
777
|
+
panic!(
|
778
|
+
"should be implemented in ISLE: inst = `{}`, type = `{:?}`",
|
779
|
+
self.f.dfg.display_inst(inst),
|
780
|
+
ty
|
781
|
+
)
|
782
|
+
});
|
783
|
+
|
784
|
+
// The ISLE generated code emits its own registers to define the
|
785
|
+
// instruction's lowered values in. However, other instructions
|
786
|
+
// that use this SSA value will be lowered assuming that the value
|
787
|
+
// is generated into a pre-assigned, different, register.
|
788
|
+
//
|
789
|
+
// To connect the two, we set up "aliases" in the VCodeBuilder
|
790
|
+
// that apply when it is building the Operand table for the
|
791
|
+
// regalloc to use. These aliases effectively rewrite any use of
|
792
|
+
// the pre-assigned register to the register that was returned by
|
793
|
+
// the ISLE lowering logic.
|
794
|
+
let results = self.f.dfg.inst_results(inst);
|
795
|
+
debug_assert_eq!(temp_regs.len(), results.len());
|
796
|
+
for (regs, &result) in temp_regs.iter().zip(results) {
|
797
|
+
let dsts = self.value_regs[result];
|
798
|
+
debug_assert_eq!(regs.len(), dsts.len());
|
799
|
+
for (&dst, &temp) in dsts.regs().iter().zip(regs.regs()) {
|
800
|
+
trace!("set vreg alias: {result:?} = {dst:?}, lowering = {temp:?}");
|
801
|
+
self.vregs.set_vreg_alias(dst, temp);
|
802
|
+
}
|
803
|
+
}
|
804
|
+
}
|
805
|
+
|
806
|
+
let loc = self.srcloc(inst);
|
807
|
+
self.finish_ir_inst(loc);
|
808
|
+
|
809
|
+
// maybe insert random instruction
|
810
|
+
if ctrl_plane.get_decision() {
|
811
|
+
if ctrl_plane.get_decision() {
|
812
|
+
let imm: u64 = ctrl_plane.get_arbitrary();
|
813
|
+
let reg = self.alloc_tmp(crate::ir::types::I64).regs()[0];
|
814
|
+
I::gen_imm_u64(imm, reg).map(|inst| self.emit(inst));
|
815
|
+
} else {
|
816
|
+
let imm: f64 = ctrl_plane.get_arbitrary();
|
817
|
+
let tmp = self.alloc_tmp(crate::ir::types::I64).regs()[0];
|
818
|
+
let reg = self.alloc_tmp(crate::ir::types::F64).regs()[0];
|
819
|
+
for inst in I::gen_imm_f64(imm, tmp, reg) {
|
820
|
+
self.emit(inst);
|
821
|
+
}
|
822
|
+
}
|
823
|
+
}
|
824
|
+
|
825
|
+
// Emit value-label markers if needed, to later recover
|
826
|
+
// debug mappings. This must happen before the instruction
|
827
|
+
// (so after we emit, in bottom-to-top pass).
|
828
|
+
self.emit_value_label_markers_for_inst(inst);
|
829
|
+
}
|
830
|
+
|
831
|
+
// Add the block params to this block.
|
832
|
+
self.add_block_params(block)?;
|
833
|
+
|
834
|
+
self.cur_scan_entry_color = None;
|
835
|
+
Ok(())
|
836
|
+
}
|
837
|
+
|
838
|
+
fn add_block_params(&mut self, block: Block) -> CodegenResult<()> {
|
839
|
+
for ¶m in self.f.dfg.block_params(block) {
|
840
|
+
for ® in self.value_regs[param].regs() {
|
841
|
+
let vreg = reg.to_virtual_reg().unwrap();
|
842
|
+
self.vcode.add_block_param(vreg);
|
843
|
+
}
|
844
|
+
}
|
845
|
+
Ok(())
|
846
|
+
}
|
847
|
+
|
848
|
+
fn get_value_labels<'a>(&'a self, val: Value, depth: usize) -> Option<&'a [ValueLabelStart]> {
|
849
|
+
if let Some(ref values_labels) = self.f.dfg.values_labels {
|
850
|
+
trace!(
|
851
|
+
"get_value_labels: val {} -> {} -> {:?}",
|
852
|
+
val,
|
853
|
+
self.f.dfg.resolve_aliases(val),
|
854
|
+
values_labels.get(&self.f.dfg.resolve_aliases(val))
|
855
|
+
);
|
856
|
+
let val = self.f.dfg.resolve_aliases(val);
|
857
|
+
match values_labels.get(&val) {
|
858
|
+
Some(&ValueLabelAssignments::Starts(ref list)) => Some(&list[..]),
|
859
|
+
Some(&ValueLabelAssignments::Alias { value, .. }) if depth < 10 => {
|
860
|
+
self.get_value_labels(value, depth + 1)
|
861
|
+
}
|
862
|
+
_ => None,
|
863
|
+
}
|
864
|
+
} else {
|
865
|
+
None
|
866
|
+
}
|
867
|
+
}
|
868
|
+
|
869
|
+
fn emit_value_label_marks_for_value(&mut self, val: Value) {
|
870
|
+
let regs = self.value_regs[val];
|
871
|
+
if regs.len() > 1 {
|
872
|
+
return;
|
873
|
+
}
|
874
|
+
let reg = regs.only_reg().unwrap();
|
875
|
+
|
876
|
+
if let Some(label_starts) = self.get_value_labels(val, 0) {
|
877
|
+
let labels = label_starts
|
878
|
+
.iter()
|
879
|
+
.map(|&ValueLabelStart { label, .. }| label)
|
880
|
+
.collect::<FxHashSet<_>>();
|
881
|
+
for label in labels {
|
882
|
+
trace!(
|
883
|
+
"value labeling: defines val {:?} -> reg {:?} -> label {:?}",
|
884
|
+
val,
|
885
|
+
reg,
|
886
|
+
label,
|
887
|
+
);
|
888
|
+
self.vcode.add_value_label(reg, label);
|
889
|
+
}
|
890
|
+
}
|
891
|
+
}
|
892
|
+
|
893
|
+
fn emit_value_label_markers_for_inst(&mut self, inst: Inst) {
|
894
|
+
if self.f.dfg.values_labels.is_none() {
|
895
|
+
return;
|
896
|
+
}
|
897
|
+
|
898
|
+
trace!(
|
899
|
+
"value labeling: srcloc {}: inst {}",
|
900
|
+
self.srcloc(inst),
|
901
|
+
inst
|
902
|
+
);
|
903
|
+
for &val in self.f.dfg.inst_results(inst) {
|
904
|
+
self.emit_value_label_marks_for_value(val);
|
905
|
+
}
|
906
|
+
}
|
907
|
+
|
908
|
+
fn emit_value_label_markers_for_block_args(&mut self, block: Block) {
|
909
|
+
if self.f.dfg.values_labels.is_none() {
|
910
|
+
return;
|
911
|
+
}
|
912
|
+
|
913
|
+
trace!("value labeling: block {}", block);
|
914
|
+
for &arg in self.f.dfg.block_params(block) {
|
915
|
+
self.emit_value_label_marks_for_value(arg);
|
916
|
+
}
|
917
|
+
self.finish_ir_inst(Default::default());
|
918
|
+
}
|
919
|
+
|
920
|
+
fn finish_ir_inst(&mut self, loc: RelSourceLoc) {
|
921
|
+
// The VCodeBuilder builds in reverse order (and reverses at
|
922
|
+
// the end), but `ir_insts` is in forward order, so reverse
|
923
|
+
// it.
|
924
|
+
for inst in self.ir_insts.drain(..).rev() {
|
925
|
+
self.vcode.push(inst, loc);
|
926
|
+
}
|
927
|
+
}
|
928
|
+
|
929
|
+
fn finish_bb(&mut self) {
|
930
|
+
self.vcode.end_bb();
|
931
|
+
}
|
932
|
+
|
933
|
+
fn lower_clif_branches<B: LowerBackend<MInst = I>>(
|
934
|
+
&mut self,
|
935
|
+
backend: &B,
|
936
|
+
// Lowered block index:
|
937
|
+
bindex: BlockIndex,
|
938
|
+
// Original CLIF block:
|
939
|
+
block: Block,
|
940
|
+
branch: Inst,
|
941
|
+
targets: &[MachLabel],
|
942
|
+
) -> CodegenResult<()> {
|
943
|
+
trace!(
|
944
|
+
"lower_clif_branches: block {} branch {:?} targets {:?}",
|
945
|
+
block,
|
946
|
+
branch,
|
947
|
+
targets,
|
948
|
+
);
|
949
|
+
// When considering code-motion opportunities, consider the current
|
950
|
+
// program point to be this branch.
|
951
|
+
self.cur_inst = Some(branch);
|
952
|
+
|
953
|
+
// Lower the branch in ISLE.
|
954
|
+
backend
|
955
|
+
.lower_branch(self, branch, targets)
|
956
|
+
.unwrap_or_else(|| {
|
957
|
+
panic!(
|
958
|
+
"should be implemented in ISLE: branch = `{}`",
|
959
|
+
self.f.dfg.display_inst(branch),
|
960
|
+
)
|
961
|
+
});
|
962
|
+
let loc = self.srcloc(branch);
|
963
|
+
self.finish_ir_inst(loc);
|
964
|
+
// Add block param outputs for current block.
|
965
|
+
self.lower_branch_blockparam_args(bindex);
|
966
|
+
Ok(())
|
967
|
+
}
|
968
|
+
|
969
|
+
fn lower_branch_blockparam_args(&mut self, block: BlockIndex) {
|
970
|
+
// TODO: why not make `block_order` public?
|
971
|
+
for succ_idx in 0..self.vcode.block_order().succ_indices(block).1.len() {
|
972
|
+
// Avoid immutable borrow by explicitly indexing.
|
973
|
+
let (opt_inst, succs) = self.vcode.block_order().succ_indices(block);
|
974
|
+
let inst = opt_inst.expect("lower_branch_blockparam_args called on a critical edge!");
|
975
|
+
let succ = succs[succ_idx];
|
976
|
+
|
977
|
+
// The use of `succ_idx` to index `branch_destination` is valid on the assumption that
|
978
|
+
// the traversal order defined in `visit_block_succs` mirrors the order returned by
|
979
|
+
// `branch_destination`. If that assumption is violated, the branch targets returned
|
980
|
+
// here will not match the clif.
|
981
|
+
let branches = self.f.dfg.insts[inst].branch_destination(&self.f.dfg.jump_tables);
|
982
|
+
let branch_args = branches[succ_idx].args_slice(&self.f.dfg.value_lists);
|
983
|
+
|
984
|
+
let mut branch_arg_vregs: SmallVec<[Reg; 16]> = smallvec![];
|
985
|
+
for &arg in branch_args {
|
986
|
+
let arg = self.f.dfg.resolve_aliases(arg);
|
987
|
+
let regs = self.put_value_in_regs(arg);
|
988
|
+
branch_arg_vregs.extend_from_slice(regs.regs());
|
989
|
+
}
|
990
|
+
self.vcode.add_succ(succ, &branch_arg_vregs[..]);
|
991
|
+
}
|
992
|
+
}
|
993
|
+
|
994
|
+
fn collect_branches_and_targets(
|
995
|
+
&self,
|
996
|
+
bindex: BlockIndex,
|
997
|
+
_bb: Block,
|
998
|
+
targets: &mut SmallVec<[MachLabel; 2]>,
|
999
|
+
) -> Option<Inst> {
|
1000
|
+
targets.clear();
|
1001
|
+
let (opt_inst, succs) = self.vcode.block_order().succ_indices(bindex);
|
1002
|
+
targets.extend(succs.iter().map(|succ| MachLabel::from_block(*succ)));
|
1003
|
+
opt_inst
|
1004
|
+
}
|
1005
|
+
|
1006
|
+
/// Lower the function.
|
1007
|
+
pub fn lower<B: LowerBackend<MInst = I>>(
|
1008
|
+
mut self,
|
1009
|
+
backend: &B,
|
1010
|
+
ctrl_plane: &mut ControlPlane,
|
1011
|
+
) -> CodegenResult<VCode<I>> {
|
1012
|
+
trace!("about to lower function: {:?}", self.f);
|
1013
|
+
|
1014
|
+
self.vcode.init_retval_area(&mut self.vregs)?;
|
1015
|
+
|
1016
|
+
// Get the pinned reg here (we only parameterize this function on `B`,
|
1017
|
+
// not the whole `Lower` impl).
|
1018
|
+
self.pinned_reg = backend.maybe_pinned_reg();
|
1019
|
+
|
1020
|
+
self.vcode.set_entry(BlockIndex::new(0));
|
1021
|
+
|
1022
|
+
// Reused vectors for branch lowering.
|
1023
|
+
let mut targets: SmallVec<[MachLabel; 2]> = SmallVec::new();
|
1024
|
+
|
1025
|
+
// get a copy of the lowered order; we hold this separately because we
|
1026
|
+
// need a mut ref to the vcode to mutate it below.
|
1027
|
+
let lowered_order: SmallVec<[LoweredBlock; 64]> = self
|
1028
|
+
.vcode
|
1029
|
+
.block_order()
|
1030
|
+
.lowered_order()
|
1031
|
+
.iter()
|
1032
|
+
.cloned()
|
1033
|
+
.collect();
|
1034
|
+
|
1035
|
+
// Main lowering loop over lowered blocks.
|
1036
|
+
for (bindex, lb) in lowered_order.iter().enumerate().rev() {
|
1037
|
+
let bindex = BlockIndex::new(bindex);
|
1038
|
+
|
1039
|
+
// Lower the block body in reverse order (see comment in
|
1040
|
+
// `lower_clif_block()` for rationale).
|
1041
|
+
|
1042
|
+
// End branches.
|
1043
|
+
if let Some(bb) = lb.orig_block() {
|
1044
|
+
if let Some(branch) = self.collect_branches_and_targets(bindex, bb, &mut targets) {
|
1045
|
+
self.lower_clif_branches(backend, bindex, bb, branch, &targets)?;
|
1046
|
+
self.finish_ir_inst(self.srcloc(branch));
|
1047
|
+
}
|
1048
|
+
} else {
|
1049
|
+
// If no orig block, this must be a pure edge block;
|
1050
|
+
// get the successor and emit a jump. Add block params
|
1051
|
+
// according to the one successor, and pass them
|
1052
|
+
// through; note that the successor must have an
|
1053
|
+
// original block.
|
1054
|
+
let (_, succs) = self.vcode.block_order().succ_indices(bindex);
|
1055
|
+
let succ = succs[0];
|
1056
|
+
|
1057
|
+
let orig_succ = lowered_order[succ.index()];
|
1058
|
+
let orig_succ = orig_succ
|
1059
|
+
.orig_block()
|
1060
|
+
.expect("Edge block succ must be body block");
|
1061
|
+
|
1062
|
+
let mut branch_arg_vregs: SmallVec<[Reg; 16]> = smallvec![];
|
1063
|
+
for ty in self.f.dfg.block_param_types(orig_succ) {
|
1064
|
+
let regs = self.vregs.alloc(ty)?;
|
1065
|
+
for ® in regs.regs() {
|
1066
|
+
branch_arg_vregs.push(reg);
|
1067
|
+
let vreg = reg.to_virtual_reg().unwrap();
|
1068
|
+
self.vcode.add_block_param(vreg);
|
1069
|
+
}
|
1070
|
+
}
|
1071
|
+
self.vcode.add_succ(succ, &branch_arg_vregs[..]);
|
1072
|
+
|
1073
|
+
self.emit(I::gen_jump(MachLabel::from_block(succ)));
|
1074
|
+
self.finish_ir_inst(Default::default());
|
1075
|
+
}
|
1076
|
+
|
1077
|
+
// Original block body.
|
1078
|
+
if let Some(bb) = lb.orig_block() {
|
1079
|
+
self.lower_clif_block(backend, bb, ctrl_plane)?;
|
1080
|
+
self.emit_value_label_markers_for_block_args(bb);
|
1081
|
+
}
|
1082
|
+
|
1083
|
+
if bindex.index() == 0 {
|
1084
|
+
// Set up the function with arg vreg inits.
|
1085
|
+
self.gen_arg_setup();
|
1086
|
+
self.finish_ir_inst(Default::default());
|
1087
|
+
}
|
1088
|
+
|
1089
|
+
self.finish_bb();
|
1090
|
+
|
1091
|
+
// Check for any deferred vreg-temp allocation errors, and
|
1092
|
+
// bubble one up at this time if it exists.
|
1093
|
+
if let Some(e) = self.vregs.take_deferred_error() {
|
1094
|
+
return Err(e);
|
1095
|
+
}
|
1096
|
+
}
|
1097
|
+
|
1098
|
+
// Now that we've emitted all instructions into the
|
1099
|
+
// VCodeBuilder, let's build the VCode.
|
1100
|
+
trace!(
|
1101
|
+
"built vcode:\n{:?}Backwards {:?}",
|
1102
|
+
&self.vregs,
|
1103
|
+
&self.vcode.vcode
|
1104
|
+
);
|
1105
|
+
let vcode = self.vcode.build(self.vregs);
|
1106
|
+
|
1107
|
+
Ok(vcode)
|
1108
|
+
}
|
1109
|
+
}
|
1110
|
+
|
1111
|
+
/// Function-level queries.
|
1112
|
+
impl<'func, I: VCodeInst> Lower<'func, I> {
|
1113
|
+
pub fn dfg(&self) -> &DataFlowGraph {
|
1114
|
+
&self.f.dfg
|
1115
|
+
}
|
1116
|
+
|
1117
|
+
/// Get the `Callee`.
|
1118
|
+
pub fn abi(&self) -> &Callee<I::ABIMachineSpec> {
|
1119
|
+
self.vcode.abi()
|
1120
|
+
}
|
1121
|
+
|
1122
|
+
/// Get the `Callee`.
|
1123
|
+
pub fn abi_mut(&mut self) -> &mut Callee<I::ABIMachineSpec> {
|
1124
|
+
self.vcode.abi_mut()
|
1125
|
+
}
|
1126
|
+
}
|
1127
|
+
|
1128
|
+
/// Instruction input/output queries.
|
1129
|
+
impl<'func, I: VCodeInst> Lower<'func, I> {
|
1130
|
+
/// Get the instdata for a given IR instruction.
|
1131
|
+
pub fn data(&self, ir_inst: Inst) -> &InstructionData {
|
1132
|
+
&self.f.dfg.insts[ir_inst]
|
1133
|
+
}
|
1134
|
+
|
1135
|
+
/// Likewise, but starting with a GlobalValue identifier.
|
1136
|
+
pub fn symbol_value_data<'b>(
|
1137
|
+
&'b self,
|
1138
|
+
global_value: GlobalValue,
|
1139
|
+
) -> Option<(&'b ExternalName, RelocDistance, i64)> {
|
1140
|
+
let gvdata = &self.f.global_values[global_value];
|
1141
|
+
match gvdata {
|
1142
|
+
&GlobalValueData::Symbol {
|
1143
|
+
ref name,
|
1144
|
+
ref offset,
|
1145
|
+
colocated,
|
1146
|
+
..
|
1147
|
+
} => {
|
1148
|
+
let offset = offset.bits();
|
1149
|
+
let dist = if colocated {
|
1150
|
+
RelocDistance::Near
|
1151
|
+
} else {
|
1152
|
+
RelocDistance::Far
|
1153
|
+
};
|
1154
|
+
Some((name, dist, offset))
|
1155
|
+
}
|
1156
|
+
_ => None,
|
1157
|
+
}
|
1158
|
+
}
|
1159
|
+
|
1160
|
+
/// Returns the memory flags of a given memory access.
|
1161
|
+
pub fn memflags(&self, ir_inst: Inst) -> Option<MemFlags> {
|
1162
|
+
match &self.f.dfg.insts[ir_inst] {
|
1163
|
+
&InstructionData::AtomicCas { flags, .. } => Some(flags),
|
1164
|
+
&InstructionData::AtomicRmw { flags, .. } => Some(flags),
|
1165
|
+
&InstructionData::Load { flags, .. }
|
1166
|
+
| &InstructionData::LoadNoOffset { flags, .. }
|
1167
|
+
| &InstructionData::Store { flags, .. } => Some(flags),
|
1168
|
+
&InstructionData::StoreNoOffset { flags, .. } => Some(flags),
|
1169
|
+
_ => None,
|
1170
|
+
}
|
1171
|
+
}
|
1172
|
+
|
1173
|
+
/// Get the source location for a given instruction.
|
1174
|
+
pub fn srcloc(&self, ir_inst: Inst) -> RelSourceLoc {
|
1175
|
+
self.f.rel_srclocs()[ir_inst]
|
1176
|
+
}
|
1177
|
+
|
1178
|
+
/// Get the number of inputs to the given IR instruction. This is a count only of the Value
|
1179
|
+
/// arguments to the instruction: block arguments will not be included in this count.
|
1180
|
+
pub fn num_inputs(&self, ir_inst: Inst) -> usize {
|
1181
|
+
self.f.dfg.inst_args(ir_inst).len()
|
1182
|
+
}
|
1183
|
+
|
1184
|
+
/// Get the number of outputs to the given IR instruction.
|
1185
|
+
pub fn num_outputs(&self, ir_inst: Inst) -> usize {
|
1186
|
+
self.f.dfg.inst_results(ir_inst).len()
|
1187
|
+
}
|
1188
|
+
|
1189
|
+
/// Get the type for an instruction's input.
|
1190
|
+
pub fn input_ty(&self, ir_inst: Inst, idx: usize) -> Type {
|
1191
|
+
self.value_ty(self.input_as_value(ir_inst, idx))
|
1192
|
+
}
|
1193
|
+
|
1194
|
+
/// Get the type for a value.
|
1195
|
+
pub fn value_ty(&self, val: Value) -> Type {
|
1196
|
+
self.f.dfg.value_type(val)
|
1197
|
+
}
|
1198
|
+
|
1199
|
+
/// Get the type for an instruction's output.
|
1200
|
+
pub fn output_ty(&self, ir_inst: Inst, idx: usize) -> Type {
|
1201
|
+
self.f.dfg.value_type(self.f.dfg.inst_results(ir_inst)[idx])
|
1202
|
+
}
|
1203
|
+
|
1204
|
+
/// Get the value of a constant instruction (`iconst`, etc.) as a 64-bit
|
1205
|
+
/// value, if possible.
|
1206
|
+
pub fn get_constant(&self, ir_inst: Inst) -> Option<u64> {
|
1207
|
+
self.inst_constants.get(&ir_inst).map(|&c| {
|
1208
|
+
// The upper bits must be zero, enforced during legalization and by
|
1209
|
+
// the CLIF verifier.
|
1210
|
+
debug_assert_eq!(c, {
|
1211
|
+
let input_size = self.output_ty(ir_inst, 0).bits() as u64;
|
1212
|
+
let shift = 64 - input_size;
|
1213
|
+
(c << shift) >> shift
|
1214
|
+
});
|
1215
|
+
c
|
1216
|
+
})
|
1217
|
+
}
|
1218
|
+
|
1219
|
+
/// Get the input as one of two options other than a direct register:
|
1220
|
+
///
|
1221
|
+
/// - An instruction, given that it is effect-free or able to sink its
|
1222
|
+
/// effect to the current instruction being lowered, and given it has only
|
1223
|
+
/// one output, and if effect-ful, given that this is the only use;
|
1224
|
+
/// - A constant, if the value is a constant.
|
1225
|
+
///
|
1226
|
+
/// The instruction input may be available in either of these forms. It may
|
1227
|
+
/// be available in neither form, if the conditions are not met; if so, use
|
1228
|
+
/// `put_input_in_regs()` instead to get it in a register.
|
1229
|
+
///
|
1230
|
+
/// If the backend merges the effect of a side-effecting instruction, it
|
1231
|
+
/// must call `sink_inst()`. When this is called, it indicates that the
|
1232
|
+
/// effect has been sunk to the current scan location. The sunk
|
1233
|
+
/// instruction's result(s) must have *no* uses remaining, because it will
|
1234
|
+
/// not be codegen'd (it has been integrated into the current instruction).
|
1235
|
+
pub fn input_as_value(&self, ir_inst: Inst, idx: usize) -> Value {
|
1236
|
+
let val = self.f.dfg.inst_args(ir_inst)[idx];
|
1237
|
+
self.f.dfg.resolve_aliases(val)
|
1238
|
+
}
|
1239
|
+
|
1240
|
+
/// Like `get_input_as_source_or_const` but with a `Value`.
|
1241
|
+
pub fn get_input_as_source_or_const(&self, ir_inst: Inst, idx: usize) -> NonRegInput {
|
1242
|
+
let val = self.input_as_value(ir_inst, idx);
|
1243
|
+
self.get_value_as_source_or_const(val)
|
1244
|
+
}
|
1245
|
+
|
1246
|
+
/// Resolves a particular input of an instruction to the `Value` that it is
|
1247
|
+
/// represented with.
|
1248
|
+
pub fn get_value_as_source_or_const(&self, val: Value) -> NonRegInput {
|
1249
|
+
trace!(
|
1250
|
+
"get_input_for_val: val {} at cur_inst {:?} cur_scan_entry_color {:?}",
|
1251
|
+
val,
|
1252
|
+
self.cur_inst,
|
1253
|
+
self.cur_scan_entry_color,
|
1254
|
+
);
|
1255
|
+
let inst = match self.f.dfg.value_def(val) {
|
1256
|
+
// OK to merge source instruction if (i) we have a source
|
1257
|
+
// instruction, and:
|
1258
|
+
// - It has no side-effects, OR
|
1259
|
+
// - It has a side-effect, has one output value, that one
|
1260
|
+
// output has only one use, directly or indirectly (so
|
1261
|
+
// cannot be duplicated -- see comment on
|
1262
|
+
// `ValueUseState`), and the instruction's color is *one
|
1263
|
+
// less than* the current scan color.
|
1264
|
+
//
|
1265
|
+
// This latter set of conditions is testing whether a
|
1266
|
+
// side-effecting instruction can sink to the current scan
|
1267
|
+
// location; this is possible if the in-color of this inst is
|
1268
|
+
// equal to the out-color of the producing inst, so no other
|
1269
|
+
// side-effecting ops occur between them (which will only be true
|
1270
|
+
// if they are in the same BB, because color increments at each BB
|
1271
|
+
// start).
|
1272
|
+
//
|
1273
|
+
// If it is actually sunk, then in `merge_inst()`, we update the
|
1274
|
+
// scan color so that as we scan over the range past which the
|
1275
|
+
// instruction was sunk, we allow other instructions (that came
|
1276
|
+
// prior to the sunk instruction) to sink.
|
1277
|
+
ValueDef::Result(src_inst, result_idx) => {
|
1278
|
+
let src_side_effect = has_lowering_side_effect(self.f, src_inst);
|
1279
|
+
trace!(" -> src inst {}", src_inst);
|
1280
|
+
trace!(" -> has lowering side effect: {}", src_side_effect);
|
1281
|
+
if !src_side_effect {
|
1282
|
+
// Pure instruction: always possible to
|
1283
|
+
// sink. Let's determine whether we are the only
|
1284
|
+
// user or not.
|
1285
|
+
if self.value_ir_uses[val] == ValueUseState::Once {
|
1286
|
+
InputSourceInst::UniqueUse(src_inst, result_idx)
|
1287
|
+
} else {
|
1288
|
+
InputSourceInst::Use(src_inst, result_idx)
|
1289
|
+
}
|
1290
|
+
} else {
|
1291
|
+
// Side-effect: test whether this is the only use of the
|
1292
|
+
// only result of the instruction, and whether colors allow
|
1293
|
+
// the code-motion.
|
1294
|
+
trace!(
|
1295
|
+
" -> side-effecting op {} for val {}: use state {:?}",
|
1296
|
+
src_inst,
|
1297
|
+
val,
|
1298
|
+
self.value_ir_uses[val]
|
1299
|
+
);
|
1300
|
+
if self.cur_scan_entry_color.is_some()
|
1301
|
+
&& self.value_ir_uses[val] == ValueUseState::Once
|
1302
|
+
&& self.num_outputs(src_inst) == 1
|
1303
|
+
&& self
|
1304
|
+
.side_effect_inst_entry_colors
|
1305
|
+
.get(&src_inst)
|
1306
|
+
.unwrap()
|
1307
|
+
.get()
|
1308
|
+
+ 1
|
1309
|
+
== self.cur_scan_entry_color.unwrap().get()
|
1310
|
+
{
|
1311
|
+
InputSourceInst::UniqueUse(src_inst, 0)
|
1312
|
+
} else {
|
1313
|
+
InputSourceInst::None
|
1314
|
+
}
|
1315
|
+
}
|
1316
|
+
}
|
1317
|
+
_ => InputSourceInst::None,
|
1318
|
+
};
|
1319
|
+
let constant = inst.as_inst().and_then(|(inst, _)| self.get_constant(inst));
|
1320
|
+
|
1321
|
+
NonRegInput { inst, constant }
|
1322
|
+
}
|
1323
|
+
|
1324
|
+
/// Increment the reference count for the Value, ensuring that it gets lowered.
|
1325
|
+
pub fn increment_lowered_uses(&mut self, val: Value) {
|
1326
|
+
self.value_lowered_uses[val] += 1
|
1327
|
+
}
|
1328
|
+
|
1329
|
+
/// Put the `idx`th input into register(s) and return the assigned register.
|
1330
|
+
pub fn put_input_in_regs(&mut self, ir_inst: Inst, idx: usize) -> ValueRegs<Reg> {
|
1331
|
+
let val = self.f.dfg.inst_args(ir_inst)[idx];
|
1332
|
+
self.put_value_in_regs(val)
|
1333
|
+
}
|
1334
|
+
|
1335
|
+
/// Put the given value into register(s) and return the assigned register.
|
1336
|
+
pub fn put_value_in_regs(&mut self, val: Value) -> ValueRegs<Reg> {
|
1337
|
+
let val = self.f.dfg.resolve_aliases(val);
|
1338
|
+
trace!("put_value_in_regs: val {}", val);
|
1339
|
+
|
1340
|
+
if let Some(inst) = self.f.dfg.value_def(val).inst() {
|
1341
|
+
assert!(!self.inst_sunk.contains(&inst));
|
1342
|
+
}
|
1343
|
+
|
1344
|
+
let regs = self.value_regs[val];
|
1345
|
+
trace!(" -> regs {:?}", regs);
|
1346
|
+
assert!(regs.is_valid());
|
1347
|
+
|
1348
|
+
self.value_lowered_uses[val] += 1;
|
1349
|
+
|
1350
|
+
regs
|
1351
|
+
}
|
1352
|
+
}
|
1353
|
+
|
1354
|
+
/// Codegen primitives: allocate temps, emit instructions, set result registers,
|
1355
|
+
/// ask for an input to be gen'd into a register.
|
1356
|
+
impl<'func, I: VCodeInst> Lower<'func, I> {
|
1357
|
+
/// Get a new temp.
|
1358
|
+
pub fn alloc_tmp(&mut self, ty: Type) -> ValueRegs<Writable<Reg>> {
|
1359
|
+
writable_value_regs(self.vregs.alloc_with_deferred_error(ty))
|
1360
|
+
}
|
1361
|
+
|
1362
|
+
/// Emit a machine instruction.
|
1363
|
+
pub fn emit(&mut self, mach_inst: I) {
|
1364
|
+
trace!("emit: {:?}", mach_inst);
|
1365
|
+
self.ir_insts.push(mach_inst);
|
1366
|
+
}
|
1367
|
+
|
1368
|
+
/// Indicate that the side-effect of an instruction has been sunk to the
|
1369
|
+
/// current scan location. This should only be done with the instruction's
|
1370
|
+
/// original results are not used (i.e., `put_input_in_regs` is not invoked
|
1371
|
+
/// for the input produced by the sunk instruction), otherwise the
|
1372
|
+
/// side-effect will occur twice.
|
1373
|
+
pub fn sink_inst(&mut self, ir_inst: Inst) {
|
1374
|
+
assert!(has_lowering_side_effect(self.f, ir_inst));
|
1375
|
+
assert!(self.cur_scan_entry_color.is_some());
|
1376
|
+
|
1377
|
+
for result in self.dfg().inst_results(ir_inst) {
|
1378
|
+
assert!(self.value_lowered_uses[*result] == 0);
|
1379
|
+
}
|
1380
|
+
|
1381
|
+
let sunk_inst_entry_color = self
|
1382
|
+
.side_effect_inst_entry_colors
|
1383
|
+
.get(&ir_inst)
|
1384
|
+
.cloned()
|
1385
|
+
.unwrap();
|
1386
|
+
let sunk_inst_exit_color = InstColor::new(sunk_inst_entry_color.get() + 1);
|
1387
|
+
assert!(sunk_inst_exit_color == self.cur_scan_entry_color.unwrap());
|
1388
|
+
self.cur_scan_entry_color = Some(sunk_inst_entry_color);
|
1389
|
+
self.inst_sunk.insert(ir_inst);
|
1390
|
+
}
|
1391
|
+
|
1392
|
+
/// Retrieve immediate data given a handle.
|
1393
|
+
pub fn get_immediate_data(&self, imm: Immediate) -> &ConstantData {
|
1394
|
+
self.f.dfg.immediates.get(imm).unwrap()
|
1395
|
+
}
|
1396
|
+
|
1397
|
+
/// Retrieve constant data given a handle.
|
1398
|
+
pub fn get_constant_data(&self, constant_handle: Constant) -> &ConstantData {
|
1399
|
+
self.f.dfg.constants.get(constant_handle)
|
1400
|
+
}
|
1401
|
+
|
1402
|
+
/// Indicate that a constant should be emitted.
|
1403
|
+
pub fn use_constant(&mut self, constant: VCodeConstantData) -> VCodeConstant {
|
1404
|
+
self.vcode.constants().insert(constant)
|
1405
|
+
}
|
1406
|
+
|
1407
|
+
/// Cause the value in `reg` to be in a virtual reg, by copying it into a new virtual reg
|
1408
|
+
/// if `reg` is a real reg. `ty` describes the type of the value in `reg`.
|
1409
|
+
pub fn ensure_in_vreg(&mut self, reg: Reg, ty: Type) -> Reg {
|
1410
|
+
if reg.to_virtual_reg().is_some() {
|
1411
|
+
reg
|
1412
|
+
} else {
|
1413
|
+
let new_reg = self.alloc_tmp(ty).only_reg().unwrap();
|
1414
|
+
self.emit(I::gen_move(new_reg, reg, ty));
|
1415
|
+
new_reg.to_reg()
|
1416
|
+
}
|
1417
|
+
}
|
1418
|
+
|
1419
|
+
/// Add a range fact to a register, if no other fact is present.
|
1420
|
+
pub fn add_range_fact(&mut self, reg: Reg, bit_width: u16, min: u64, max: u64) {
|
1421
|
+
if self.flags.enable_pcc() {
|
1422
|
+
self.vregs.set_fact_if_missing(
|
1423
|
+
reg.to_virtual_reg().unwrap(),
|
1424
|
+
Fact::Range {
|
1425
|
+
bit_width,
|
1426
|
+
min,
|
1427
|
+
max,
|
1428
|
+
},
|
1429
|
+
);
|
1430
|
+
}
|
1431
|
+
}
|
1432
|
+
}
|