wasmtime 20.0.2 → 21.0.1

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Files changed (2089) hide show
  1. checksums.yaml +4 -4
  2. data/Cargo.lock +129 -124
  3. data/ext/Cargo.toml +8 -6
  4. data/ext/cargo-vendor/cobs-0.2.3/.cargo-checksum.json +1 -0
  5. data/ext/cargo-vendor/cobs-0.2.3/Cargo.toml +39 -0
  6. data/ext/cargo-vendor/cobs-0.2.3/LICENSE-APACHE +202 -0
  7. data/ext/cargo-vendor/cobs-0.2.3/LICENSE-MIT +19 -0
  8. data/ext/cargo-vendor/cobs-0.2.3/README.md +23 -0
  9. data/ext/cargo-vendor/cobs-0.2.3/src/dec.rs +360 -0
  10. data/ext/cargo-vendor/cobs-0.2.3/src/enc.rs +216 -0
  11. data/ext/cargo-vendor/cobs-0.2.3/src/lib.rs +14 -0
  12. data/ext/cargo-vendor/cobs-0.2.3/tests/test.rs +265 -0
  13. data/ext/cargo-vendor/cranelift-bforest-0.108.1/.cargo-checksum.json +1 -0
  14. data/ext/cargo-vendor/cranelift-bforest-0.108.1/Cargo.toml +40 -0
  15. data/ext/cargo-vendor/cranelift-codegen-0.108.1/.cargo-checksum.json +1 -0
  16. data/ext/cargo-vendor/cranelift-codegen-0.108.1/Cargo.toml +189 -0
  17. data/ext/cargo-vendor/cranelift-codegen-0.108.1/build.rs +266 -0
  18. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/alias_analysis.rs +403 -0
  19. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/context.rs +395 -0
  20. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/ctxhash.rs +167 -0
  21. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/egraph/elaborate.rs +835 -0
  22. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/egraph.rs +839 -0
  23. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/incremental_cache.rs +256 -0
  24. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/ir/instructions.rs +1020 -0
  25. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/aarch64/abi.rs +1580 -0
  26. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/aarch64/inst/args.rs +721 -0
  27. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/aarch64/inst/emit.rs +3846 -0
  28. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/aarch64/inst/emit_tests.rs +7902 -0
  29. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/aarch64/inst/imms.rs +1213 -0
  30. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/aarch64/inst/mod.rs +3094 -0
  31. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/aarch64/inst/regs.rs +288 -0
  32. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/aarch64/inst.isle +4225 -0
  33. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/aarch64/lower/isle.rs +810 -0
  34. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/aarch64/pcc.rs +568 -0
  35. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/mod.rs +449 -0
  36. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/riscv64/abi.rs +1051 -0
  37. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/riscv64/inst/args.rs +1938 -0
  38. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/riscv64/inst/emit.rs +2681 -0
  39. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/riscv64/inst/emit_tests.rs +2197 -0
  40. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/riscv64/inst/mod.rs +1975 -0
  41. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/riscv64/inst/regs.rs +168 -0
  42. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/riscv64/inst/vector.rs +1144 -0
  43. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/riscv64/inst.isle +2969 -0
  44. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/riscv64/lower/isle.rs +625 -0
  45. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/riscv64/lower.isle +2883 -0
  46. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/s390x/abi.rs +1037 -0
  47. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/s390x/inst/args.rs +314 -0
  48. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/s390x/inst/emit.rs +3646 -0
  49. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/s390x/inst/imms.rs +202 -0
  50. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/s390x/inst/mod.rs +3421 -0
  51. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/s390x/inst/regs.rs +180 -0
  52. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/x64/abi.rs +1410 -0
  53. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/x64/inst/args.rs +2256 -0
  54. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/x64/inst/emit.rs +4311 -0
  55. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/x64/inst/emit_tests.rs +5171 -0
  56. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/x64/inst/mod.rs +2838 -0
  57. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/x64/inst/regs.rs +276 -0
  58. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/x64/inst.isle +5294 -0
  59. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/x64/lower/isle.rs +1064 -0
  60. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/x64/lower.isle +4808 -0
  61. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/x64/lower.rs +337 -0
  62. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/isa/x64/pcc.rs +1014 -0
  63. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/lib.rs +106 -0
  64. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/machinst/abi.rs +2506 -0
  65. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/machinst/blockorder.rs +465 -0
  66. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/machinst/isle.rs +903 -0
  67. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/machinst/lower.rs +1432 -0
  68. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/machinst/mod.rs +555 -0
  69. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/machinst/reg.rs +522 -0
  70. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/machinst/valueregs.rs +138 -0
  71. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/machinst/vcode.rs +1741 -0
  72. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/nan_canonicalization.rs +130 -0
  73. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/opts/arithmetic.isle +240 -0
  74. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/opts/icmp.isle +215 -0
  75. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/ranges.rs +131 -0
  76. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/remove_constant_phis.rs +419 -0
  77. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/scoped_hash_map.rs +310 -0
  78. data/ext/cargo-vendor/cranelift-codegen-0.108.1/src/settings.rs +590 -0
  79. data/ext/cargo-vendor/cranelift-codegen-meta-0.108.1/.cargo-checksum.json +1 -0
  80. data/ext/cargo-vendor/cranelift-codegen-meta-0.108.1/Cargo.toml +35 -0
  81. data/ext/cargo-vendor/cranelift-codegen-meta-0.108.1/src/gen_inst.rs +1278 -0
  82. data/ext/cargo-vendor/cranelift-codegen-meta-0.108.1/src/gen_isle.rs +519 -0
  83. data/ext/cargo-vendor/cranelift-codegen-meta-0.108.1/src/gen_settings.rs +508 -0
  84. data/ext/cargo-vendor/cranelift-codegen-meta-0.108.1/src/gen_types.rs +75 -0
  85. data/ext/cargo-vendor/cranelift-codegen-meta-0.108.1/src/isa/riscv64.rs +168 -0
  86. data/ext/cargo-vendor/cranelift-codegen-meta-0.108.1/src/isa/x86.rs +414 -0
  87. data/ext/cargo-vendor/cranelift-codegen-meta-0.108.1/src/isle.rs +126 -0
  88. data/ext/cargo-vendor/cranelift-codegen-meta-0.108.1/src/lib.rs +98 -0
  89. data/ext/cargo-vendor/cranelift-codegen-meta-0.108.1/src/shared/settings.rs +348 -0
  90. data/ext/cargo-vendor/cranelift-codegen-meta-0.108.1/src/srcgen.rs +464 -0
  91. data/ext/cargo-vendor/cranelift-codegen-shared-0.108.1/.cargo-checksum.json +1 -0
  92. data/ext/cargo-vendor/cranelift-codegen-shared-0.108.1/Cargo.toml +22 -0
  93. data/ext/cargo-vendor/cranelift-control-0.108.1/.cargo-checksum.json +1 -0
  94. data/ext/cargo-vendor/cranelift-control-0.108.1/Cargo.toml +30 -0
  95. data/ext/cargo-vendor/cranelift-entity-0.108.1/.cargo-checksum.json +1 -0
  96. data/ext/cargo-vendor/cranelift-entity-0.108.1/Cargo.toml +52 -0
  97. data/ext/cargo-vendor/cranelift-entity-0.108.1/src/lib.rs +381 -0
  98. data/ext/cargo-vendor/cranelift-frontend-0.108.1/.cargo-checksum.json +1 -0
  99. data/ext/cargo-vendor/cranelift-frontend-0.108.1/Cargo.toml +67 -0
  100. data/ext/cargo-vendor/cranelift-frontend-0.108.1/src/switch.rs +696 -0
  101. data/ext/cargo-vendor/cranelift-isle-0.108.1/.cargo-checksum.json +1 -0
  102. data/ext/cargo-vendor/cranelift-isle-0.108.1/Cargo.toml +46 -0
  103. data/ext/cargo-vendor/cranelift-isle-0.108.1/src/codegen.rs +886 -0
  104. data/ext/cargo-vendor/cranelift-isle-0.108.1/src/disjointsets.rs +169 -0
  105. data/ext/cargo-vendor/cranelift-isle-0.108.1/src/lib.rs +33 -0
  106. data/ext/cargo-vendor/cranelift-isle-0.108.1/src/sema.rs +2492 -0
  107. data/ext/cargo-vendor/cranelift-isle-0.108.1/src/serialize.rs +846 -0
  108. data/ext/cargo-vendor/cranelift-isle-0.108.1/src/stablemapset.rs +79 -0
  109. data/ext/cargo-vendor/cranelift-isle-0.108.1/src/trie_again.rs +684 -0
  110. data/ext/cargo-vendor/cranelift-native-0.108.1/.cargo-checksum.json +1 -0
  111. data/ext/cargo-vendor/cranelift-native-0.108.1/Cargo.toml +43 -0
  112. data/ext/cargo-vendor/cranelift-wasm-0.108.1/.cargo-checksum.json +1 -0
  113. data/ext/cargo-vendor/cranelift-wasm-0.108.1/Cargo.toml +109 -0
  114. data/ext/cargo-vendor/cranelift-wasm-0.108.1/src/code_translator.rs +3687 -0
  115. data/ext/cargo-vendor/cranelift-wasm-0.108.1/src/environ/dummy.rs +906 -0
  116. data/ext/cargo-vendor/cranelift-wasm-0.108.1/src/environ/spec.rs +945 -0
  117. data/ext/cargo-vendor/cranelift-wasm-0.108.1/src/sections_translator.rs +389 -0
  118. data/ext/cargo-vendor/deterministic-wasi-ctx-0.1.22/.cargo-checksum.json +1 -0
  119. data/ext/cargo-vendor/deterministic-wasi-ctx-0.1.22/Cargo.toml +48 -0
  120. data/ext/cargo-vendor/embedded-io-0.4.0/.cargo-checksum.json +1 -0
  121. data/ext/cargo-vendor/embedded-io-0.4.0/CHANGELOG.md +28 -0
  122. data/ext/cargo-vendor/embedded-io-0.4.0/Cargo.toml +73 -0
  123. data/ext/cargo-vendor/embedded-io-0.4.0/LICENSE-APACHE +201 -0
  124. data/ext/cargo-vendor/embedded-io-0.4.0/LICENSE-MIT +25 -0
  125. data/ext/cargo-vendor/embedded-io-0.4.0/README.md +33 -0
  126. data/ext/cargo-vendor/embedded-io-0.4.0/ci.sh +21 -0
  127. data/ext/cargo-vendor/embedded-io-0.4.0/rust-toolchain.toml +3 -0
  128. data/ext/cargo-vendor/embedded-io-0.4.0/src/adapters/futures_io.rs +65 -0
  129. data/ext/cargo-vendor/embedded-io-0.4.0/src/adapters/mod.rs +40 -0
  130. data/ext/cargo-vendor/embedded-io-0.4.0/src/adapters/std_io.rs +107 -0
  131. data/ext/cargo-vendor/embedded-io-0.4.0/src/adapters/tokio.rs +108 -0
  132. data/ext/cargo-vendor/embedded-io-0.4.0/src/asynch.rs +230 -0
  133. data/ext/cargo-vendor/embedded-io-0.4.0/src/blocking.rs +309 -0
  134. data/ext/cargo-vendor/embedded-io-0.4.0/src/fmt.rs +228 -0
  135. data/ext/cargo-vendor/embedded-io-0.4.0/src/lib.rs +125 -0
  136. data/ext/cargo-vendor/libm-0.2.8/.cargo-checksum.json +1 -0
  137. data/ext/cargo-vendor/libm-0.2.8/CHANGELOG.md +123 -0
  138. data/ext/cargo-vendor/libm-0.2.8/CONTRIBUTING.md +95 -0
  139. data/ext/cargo-vendor/libm-0.2.8/Cargo.toml +45 -0
  140. data/ext/cargo-vendor/libm-0.2.8/LICENSE-APACHE +201 -0
  141. data/ext/cargo-vendor/libm-0.2.8/LICENSE-MIT +25 -0
  142. data/ext/cargo-vendor/libm-0.2.8/README.md +51 -0
  143. data/ext/cargo-vendor/libm-0.2.8/build.rs +463 -0
  144. data/ext/cargo-vendor/libm-0.2.8/src/lib.rs +59 -0
  145. data/ext/cargo-vendor/libm-0.2.8/src/libm_helper.rs +171 -0
  146. data/ext/cargo-vendor/libm-0.2.8/src/math/acos.rs +112 -0
  147. data/ext/cargo-vendor/libm-0.2.8/src/math/acosf.rs +79 -0
  148. data/ext/cargo-vendor/libm-0.2.8/src/math/acosh.rs +27 -0
  149. data/ext/cargo-vendor/libm-0.2.8/src/math/acoshf.rs +26 -0
  150. data/ext/cargo-vendor/libm-0.2.8/src/math/asin.rs +119 -0
  151. data/ext/cargo-vendor/libm-0.2.8/src/math/asinf.rs +72 -0
  152. data/ext/cargo-vendor/libm-0.2.8/src/math/asinh.rs +40 -0
  153. data/ext/cargo-vendor/libm-0.2.8/src/math/asinhf.rs +39 -0
  154. data/ext/cargo-vendor/libm-0.2.8/src/math/atan.rs +184 -0
  155. data/ext/cargo-vendor/libm-0.2.8/src/math/atan2.rs +126 -0
  156. data/ext/cargo-vendor/libm-0.2.8/src/math/atan2f.rs +91 -0
  157. data/ext/cargo-vendor/libm-0.2.8/src/math/atanf.rs +112 -0
  158. data/ext/cargo-vendor/libm-0.2.8/src/math/atanh.rs +37 -0
  159. data/ext/cargo-vendor/libm-0.2.8/src/math/atanhf.rs +37 -0
  160. data/ext/cargo-vendor/libm-0.2.8/src/math/cbrt.rs +113 -0
  161. data/ext/cargo-vendor/libm-0.2.8/src/math/cbrtf.rs +75 -0
  162. data/ext/cargo-vendor/libm-0.2.8/src/math/ceil.rs +82 -0
  163. data/ext/cargo-vendor/libm-0.2.8/src/math/ceilf.rs +65 -0
  164. data/ext/cargo-vendor/libm-0.2.8/src/math/copysign.rs +12 -0
  165. data/ext/cargo-vendor/libm-0.2.8/src/math/copysignf.rs +12 -0
  166. data/ext/cargo-vendor/libm-0.2.8/src/math/cos.rs +73 -0
  167. data/ext/cargo-vendor/libm-0.2.8/src/math/cosf.rs +83 -0
  168. data/ext/cargo-vendor/libm-0.2.8/src/math/cosh.rs +38 -0
  169. data/ext/cargo-vendor/libm-0.2.8/src/math/coshf.rs +38 -0
  170. data/ext/cargo-vendor/libm-0.2.8/src/math/erf.rs +318 -0
  171. data/ext/cargo-vendor/libm-0.2.8/src/math/erff.rs +230 -0
  172. data/ext/cargo-vendor/libm-0.2.8/src/math/exp.rs +154 -0
  173. data/ext/cargo-vendor/libm-0.2.8/src/math/exp10.rs +22 -0
  174. data/ext/cargo-vendor/libm-0.2.8/src/math/exp10f.rs +22 -0
  175. data/ext/cargo-vendor/libm-0.2.8/src/math/exp2.rs +394 -0
  176. data/ext/cargo-vendor/libm-0.2.8/src/math/exp2f.rs +135 -0
  177. data/ext/cargo-vendor/libm-0.2.8/src/math/expf.rs +101 -0
  178. data/ext/cargo-vendor/libm-0.2.8/src/math/expm1.rs +144 -0
  179. data/ext/cargo-vendor/libm-0.2.8/src/math/expm1f.rs +134 -0
  180. data/ext/cargo-vendor/libm-0.2.8/src/math/expo2.rs +14 -0
  181. data/ext/cargo-vendor/libm-0.2.8/src/math/fabs.rs +41 -0
  182. data/ext/cargo-vendor/libm-0.2.8/src/math/fabsf.rs +41 -0
  183. data/ext/cargo-vendor/libm-0.2.8/src/math/fdim.rs +22 -0
  184. data/ext/cargo-vendor/libm-0.2.8/src/math/fdimf.rs +22 -0
  185. data/ext/cargo-vendor/libm-0.2.8/src/math/fenv.rs +27 -0
  186. data/ext/cargo-vendor/libm-0.2.8/src/math/floor.rs +81 -0
  187. data/ext/cargo-vendor/libm-0.2.8/src/math/floorf.rs +66 -0
  188. data/ext/cargo-vendor/libm-0.2.8/src/math/fma.rs +232 -0
  189. data/ext/cargo-vendor/libm-0.2.8/src/math/fmaf.rs +117 -0
  190. data/ext/cargo-vendor/libm-0.2.8/src/math/fmax.rs +12 -0
  191. data/ext/cargo-vendor/libm-0.2.8/src/math/fmaxf.rs +12 -0
  192. data/ext/cargo-vendor/libm-0.2.8/src/math/fmin.rs +12 -0
  193. data/ext/cargo-vendor/libm-0.2.8/src/math/fminf.rs +12 -0
  194. data/ext/cargo-vendor/libm-0.2.8/src/math/fmod.rs +80 -0
  195. data/ext/cargo-vendor/libm-0.2.8/src/math/fmodf.rs +89 -0
  196. data/ext/cargo-vendor/libm-0.2.8/src/math/frexp.rs +20 -0
  197. data/ext/cargo-vendor/libm-0.2.8/src/math/frexpf.rs +21 -0
  198. data/ext/cargo-vendor/libm-0.2.8/src/math/hypot.rs +74 -0
  199. data/ext/cargo-vendor/libm-0.2.8/src/math/hypotf.rs +43 -0
  200. data/ext/cargo-vendor/libm-0.2.8/src/math/ilogb.rs +32 -0
  201. data/ext/cargo-vendor/libm-0.2.8/src/math/ilogbf.rs +32 -0
  202. data/ext/cargo-vendor/libm-0.2.8/src/math/j0.rs +422 -0
  203. data/ext/cargo-vendor/libm-0.2.8/src/math/j0f.rs +359 -0
  204. data/ext/cargo-vendor/libm-0.2.8/src/math/j1.rs +414 -0
  205. data/ext/cargo-vendor/libm-0.2.8/src/math/j1f.rs +380 -0
  206. data/ext/cargo-vendor/libm-0.2.8/src/math/jn.rs +343 -0
  207. data/ext/cargo-vendor/libm-0.2.8/src/math/jnf.rs +259 -0
  208. data/ext/cargo-vendor/libm-0.2.8/src/math/k_cos.rs +62 -0
  209. data/ext/cargo-vendor/libm-0.2.8/src/math/k_cosf.rs +29 -0
  210. data/ext/cargo-vendor/libm-0.2.8/src/math/k_expo2.rs +14 -0
  211. data/ext/cargo-vendor/libm-0.2.8/src/math/k_expo2f.rs +14 -0
  212. data/ext/cargo-vendor/libm-0.2.8/src/math/k_sin.rs +57 -0
  213. data/ext/cargo-vendor/libm-0.2.8/src/math/k_sinf.rs +30 -0
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  1235. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/isa/s390x/inst/unwind.rs +0 -0
  1236. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/isa/s390x/inst.isle +0 -0
  1237. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/isa/s390x/lower/isle/generated_code.rs +0 -0
  1238. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/isa/s390x/lower/isle.rs +0 -0
  1239. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/isa/s390x/lower.isle +0 -0
  1240. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/isa/s390x/lower.rs +0 -0
  1241. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/isa/s390x/mod.rs +0 -0
  1242. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/isa/s390x/settings.rs +0 -0
  1243. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/isa/unwind/systemv.rs +0 -0
  1244. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/isa/unwind/winx64.rs +0 -0
  1245. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/isa/unwind.rs +0 -0
  1246. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/isa/x64/encoding/evex.rs +0 -0
  1247. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/isa/x64/encoding/mod.rs +0 -0
  1248. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/isa/x64/encoding/rex.rs +0 -0
  1249. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/isa/x64/encoding/vex.rs +0 -0
  1250. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/isa/x64/inst/emit_state.rs +0 -0
  1251. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/isa/x64/inst/unwind/systemv.rs +0 -0
  1252. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/isa/x64/inst/unwind/winx64.rs +0 -0
  1253. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/isa/x64/inst/unwind.rs +0 -0
  1254. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/isa/x64/lower/isle/generated_code.rs +0 -0
  1255. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/isa/x64/mod.rs +0 -0
  1256. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/isa/x64/settings.rs +0 -0
  1257. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/isle_prelude.rs +0 -0
  1258. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/iterators.rs +0 -0
  1259. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/legalizer/globalvalue.rs +0 -0
  1260. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/legalizer/mod.rs +0 -0
  1261. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/loop_analysis.rs +0 -0
  1262. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/machinst/buffer.rs +0 -0
  1263. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/machinst/compile.rs +0 -0
  1264. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/machinst/helpers.rs +0 -0
  1265. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/machinst/inst_common.rs +0 -0
  1266. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/machinst/pcc.rs +0 -0
  1267. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/opts/README.md +0 -0
  1268. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/opts/bitops.isle +0 -0
  1269. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/opts/cprop.isle +0 -0
  1270. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/opts/extends.isle +0 -0
  1271. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/opts/generated_code.rs +0 -0
  1272. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/opts/remat.isle +0 -0
  1273. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/opts/selects.isle +0 -0
  1274. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/opts/shifts.isle +0 -0
  1275. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/opts/spaceship.isle +0 -0
  1276. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/opts/spectre.isle +0 -0
  1277. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/opts/vector.isle +0 -0
  1278. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/opts.rs +0 -0
  1279. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/prelude.isle +0 -0
  1280. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/prelude_lower.isle +0 -0
  1281. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/prelude_opt.isle +0 -0
  1282. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/print_errors.rs +0 -0
  1283. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/result.rs +0 -0
  1284. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/souper_harvest.rs +0 -0
  1285. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/timing.rs +0 -0
  1286. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/unionfind.rs +0 -0
  1287. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/unreachable_code.rs +0 -0
  1288. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/value_label.rs +0 -0
  1289. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/verifier/mod.rs +0 -0
  1290. /data/ext/cargo-vendor/{cranelift-codegen-0.107.2 → cranelift-codegen-0.108.1}/src/write.rs +0 -0
  1291. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.107.2 → cranelift-codegen-meta-0.108.1}/LICENSE +0 -0
  1292. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.107.2 → cranelift-codegen-meta-0.108.1}/README.md +0 -0
  1293. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.107.2 → cranelift-codegen-meta-0.108.1}/src/cdsl/formats.rs +0 -0
  1294. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.107.2 → cranelift-codegen-meta-0.108.1}/src/cdsl/instructions.rs +0 -0
  1295. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.107.2 → cranelift-codegen-meta-0.108.1}/src/cdsl/isa.rs +0 -0
  1296. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.107.2 → cranelift-codegen-meta-0.108.1}/src/cdsl/mod.rs +0 -0
  1297. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.107.2 → cranelift-codegen-meta-0.108.1}/src/cdsl/operands.rs +0 -0
  1298. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.107.2 → cranelift-codegen-meta-0.108.1}/src/cdsl/settings.rs +0 -0
  1299. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.107.2 → cranelift-codegen-meta-0.108.1}/src/cdsl/types.rs +0 -0
  1300. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.107.2 → cranelift-codegen-meta-0.108.1}/src/cdsl/typevar.rs +0 -0
  1301. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.107.2 → cranelift-codegen-meta-0.108.1}/src/constant_hash.rs +0 -0
  1302. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.107.2 → cranelift-codegen-meta-0.108.1}/src/error.rs +0 -0
  1303. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.107.2 → cranelift-codegen-meta-0.108.1}/src/isa/arm64.rs +0 -0
  1304. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.107.2 → cranelift-codegen-meta-0.108.1}/src/isa/mod.rs +0 -0
  1305. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.107.2 → cranelift-codegen-meta-0.108.1}/src/isa/s390x.rs +0 -0
  1306. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.107.2 → cranelift-codegen-meta-0.108.1}/src/shared/entities.rs +0 -0
  1307. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.107.2 → cranelift-codegen-meta-0.108.1}/src/shared/formats.rs +0 -0
  1308. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.107.2 → cranelift-codegen-meta-0.108.1}/src/shared/immediates.rs +0 -0
  1309. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.107.2 → cranelift-codegen-meta-0.108.1}/src/shared/instructions.rs +0 -0
  1310. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.107.2 → cranelift-codegen-meta-0.108.1}/src/shared/mod.rs +0 -0
  1311. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.107.2 → cranelift-codegen-meta-0.108.1}/src/shared/types.rs +0 -0
  1312. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.107.2 → cranelift-codegen-meta-0.108.1}/src/unique_table.rs +0 -0
  1313. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.107.2 → cranelift-codegen-shared-0.108.1}/LICENSE +0 -0
  1314. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.107.2 → cranelift-codegen-shared-0.108.1}/README.md +0 -0
  1315. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.107.2 → cranelift-codegen-shared-0.108.1}/src/constant_hash.rs +0 -0
  1316. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.107.2 → cranelift-codegen-shared-0.108.1}/src/constants.rs +0 -0
  1317. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.107.2 → cranelift-codegen-shared-0.108.1}/src/lib.rs +0 -0
  1318. /data/ext/cargo-vendor/{cranelift-control-0.107.2 → cranelift-control-0.108.1}/LICENSE +0 -0
  1319. /data/ext/cargo-vendor/{cranelift-control-0.107.2 → cranelift-control-0.108.1}/README.md +0 -0
  1320. /data/ext/cargo-vendor/{cranelift-control-0.107.2 → cranelift-control-0.108.1}/src/chaos.rs +0 -0
  1321. /data/ext/cargo-vendor/{cranelift-control-0.107.2 → cranelift-control-0.108.1}/src/lib.rs +0 -0
  1322. /data/ext/cargo-vendor/{cranelift-control-0.107.2 → cranelift-control-0.108.1}/src/zero_sized.rs +0 -0
  1323. /data/ext/cargo-vendor/{cranelift-entity-0.107.2 → cranelift-entity-0.108.1}/LICENSE +0 -0
  1324. /data/ext/cargo-vendor/{cranelift-entity-0.107.2 → cranelift-entity-0.108.1}/README.md +0 -0
  1325. /data/ext/cargo-vendor/{cranelift-entity-0.107.2 → cranelift-entity-0.108.1}/src/boxed_slice.rs +0 -0
  1326. /data/ext/cargo-vendor/{cranelift-entity-0.107.2 → cranelift-entity-0.108.1}/src/iter.rs +0 -0
  1327. /data/ext/cargo-vendor/{cranelift-entity-0.107.2 → cranelift-entity-0.108.1}/src/keys.rs +0 -0
  1328. /data/ext/cargo-vendor/{cranelift-entity-0.107.2 → cranelift-entity-0.108.1}/src/list.rs +0 -0
  1329. /data/ext/cargo-vendor/{cranelift-entity-0.107.2 → cranelift-entity-0.108.1}/src/map.rs +0 -0
  1330. /data/ext/cargo-vendor/{cranelift-entity-0.107.2 → cranelift-entity-0.108.1}/src/packed_option.rs +0 -0
  1331. /data/ext/cargo-vendor/{cranelift-entity-0.107.2 → cranelift-entity-0.108.1}/src/primary.rs +0 -0
  1332. /data/ext/cargo-vendor/{cranelift-entity-0.107.2 → cranelift-entity-0.108.1}/src/set.rs +0 -0
  1333. /data/ext/cargo-vendor/{cranelift-entity-0.107.2 → cranelift-entity-0.108.1}/src/sparse.rs +0 -0
  1334. /data/ext/cargo-vendor/{cranelift-entity-0.107.2 → cranelift-entity-0.108.1}/src/unsigned.rs +0 -0
  1335. /data/ext/cargo-vendor/{cranelift-frontend-0.107.2 → cranelift-frontend-0.108.1}/LICENSE +0 -0
  1336. /data/ext/cargo-vendor/{cranelift-frontend-0.107.2 → cranelift-frontend-0.108.1}/README.md +0 -0
  1337. /data/ext/cargo-vendor/{cranelift-frontend-0.107.2 → cranelift-frontend-0.108.1}/src/frontend.rs +0 -0
  1338. /data/ext/cargo-vendor/{cranelift-frontend-0.107.2 → cranelift-frontend-0.108.1}/src/lib.rs +0 -0
  1339. /data/ext/cargo-vendor/{cranelift-frontend-0.107.2 → cranelift-frontend-0.108.1}/src/ssa.rs +0 -0
  1340. /data/ext/cargo-vendor/{cranelift-frontend-0.107.2 → cranelift-frontend-0.108.1}/src/variable.rs +0 -0
  1341. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/README.md +0 -0
  1342. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/build.rs +0 -0
  1343. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/isle_examples/fail/bad_converters.isle +0 -0
  1344. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/isle_examples/fail/bound_var_type_mismatch.isle +0 -0
  1345. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/isle_examples/fail/converter_extractor_constructor.isle +0 -0
  1346. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/isle_examples/fail/error1.isle +0 -0
  1347. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/isle_examples/fail/extra_parens.isle +0 -0
  1348. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/isle_examples/fail/impure_expression.isle +0 -0
  1349. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/isle_examples/fail/impure_rhs.isle +0 -0
  1350. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/isle_examples/fail/multi_internal_etor.isle +0 -0
  1351. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/isle_examples/fail/multi_prio.isle +0 -0
  1352. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/isle_examples/link/borrows.isle +0 -0
  1353. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/isle_examples/link/borrows_main.rs +0 -0
  1354. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/isle_examples/link/iflets.isle +0 -0
  1355. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/isle_examples/link/iflets_main.rs +0 -0
  1356. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/isle_examples/link/multi_constructor.isle +0 -0
  1357. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/isle_examples/link/multi_constructor_main.rs +0 -0
  1358. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/isle_examples/link/multi_extractor.isle +0 -0
  1359. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/isle_examples/link/multi_extractor_main.rs +0 -0
  1360. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/isle_examples/link/test.isle +0 -0
  1361. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/isle_examples/link/test_main.rs +0 -0
  1362. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/isle_examples/pass/bound_var.isle +0 -0
  1363. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/isle_examples/pass/construct_and_extract.isle +0 -0
  1364. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/isle_examples/pass/conversions.isle +0 -0
  1365. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/isle_examples/pass/conversions_extern.isle +0 -0
  1366. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/isle_examples/pass/let.isle +0 -0
  1367. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/isle_examples/pass/nodebug.isle +0 -0
  1368. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/isle_examples/pass/prio_trie_bug.isle +0 -0
  1369. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/isle_examples/pass/test2.isle +0 -0
  1370. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/isle_examples/pass/test3.isle +0 -0
  1371. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/isle_examples/pass/test4.isle +0 -0
  1372. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/isle_examples/pass/tutorial.isle +0 -0
  1373. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/isle_examples/run/iconst.isle +0 -0
  1374. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/isle_examples/run/iconst_main.rs +0 -0
  1375. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/isle_examples/run/let_shadowing.isle +0 -0
  1376. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/isle_examples/run/let_shadowing_main.rs +0 -0
  1377. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/src/ast.rs +0 -0
  1378. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/src/compile.rs +0 -0
  1379. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/src/error.rs +0 -0
  1380. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/src/lexer.rs +0 -0
  1381. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/src/log.rs +0 -0
  1382. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/src/overlap.rs +0 -0
  1383. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/src/parser.rs +0 -0
  1384. /data/ext/cargo-vendor/{cranelift-isle-0.107.2 → cranelift-isle-0.108.1}/tests/run_tests.rs +0 -0
  1385. /data/ext/cargo-vendor/{cranelift-native-0.107.2 → cranelift-native-0.108.1}/LICENSE +0 -0
  1386. /data/ext/cargo-vendor/{cranelift-native-0.107.2 → cranelift-native-0.108.1}/README.md +0 -0
  1387. /data/ext/cargo-vendor/{cranelift-native-0.107.2 → cranelift-native-0.108.1}/src/lib.rs +0 -0
  1388. /data/ext/cargo-vendor/{cranelift-native-0.107.2 → cranelift-native-0.108.1}/src/riscv.rs +0 -0
  1389. /data/ext/cargo-vendor/{cranelift-wasm-0.107.2 → cranelift-wasm-0.108.1}/LICENSE +0 -0
  1390. /data/ext/cargo-vendor/{cranelift-wasm-0.107.2 → cranelift-wasm-0.108.1}/README.md +0 -0
  1391. /data/ext/cargo-vendor/{cranelift-wasm-0.107.2 → cranelift-wasm-0.108.1}/src/code_translator/bounds_checks.rs +0 -0
  1392. /data/ext/cargo-vendor/{cranelift-wasm-0.107.2 → cranelift-wasm-0.108.1}/src/environ/mod.rs +0 -0
  1393. /data/ext/cargo-vendor/{cranelift-wasm-0.107.2 → cranelift-wasm-0.108.1}/src/func_translator.rs +0 -0
  1394. /data/ext/cargo-vendor/{cranelift-wasm-0.107.2 → cranelift-wasm-0.108.1}/src/heap.rs +0 -0
  1395. /data/ext/cargo-vendor/{cranelift-wasm-0.107.2 → cranelift-wasm-0.108.1}/src/lib.rs +0 -0
  1396. /data/ext/cargo-vendor/{cranelift-wasm-0.107.2 → cranelift-wasm-0.108.1}/src/module_translator.rs +0 -0
  1397. /data/ext/cargo-vendor/{cranelift-wasm-0.107.2 → cranelift-wasm-0.108.1}/src/state.rs +0 -0
  1398. /data/ext/cargo-vendor/{cranelift-wasm-0.107.2 → cranelift-wasm-0.108.1}/src/table.rs +0 -0
  1399. /data/ext/cargo-vendor/{cranelift-wasm-0.107.2 → cranelift-wasm-0.108.1}/src/translation_utils.rs +0 -0
  1400. /data/ext/cargo-vendor/{deterministic-wasi-ctx-0.1.21 → deterministic-wasi-ctx-0.1.22}/README.md +0 -0
  1401. /data/ext/cargo-vendor/{deterministic-wasi-ctx-0.1.21 → deterministic-wasi-ctx-0.1.22}/src/clocks.rs +0 -0
  1402. /data/ext/cargo-vendor/{deterministic-wasi-ctx-0.1.21 → deterministic-wasi-ctx-0.1.22}/src/lib.rs +0 -0
  1403. /data/ext/cargo-vendor/{deterministic-wasi-ctx-0.1.21 → deterministic-wasi-ctx-0.1.22}/src/noop_scheduler.rs +0 -0
  1404. /data/ext/cargo-vendor/{deterministic-wasi-ctx-0.1.21 → deterministic-wasi-ctx-0.1.22}/tests/clocks.rs +0 -0
  1405. /data/ext/cargo-vendor/{deterministic-wasi-ctx-0.1.21 → deterministic-wasi-ctx-0.1.22}/tests/common/mod.rs +0 -0
  1406. /data/ext/cargo-vendor/{deterministic-wasi-ctx-0.1.21 → deterministic-wasi-ctx-0.1.22}/tests/random.rs +0 -0
  1407. /data/ext/cargo-vendor/{deterministic-wasi-ctx-0.1.21 → deterministic-wasi-ctx-0.1.22}/tests/scheduler.rs +0 -0
  1408. /data/ext/cargo-vendor/{rb-sys-0.9.97 → rb-sys-0.9.100}/LICENSE-APACHE +0 -0
  1409. /data/ext/cargo-vendor/{rb-sys-0.9.97 → rb-sys-0.9.100}/LICENSE-MIT +0 -0
  1410. /data/ext/cargo-vendor/{rb-sys-0.9.97 → rb-sys-0.9.100}/bin/release.sh +0 -0
  1411. /data/ext/cargo-vendor/{rb-sys-0.9.97 → rb-sys-0.9.100}/build/features.rs +0 -0
  1412. /data/ext/cargo-vendor/{rb-sys-0.9.97 → rb-sys-0.9.100}/build/version.rs +0 -0
  1413. /data/ext/cargo-vendor/{rb-sys-0.9.97 → rb-sys-0.9.100}/readme.md +0 -0
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  1416. /data/ext/cargo-vendor/{rb-sys-0.9.97 → rb-sys-0.9.100}/src/macros.rs +0 -0
  1417. /data/ext/cargo-vendor/{rb-sys-0.9.97 → rb-sys-0.9.100}/src/memory.rs +0 -0
  1418. /data/ext/cargo-vendor/{rb-sys-0.9.97 → rb-sys-0.9.100}/src/ruby_abi_version.rs +0 -0
  1419. /data/ext/cargo-vendor/{rb-sys-0.9.97 → rb-sys-0.9.100}/src/special_consts.rs +0 -0
  1420. /data/ext/cargo-vendor/{rb-sys-0.9.97 → rb-sys-0.9.100}/src/stable_api/compiled.c +0 -0
  1421. /data/ext/cargo-vendor/{rb-sys-0.9.97 → rb-sys-0.9.100}/src/stable_api/compiled.rs +0 -0
  1422. /data/ext/cargo-vendor/{rb-sys-0.9.97 → rb-sys-0.9.100}/src/stable_api/ruby_2_6.rs +0 -0
  1423. /data/ext/cargo-vendor/{rb-sys-0.9.97 → rb-sys-0.9.100}/src/stable_api/ruby_2_7.rs +0 -0
  1424. /data/ext/cargo-vendor/{rb-sys-0.9.97 → rb-sys-0.9.100}/src/stable_api/ruby_3_0.rs +0 -0
  1425. /data/ext/cargo-vendor/{rb-sys-0.9.97 → rb-sys-0.9.100}/src/stable_api/ruby_3_1.rs +0 -0
  1426. /data/ext/cargo-vendor/{rb-sys-0.9.97 → rb-sys-0.9.100}/src/stable_api/ruby_3_2.rs +0 -0
  1427. /data/ext/cargo-vendor/{rb-sys-0.9.97 → rb-sys-0.9.100}/src/stable_api/ruby_3_3.rs +0 -0
  1428. /data/ext/cargo-vendor/{rb-sys-0.9.97 → rb-sys-0.9.100}/src/stable_api.rs +0 -0
  1429. /data/ext/cargo-vendor/{rb-sys-0.9.97 → rb-sys-0.9.100}/src/symbol.rs +0 -0
  1430. /data/ext/cargo-vendor/{rb-sys-0.9.97 → rb-sys-0.9.100}/src/utils.rs +0 -0
  1431. /data/ext/cargo-vendor/{rb-sys-0.9.97 → rb-sys-0.9.100}/src/value_type.rs +0 -0
  1432. /data/ext/cargo-vendor/{rb-sys-build-0.9.97 → rb-sys-build-0.9.100}/LICENSE-APACHE +0 -0
  1433. /data/ext/cargo-vendor/{rb-sys-build-0.9.97 → rb-sys-build-0.9.100}/LICENSE-MIT +0 -0
  1434. /data/ext/cargo-vendor/{rb-sys-build-0.9.97 → rb-sys-build-0.9.100}/src/bindings/sanitizer.rs +0 -0
  1435. /data/ext/cargo-vendor/{rb-sys-build-0.9.97 → rb-sys-build-0.9.100}/src/bindings/wrapper.h +0 -0
  1436. /data/ext/cargo-vendor/{rb-sys-build-0.9.97 → rb-sys-build-0.9.100}/src/lib.rs +0 -0
  1437. /data/ext/cargo-vendor/{rb-sys-build-0.9.97 → rb-sys-build-0.9.100}/src/rb_config/flags.rs +0 -0
  1438. /data/ext/cargo-vendor/{rb-sys-build-0.9.97 → rb-sys-build-0.9.100}/src/rb_config/library.rs +0 -0
  1439. /data/ext/cargo-vendor/{rb-sys-build-0.9.97 → rb-sys-build-0.9.100}/src/rb_config/search_path.rs +0 -0
  1440. /data/ext/cargo-vendor/{rb-sys-build-0.9.97 → rb-sys-build-0.9.100}/src/rb_config.rs +0 -0
  1441. /data/ext/cargo-vendor/{wasi-common-20.0.2 → wasi-common-21.0.1}/LICENSE +0 -0
  1442. /data/ext/cargo-vendor/{wasi-common-20.0.2 → wasi-common-21.0.1}/README.md +0 -0
  1443. /data/ext/cargo-vendor/{wasi-common-20.0.2 → wasi-common-21.0.1}/src/clocks.rs +0 -0
  1444. /data/ext/cargo-vendor/{wasi-common-20.0.2 → wasi-common-21.0.1}/src/ctx.rs +0 -0
  1445. /data/ext/cargo-vendor/{wasi-common-20.0.2 → wasi-common-21.0.1}/src/dir.rs +0 -0
  1446. /data/ext/cargo-vendor/{wasi-common-20.0.2 → wasi-common-21.0.1}/src/error.rs +0 -0
  1447. /data/ext/cargo-vendor/{wasi-common-20.0.2 → wasi-common-21.0.1}/src/file.rs +0 -0
  1448. /data/ext/cargo-vendor/{wasi-common-20.0.2 → wasi-common-21.0.1}/src/lib.rs +0 -0
  1449. /data/ext/cargo-vendor/{wasi-common-20.0.2 → wasi-common-21.0.1}/src/pipe.rs +0 -0
  1450. /data/ext/cargo-vendor/{wasi-common-20.0.2 → wasi-common-21.0.1}/src/random.rs +0 -0
  1451. /data/ext/cargo-vendor/{wasi-common-20.0.2 → wasi-common-21.0.1}/src/sched/subscription.rs +0 -0
  1452. /data/ext/cargo-vendor/{wasi-common-20.0.2 → wasi-common-21.0.1}/src/sched.rs +0 -0
  1453. /data/ext/cargo-vendor/{wasi-common-20.0.2 → wasi-common-21.0.1}/src/snapshots/mod.rs +0 -0
  1454. /data/ext/cargo-vendor/{wasi-common-20.0.2 → wasi-common-21.0.1}/src/snapshots/preview_0.rs +0 -0
  1455. /data/ext/cargo-vendor/{wasi-common-20.0.2 → wasi-common-21.0.1}/src/snapshots/preview_1/error.rs +0 -0
  1456. /data/ext/cargo-vendor/{wasi-common-20.0.2 → wasi-common-21.0.1}/src/snapshots/preview_1.rs +0 -0
  1457. /data/ext/cargo-vendor/{wasi-common-20.0.2 → wasi-common-21.0.1}/src/string_array.rs +0 -0
  1458. /data/ext/cargo-vendor/{wasi-common-20.0.2 → wasi-common-21.0.1}/src/sync/clocks.rs +0 -0
  1459. /data/ext/cargo-vendor/{wasi-common-20.0.2 → wasi-common-21.0.1}/src/sync/dir.rs +0 -0
  1460. /data/ext/cargo-vendor/{wasi-common-20.0.2 → wasi-common-21.0.1}/src/sync/file.rs +0 -0
  1461. /data/ext/cargo-vendor/{wasi-common-20.0.2 → wasi-common-21.0.1}/src/sync/mod.rs +0 -0
  1462. /data/ext/cargo-vendor/{wasi-common-20.0.2 → wasi-common-21.0.1}/src/sync/net.rs +0 -0
  1463. /data/ext/cargo-vendor/{wasi-common-20.0.2 → wasi-common-21.0.1}/src/sync/sched/unix.rs +0 -0
  1464. /data/ext/cargo-vendor/{wasi-common-20.0.2 → wasi-common-21.0.1}/src/sync/sched/windows.rs +0 -0
  1465. /data/ext/cargo-vendor/{wasi-common-20.0.2 → wasi-common-21.0.1}/src/sync/sched.rs +0 -0
  1466. /data/ext/cargo-vendor/{wasi-common-20.0.2 → wasi-common-21.0.1}/src/sync/stdio.rs +0 -0
  1467. /data/ext/cargo-vendor/{wasi-common-20.0.2 → wasi-common-21.0.1}/src/table.rs +0 -0
  1468. /data/ext/cargo-vendor/{wasi-common-20.0.2 → wasi-common-21.0.1}/src/tokio/dir.rs +0 -0
  1469. /data/ext/cargo-vendor/{wasi-common-20.0.2 → wasi-common-21.0.1}/src/tokio/file.rs +0 -0
  1470. /data/ext/cargo-vendor/{wasi-common-20.0.2 → wasi-common-21.0.1}/src/tokio/mod.rs +0 -0
  1471. /data/ext/cargo-vendor/{wasi-common-20.0.2 → wasi-common-21.0.1}/src/tokio/net.rs +0 -0
  1472. /data/ext/cargo-vendor/{wasi-common-20.0.2 → wasi-common-21.0.1}/src/tokio/sched/unix.rs +0 -0
  1473. /data/ext/cargo-vendor/{wasi-common-20.0.2 → wasi-common-21.0.1}/src/tokio/sched/windows.rs +0 -0
  1474. /data/ext/cargo-vendor/{wasi-common-20.0.2 → wasi-common-21.0.1}/src/tokio/sched.rs +0 -0
  1475. /data/ext/cargo-vendor/{wasi-common-20.0.2 → wasi-common-21.0.1}/src/tokio/stdio.rs +0 -0
  1476. /data/ext/cargo-vendor/{wasi-common-20.0.2 → wasi-common-21.0.1}/witx/preview0/typenames.witx +0 -0
  1477. /data/ext/cargo-vendor/{wasi-common-20.0.2 → wasi-common-21.0.1}/witx/preview0/wasi_unstable.witx +0 -0
  1478. /data/ext/cargo-vendor/{wasi-common-20.0.2 → wasi-common-21.0.1}/witx/preview1/typenames.witx +0 -0
  1479. /data/ext/cargo-vendor/{wasi-common-20.0.2 → wasi-common-21.0.1}/witx/preview1/wasi_snapshot_preview1.witx +0 -0
  1480. /data/ext/cargo-vendor/{wasm-encoder-0.202.0 → wasm-encoder-0.207.0}/LICENSE +0 -0
  1481. /data/ext/cargo-vendor/{wasm-encoder-0.202.0 → wasm-encoder-0.207.0}/README.md +0 -0
  1482. /data/ext/cargo-vendor/{wasm-encoder-0.202.0 → wasm-encoder-0.207.0}/src/component/aliases.rs +0 -0
  1483. /data/ext/cargo-vendor/{wasm-encoder-0.202.0 → wasm-encoder-0.207.0}/src/component/builder.rs +0 -0
  1484. /data/ext/cargo-vendor/{wasm-encoder-0.202.0 → wasm-encoder-0.207.0}/src/component/canonicals.rs +0 -0
  1485. /data/ext/cargo-vendor/{wasm-encoder-0.202.0 → wasm-encoder-0.207.0}/src/component/components.rs +0 -0
  1486. /data/ext/cargo-vendor/{wasm-encoder-0.202.0 → wasm-encoder-0.207.0}/src/component/exports.rs +0 -0
  1487. /data/ext/cargo-vendor/{wasm-encoder-0.202.0 → wasm-encoder-0.207.0}/src/component/imports.rs +0 -0
  1488. /data/ext/cargo-vendor/{wasm-encoder-0.202.0 → wasm-encoder-0.207.0}/src/component/instances.rs +0 -0
  1489. /data/ext/cargo-vendor/{wasm-encoder-0.202.0 → wasm-encoder-0.207.0}/src/component/modules.rs +0 -0
  1490. /data/ext/cargo-vendor/{wasm-encoder-0.202.0 → wasm-encoder-0.207.0}/src/component/names.rs +0 -0
  1491. /data/ext/cargo-vendor/{wasm-encoder-0.202.0 → wasm-encoder-0.207.0}/src/component/start.rs +0 -0
  1492. /data/ext/cargo-vendor/{wasm-encoder-0.202.0 → wasm-encoder-0.207.0}/src/component/types.rs +0 -0
  1493. /data/ext/cargo-vendor/{wasm-encoder-0.202.0 → wasm-encoder-0.207.0}/src/component.rs +0 -0
  1494. /data/ext/cargo-vendor/{wasm-encoder-0.202.0 → wasm-encoder-0.207.0}/src/core/custom.rs +0 -0
  1495. /data/ext/cargo-vendor/{wasm-encoder-0.202.0 → wasm-encoder-0.207.0}/src/core/dump.rs +0 -0
  1496. /data/ext/cargo-vendor/{wasm-encoder-0.202.0 → wasm-encoder-0.207.0}/src/core/exports.rs +0 -0
  1497. /data/ext/cargo-vendor/{wasm-encoder-0.202.0 → wasm-encoder-0.207.0}/src/core/functions.rs +0 -0
  1498. /data/ext/cargo-vendor/{wasm-encoder-0.202.0 → wasm-encoder-0.207.0}/src/core/linking.rs +0 -0
  1499. /data/ext/cargo-vendor/{wasm-encoder-0.202.0 → wasm-encoder-0.207.0}/src/core/names.rs +0 -0
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  1502. /data/ext/cargo-vendor/{wasm-encoder-0.202.0 → wasm-encoder-0.207.0}/src/core/tags.rs +0 -0
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  1507. /data/ext/cargo-vendor/{wasmparser-0.202.0 → wasmparser-0.207.0}/benches/benchmark.rs +0 -0
  1508. /data/ext/cargo-vendor/{wasmparser-0.202.0 → wasmparser-0.207.0}/examples/simple.rs +0 -0
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  1510. /data/ext/cargo-vendor/{wasmparser-0.202.0 → wasmparser-0.207.0}/src/readers/component/exports.rs +0 -0
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  1513. /data/ext/cargo-vendor/{wasmparser-0.202.0 → wasmparser-0.207.0}/src/readers/core/branch_hinting.rs +0 -0
  1514. /data/ext/cargo-vendor/{wasmparser-0.202.0 → wasmparser-0.207.0}/src/readers/core/exports.rs +0 -0
  1515. /data/ext/cargo-vendor/{wasmparser-0.202.0 → wasmparser-0.207.0}/src/readers/core/functions.rs +0 -0
  1516. /data/ext/cargo-vendor/{wasmparser-0.202.0 → wasmparser-0.207.0}/src/readers/core/imports.rs +0 -0
  1517. /data/ext/cargo-vendor/{wasmparser-0.202.0 → wasmparser-0.207.0}/src/readers/core/init.rs +0 -0
  1518. /data/ext/cargo-vendor/{wasmparser-0.202.0 → wasmparser-0.207.0}/src/readers/core/producers.rs +0 -0
  1519. /data/ext/cargo-vendor/{wasmparser-0.202.0 → wasmparser-0.207.0}/src/readers/core/tags.rs +0 -0
  1520. /data/ext/cargo-vendor/{wasmparser-0.202.0 → wasmparser-0.207.0}/tests/big-module.rs +0 -0
  1521. /data/ext/cargo-vendor/{wasmparser-0.202.0 → wasmprinter-0.207.0}/LICENSE +0 -0
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  1523. /data/ext/cargo-vendor/{wasmprinter-0.202.0 → wasmtime-21.0.1}/LICENSE +0 -0
  1524. /data/ext/cargo-vendor/{wasmtime-20.0.2 → wasmtime-21.0.1}/README.md +0 -0
  1525. /data/ext/cargo-vendor/{wasmtime-runtime-20.0.2/proptest-regressions → wasmtime-21.0.1/proptest-regressions/runtime/vm}/instance/allocator/pooling/memory_pool.txt +0 -0
  1526. /data/ext/cargo-vendor/{wasmtime-20.0.2 → wasmtime-21.0.1}/src/runtime/gc/disabled/i31.rs +0 -0
  1527. /data/ext/cargo-vendor/{wasmtime-20.0.2 → wasmtime-21.0.1}/src/runtime/gc/disabled.rs +0 -0
  1528. /data/ext/cargo-vendor/{wasmtime-20.0.2 → wasmtime-21.0.1}/src/runtime/gc/enabled.rs +0 -0
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  1530. /data/ext/cargo-vendor/{wasmtime-runtime-20.0.2/src → wasmtime-21.0.1/src/runtime/vm}/arch/mod.rs +0 -0
  1531. /data/ext/cargo-vendor/{wasmtime-runtime-20.0.2/src → wasmtime-21.0.1/src/runtime/vm}/arch/riscv64.rs +0 -0
  1532. /data/ext/cargo-vendor/{wasmtime-runtime-20.0.2/src → wasmtime-21.0.1/src/runtime/vm}/arch/s390x.S +0 -0
  1533. /data/ext/cargo-vendor/{wasmtime-runtime-20.0.2/src → wasmtime-21.0.1/src/runtime/vm}/arch/s390x.rs +0 -0
  1534. /data/ext/cargo-vendor/{wasmtime-runtime-20.0.2/src → wasmtime-21.0.1/src/runtime/vm}/helpers.c +0 -0
  1535. /data/ext/cargo-vendor/{wasmtime-runtime-20.0.2/src → wasmtime-21.0.1/src/runtime/vm}/mpk/disabled.rs +0 -0
  1536. /data/ext/cargo-vendor/{wasmtime-runtime-20.0.2/src → wasmtime-21.0.1/src/runtime/vm}/sys/custom/unwind.rs +0 -0
  1537. /data/ext/cargo-vendor/{wasmtime-runtime-20.0.2/src → wasmtime-21.0.1/src/runtime/vm}/sys/miri/unwind.rs +0 -0
  1538. /data/ext/cargo-vendor/{wasmtime-runtime-20.0.2/src → wasmtime-21.0.1/src/runtime/vm}/sys/miri/vm.rs +0 -0
  1539. /data/ext/cargo-vendor/{wasmtime-runtime-20.0.2/src → wasmtime-21.0.1/src/runtime/vm}/sys/unix/macos_traphandlers.rs +0 -0
  1540. /data/ext/cargo-vendor/{wasmtime-runtime-20.0.2/src → wasmtime-21.0.1/src/runtime/vm}/sys/windows/unwind.rs +0 -0
  1541. /data/ext/cargo-vendor/{wasmtime-runtime-20.0.2/src → wasmtime-21.0.1/src/runtime/vm}/sys/windows/vm.rs +0 -0
  1542. /data/ext/cargo-vendor/{wasmtime-runtime-20.0.2/src → wasmtime-21.0.1/src/runtime/vm}/threads/mod.rs +0 -0
  1543. /data/ext/cargo-vendor/{wasmtime-20.0.2 → wasmtime-cache-21.0.1}/LICENSE +0 -0
  1544. /data/ext/cargo-vendor/{wasmtime-cache-20.0.2 → wasmtime-cache-21.0.1}/build.rs +0 -0
  1545. /data/ext/cargo-vendor/{wasmtime-cache-20.0.2 → wasmtime-cache-21.0.1}/src/config/tests.rs +0 -0
  1546. /data/ext/cargo-vendor/{wasmtime-cache-20.0.2 → wasmtime-cache-21.0.1}/src/config.rs +0 -0
  1547. /data/ext/cargo-vendor/{wasmtime-cache-20.0.2 → wasmtime-cache-21.0.1}/src/tests.rs +0 -0
  1548. /data/ext/cargo-vendor/{wasmtime-cache-20.0.2 → wasmtime-cache-21.0.1}/src/worker/tests/system_time_stub.rs +0 -0
  1549. /data/ext/cargo-vendor/{wasmtime-cache-20.0.2 → wasmtime-cache-21.0.1}/src/worker/tests.rs +0 -0
  1550. /data/ext/cargo-vendor/{wasmtime-cache-20.0.2 → wasmtime-cache-21.0.1}/src/worker.rs +0 -0
  1551. /data/ext/cargo-vendor/{wasmtime-cache-20.0.2 → wasmtime-cache-21.0.1}/tests/cache_write_default_config.rs +0 -0
  1552. /data/ext/cargo-vendor/{wasmtime-component-macro-20.0.2 → wasmtime-component-macro-21.0.1}/build.rs +0 -0
  1553. /data/ext/cargo-vendor/{wasmtime-component-macro-20.0.2 → wasmtime-component-macro-21.0.1}/src/lib.rs +0 -0
  1554. /data/ext/cargo-vendor/{wasmtime-component-macro-20.0.2 → wasmtime-component-macro-21.0.1}/tests/codegen/char.wit +0 -0
  1555. /data/ext/cargo-vendor/{wasmtime-component-macro-20.0.2 → wasmtime-component-macro-21.0.1}/tests/codegen/conventions.wit +0 -0
  1556. /data/ext/cargo-vendor/{wasmtime-component-macro-20.0.2 → wasmtime-component-macro-21.0.1}/tests/codegen/dead-code.wit +0 -0
  1557. /data/ext/cargo-vendor/{wasmtime-component-macro-20.0.2 → wasmtime-component-macro-21.0.1}/tests/codegen/direct-import.wit +0 -0
  1558. /data/ext/cargo-vendor/{wasmtime-component-macro-20.0.2 → wasmtime-component-macro-21.0.1}/tests/codegen/empty.wit +0 -0
  1559. /data/ext/cargo-vendor/{wasmtime-component-macro-20.0.2 → wasmtime-component-macro-21.0.1}/tests/codegen/flags.wit +0 -0
  1560. /data/ext/cargo-vendor/{wasmtime-component-macro-20.0.2 → wasmtime-component-macro-21.0.1}/tests/codegen/floats.wit +0 -0
  1561. /data/ext/cargo-vendor/{wasmtime-component-macro-20.0.2 → wasmtime-component-macro-21.0.1}/tests/codegen/function-new.wit +0 -0
  1562. /data/ext/cargo-vendor/{wasmtime-component-macro-20.0.2 → wasmtime-component-macro-21.0.1}/tests/codegen/integers.wit +0 -0
  1563. /data/ext/cargo-vendor/{wasmtime-component-macro-20.0.2 → wasmtime-component-macro-21.0.1}/tests/codegen/lists.wit +0 -0
  1564. /data/ext/cargo-vendor/{wasmtime-component-macro-20.0.2 → wasmtime-component-macro-21.0.1}/tests/codegen/many-arguments.wit +0 -0
  1565. /data/ext/cargo-vendor/{wasmtime-component-macro-20.0.2 → wasmtime-component-macro-21.0.1}/tests/codegen/multi-return.wit +0 -0
  1566. /data/ext/cargo-vendor/{wasmtime-component-macro-20.0.2 → wasmtime-component-macro-21.0.1}/tests/codegen/multiversion/deps/v1/root.wit +0 -0
  1567. /data/ext/cargo-vendor/{wasmtime-component-macro-20.0.2 → wasmtime-component-macro-21.0.1}/tests/codegen/multiversion/deps/v2/root.wit +0 -0
  1568. /data/ext/cargo-vendor/{wasmtime-component-macro-20.0.2 → wasmtime-component-macro-21.0.1}/tests/codegen/multiversion/root.wit +0 -0
  1569. /data/ext/cargo-vendor/{wasmtime-component-macro-20.0.2 → wasmtime-component-macro-21.0.1}/tests/codegen/records.wit +0 -0
  1570. /data/ext/cargo-vendor/{wasmtime-component-macro-20.0.2 → wasmtime-component-macro-21.0.1}/tests/codegen/rename.wit +0 -0
  1571. /data/ext/cargo-vendor/{wasmtime-component-macro-20.0.2 → wasmtime-component-macro-21.0.1}/tests/codegen/resources-export.wit +0 -0
  1572. /data/ext/cargo-vendor/{wasmtime-component-macro-20.0.2 → wasmtime-component-macro-21.0.1}/tests/codegen/resources-import.wit +0 -0
  1573. /data/ext/cargo-vendor/{wasmtime-component-macro-20.0.2 → wasmtime-component-macro-21.0.1}/tests/codegen/share-types.wit +0 -0
  1574. /data/ext/cargo-vendor/{wasmtime-component-macro-20.0.2 → wasmtime-component-macro-21.0.1}/tests/codegen/simple-functions.wit +0 -0
  1575. /data/ext/cargo-vendor/{wasmtime-component-macro-20.0.2 → wasmtime-component-macro-21.0.1}/tests/codegen/simple-lists.wit +0 -0
  1576. /data/ext/cargo-vendor/{wasmtime-component-macro-20.0.2 → wasmtime-component-macro-21.0.1}/tests/codegen/simple-wasi.wit +0 -0
  1577. /data/ext/cargo-vendor/{wasmtime-component-macro-20.0.2 → wasmtime-component-macro-21.0.1}/tests/codegen/small-anonymous.wit +0 -0
  1578. /data/ext/cargo-vendor/{wasmtime-component-macro-20.0.2 → wasmtime-component-macro-21.0.1}/tests/codegen/smoke-default.wit +0 -0
  1579. /data/ext/cargo-vendor/{wasmtime-component-macro-20.0.2 → wasmtime-component-macro-21.0.1}/tests/codegen/smoke-export.wit +0 -0
  1580. /data/ext/cargo-vendor/{wasmtime-component-macro-20.0.2 → wasmtime-component-macro-21.0.1}/tests/codegen/smoke.wit +0 -0
  1581. /data/ext/cargo-vendor/{wasmtime-component-macro-20.0.2 → wasmtime-component-macro-21.0.1}/tests/codegen/strings.wit +0 -0
  1582. /data/ext/cargo-vendor/{wasmtime-component-macro-20.0.2 → wasmtime-component-macro-21.0.1}/tests/codegen/unversioned-foo.wit +0 -0
  1583. /data/ext/cargo-vendor/{wasmtime-component-macro-20.0.2 → wasmtime-component-macro-21.0.1}/tests/codegen/use-paths.wit +0 -0
  1584. /data/ext/cargo-vendor/{wasmtime-component-macro-20.0.2 → wasmtime-component-macro-21.0.1}/tests/codegen/variants.wit +0 -0
  1585. /data/ext/cargo-vendor/{wasmtime-component-macro-20.0.2 → wasmtime-component-macro-21.0.1}/tests/codegen/wat.wit +0 -0
  1586. /data/ext/cargo-vendor/{wasmtime-component-macro-20.0.2 → wasmtime-component-macro-21.0.1}/tests/codegen/worlds-with-types.wit +0 -0
  1587. /data/ext/cargo-vendor/{wasmtime-cache-20.0.2 → wasmtime-cranelift-21.0.1}/LICENSE +0 -0
  1588. /data/ext/cargo-vendor/{wasmtime-cranelift-20.0.2 → wasmtime-cranelift-21.0.1}/SECURITY.md +0 -0
  1589. /data/ext/cargo-vendor/{wasmtime-cranelift-20.0.2 → wasmtime-cranelift-21.0.1}/src/builder.rs +0 -0
  1590. /data/ext/cargo-vendor/{wasmtime-cranelift-20.0.2 → wasmtime-cranelift-21.0.1}/src/compiled_function.rs +0 -0
  1591. /data/ext/cargo-vendor/{wasmtime-cranelift-20.0.2 → wasmtime-cranelift-21.0.1}/src/debug/transform/address_transform.rs +0 -0
  1592. /data/ext/cargo-vendor/{wasmtime-cranelift-20.0.2 → wasmtime-cranelift-21.0.1}/src/debug/transform/range_info_builder.rs +0 -0
  1593. /data/ext/cargo-vendor/{wasmtime-cranelift-20.0.2 → wasmtime-cranelift-21.0.1}/src/debug/transform/refs.rs +0 -0
  1594. /data/ext/cargo-vendor/{wasmtime-cranelift-20.0.2 → wasmtime-cranelift-21.0.1}/src/debug/transform/simulate.rs +0 -0
  1595. /data/ext/cargo-vendor/{wasmtime-cranelift-20.0.2 → wasmtime-cranelift-21.0.1}/src/gc/disabled.rs +0 -0
  1596. /data/ext/cargo-vendor/{wasmtime-cranelift-20.0.2 → wasmtime-cranelift-21.0.1}/src/isa_builder.rs +0 -0
  1597. /data/ext/cargo-vendor/{wasmtime-cranelift-20.0.2 → wasmtime-cranelift-21.0.1}/src/obj.rs +0 -0
  1598. /data/ext/cargo-vendor/{wasmtime-cranelift-20.0.2 → wasmtime-environ-21.0.1}/LICENSE +0 -0
  1599. /data/ext/cargo-vendor/{wasmtime-environ-20.0.2 → wasmtime-environ-21.0.1}/src/address_map.rs +0 -0
  1600. /data/ext/cargo-vendor/{wasmtime-environ-20.0.2 → wasmtime-environ-21.0.1}/src/builtin.rs +0 -0
  1601. /data/ext/cargo-vendor/{wasmtime-environ-20.0.2 → wasmtime-environ-21.0.1}/src/component/artifacts.rs +0 -0
  1602. /data/ext/cargo-vendor/{wasmtime-environ-20.0.2 → wasmtime-environ-21.0.1}/src/component/translate/inline.rs +0 -0
  1603. /data/ext/cargo-vendor/{wasmtime-environ-20.0.2 → wasmtime-environ-21.0.1}/src/component/vmcomponent_offsets.rs +0 -0
  1604. /data/ext/cargo-vendor/{wasmtime-environ-20.0.2 → wasmtime-environ-21.0.1}/src/gc.rs +0 -0
  1605. /data/ext/cargo-vendor/{wasmtime-environ-20.0.2 → wasmtime-environ-21.0.1}/src/obj.rs +0 -0
  1606. /data/ext/cargo-vendor/{wasmtime-environ-20.0.2 → wasmtime-environ-21.0.1}/src/ref_bits.rs +0 -0
  1607. /data/ext/cargo-vendor/{wasmtime-environ-20.0.2 → wasmtime-fiber-21.0.1}/LICENSE +0 -0
  1608. /data/ext/cargo-vendor/{wasmtime-fiber-20.0.2 → wasmtime-fiber-21.0.1}/src/unix/aarch64.rs +0 -0
  1609. /data/ext/cargo-vendor/{wasmtime-fiber-20.0.2 → wasmtime-fiber-21.0.1}/src/unix/arm.rs +0 -0
  1610. /data/ext/cargo-vendor/{wasmtime-fiber-20.0.2 → wasmtime-fiber-21.0.1}/src/unix/riscv64.rs +0 -0
  1611. /data/ext/cargo-vendor/{wasmtime-fiber-20.0.2 → wasmtime-fiber-21.0.1}/src/unix/s390x.S +0 -0
  1612. /data/ext/cargo-vendor/{wasmtime-fiber-20.0.2 → wasmtime-fiber-21.0.1}/src/unix/x86.rs +0 -0
  1613. /data/ext/cargo-vendor/{wasmtime-fiber-20.0.2 → wasmtime-fiber-21.0.1}/src/unix/x86_64.rs +0 -0
  1614. /data/ext/cargo-vendor/{wasmtime-fiber-20.0.2 → wasmtime-fiber-21.0.1}/src/windows.c +0 -0
  1615. /data/ext/cargo-vendor/{wasmtime-jit-debug-20.0.2 → wasmtime-jit-debug-21.0.1}/README.md +0 -0
  1616. /data/ext/cargo-vendor/{wasmtime-jit-debug-20.0.2 → wasmtime-jit-debug-21.0.1}/src/gdb_jit_int.rs +0 -0
  1617. /data/ext/cargo-vendor/{wasmtime-jit-debug-20.0.2 → wasmtime-jit-debug-21.0.1}/src/lib.rs +0 -0
  1618. /data/ext/cargo-vendor/{wasmtime-jit-debug-20.0.2 → wasmtime-jit-debug-21.0.1}/src/perf_jitdump.rs +0 -0
  1619. /data/ext/cargo-vendor/{wasmtime-fiber-20.0.2 → wasmtime-types-21.0.1}/LICENSE +0 -0
  1620. /data/ext/cargo-vendor/{wasmtime-versioned-export-macros-20.0.2 → wasmtime-versioned-export-macros-21.0.1}/src/lib.rs +0 -0
  1621. /data/ext/cargo-vendor/{wasmtime-runtime-20.0.2 → wasmtime-wasi-21.0.1}/LICENSE +0 -0
  1622. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/README.md +0 -0
  1623. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/src/clocks/host.rs +0 -0
  1624. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/src/clocks.rs +0 -0
  1625. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/src/error.rs +0 -0
  1626. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/src/host/clocks.rs +0 -0
  1627. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/src/host/env.rs +0 -0
  1628. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/src/host/exit.rs +0 -0
  1629. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/src/host/filesystem/sync.rs +0 -0
  1630. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/src/host/filesystem.rs +0 -0
  1631. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/src/host/instance_network.rs +0 -0
  1632. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/src/host/io.rs +0 -0
  1633. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/src/host/mod.rs +0 -0
  1634. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/src/host/network.rs +0 -0
  1635. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/src/host/random.rs +0 -0
  1636. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/src/host/tcp.rs +0 -0
  1637. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/src/host/tcp_create_socket.rs +0 -0
  1638. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/src/host/udp.rs +0 -0
  1639. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/src/host/udp_create_socket.rs +0 -0
  1640. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/src/ip_name_lookup.rs +0 -0
  1641. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/src/network.rs +0 -0
  1642. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/src/pipe.rs +0 -0
  1643. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/src/poll.rs +0 -0
  1644. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/src/random.rs +0 -0
  1645. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/src/runtime.rs +0 -0
  1646. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/src/stdio/worker_thread_stdin.rs +0 -0
  1647. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/src/stdio.rs +0 -0
  1648. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/src/stream.rs +0 -0
  1649. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/src/tcp.rs +0 -0
  1650. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/src/udp.rs +0 -0
  1651. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/src/write_stream.rs +0 -0
  1652. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/tests/process_stdin.rs +0 -0
  1653. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/wit/command-extended.wit +0 -0
  1654. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/wit/deps/cli/command.wit +0 -0
  1655. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/wit/deps/cli/environment.wit +0 -0
  1656. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/wit/deps/cli/exit.wit +0 -0
  1657. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/wit/deps/cli/imports.wit +0 -0
  1658. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/wit/deps/cli/run.wit +0 -0
  1659. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/wit/deps/cli/stdio.wit +0 -0
  1660. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/wit/deps/cli/terminal.wit +0 -0
  1661. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/wit/deps/clocks/monotonic-clock.wit +0 -0
  1662. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/wit/deps/clocks/wall-clock.wit +0 -0
  1663. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/wit/deps/clocks/world.wit +0 -0
  1664. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/wit/deps/filesystem/preopens.wit +0 -0
  1665. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/wit/deps/filesystem/types.wit +0 -0
  1666. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/wit/deps/filesystem/world.wit +0 -0
  1667. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/wit/deps/http/handler.wit +0 -0
  1668. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/wit/deps/http/proxy.wit +0 -0
  1669. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/wit/deps/http/types.wit +0 -0
  1670. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/wit/deps/io/error.wit +0 -0
  1671. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/wit/deps/io/poll.wit +0 -0
  1672. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/wit/deps/io/streams.wit +0 -0
  1673. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/wit/deps/io/world.wit +0 -0
  1674. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/wit/deps/random/insecure-seed.wit +0 -0
  1675. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/wit/deps/random/insecure.wit +0 -0
  1676. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/wit/deps/random/random.wit +0 -0
  1677. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/wit/deps/random/world.wit +0 -0
  1678. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/wit/deps/sockets/instance-network.wit +0 -0
  1679. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/wit/deps/sockets/ip-name-lookup.wit +0 -0
  1680. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/wit/deps/sockets/network.wit +0 -0
  1681. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/wit/deps/sockets/tcp-create-socket.wit +0 -0
  1682. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/wit/deps/sockets/tcp.wit +0 -0
  1683. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/wit/deps/sockets/udp-create-socket.wit +0 -0
  1684. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/wit/deps/sockets/udp.wit +0 -0
  1685. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/wit/deps/sockets/world.wit +0 -0
  1686. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/wit/test.wit +0 -0
  1687. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/witx/preview0/typenames.witx +0 -0
  1688. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/witx/preview0/wasi_unstable.witx +0 -0
  1689. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/witx/preview1/typenames.witx +0 -0
  1690. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wasmtime-wasi-21.0.1}/witx/preview1/wasi_snapshot_preview1.witx +0 -0
  1691. /data/ext/cargo-vendor/{wasmtime-winch-20.0.2 → wasmtime-winch-21.0.1}/LICENSE +0 -0
  1692. /data/ext/cargo-vendor/{wasmtime-winch-20.0.2 → wasmtime-winch-21.0.1}/src/builder.rs +0 -0
  1693. /data/ext/cargo-vendor/{wasmtime-winch-20.0.2 → wasmtime-winch-21.0.1}/src/lib.rs +0 -0
  1694. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-20.0.2 → wasmtime-wit-bindgen-21.0.1}/src/source.rs +0 -0
  1695. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-20.0.2 → wasmtime-wit-bindgen-21.0.1}/src/types.rs +0 -0
  1696. /data/ext/cargo-vendor/{wasmtime-types-20.0.2 → wiggle-21.0.1}/LICENSE +0 -0
  1697. /data/ext/cargo-vendor/{wiggle-20.0.2 → wiggle-21.0.1}/README.md +0 -0
  1698. /data/ext/cargo-vendor/{wiggle-20.0.2 → wiggle-21.0.1}/src/borrow.rs +0 -0
  1699. /data/ext/cargo-vendor/{wiggle-20.0.2 → wiggle-21.0.1}/src/error.rs +0 -0
  1700. /data/ext/cargo-vendor/{wiggle-20.0.2 → wiggle-21.0.1}/src/guest_type.rs +0 -0
  1701. /data/ext/cargo-vendor/{wiggle-20.0.2 → wiggle-21.0.1}/src/lib.rs +0 -0
  1702. /data/ext/cargo-vendor/{wiggle-20.0.2 → wiggle-21.0.1}/src/region.rs +0 -0
  1703. /data/ext/cargo-vendor/{wiggle-20.0.2 → wiggle-21.0.1}/src/wasmtime.rs +0 -0
  1704. /data/ext/cargo-vendor/{wasmtime-wasi-20.0.2 → wiggle-generate-21.0.1}/LICENSE +0 -0
  1705. /data/ext/cargo-vendor/{wiggle-generate-20.0.2 → wiggle-generate-21.0.1}/README.md +0 -0
  1706. /data/ext/cargo-vendor/{wiggle-generate-20.0.2 → wiggle-generate-21.0.1}/src/codegen_settings.rs +0 -0
  1707. /data/ext/cargo-vendor/{wiggle-generate-20.0.2 → wiggle-generate-21.0.1}/src/config.rs +0 -0
  1708. /data/ext/cargo-vendor/{wiggle-generate-20.0.2 → wiggle-generate-21.0.1}/src/funcs.rs +0 -0
  1709. /data/ext/cargo-vendor/{wiggle-generate-20.0.2 → wiggle-generate-21.0.1}/src/lib.rs +0 -0
  1710. /data/ext/cargo-vendor/{wiggle-generate-20.0.2 → wiggle-generate-21.0.1}/src/lifetimes.rs +0 -0
  1711. /data/ext/cargo-vendor/{wiggle-generate-20.0.2 → wiggle-generate-21.0.1}/src/module_trait.rs +0 -0
  1712. /data/ext/cargo-vendor/{wiggle-generate-20.0.2 → wiggle-generate-21.0.1}/src/names.rs +0 -0
  1713. /data/ext/cargo-vendor/{wiggle-generate-20.0.2 → wiggle-generate-21.0.1}/src/types/error.rs +0 -0
  1714. /data/ext/cargo-vendor/{wiggle-generate-20.0.2 → wiggle-generate-21.0.1}/src/types/flags.rs +0 -0
  1715. /data/ext/cargo-vendor/{wiggle-generate-20.0.2 → wiggle-generate-21.0.1}/src/types/handle.rs +0 -0
  1716. /data/ext/cargo-vendor/{wiggle-generate-20.0.2 → wiggle-generate-21.0.1}/src/types/mod.rs +0 -0
  1717. /data/ext/cargo-vendor/{wiggle-generate-20.0.2 → wiggle-generate-21.0.1}/src/types/record.rs +0 -0
  1718. /data/ext/cargo-vendor/{wiggle-generate-20.0.2 → wiggle-generate-21.0.1}/src/types/variant.rs +0 -0
  1719. /data/ext/cargo-vendor/{wiggle-generate-20.0.2 → wiggle-generate-21.0.1}/src/wasmtime.rs +0 -0
  1720. /data/ext/cargo-vendor/{wiggle-20.0.2 → wiggle-macro-21.0.1}/LICENSE +0 -0
  1721. /data/ext/cargo-vendor/{wiggle-macro-20.0.2 → wiggle-macro-21.0.1}/src/lib.rs +0 -0
  1722. /data/ext/cargo-vendor/{winch-codegen-0.18.2 → winch-codegen-0.19.1}/LICENSE +0 -0
  1723. /data/ext/cargo-vendor/{winch-codegen-0.18.2 → winch-codegen-0.19.1}/build.rs +0 -0
  1724. /data/ext/cargo-vendor/{winch-codegen-0.18.2 → winch-codegen-0.19.1}/src/abi/local.rs +0 -0
  1725. /data/ext/cargo-vendor/{winch-codegen-0.18.2 → winch-codegen-0.19.1}/src/abi/mod.rs +0 -0
  1726. /data/ext/cargo-vendor/{winch-codegen-0.18.2 → winch-codegen-0.19.1}/src/codegen/bounds.rs +0 -0
  1727. /data/ext/cargo-vendor/{winch-codegen-0.18.2 → winch-codegen-0.19.1}/src/codegen/builtin.rs +0 -0
  1728. /data/ext/cargo-vendor/{winch-codegen-0.18.2 → winch-codegen-0.19.1}/src/codegen/call.rs +0 -0
  1729. /data/ext/cargo-vendor/{winch-codegen-0.18.2 → winch-codegen-0.19.1}/src/codegen/control.rs +0 -0
  1730. /data/ext/cargo-vendor/{winch-codegen-0.18.2 → winch-codegen-0.19.1}/src/frame/mod.rs +0 -0
  1731. /data/ext/cargo-vendor/{winch-codegen-0.18.2 → winch-codegen-0.19.1}/src/isa/mod.rs +0 -0
  1732. /data/ext/cargo-vendor/{winch-codegen-0.18.2 → winch-codegen-0.19.1}/src/isa/x64/abi.rs +0 -0
  1733. /data/ext/cargo-vendor/{winch-codegen-0.18.2 → winch-codegen-0.19.1}/src/isa/x64/address.rs +0 -0
  1734. /data/ext/cargo-vendor/{winch-codegen-0.18.2 → winch-codegen-0.19.1}/src/isa/x64/mod.rs +0 -0
  1735. /data/ext/cargo-vendor/{winch-codegen-0.18.2 → winch-codegen-0.19.1}/src/isa/x64/regs.rs +0 -0
  1736. /data/ext/cargo-vendor/{winch-codegen-0.18.2 → winch-codegen-0.19.1}/src/lib.rs +0 -0
  1737. /data/ext/cargo-vendor/{winch-codegen-0.18.2 → winch-codegen-0.19.1}/src/stack.rs +0 -0
  1738. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/README.md +0 -0
  1739. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/src/abi.rs +0 -0
  1740. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/src/ast/lex.rs +0 -0
  1741. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/src/ast/toposort.rs +0 -0
  1742. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/src/ast.rs +0 -0
  1743. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/src/docs.rs +0 -0
  1744. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/src/serde_.rs +0 -0
  1745. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/src/sizealign.rs +0 -0
  1746. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/all.rs +0 -0
  1747. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/comments.wit +0 -0
  1748. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/comments.wit.json +0 -0
  1749. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/complex-include/deps/bar/root.wit +0 -0
  1750. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/complex-include/deps/baz/root.wit +0 -0
  1751. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/complex-include/root.wit +0 -0
  1752. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/complex-include.wit.json +0 -0
  1753. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/cross-package-resource/deps/foo/foo.wit +0 -0
  1754. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/cross-package-resource/foo.wit +0 -0
  1755. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/cross-package-resource.wit.json +0 -0
  1756. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/diamond1/deps/dep1/types.wit +0 -0
  1757. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/diamond1/deps/dep2/types.wit +0 -0
  1758. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/diamond1/join.wit +0 -0
  1759. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/diamond1.wit.json +0 -0
  1760. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/disambiguate-diamond/shared1.wit +0 -0
  1761. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/disambiguate-diamond/shared2.wit +0 -0
  1762. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/disambiguate-diamond/world.wit +0 -0
  1763. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/disambiguate-diamond.wit.json +0 -0
  1764. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/empty.wit +0 -0
  1765. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/empty.wit.json +0 -0
  1766. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/foreign-deps/deps/another-pkg/other-doc.wit +0 -0
  1767. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/foreign-deps/deps/corp/saas.wit +0 -0
  1768. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/foreign-deps/deps/different-pkg/the-doc.wit +0 -0
  1769. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/foreign-deps/deps/foreign-pkg/the-doc.wit +0 -0
  1770. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/foreign-deps/deps/some-pkg/some-doc.wit +0 -0
  1771. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/foreign-deps/deps/wasi/clocks.wit +0 -0
  1772. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/foreign-deps/deps/wasi/filesystem.wit +0 -0
  1773. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/foreign-deps/root.wit +0 -0
  1774. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/foreign-deps-union/deps/another-pkg/other-doc.wit +0 -0
  1775. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/foreign-deps-union/deps/corp/saas.wit +0 -0
  1776. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/foreign-deps-union/deps/different-pkg/the-doc.wit +0 -0
  1777. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/foreign-deps-union/deps/foreign-pkg/the-doc.wit +0 -0
  1778. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/foreign-deps-union/deps/some-pkg/some-doc.wit +0 -0
  1779. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/foreign-deps-union/deps/wasi/clocks.wit +0 -0
  1780. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/foreign-deps-union/deps/wasi/filesystem.wit +0 -0
  1781. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/foreign-deps-union/deps/wasi/wasi.wit +0 -0
  1782. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/foreign-deps-union/root.wit +0 -0
  1783. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/foreign-deps-union.wit.json +0 -0
  1784. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/foreign-deps.wit.json +0 -0
  1785. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/functions.wit +0 -0
  1786. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/functions.wit.json +0 -0
  1787. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/ignore-files-deps/deps/bar/types.wit +0 -0
  1788. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/ignore-files-deps/deps/ignore-me.txt +0 -0
  1789. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/ignore-files-deps/world.wit +0 -0
  1790. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/ignore-files-deps.wit.json +0 -0
  1791. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/import-export-overlap1.wit +0 -0
  1792. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/import-export-overlap1.wit.json +0 -0
  1793. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/import-export-overlap2.wit +0 -0
  1794. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/import-export-overlap2.wit.json +0 -0
  1795. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/include-reps.wit +0 -0
  1796. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/include-reps.wit.json +0 -0
  1797. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/kebab-name-include-with.wit +0 -0
  1798. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/kebab-name-include-with.wit.json +0 -0
  1799. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/kinds-of-deps/a.wit +0 -0
  1800. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/kinds-of-deps/deps/b/root.wit +0 -0
  1801. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/kinds-of-deps/deps/c.wit +0 -0
  1802. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/kinds-of-deps/deps/d.wat +0 -0
  1803. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/kinds-of-deps/deps/e.wasm +0 -0
  1804. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/kinds-of-deps.wit.json +0 -0
  1805. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/many-names/a.wit +0 -0
  1806. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/many-names/b.wit +0 -0
  1807. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/many-names.wit.json +0 -0
  1808. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/multi-file/bar.wit +0 -0
  1809. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/multi-file/cycle-a.wit +0 -0
  1810. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/multi-file/cycle-b.wit +0 -0
  1811. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/multi-file/foo.wit +0 -0
  1812. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/multi-file.wit.json +0 -0
  1813. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/name-both-resource-and-type/deps/dep/foo.wit +0 -0
  1814. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/name-both-resource-and-type/foo.wit +0 -0
  1815. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/name-both-resource-and-type.wit.json +0 -0
  1816. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/package-syntax1.wit +0 -0
  1817. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/package-syntax1.wit.json +0 -0
  1818. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/package-syntax3.wit +0 -0
  1819. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/package-syntax3.wit.json +0 -0
  1820. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/package-syntax4.wit +0 -0
  1821. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/package-syntax4.wit.json +0 -0
  1822. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/alias-no-type.wit +0 -0
  1823. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/alias-no-type.wit.result +0 -0
  1824. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/async.wit.result +0 -0
  1825. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/async1.wit.result +0 -0
  1826. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-function.wit +0 -0
  1827. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-function.wit.result +0 -0
  1828. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-function2.wit +0 -0
  1829. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-function2.wit.result +0 -0
  1830. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-include1.wit +0 -0
  1831. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-include1.wit.result +0 -0
  1832. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-include2.wit +0 -0
  1833. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-include2.wit.result +0 -0
  1834. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-include3.wit +0 -0
  1835. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-include3.wit.result +0 -0
  1836. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-list.wit +0 -0
  1837. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-list.wit.result +0 -0
  1838. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-pkg1/root.wit +0 -0
  1839. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-pkg1.wit.result +0 -0
  1840. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-pkg2/deps/bar/empty.wit +0 -0
  1841. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-pkg2/root.wit +0 -0
  1842. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-pkg2.wit.result +0 -0
  1843. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-pkg3/deps/bar/baz.wit +0 -0
  1844. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-pkg3/root.wit +0 -0
  1845. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-pkg3.wit.result +0 -0
  1846. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-pkg4/deps/bar/baz.wit +0 -0
  1847. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-pkg4/root.wit +0 -0
  1848. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-pkg4.wit.result +0 -0
  1849. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-pkg5/deps/bar/baz.wit +0 -0
  1850. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-pkg5/root.wit +0 -0
  1851. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-pkg5.wit.result +0 -0
  1852. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-pkg6/deps/bar/baz.wit +0 -0
  1853. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-pkg6/root.wit +0 -0
  1854. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-pkg6.wit.result +0 -0
  1855. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-resource1.wit +0 -0
  1856. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-resource1.wit.result +0 -0
  1857. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-resource10.wit +0 -0
  1858. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-resource10.wit.result +0 -0
  1859. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-resource11.wit +0 -0
  1860. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-resource11.wit.result +0 -0
  1861. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-resource12.wit +0 -0
  1862. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-resource12.wit.result +0 -0
  1863. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-resource13.wit +0 -0
  1864. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-resource13.wit.result +0 -0
  1865. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-resource14.wit +0 -0
  1866. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-resource14.wit.result +0 -0
  1867. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-resource15/deps/foo/foo.wit +0 -0
  1868. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-resource15/foo.wit +0 -0
  1869. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-resource15.wit.result +0 -0
  1870. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-resource2.wit +0 -0
  1871. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-resource2.wit.result +0 -0
  1872. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-resource3.wit +0 -0
  1873. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-resource3.wit.result +0 -0
  1874. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-resource4.wit +0 -0
  1875. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-resource4.wit.result +0 -0
  1876. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-resource5.wit +0 -0
  1877. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-resource5.wit.result +0 -0
  1878. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-resource6.wit +0 -0
  1879. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-resource6.wit.result +0 -0
  1880. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-resource7.wit +0 -0
  1881. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-resource7.wit.result +0 -0
  1882. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-resource8.wit +0 -0
  1883. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-resource8.wit.result +0 -0
  1884. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-resource9.wit +0 -0
  1885. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-resource9.wit.result +0 -0
  1886. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-world-type1.wit +0 -0
  1887. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/bad-world-type1.wit.result +0 -0
  1888. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/conflicting-package/a.wit +0 -0
  1889. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/conflicting-package/b.wit +0 -0
  1890. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/conflicting-package.wit.result +0 -0
  1891. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/cycle.wit +0 -0
  1892. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/cycle.wit.result +0 -0
  1893. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/cycle2.wit +0 -0
  1894. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/cycle2.wit.result +0 -0
  1895. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/cycle3.wit +0 -0
  1896. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/cycle3.wit.result +0 -0
  1897. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/cycle4.wit +0 -0
  1898. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/cycle4.wit.result +0 -0
  1899. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/cycle5.wit +0 -0
  1900. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/cycle5.wit.result +0 -0
  1901. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/dangling-type.wit +0 -0
  1902. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/dangling-type.wit.result +0 -0
  1903. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/duplicate-function-params.wit +0 -0
  1904. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/duplicate-function-params.wit.result +0 -0
  1905. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/duplicate-functions.wit +0 -0
  1906. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/duplicate-functions.wit.result +0 -0
  1907. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/duplicate-interface.wit +0 -0
  1908. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/duplicate-interface.wit.result +0 -0
  1909. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/duplicate-interface2/foo.wit +0 -0
  1910. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/duplicate-interface2/foo2.wit +0 -0
  1911. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/duplicate-interface2.wit.result +0 -0
  1912. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/duplicate-type.wit +0 -0
  1913. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/duplicate-type.wit.result +0 -0
  1914. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/empty-enum.wit +0 -0
  1915. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/empty-enum.wit.result +0 -0
  1916. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/empty-variant1.wit +0 -0
  1917. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/empty-variant1.wit.result +0 -0
  1918. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/export-twice.wit +0 -0
  1919. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/export-twice.wit.result +0 -0
  1920. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/import-and-export1.wit +0 -0
  1921. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/import-and-export1.wit.result +0 -0
  1922. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/import-and-export2.wit +0 -0
  1923. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/import-and-export2.wit.result +0 -0
  1924. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/import-and-export3.wit +0 -0
  1925. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/import-and-export3.wit.result +0 -0
  1926. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/import-and-export4.wit +0 -0
  1927. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/import-and-export4.wit.result +0 -0
  1928. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/import-and-export5.wit +0 -0
  1929. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/import-and-export5.wit.result +0 -0
  1930. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/import-twice.wit +0 -0
  1931. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/import-twice.wit.result +0 -0
  1932. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/include-cycle.wit +0 -0
  1933. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/include-cycle.wit.result +0 -0
  1934. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/include-foreign/deps/bar/empty.wit +0 -0
  1935. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/include-foreign/root.wit +0 -0
  1936. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/include-foreign.wit.result +0 -0
  1937. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/include-with-id.wit +0 -0
  1938. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/include-with-id.wit.result +0 -0
  1939. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/include-with-on-id.wit +0 -0
  1940. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/include-with-on-id.wit.result +0 -0
  1941. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/invalid-toplevel.wit +0 -0
  1942. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/invalid-toplevel.wit.result +0 -0
  1943. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/invalid-type-reference.wit +0 -0
  1944. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/invalid-type-reference.wit.result +0 -0
  1945. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/invalid-type-reference2.wit +0 -0
  1946. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/invalid-type-reference2.wit.result +0 -0
  1947. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/kebab-name-include-not-found.wit +0 -0
  1948. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/kebab-name-include-not-found.wit.result +0 -0
  1949. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/kebab-name-include.wit +0 -0
  1950. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/kebab-name-include.wit.result +0 -0
  1951. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/keyword.wit +0 -0
  1952. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/keyword.wit.result +0 -0
  1953. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/missing-package.wit +0 -0
  1954. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/missing-package.wit.result +0 -0
  1955. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/multiple-package-docs/a.wit +0 -0
  1956. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/multiple-package-docs/b.wit +0 -0
  1957. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/multiple-package-docs.wit.result +0 -0
  1958. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/no-access-to-sibling-use/bar.wit +0 -0
  1959. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/no-access-to-sibling-use/foo.wit +0 -0
  1960. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/no-access-to-sibling-use.wit.result +0 -0
  1961. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/non-existance-world-include/deps/bar/baz.wit +0 -0
  1962. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/non-existance-world-include/root.wit +0 -0
  1963. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/non-existance-world-include.wit.result +0 -0
  1964. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/pkg-cycle/deps/a1/root.wit +0 -0
  1965. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/pkg-cycle/root.wit +0 -0
  1966. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/pkg-cycle.wit.result +0 -0
  1967. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/pkg-cycle2/deps/a1/root.wit +0 -0
  1968. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/pkg-cycle2/deps/a2/root.wit +0 -0
  1969. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/pkg-cycle2/root.wit +0 -0
  1970. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/pkg-cycle2.wit.result +0 -0
  1971. /data/ext/cargo-vendor/{wit-parser-0.202.0/tests/ui → wit-parser-0.207.0/tests/ui/parse-fail}/resources-multiple-returns-borrow.wit +0 -0
  1972. /data/ext/cargo-vendor/{wit-parser-0.202.0/tests/ui → wit-parser-0.207.0/tests/ui/parse-fail}/resources-return-borrow.wit +0 -0
  1973. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/type-and-resource-same-name/deps/dep/foo.wit +0 -0
  1974. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/type-and-resource-same-name/foo.wit +0 -0
  1975. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/type-and-resource-same-name.wit.result +0 -0
  1976. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/undefined-typed.wit +0 -0
  1977. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/undefined-typed.wit.result +0 -0
  1978. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/unknown-interface.wit +0 -0
  1979. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/unknown-interface.wit.result +0 -0
  1980. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/unresolved-interface1.wit +0 -0
  1981. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/unresolved-interface1.wit.result +0 -0
  1982. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/unresolved-interface2.wit +0 -0
  1983. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/unresolved-interface2.wit.result +0 -0
  1984. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/unresolved-interface3.wit +0 -0
  1985. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/unresolved-interface3.wit.result +0 -0
  1986. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/unresolved-interface4.wit +0 -0
  1987. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/unresolved-interface4.wit.result +0 -0
  1988. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/unresolved-use1.wit +0 -0
  1989. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/unresolved-use1.wit.result +0 -0
  1990. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/unresolved-use10/bar.wit +0 -0
  1991. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/unresolved-use10/foo.wit +0 -0
  1992. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/unresolved-use10.wit.result +0 -0
  1993. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/unresolved-use2.wit +0 -0
  1994. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/unresolved-use2.wit.result +0 -0
  1995. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/unresolved-use3.wit +0 -0
  1996. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/unresolved-use3.wit.result +0 -0
  1997. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/unresolved-use7.wit +0 -0
  1998. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/unresolved-use7.wit.result +0 -0
  1999. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/unresolved-use8.wit +0 -0
  2000. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/unresolved-use8.wit.result +0 -0
  2001. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/unresolved-use9.wit +0 -0
  2002. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/unresolved-use9.wit.result +0 -0
  2003. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/unterminated-string.wit.result +0 -0
  2004. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/use-and-include-world/deps/bar/baz.wit +0 -0
  2005. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/use-and-include-world/root.wit +0 -0
  2006. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/use-and-include-world.wit.result +0 -0
  2007. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/use-conflict.wit +0 -0
  2008. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/use-conflict.wit.result +0 -0
  2009. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/use-conflict2.wit +0 -0
  2010. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/use-conflict2.wit.result +0 -0
  2011. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/use-conflict3.wit +0 -0
  2012. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/use-conflict3.wit.result +0 -0
  2013. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/use-cycle1.wit +0 -0
  2014. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/use-cycle1.wit.result +0 -0
  2015. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/use-cycle4.wit +0 -0
  2016. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/use-cycle4.wit.result +0 -0
  2017. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/use-shadow1.wit +0 -0
  2018. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/use-shadow1.wit.result +0 -0
  2019. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/use-world/deps/bar/baz.wit +0 -0
  2020. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/use-world/root.wit +0 -0
  2021. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/use-world.wit.result +0 -0
  2022. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/world-interface-clash.wit +0 -0
  2023. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/world-interface-clash.wit.result +0 -0
  2024. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/world-same-fields2.wit +0 -0
  2025. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/world-same-fields2.wit.result +0 -0
  2026. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/world-same-fields3.wit +0 -0
  2027. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/world-same-fields3.wit.result +0 -0
  2028. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/world-top-level-func.wit +0 -0
  2029. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/world-top-level-func.wit.result +0 -0
  2030. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/world-top-level-func2.wit +0 -0
  2031. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/parse-fail/world-top-level-func2.wit.result +0 -0
  2032. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/random.wit +0 -0
  2033. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/random.wit.json +0 -0
  2034. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/resources-empty.wit +0 -0
  2035. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/resources-empty.wit.json +0 -0
  2036. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/resources-multiple-returns-own.wit +0 -0
  2037. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/resources-multiple-returns-own.wit.json +0 -0
  2038. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/resources-multiple.wit +0 -0
  2039. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/resources-multiple.wit.json +0 -0
  2040. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/resources-return-own.wit +0 -0
  2041. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/resources-return-own.wit.json +0 -0
  2042. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/resources.wit +0 -0
  2043. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/resources.wit.json +0 -0
  2044. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/resources1.wit +0 -0
  2045. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/resources1.wit.json +0 -0
  2046. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/same-name-import-export.wit +0 -0
  2047. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/same-name-import-export.wit.json +0 -0
  2048. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/shared-types.wit +0 -0
  2049. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/shared-types.wit.json +0 -0
  2050. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/simple-wasm-text.wat +0 -0
  2051. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/simple-wasm-text.wit.json +0 -0
  2052. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/stress-export-elaborate.wit +0 -0
  2053. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/stress-export-elaborate.wit.json +0 -0
  2054. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/type-then-eof.wit +0 -0
  2055. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/type-then-eof.wit.json +0 -0
  2056. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/types.wit +0 -0
  2057. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/types.wit.json +0 -0
  2058. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/union-fuzz-1.wit +0 -0
  2059. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/union-fuzz-1.wit.json +0 -0
  2060. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/union-fuzz-2.wit +0 -0
  2061. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/union-fuzz-2.wit.json +0 -0
  2062. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/use-chain.wit +0 -0
  2063. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/use-chain.wit.json +0 -0
  2064. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/use.wit +0 -0
  2065. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/use.wit.json +0 -0
  2066. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/versions/deps/a1/foo.wit +0 -0
  2067. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/versions/deps/a2/foo.wit +0 -0
  2068. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/versions/foo.wit +0 -0
  2069. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/versions.wit.json +0 -0
  2070. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/wasi.wit +0 -0
  2071. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/wasi.wit.json +0 -0
  2072. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/world-diamond.wit +0 -0
  2073. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/world-diamond.wit.json +0 -0
  2074. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/world-iface-no-collide.wit +0 -0
  2075. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/world-iface-no-collide.wit.json +0 -0
  2076. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/world-implicit-import1.wit +0 -0
  2077. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/world-implicit-import1.wit.json +0 -0
  2078. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/world-implicit-import2.wit +0 -0
  2079. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/world-implicit-import2.wit.json +0 -0
  2080. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/world-implicit-import3.wit +0 -0
  2081. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/world-implicit-import3.wit.json +0 -0
  2082. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/world-same-fields4.wit +0 -0
  2083. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/world-same-fields4.wit.json +0 -0
  2084. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/world-top-level-funcs.wit +0 -0
  2085. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/world-top-level-funcs.wit.json +0 -0
  2086. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/worlds-union-dedup.wit +0 -0
  2087. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/worlds-union-dedup.wit.json +0 -0
  2088. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/worlds-with-types.wit +0 -0
  2089. /data/ext/cargo-vendor/{wit-parser-0.202.0 → wit-parser-0.207.0}/tests/ui/worlds-with-types.wit.json +0 -0
@@ -0,0 +1,4808 @@
1
+ ;; x86-64 instruction selection and CLIF-to-MachInst lowering.
2
+
3
+ ;; The main lowering constructor term: takes a clif `Inst` and returns the
4
+ ;; register(s) within which the lowered instruction's result values live.
5
+ (decl partial lower (Inst) InstOutput)
6
+
7
+ ;; A variant of the main lowering constructor term, used for branches.
8
+ ;; The only difference is that it gets an extra argument holding a vector
9
+ ;; of branch targets to be used.
10
+ (decl partial lower_branch (Inst MachLabelSlice) Unit)
11
+
12
+ ;;;; Rules for `iconst` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
13
+
14
+ ;; `i64` and smaller.
15
+ (rule (lower (has_type (fits_in_64 ty)
16
+ (iconst (u64_from_imm64 x))))
17
+ (imm ty x))
18
+
19
+ ;; `i128`
20
+ (rule 1 (lower (has_type $I128
21
+ (iconst (u64_from_imm64 x))))
22
+ (value_regs (imm $I64 x)
23
+ (imm $I64 0)))
24
+
25
+ ;;;; Rules for `f32const` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
26
+
27
+ (rule (lower (f32const (u32_from_ieee32 x)))
28
+ (imm $F32 x))
29
+
30
+ ;;;; Rules for `f64const` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
31
+
32
+ (rule (lower (f64const (u64_from_ieee64 x)))
33
+ (imm $F64 x))
34
+
35
+ ;;;; Rules for `null` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
36
+
37
+ (rule (lower (has_type ty (null)))
38
+ (imm ty 0))
39
+
40
+ ;;;; Rules for `iadd` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
41
+
42
+ ;; `i64` and smaller.
43
+
44
+ ;; Base case for 8 and 16-bit types
45
+ (rule -6 (lower (has_type (fits_in_16 ty)
46
+ (iadd x y)))
47
+ (x64_add ty x y))
48
+
49
+ ;; Base case for 32 and 64-bit types which might end up using the `lea`
50
+ ;; instruction to fold multiple operations into one.
51
+ ;;
52
+ ;; Note that at this time this always generates a `lea` pseudo-instruction,
53
+ ;; but the actual instruction emitted might be an `add` if it's equivalent.
54
+ ;; For more details on this see the `emit.rs` logic to emit
55
+ ;; `LoadEffectiveAddress`.
56
+ (rule -5 (lower (has_type (ty_32_or_64 ty) (iadd x y)))
57
+ (x64_lea ty (to_amode_add (mem_flags_trusted) x y (zero_offset))))
58
+
59
+ ;; Higher-priority cases than the previous two where a load can be sunk into
60
+ ;; the add instruction itself. Note that both operands are tested for
61
+ ;; sink-ability since addition is commutative
62
+ (rule -4 (lower (has_type (fits_in_64 ty)
63
+ (iadd x (sinkable_load y))))
64
+ (x64_add ty x y))
65
+ (rule -3 (lower (has_type (fits_in_64 ty)
66
+ (iadd (sinkable_load x) y)))
67
+ (x64_add ty y x))
68
+
69
+ ;; SSE.
70
+
71
+ (rule (lower (has_type (multi_lane 8 16)
72
+ (iadd x y)))
73
+ (x64_paddb x y))
74
+
75
+ (rule (lower (has_type (multi_lane 16 8)
76
+ (iadd x y)))
77
+ (x64_paddw x y))
78
+
79
+ (rule (lower (has_type (multi_lane 32 4)
80
+ (iadd x y)))
81
+ (x64_paddd x y))
82
+
83
+ (rule (lower (has_type (multi_lane 64 2)
84
+ (iadd x y)))
85
+ (x64_paddq x y))
86
+
87
+ ;; `i128`
88
+ (rule 1 (lower (has_type $I128 (iadd x y)))
89
+ ;; Get the high/low registers for `x`.
90
+ (let ((x_regs ValueRegs x)
91
+ (x_lo Gpr (value_regs_get_gpr x_regs 0))
92
+ (x_hi Gpr (value_regs_get_gpr x_regs 1)))
93
+ ;; Get the high/low registers for `y`.
94
+ (let ((y_regs ValueRegs y)
95
+ (y_lo Gpr (value_regs_get_gpr y_regs 0))
96
+ (y_hi Gpr (value_regs_get_gpr y_regs 1)))
97
+ ;; Do an add followed by an add-with-carry.
98
+ (with_flags (x64_add_with_flags_paired $I64 x_lo y_lo)
99
+ (x64_adc_paired $I64 x_hi y_hi)))))
100
+
101
+ ;;;; Helpers for `*_overflow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
102
+
103
+ (decl construct_overflow_op (CC ProducesFlags) InstOutput)
104
+ (rule (construct_overflow_op cc inst)
105
+ (let ((results ValueRegs (with_flags inst
106
+ (x64_setcc_paired cc))))
107
+ (output_pair (value_regs_get results 0)
108
+ (value_regs_get results 1))))
109
+
110
+ (decl construct_overflow_op_alu (Type CC AluRmiROpcode Gpr GprMemImm) InstOutput)
111
+ (rule (construct_overflow_op_alu ty cc alu_op src1 src2)
112
+ (construct_overflow_op cc (x64_alurmi_with_flags_paired alu_op ty src1 src2)))
113
+
114
+ ;; This essentially creates
115
+ ;; alu_<op1> x_lo, y_lo
116
+ ;; alu_<op2> x_hi, y_hi
117
+ ;; set<cc> r8
118
+ (decl construct_overflow_op_alu_128 (CC AluRmiROpcode AluRmiROpcode Value Value) InstOutput)
119
+ (rule (construct_overflow_op_alu_128 cc op1 op2 x y)
120
+ ;; Get the high/low registers for `x`.
121
+ (let ((x_regs ValueRegs x)
122
+ (x_lo Gpr (value_regs_get_gpr x_regs 0))
123
+ (x_hi Gpr (value_regs_get_gpr x_regs 1)))
124
+ ;; Get the high/low registers for `y`.
125
+ (let ((y_regs ValueRegs y)
126
+ (y_lo Gpr (value_regs_get_gpr y_regs 0))
127
+ (y_hi Gpr (value_regs_get_gpr y_regs 1)))
128
+ (let ((lo_inst ProducesFlags (x64_alurmi_with_flags_paired op1 $I64 x_lo y_lo))
129
+ (hi_inst ConsumesAndProducesFlags (x64_alurmi_with_flags_chained op2 $I64 x_hi y_hi))
130
+ (of_inst ConsumesFlags (x64_setcc_paired cc))
131
+
132
+ (result MultiReg (with_flags_chained lo_inst hi_inst of_inst)))
133
+ (multi_reg_to_pair_and_single result)))))
134
+
135
+ ;;;; Rules for `uadd_overflow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
136
+
137
+ (rule 1 (lower (uadd_overflow x y @ (value_type (fits_in_64 ty))))
138
+ (construct_overflow_op_alu ty (CC.B) (AluRmiROpcode.Add) x y))
139
+
140
+ ;; i128 gets lowered into adc and add
141
+ (rule 0 (lower (uadd_overflow x y @ (value_type $I128)))
142
+ (construct_overflow_op_alu_128 (CC.B) (AluRmiROpcode.Add) (AluRmiROpcode.Adc) x y))
143
+
144
+ ;;;; Rules for `sadd_overflow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
145
+
146
+ (rule 1 (lower (sadd_overflow x y @ (value_type (fits_in_64 ty))))
147
+ (construct_overflow_op_alu ty (CC.O) (AluRmiROpcode.Add) x y))
148
+
149
+ (rule 0 (lower (sadd_overflow x y @ (value_type $I128)))
150
+ (construct_overflow_op_alu_128 (CC.O) (AluRmiROpcode.Add) (AluRmiROpcode.Adc) x y))
151
+
152
+ ;;;; Rules for `usub_overflow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
153
+
154
+ (rule 1 (lower (usub_overflow x y @ (value_type (fits_in_64 ty))))
155
+ (construct_overflow_op_alu ty (CC.B) (AluRmiROpcode.Sub) x y))
156
+
157
+ (rule 0 (lower (usub_overflow x y @ (value_type $I128)))
158
+ (construct_overflow_op_alu_128 (CC.B) (AluRmiROpcode.Sub) (AluRmiROpcode.Sbb) x y))
159
+
160
+ ;;;; Rules for `ssub_overflow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
161
+
162
+ (rule 1 (lower (ssub_overflow x y @ (value_type (fits_in_64 ty))))
163
+ (construct_overflow_op_alu ty (CC.O) (AluRmiROpcode.Sub) x y))
164
+
165
+ (rule 0 (lower (ssub_overflow x y @ (value_type $I128)))
166
+ (construct_overflow_op_alu_128 (CC.O) (AluRmiROpcode.Sub) (AluRmiROpcode.Sbb) x y))
167
+
168
+ ;;;; Rules for `umul_overflow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
169
+
170
+ (rule 2 (lower (umul_overflow x y @ (value_type $I8)))
171
+ (construct_overflow_op (CC.O) (x64_mul8_with_flags_paired $false x y)))
172
+
173
+ (rule 3 (lower (umul_overflow x y @ (value_type (ty_int_ref_16_to_64 ty))))
174
+ (construct_overflow_op (CC.O) (x64_mul_lo_with_flags_paired ty $false x y)))
175
+
176
+ ;;;; Rules for `smul_overflow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
177
+
178
+ (rule 2 (lower (smul_overflow x y @ (value_type $I8)))
179
+ (construct_overflow_op (CC.O) (x64_mul8_with_flags_paired $true x y)))
180
+
181
+ (rule 3 (lower (smul_overflow x y @ (value_type (ty_int_ref_16_to_64 ty))))
182
+ (construct_overflow_op (CC.O) (x64_mul_lo_with_flags_paired ty $true x y)))
183
+
184
+ ;;;; Rules for `sadd_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
185
+
186
+ (rule (lower (has_type (multi_lane 8 16)
187
+ (sadd_sat x y)))
188
+ (x64_paddsb x y))
189
+
190
+ (rule (lower (has_type (multi_lane 16 8)
191
+ (sadd_sat x y)))
192
+ (x64_paddsw x y))
193
+
194
+ ;;;; Rules for `uadd_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
195
+
196
+ (rule (lower (has_type (multi_lane 8 16)
197
+ (uadd_sat x y)))
198
+ (x64_paddusb x y))
199
+
200
+ (rule (lower (has_type (multi_lane 16 8)
201
+ (uadd_sat x y)))
202
+ (x64_paddusw x y))
203
+
204
+ ;;;; Rules for `isub` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
205
+
206
+ ;; `i64` and smaller.
207
+
208
+ ;; Sub two registers.
209
+ (rule -3 (lower (has_type (fits_in_64 ty)
210
+ (isub x y)))
211
+ (x64_sub ty x y))
212
+
213
+ ;; SSE.
214
+
215
+ (rule (lower (has_type (multi_lane 8 16)
216
+ (isub x y)))
217
+ (x64_psubb x y))
218
+
219
+ (rule (lower (has_type (multi_lane 16 8)
220
+ (isub x y)))
221
+ (x64_psubw x y))
222
+
223
+ (rule (lower (has_type (multi_lane 32 4)
224
+ (isub x y)))
225
+ (x64_psubd x y))
226
+
227
+ (rule (lower (has_type (multi_lane 64 2)
228
+ (isub x y)))
229
+ (x64_psubq x y))
230
+
231
+ ;; `i128`
232
+ (rule 1 (lower (has_type $I128 (isub x y)))
233
+ ;; Get the high/low registers for `x`.
234
+ (let ((x_regs ValueRegs x)
235
+ (x_lo Gpr (value_regs_get_gpr x_regs 0))
236
+ (x_hi Gpr (value_regs_get_gpr x_regs 1)))
237
+ ;; Get the high/low registers for `y`.
238
+ (let ((y_regs ValueRegs y)
239
+ (y_lo Gpr (value_regs_get_gpr y_regs 0))
240
+ (y_hi Gpr (value_regs_get_gpr y_regs 1)))
241
+ ;; Do a sub followed by an sub-with-borrow.
242
+ (with_flags (x64_sub_with_flags_paired $I64 x_lo y_lo)
243
+ (x64_sbb_paired $I64 x_hi y_hi)))))
244
+
245
+ ;;;; Rules for `ssub_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
246
+
247
+ (rule (lower (has_type (multi_lane 8 16)
248
+ (ssub_sat x y)))
249
+ (x64_psubsb x y))
250
+
251
+ (rule (lower (has_type (multi_lane 16 8)
252
+ (ssub_sat x y)))
253
+ (x64_psubsw x y))
254
+
255
+ ;;;; Rules for `usub_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
256
+
257
+ (rule (lower (has_type (multi_lane 8 16)
258
+ (usub_sat x y)))
259
+ (x64_psubusb x y))
260
+
261
+ (rule (lower (has_type (multi_lane 16 8)
262
+ (usub_sat x y)))
263
+ (x64_psubusw x y))
264
+
265
+ ;;;; Rules for `band` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
266
+
267
+ ;; `{i,b}64` and smaller.
268
+
269
+ ;; And two registers.
270
+ (rule 0 (lower (has_type ty (band x y)))
271
+ (if (ty_int_ref_scalar_64 ty))
272
+ (x64_and ty x y))
273
+
274
+ ;; The above case automatically handles when the rhs is an immediate or a
275
+ ;; sinkable load, but additionally handle the lhs here.
276
+
277
+ (rule 1 (lower (has_type ty (band (sinkable_load x) y)))
278
+ (if (ty_int_ref_scalar_64 ty))
279
+ (x64_and ty y x))
280
+
281
+ (rule 2 (lower (has_type ty (band (simm32_from_value x) y)))
282
+ (if (ty_int_ref_scalar_64 ty))
283
+ (x64_and ty y x))
284
+
285
+ ;; f32 and f64
286
+
287
+ (rule 5 (lower (has_type (ty_scalar_float ty) (band x y)))
288
+ (sse_and ty x y))
289
+
290
+ ;; SSE.
291
+
292
+ (decl sse_and (Type Xmm XmmMem) Xmm)
293
+ (rule (sse_and $F32X4 x y) (x64_andps x y))
294
+ (rule (sse_and $F64X2 x y) (x64_andpd x y))
295
+ (rule (sse_and $F32 x y) (x64_andps x y))
296
+ (rule (sse_and $F64 x y) (x64_andpd x y))
297
+ (rule -1 (sse_and (multi_lane _bits _lanes) x y) (x64_pand x y))
298
+
299
+ (rule 6 (lower (has_type ty @ (multi_lane _bits _lanes)
300
+ (band x y)))
301
+ (sse_and ty x y))
302
+
303
+ ;; `i128`.
304
+
305
+ (decl and_i128 (ValueRegs ValueRegs) ValueRegs)
306
+ (rule (and_i128 x y)
307
+ (let ((x_regs ValueRegs x)
308
+ (x_lo Gpr (value_regs_get_gpr x_regs 0))
309
+ (x_hi Gpr (value_regs_get_gpr x_regs 1))
310
+ (y_regs ValueRegs y)
311
+ (y_lo Gpr (value_regs_get_gpr y_regs 0))
312
+ (y_hi Gpr (value_regs_get_gpr y_regs 1)))
313
+ (value_gprs (x64_and $I64 x_lo y_lo)
314
+ (x64_and $I64 x_hi y_hi))))
315
+
316
+ (rule 7 (lower (has_type $I128 (band x y)))
317
+ (and_i128 x y))
318
+
319
+ ;; Specialized lowerings for `(band x (bnot y))` which is additionally produced
320
+ ;; by Cranelift's `band_not` instruction that is legalized into the simpler
321
+ ;; forms early on.
322
+
323
+ (decl sse_and_not (Type Xmm XmmMem) Xmm)
324
+ (rule (sse_and_not $F32X4 x y) (x64_andnps x y))
325
+ (rule (sse_and_not $F64X2 x y) (x64_andnpd x y))
326
+ (rule -1 (sse_and_not (multi_lane _bits _lanes) x y) (x64_pandn x y))
327
+
328
+ ;; Note the flipping of operands below as we're match
329
+ ;;
330
+ ;; (band x (bnot y))
331
+ ;;
332
+ ;; while x86 does
333
+ ;;
334
+ ;; pandn(x, y) = and(not(x), y)
335
+ (rule 8 (lower (has_type ty @ (multi_lane _bits _lane) (band x (bnot y))))
336
+ (sse_and_not ty y x))
337
+ (rule 9 (lower (has_type ty @ (multi_lane _bits _lane) (band (bnot y) x)))
338
+ (sse_and_not ty y x))
339
+
340
+ (rule 10 (lower (has_type ty (band x (bnot y))))
341
+ (if (ty_int_ref_scalar_64 ty))
342
+ (if-let $true (use_bmi1))
343
+ ;; the first argument is the one that gets inverted with andn
344
+ (x64_andn ty y x))
345
+ (rule 11 (lower (has_type ty (band (bnot y) x)))
346
+ (if (ty_int_ref_scalar_64 ty))
347
+ (if-let $true (use_bmi1))
348
+ (x64_andn ty y x))
349
+
350
+ ;; Specialization of `blsr` for BMI1
351
+
352
+ (decl pure partial val_minus_one (Value) Value)
353
+ (rule 0 (val_minus_one (isub x (u64_from_iconst 1))) x)
354
+ (rule 0 (val_minus_one (iadd x (i64_from_iconst -1))) x)
355
+ (rule 1 (val_minus_one (iadd (i64_from_iconst -1) x)) x)
356
+
357
+ (rule 12 (lower (has_type (ty_32_or_64 ty) (band x y)))
358
+ (if-let $true (use_bmi1))
359
+ (if-let x (val_minus_one y))
360
+ (x64_blsr ty x))
361
+ (rule 13 (lower (has_type (ty_32_or_64 ty) (band y x)))
362
+ (if-let $true (use_bmi1))
363
+ (if-let x (val_minus_one y))
364
+ (x64_blsr ty x))
365
+
366
+ ;; Specialization of `blsi` for BMI1
367
+
368
+ (rule 14 (lower (has_type (ty_32_or_64 ty) (band (ineg x) x)))
369
+ (if-let $true (use_bmi1))
370
+ (x64_blsi ty x))
371
+ (rule 15 (lower (has_type (ty_32_or_64 ty) (band x (ineg x))))
372
+ (if-let $true (use_bmi1))
373
+ (x64_blsi ty x))
374
+
375
+ ;; Specialization of `bzhi` for BMI2
376
+ ;;
377
+ ;; The `bzhi` instruction clears all bits indexed by the second operand of the
378
+ ;; first operand. This is pattern-matched here with a `band` against a mask
379
+ ;; which is generated to be N bits large. Note that if the index is larger than
380
+ ;; the bit-width of the type then `bzhi` doesn't have the same semantics as
381
+ ;; `ishl`, so an `and` instruction is required to mask the index to match the
382
+ ;; semantics of Cranelift's `ishl`.
383
+
384
+ (rule 16 (lower (has_type (ty_32_or_64 ty) (band x y)))
385
+ (if-let $true (use_bmi2))
386
+ (if-let (ishl (u64_from_iconst 1) index) (val_minus_one y))
387
+ (x64_bzhi ty x (x64_and ty index (RegMemImm.Imm (u32_sub (ty_bits ty) 1)))))
388
+
389
+ ;;;; Rules for `bor` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
390
+
391
+ ;; `{i,b}64` and smaller.
392
+
393
+ ;; Or two registers.
394
+ (rule 0 (lower (has_type ty (bor x y)))
395
+ (if (ty_int_ref_scalar_64 ty))
396
+ (x64_or ty x y))
397
+
398
+ ;; Handle immediates/sinkable loads on the lhs in addition to the automatic
399
+ ;; handling of the rhs above
400
+
401
+ (rule 1 (lower (has_type ty (bor (sinkable_load x) y)))
402
+ (if (ty_int_ref_scalar_64 ty))
403
+ (x64_or ty y x))
404
+
405
+ (rule 2 (lower (has_type ty (bor (simm32_from_value x) y)))
406
+ (if (ty_int_ref_scalar_64 ty))
407
+ (x64_or ty y x))
408
+
409
+ ;; f32 and f64
410
+
411
+ (rule 5 (lower (has_type (ty_scalar_float ty) (bor x y)))
412
+ (sse_or ty x y))
413
+
414
+ ;; SSE.
415
+
416
+ (decl sse_or (Type Xmm XmmMem) Xmm)
417
+ (rule (sse_or $F32X4 x y) (x64_orps x y))
418
+ (rule (sse_or $F64X2 x y) (x64_orpd x y))
419
+ (rule (sse_or $F32 x y) (x64_orps x y))
420
+ (rule (sse_or $F64 x y) (x64_orpd x y))
421
+ (rule -1 (sse_or (multi_lane _bits _lanes) x y) (x64_por x y))
422
+
423
+ (rule 6 (lower (has_type ty @ (multi_lane _bits _lanes)
424
+ (bor x y)))
425
+ (sse_or ty x y))
426
+
427
+ ;; `{i,b}128`.
428
+
429
+ (decl or_i128 (ValueRegs ValueRegs) ValueRegs)
430
+ (rule (or_i128 x y)
431
+ (let ((x_lo Gpr (value_regs_get_gpr x 0))
432
+ (x_hi Gpr (value_regs_get_gpr x 1))
433
+ (y_lo Gpr (value_regs_get_gpr y 0))
434
+ (y_hi Gpr (value_regs_get_gpr y 1)))
435
+ (value_gprs (x64_or $I64 x_lo y_lo)
436
+ (x64_or $I64 x_hi y_hi))))
437
+
438
+ (rule 7 (lower (has_type $I128 (bor x y)))
439
+ (or_i128 x y))
440
+
441
+ ;;;; Rules for `bxor` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
442
+
443
+ ;; `{i,b}64` and smaller.
444
+
445
+ ;; Xor two registers.
446
+ (rule 0 (lower (has_type ty (bxor x y)))
447
+ (if (ty_int_ref_scalar_64 ty))
448
+ (x64_xor ty x y))
449
+
450
+ ;; Handle xor with lhs immediates/sinkable loads in addition to the automatic
451
+ ;; handling of the rhs above.
452
+
453
+ (rule 1 (lower (has_type ty (bxor (sinkable_load x) y)))
454
+ (if (ty_int_ref_scalar_64 ty))
455
+ (x64_xor ty y x))
456
+
457
+ (rule 4 (lower (has_type ty (bxor (simm32_from_value x) y)))
458
+ (if (ty_int_ref_scalar_64 ty))
459
+ (x64_xor ty y x))
460
+
461
+ ;; f32 and f64
462
+
463
+ (rule 5 (lower (has_type (ty_scalar_float ty) (bxor x y)))
464
+ (x64_xor_vector ty x y))
465
+
466
+ ;; SSE.
467
+
468
+ (rule 6 (lower (has_type ty @ (multi_lane _bits _lanes) (bxor x y)))
469
+ (x64_xor_vector ty x y))
470
+
471
+ ;; `{i,b}128`.
472
+
473
+ (rule 7 (lower (has_type $I128 (bxor x y)))
474
+ (let ((x_regs ValueRegs x)
475
+ (x_lo Gpr (value_regs_get_gpr x_regs 0))
476
+ (x_hi Gpr (value_regs_get_gpr x_regs 1))
477
+ (y_regs ValueRegs y)
478
+ (y_lo Gpr (value_regs_get_gpr y_regs 0))
479
+ (y_hi Gpr (value_regs_get_gpr y_regs 1)))
480
+ (value_gprs (x64_xor $I64 x_lo y_lo)
481
+ (x64_xor $I64 x_hi y_hi))))
482
+
483
+ ;; Specialization of `blsmsk` for BMI1
484
+
485
+ (rule 8 (lower (has_type (ty_32_or_64 ty) (bxor x y)))
486
+ (if-let $true (use_bmi1))
487
+ (if-let x (val_minus_one y))
488
+ (x64_blsmsk ty x))
489
+ (rule 9 (lower (has_type (ty_32_or_64 ty) (bxor y x)))
490
+ (if-let $true (use_bmi1))
491
+ (if-let x (val_minus_one y))
492
+ (x64_blsmsk ty x))
493
+
494
+ ;;;; Rules for `ishl` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
495
+
496
+ ;; `i64` and smaller.
497
+
498
+ (rule -1 (lower (has_type (fits_in_64 ty) (ishl src amt)))
499
+ (x64_shl ty src (put_masked_in_imm8_gpr amt ty)))
500
+
501
+ ;; `i128`.
502
+
503
+ (decl shl_i128 (ValueRegs Gpr) ValueRegs)
504
+ (rule (shl_i128 src amt)
505
+ ;; Unpack the registers that make up the 128-bit value being shifted.
506
+ (let ((src_lo Gpr (value_regs_get_gpr src 0))
507
+ (src_hi Gpr (value_regs_get_gpr src 1))
508
+ ;; Do two 64-bit shifts.
509
+ (lo_shifted Gpr (x64_shl $I64 src_lo amt))
510
+ (hi_shifted Gpr (x64_shl $I64 src_hi amt))
511
+ ;; `src_lo >> (64 - amt)` are the bits to carry over from the lo
512
+ ;; into the hi.
513
+ (carry Gpr (x64_shr $I64
514
+ src_lo
515
+ (x64_sub $I64
516
+ (imm $I64 64)
517
+ amt)))
518
+ (zero Gpr (imm $I64 0))
519
+ ;; Nullify the carry if we are shifting in by a multiple of 128.
520
+ (carry_ Gpr (with_flags_reg (x64_test (OperandSize.Size64)
521
+ amt
522
+ (RegMemImm.Imm 127))
523
+ (cmove $I64
524
+ (CC.Z)
525
+ zero
526
+ carry)))
527
+ ;; Add the carry into the high half.
528
+ (hi_shifted_ Gpr (x64_or $I64 carry_ hi_shifted)))
529
+ ;; Combine the two shifted halves. However, if we are shifting by >= 64
530
+ ;; (modulo 128), then the low bits are zero and the high bits are our
531
+ ;; low bits.
532
+ (with_flags (x64_test (OperandSize.Size64) amt (RegMemImm.Imm 64))
533
+ (consumes_flags_concat
534
+ (cmove $I64 (CC.Z) lo_shifted zero)
535
+ (cmove $I64 (CC.Z) hi_shifted_ lo_shifted)))))
536
+
537
+ (rule (lower (has_type $I128 (ishl src amt)))
538
+ ;; NB: Only the low bits of `amt` matter since we logically mask the shift
539
+ ;; amount to the value's bit width.
540
+ (let ((amt_ Gpr (lo_gpr amt)))
541
+ (shl_i128 src amt_)))
542
+
543
+ ;; SSE.
544
+
545
+ ;; Since the x86 instruction set does not have any 8x16 shift instructions (even
546
+ ;; in higher feature sets like AVX), we lower the `ishl.i8x16` to a sequence of
547
+ ;; instructions. The basic idea, whether the amount to shift by is an immediate
548
+ ;; or not, is to use a 16x8 shift and then mask off the incorrect bits to 0s.
549
+ (rule (lower (has_type ty @ $I8X16 (ishl src amt)))
550
+ (let (
551
+ ;; Mask the amount to ensure wrapping behaviour
552
+ (masked_amt RegMemImm (mask_xmm_shift ty amt))
553
+ ;; Shift `src` using 16x8. Unfortunately, a 16x8 shift will only be
554
+ ;; correct for half of the lanes; the others must be fixed up with
555
+ ;; the mask below.
556
+ (unmasked Xmm (x64_psllw src (mov_rmi_to_xmm masked_amt)))
557
+ (mask_addr SyntheticAmode (ishl_i8x16_mask masked_amt))
558
+ (mask Reg (x64_load $I8X16 mask_addr (ExtKind.None))))
559
+ (sse_and $I8X16 unmasked (RegMem.Reg mask))))
560
+
561
+ ;; Get the address of the mask to use when fixing up the lanes that weren't
562
+ ;; correctly generated by the 16x8 shift.
563
+ (decl ishl_i8x16_mask (RegMemImm) SyntheticAmode)
564
+
565
+ ;; When the shift amount is known, we can statically (i.e. at compile time)
566
+ ;; determine the mask to use and only emit that.
567
+ (decl ishl_i8x16_mask_for_const (u32) SyntheticAmode)
568
+ (extern constructor ishl_i8x16_mask_for_const ishl_i8x16_mask_for_const)
569
+ (rule (ishl_i8x16_mask (RegMemImm.Imm amt))
570
+ (ishl_i8x16_mask_for_const amt))
571
+
572
+ ;; Otherwise, we must emit the entire mask table and dynamically (i.e. at run
573
+ ;; time) find the correct mask offset in the table. We use `lea` to find the
574
+ ;; base address of the mask table and then complex addressing to offset to the
575
+ ;; right mask: `base_address + amt << 4`
576
+ (decl ishl_i8x16_mask_table () SyntheticAmode)
577
+ (extern constructor ishl_i8x16_mask_table ishl_i8x16_mask_table)
578
+ (rule (ishl_i8x16_mask (RegMemImm.Reg amt))
579
+ (let ((mask_table SyntheticAmode (ishl_i8x16_mask_table))
580
+ (base_mask_addr Gpr (x64_lea $I64 mask_table))
581
+ (mask_offset Gpr (x64_shl $I64 amt
582
+ (imm8_to_imm8_gpr 4))))
583
+ (Amode.ImmRegRegShift 0
584
+ base_mask_addr
585
+ mask_offset
586
+ 0
587
+ (mem_flags_trusted))))
588
+
589
+ (rule (ishl_i8x16_mask (RegMemImm.Mem amt))
590
+ (ishl_i8x16_mask (RegMemImm.Reg (x64_load $I64 amt (ExtKind.None)))))
591
+
592
+ ;; 16x8, 32x4, and 64x2 shifts can each use a single instruction, once the shift amount is masked.
593
+
594
+ (rule (lower (has_type ty @ $I16X8 (ishl src amt)))
595
+ (x64_psllw src (mov_rmi_to_xmm (mask_xmm_shift ty amt))))
596
+
597
+ (rule (lower (has_type ty @ $I32X4 (ishl src amt)))
598
+ (x64_pslld src (mov_rmi_to_xmm (mask_xmm_shift ty amt))))
599
+
600
+ (rule (lower (has_type ty @ $I64X2 (ishl src amt)))
601
+ (x64_psllq src (mov_rmi_to_xmm (mask_xmm_shift ty amt))))
602
+
603
+ ;;;; Rules for `ushr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
604
+
605
+ ;; `i64` and smaller.
606
+
607
+ (rule -1 (lower (has_type (fits_in_64 ty) (ushr src amt)))
608
+ (let ((src_ Gpr (extend_to_gpr src ty (ExtendKind.Zero))))
609
+ (x64_shr ty src_ (put_masked_in_imm8_gpr amt ty))))
610
+
611
+ ;; `i128`.
612
+
613
+ (decl shr_i128 (ValueRegs Gpr) ValueRegs)
614
+ (rule (shr_i128 src amt)
615
+ ;; Unpack the lo/hi halves of `src`.
616
+ (let ((src_lo Gpr (value_regs_get_gpr src 0))
617
+ (src_hi Gpr (value_regs_get_gpr src 1))
618
+ ;; Do a shift on each half.
619
+ (lo_shifted Gpr (x64_shr $I64 src_lo amt))
620
+ (hi_shifted Gpr (x64_shr $I64 src_hi amt))
621
+ ;; `src_hi << (64 - amt)` are the bits to carry over from the hi
622
+ ;; into the lo.
623
+ (carry Gpr (x64_shl $I64
624
+ src_hi
625
+ (x64_sub $I64
626
+ (imm $I64 64)
627
+ amt)))
628
+ ;; Share the zero value to reduce register pressure
629
+ (zero Gpr (imm $I64 0))
630
+
631
+ ;; Nullify the carry if we are shifting by a multiple of 128.
632
+ (carry_ Gpr (with_flags_reg (x64_test (OperandSize.Size64) amt (RegMemImm.Imm 127))
633
+ (cmove $I64 (CC.Z) zero carry)))
634
+ ;; Add the carry bits into the lo.
635
+ (lo_shifted_ Gpr (x64_or $I64 carry_ lo_shifted)))
636
+ ;; Combine the two shifted halves. However, if we are shifting by >= 64
637
+ ;; (modulo 128), then the hi bits are zero and the lo bits are what
638
+ ;; would otherwise be our hi bits.
639
+ (with_flags (x64_test (OperandSize.Size64) amt (RegMemImm.Imm 64))
640
+ (consumes_flags_concat
641
+ (cmove $I64 (CC.Z) lo_shifted_ hi_shifted)
642
+ (cmove $I64 (CC.Z) hi_shifted zero)))))
643
+
644
+ (rule (lower (has_type $I128 (ushr src amt)))
645
+ ;; NB: Only the low bits of `amt` matter since we logically mask the shift
646
+ ;; amount to the value's bit width.
647
+ (let ((amt_ Gpr (lo_gpr amt)))
648
+ (shr_i128 src amt_)))
649
+
650
+ ;; SSE.
651
+
652
+ ;; There are no 8x16 shifts in x64. Do the same 16x8-shift-and-mask thing we do
653
+ ;; with 8x16 `ishl`.
654
+ (rule (lower (has_type ty @ $I8X16 (ushr src amt)))
655
+ (let (
656
+ ;; Mask the amount to ensure wrapping behaviour
657
+ (masked_amt RegMemImm (mask_xmm_shift ty amt))
658
+ ;; Shift `src` using 16x8. Unfortunately, a 16x8 shift will only be
659
+ ;; correct for half of the lanes; the others must be fixed up with
660
+ ;; the mask below.
661
+ (unmasked Xmm (x64_psrlw src (mov_rmi_to_xmm masked_amt))))
662
+ (sse_and $I8X16
663
+ unmasked
664
+ (ushr_i8x16_mask masked_amt))))
665
+
666
+ ;; Get the address of the mask to use when fixing up the lanes that weren't
667
+ ;; correctly generated by the 16x8 shift.
668
+ (decl ushr_i8x16_mask (RegMemImm) SyntheticAmode)
669
+
670
+ ;; When the shift amount is known, we can statically (i.e. at compile time)
671
+ ;; determine the mask to use and only emit that.
672
+ (decl ushr_i8x16_mask_for_const (u32) SyntheticAmode)
673
+ (extern constructor ushr_i8x16_mask_for_const ushr_i8x16_mask_for_const)
674
+ (rule (ushr_i8x16_mask (RegMemImm.Imm amt))
675
+ (ushr_i8x16_mask_for_const amt))
676
+
677
+ ;; Otherwise, we must emit the entire mask table and dynamically (i.e. at run
678
+ ;; time) find the correct mask offset in the table. We use `lea` to find the
679
+ ;; base address of the mask table and then complex addressing to offset to the
680
+ ;; right mask: `base_address + amt << 4`
681
+ (decl ushr_i8x16_mask_table () SyntheticAmode)
682
+ (extern constructor ushr_i8x16_mask_table ushr_i8x16_mask_table)
683
+ (rule (ushr_i8x16_mask (RegMemImm.Reg amt))
684
+ (let ((mask_table SyntheticAmode (ushr_i8x16_mask_table))
685
+ (base_mask_addr Gpr (x64_lea $I64 mask_table))
686
+ (mask_offset Gpr (x64_shl $I64
687
+ amt
688
+ (imm8_to_imm8_gpr 4))))
689
+ (Amode.ImmRegRegShift 0
690
+ base_mask_addr
691
+ mask_offset
692
+ 0
693
+ (mem_flags_trusted))))
694
+
695
+ (rule (ushr_i8x16_mask (RegMemImm.Mem amt))
696
+ (ushr_i8x16_mask (RegMemImm.Reg (x64_load $I64 amt (ExtKind.None)))))
697
+
698
+ ;; 16x8, 32x4, and 64x2 shifts can each use a single instruction, once the shift amount is masked.
699
+
700
+ (rule (lower (has_type ty @ $I16X8 (ushr src amt)))
701
+ (x64_psrlw src (mov_rmi_to_xmm (mask_xmm_shift ty amt))))
702
+
703
+ (rule (lower (has_type ty @ $I32X4 (ushr src amt)))
704
+ (x64_psrld src (mov_rmi_to_xmm (mask_xmm_shift ty amt))))
705
+
706
+ (rule (lower (has_type ty @ $I64X2 (ushr src amt)))
707
+ (x64_psrlq src (mov_rmi_to_xmm (mask_xmm_shift ty amt))))
708
+
709
+ (decl mask_xmm_shift (Type Value) RegMemImm)
710
+ (rule (mask_xmm_shift ty amt)
711
+ (gpr_to_reg (x64_and $I64 amt (RegMemImm.Imm (shift_mask ty)))))
712
+ (rule 1 (mask_xmm_shift ty (iconst n))
713
+ (RegMemImm.Imm (shift_amount_masked ty n)))
714
+
715
+ ;;;; Rules for `sshr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
716
+
717
+ ;; `i64` and smaller.
718
+
719
+ (rule -1 (lower (has_type (fits_in_64 ty) (sshr src amt)))
720
+ (let ((src_ Gpr (extend_to_gpr src ty (ExtendKind.Sign))))
721
+ (x64_sar ty src_ (put_masked_in_imm8_gpr amt ty))))
722
+
723
+ ;; `i128`.
724
+
725
+ (decl sar_i128 (ValueRegs Gpr) ValueRegs)
726
+ (rule (sar_i128 src amt)
727
+ ;; Unpack the low/high halves of `src`.
728
+ (let ((src_lo Gpr (value_regs_get_gpr src 0))
729
+ (src_hi Gpr (value_regs_get_gpr src 1))
730
+ ;; Do a shift of each half. NB: the low half uses an unsigned shift
731
+ ;; because its MSB is not a sign bit.
732
+ (lo_shifted Gpr (x64_shr $I64 src_lo amt))
733
+ (hi_shifted Gpr (x64_sar $I64 src_hi amt))
734
+ ;; `src_hi << (64 - amt)` are the bits to carry over from the low
735
+ ;; half to the high half.
736
+ (carry Gpr (x64_shl $I64
737
+ src_hi
738
+ (x64_sub $I64
739
+ (imm $I64 64)
740
+ amt)))
741
+ ;; Nullify the carry if we are shifting by a multiple of 128.
742
+ (carry_ Gpr (with_flags_reg (x64_test (OperandSize.Size64) amt (RegMemImm.Imm 127))
743
+ (cmove $I64 (CC.Z) (imm $I64 0) carry)))
744
+ ;; Add the carry into the low half.
745
+ (lo_shifted_ Gpr (x64_or $I64 lo_shifted carry_))
746
+ ;; Get all sign bits.
747
+ (sign_bits Gpr (x64_sar $I64 src_hi (imm8_to_imm8_gpr 63))))
748
+ ;; Combine the two shifted halves. However, if we are shifting by >= 64
749
+ ;; (modulo 128), then the hi bits are all sign bits and the lo bits are
750
+ ;; what would otherwise be our hi bits.
751
+ (with_flags (x64_test (OperandSize.Size64) amt (RegMemImm.Imm 64))
752
+ (consumes_flags_concat
753
+ (cmove $I64 (CC.Z) lo_shifted_ hi_shifted)
754
+ (cmove $I64 (CC.Z) hi_shifted sign_bits)))))
755
+
756
+ (rule (lower (has_type $I128 (sshr src amt)))
757
+ ;; NB: Only the low bits of `amt` matter since we logically mask the shift
758
+ ;; amount to the value's bit width.
759
+ (let ((amt_ Gpr (lo_gpr amt)))
760
+ (sar_i128 src amt_)))
761
+
762
+ ;; SSE.
763
+
764
+ ;; Since the x86 instruction set does not have an 8x16 shift instruction and the
765
+ ;; approach used for `ishl` and `ushr` cannot be easily used (the masks do not
766
+ ;; preserve the sign), we use a different approach here: separate the low and
767
+ ;; high lanes, shift them separately, and merge them into the final result.
768
+ ;;
769
+ ;; Visually, this looks like the following, where `src.i8x16 = [s0, s1, ...,
770
+ ;; s15]:
771
+ ;;
772
+ ;; lo.i16x8 = [(s0, s0), (s1, s1), ..., (s7, s7)]
773
+ ;; shifted_lo.i16x8 = shift each lane of `low`
774
+ ;; hi.i16x8 = [(s8, s8), (s9, s9), ..., (s15, s15)]
775
+ ;; shifted_hi.i16x8 = shift each lane of `high`
776
+ ;; result = [s0'', s1'', ..., s15'']
777
+ (rule (lower (has_type ty @ $I8X16 (sshr src amt @ (value_type amt_ty))))
778
+ (let ((src_ Xmm (put_in_xmm src))
779
+ ;; Mask the amount to ensure wrapping behaviour
780
+ (masked_amt RegMemImm (mask_xmm_shift ty amt))
781
+ ;; In order for `packsswb` later to only use the high byte of each
782
+ ;; 16x8 lane, we shift right an extra 8 bits, relying on `psraw` to
783
+ ;; fill in the upper bits appropriately.
784
+ (lo Xmm (x64_punpcklbw src_ src_))
785
+ (hi Xmm (x64_punpckhbw src_ src_))
786
+ (amt_ XmmMemImm (sshr_i8x16_bigger_shift amt_ty masked_amt))
787
+ (shifted_lo Xmm (x64_psraw lo amt_))
788
+ (shifted_hi Xmm (x64_psraw hi amt_)))
789
+ (x64_packsswb shifted_lo shifted_hi)))
790
+
791
+ (decl sshr_i8x16_bigger_shift (Type RegMemImm) XmmMemImm)
792
+ (rule (sshr_i8x16_bigger_shift _ty (RegMemImm.Imm i))
793
+ (xmm_mem_imm_new (RegMemImm.Imm (u32_add i 8))))
794
+ (rule (sshr_i8x16_bigger_shift ty (RegMemImm.Reg r))
795
+ (mov_rmi_to_xmm (RegMemImm.Reg (x64_add ty
796
+ r
797
+ (RegMemImm.Imm 8)))))
798
+ (rule (sshr_i8x16_bigger_shift ty rmi @ (RegMemImm.Mem _m))
799
+ (mov_rmi_to_xmm (RegMemImm.Reg (x64_add ty
800
+ (imm ty 8)
801
+ rmi))))
802
+
803
+ ;; `sshr.{i16x8,i32x4}` can be a simple `psra{w,d}`, we just have to make sure
804
+ ;; that if the shift amount is in a register, it is in an XMM register.
805
+
806
+ (rule (lower (has_type ty @ $I16X8 (sshr src amt)))
807
+ (x64_psraw src (mov_rmi_to_xmm (mask_xmm_shift ty amt))))
808
+
809
+ (rule (lower (has_type ty @ $I32X4 (sshr src amt)))
810
+ (x64_psrad src (mov_rmi_to_xmm (mask_xmm_shift ty amt))))
811
+
812
+ ;; The `sshr.i64x2` CLIF instruction has no single x86 instruction in the older
813
+ ;; feature sets. To remedy this, a small dance is done with an unsigned right
814
+ ;; shift plus some extra ops.
815
+ (rule 3 (lower (has_type ty @ $I64X2 (sshr src (iconst n))))
816
+ (if-let $true (use_avx512vl))
817
+ (if-let $true (use_avx512f))
818
+ (x64_vpsraq_imm src (shift_amount_masked ty n)))
819
+
820
+ (rule 2 (lower (has_type ty @ $I64X2 (sshr src amt)))
821
+ (if-let $true (use_avx512vl))
822
+ (if-let $true (use_avx512f))
823
+ (let ((masked Gpr (x64_and $I64 amt (RegMemImm.Imm (shift_mask ty)))))
824
+ (x64_vpsraq src (x64_movd_to_xmm masked))))
825
+
826
+ (rule 1 (lower (has_type $I64X2 (sshr src (iconst (u64_from_imm64 (u64_as_u32 amt))))))
827
+ (lower_i64x2_sshr_imm src (u32_and amt 63)))
828
+
829
+ (rule (lower (has_type $I64X2 (sshr src amt)))
830
+ (lower_i64x2_sshr_gpr src (x64_and $I64 amt (RegMemImm.Imm 63))))
831
+
832
+ (decl lower_i64x2_sshr_imm (Xmm u32) Xmm)
833
+
834
+ ;; If the shift amount is less than 32 then do an sshr with 32-bit lanes to
835
+ ;; produce the upper halves of each result, followed by a ushr of 64-bit lanes
836
+ ;; to produce the lower halves of each result. Interleave results at the end.
837
+ (rule 2 (lower_i64x2_sshr_imm vec imm)
838
+ (if-let $true (u64_lt imm 32))
839
+ (let (
840
+ (high32 Xmm (x64_psrad vec (xmi_imm imm)))
841
+ (high32 Xmm (x64_pshufd high32 0b11_10_11_01))
842
+ (low32 Xmm (x64_psrlq vec (xmi_imm imm)))
843
+ (low32 Xmm (x64_pshufd low32 0b11_10_10_00))
844
+ )
845
+ (x64_punpckldq low32 high32)))
846
+
847
+ ;; If the shift amount is 32 then the `psrlq` from the above rule can be avoided
848
+ (rule 1 (lower_i64x2_sshr_imm vec 32)
849
+ (let (
850
+ (low32 Xmm (x64_pshufd vec 0b11_10_11_01))
851
+ (high32 Xmm (x64_psrad vec (xmi_imm 31)))
852
+ (high32 Xmm (x64_pshufd high32 0b11_10_11_01))
853
+ )
854
+ (x64_punpckldq low32 high32)))
855
+
856
+ ;; Shifts >= 32 use one `psrad` to generate the upper bits and second `psrad` to
857
+ ;; generate the lower bits. Everything is then woven back together with
858
+ ;; shuffles.
859
+ (rule (lower_i64x2_sshr_imm vec imm)
860
+ (if-let $true (u64_lt 32 imm))
861
+ (let (
862
+ (high32 Xmm (x64_psrad vec (xmi_imm 31)))
863
+ (high32 Xmm (x64_pshufd high32 0b11_10_11_01))
864
+ (low32 Xmm (x64_psrad vec (xmi_imm (u32_sub imm 32))))
865
+ (low32 Xmm (x64_pshufd low32 0b11_10_11_01))
866
+ )
867
+ (x64_punpckldq low32 high32)))
868
+
869
+ ;; A variable shift amount is slightly more complicated than the immediate
870
+ ;; shift amounts from above. The `Gpr` argument is guaranteed to be <= 63 by
871
+ ;; earlier masking. A `ushr` operation is used with some xor/sub math to
872
+ ;; generate the sign bits.
873
+ (decl lower_i64x2_sshr_gpr (Xmm Gpr) Xmm)
874
+ (rule (lower_i64x2_sshr_gpr vec val)
875
+ (let (
876
+ (val Xmm (x64_movq_to_xmm val))
877
+ (mask Xmm (flip_high_bit_mask $I64X2))
878
+ (sign_bit_loc Xmm (x64_psrlq mask val))
879
+ (ushr Xmm (x64_psrlq vec val))
880
+ (ushr_sign_bit_flip Xmm (x64_pxor sign_bit_loc ushr))
881
+ )
882
+ (x64_psubq ushr_sign_bit_flip sign_bit_loc)))
883
+
884
+ ;;;; Rules for `rotl` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
885
+
886
+ ;; `i64` and smaller: we can rely on x86's rotate-amount masking since
887
+ ;; we operate on the whole register. For const's we mask the constant.
888
+
889
+ (rule -1 (lower (has_type (fits_in_64 ty) (rotl src amt)))
890
+ (x64_rotl ty src (put_masked_in_imm8_gpr amt ty)))
891
+
892
+
893
+ ;; `i128`.
894
+
895
+ (rule (lower (has_type $I128 (rotl src amt)))
896
+ (let ((src_ ValueRegs src)
897
+ ;; NB: Only the low bits of `amt` matter since we logically mask the
898
+ ;; rotation amount to the value's bit width.
899
+ (amt_ Gpr (lo_gpr amt)))
900
+ (or_i128 (shl_i128 src_ amt_)
901
+ (shr_i128 src_ (x64_sub $I64
902
+ (imm $I64 128)
903
+ amt_)))))
904
+
905
+ ;;;; Rules for `rotr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
906
+
907
+ ;; `i64` and smaller: we can rely on x86's rotate-amount masking since
908
+ ;; we operate on the whole register. For const's we mask the constant.
909
+
910
+ (rule -1 (lower (has_type (fits_in_64 ty) (rotr src amt)))
911
+ (x64_rotr ty src (put_masked_in_imm8_gpr amt ty)))
912
+
913
+
914
+ ;; `i128`.
915
+
916
+ (rule (lower (has_type $I128 (rotr src amt)))
917
+ (let ((src_ ValueRegs src)
918
+ ;; NB: Only the low bits of `amt` matter since we logically mask the
919
+ ;; rotation amount to the value's bit width.
920
+ (amt_ Gpr (lo_gpr amt)))
921
+ (or_i128 (shr_i128 src_ amt_)
922
+ (shl_i128 src_ (x64_sub $I64
923
+ (imm $I64 128)
924
+ amt_)))))
925
+
926
+ ;;;; Rules for `ineg` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
927
+
928
+ ;; `i64` and smaller.
929
+
930
+ (rule -1 (lower (has_type (fits_in_64 ty) (ineg x)))
931
+ (x64_neg ty x))
932
+
933
+ (rule -2 (lower (has_type $I128 (ineg x)))
934
+ ;; Get the high/low registers for `x`.
935
+ (let ((regs ValueRegs x)
936
+ (lo Gpr (value_regs_get_gpr regs 0))
937
+ (hi Gpr (value_regs_get_gpr regs 1)))
938
+ ;; Do a neg followed by an sub-with-borrow.
939
+ (with_flags (x64_neg_paired $I64 lo)
940
+ (x64_sbb_paired $I64 (imm $I64 0) hi))))
941
+
942
+ ;; SSE.
943
+
944
+ (rule (lower (has_type $I8X16 (ineg x)))
945
+ (x64_psubb (imm $I8X16 0) x))
946
+
947
+ (rule (lower (has_type $I16X8 (ineg x)))
948
+ (x64_psubw (imm $I16X8 0) x))
949
+
950
+ (rule (lower (has_type $I32X4 (ineg x)))
951
+ (x64_psubd (imm $I32X4 0) x))
952
+
953
+ (rule (lower (has_type $I64X2 (ineg x)))
954
+ (x64_psubq (imm $I64X2 0) x))
955
+
956
+ ;;;; Rules for `avg_round` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
957
+
958
+ (rule (lower (has_type (multi_lane 8 16)
959
+ (avg_round x y)))
960
+ (x64_pavgb x y))
961
+
962
+ (rule (lower (has_type (multi_lane 16 8)
963
+ (avg_round x y)))
964
+ (x64_pavgw x y))
965
+
966
+ ;;;; Rules for `imul` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
967
+
968
+ ;; `i64` and smaller.
969
+
970
+ ;; 8-bit base case, needs a special instruction encoding and additionally
971
+ ;; move sinkable loads to the right.
972
+ (rule -7 (lower (has_type $I8 (imul x y))) (x64_mul8 $false x y))
973
+ (rule -6 (lower (has_type $I8 (imul (sinkable_load x) y))) (x64_mul8 $false y x))
974
+
975
+ ;; 16-to-64-bit base cases, same as above by moving sinkable loads to the right.
976
+ (rule -5 (lower (has_type (ty_int_ref_16_to_64 ty) (imul x y)))
977
+ (x64_imul ty x y))
978
+ (rule -4 (lower (has_type (ty_int_ref_16_to_64 ty) (imul (sinkable_load x) y)))
979
+ (x64_imul ty y x))
980
+
981
+ ;; lift out constants to use 3-operand form
982
+ (rule -3 (lower (has_type (ty_int_ref_16_to_64 ty) (imul x (iconst (simm32 y)))))
983
+ (x64_imul_imm ty x y))
984
+ (rule -2 (lower (has_type (ty_int_ref_16_to_64 ty) (imul (iconst (simm32 x)) y)))
985
+ (x64_imul_imm ty y x))
986
+
987
+ ;; `i128`.
988
+
989
+ ;; mul:
990
+ ;; dst_lo = lhs_lo * rhs_lo
991
+ ;; dst_hi = umulhi(lhs_lo, rhs_lo) +
992
+ ;; lhs_lo * rhs_hi +
993
+ ;; lhs_hi * rhs_lo
994
+ ;;
995
+ ;; so we emit:
996
+ ;; lo_hi = mul x_lo, y_hi
997
+ ;; hi_lo = mul x_hi, y_lo
998
+ ;; hilo_hilo = add lo_hi, hi_lo
999
+ ;; dst_lo:hi_lolo = mulhi_u x_lo, y_lo
1000
+ ;; dst_hi = add hilo_hilo, hi_lolo
1001
+ ;; return (dst_lo, dst_hi)
1002
+ (rule 2 (lower (has_type $I128 (imul x y)))
1003
+ ;; Put `x` into registers and unpack its hi/lo halves.
1004
+ (let ((x_regs ValueRegs x)
1005
+ (x_lo Gpr (value_regs_get_gpr x_regs 0))
1006
+ (x_hi Gpr (value_regs_get_gpr x_regs 1))
1007
+ ;; Put `y` into registers and unpack its hi/lo halves.
1008
+ (y_regs ValueRegs y)
1009
+ (y_lo Gpr (value_regs_get_gpr y_regs 0))
1010
+ (y_hi Gpr (value_regs_get_gpr y_regs 1))
1011
+ ;; lo_hi = mul x_lo, y_hi
1012
+ (lo_hi Gpr (x64_imul $I64 x_lo y_hi))
1013
+ ;; hi_lo = mul x_hi, y_lo
1014
+ (hi_lo Gpr (x64_imul $I64 x_hi y_lo))
1015
+ ;; hilo_hilo = add lo_hi, hi_lo
1016
+ (hilo_hilo Gpr (x64_add $I64 lo_hi hi_lo))
1017
+ ;; dst_lo:hi_lolo = x64_mul x_lo, y_lo
1018
+ (mul_regs ValueRegs (x64_mul $I64 $false x_lo y_lo))
1019
+ (dst_lo Gpr (value_regs_get_gpr mul_regs 0))
1020
+ (hi_lolo Gpr (value_regs_get_gpr mul_regs 1))
1021
+ ;; dst_hi = add hilo_hilo, hi_lolo
1022
+ (dst_hi Gpr (x64_add $I64 hilo_hilo hi_lolo)))
1023
+ (value_gprs dst_lo dst_hi)))
1024
+
1025
+ ;; SSE.
1026
+
1027
+ ;; (No i8x16 multiply.)
1028
+
1029
+ (rule (lower (has_type (multi_lane 16 8) (imul x y)))
1030
+ (x64_pmullw x y))
1031
+
1032
+ (rule (lower (has_type (multi_lane 32 4) (imul x y)))
1033
+ (if-let $true (use_sse41))
1034
+ (x64_pmulld x y))
1035
+
1036
+ ;; Without `pmulld` the `pmuludq` instruction is used instead which performs
1037
+ ;; 32-bit multiplication storing the 64-bit result. The 64-bit result is
1038
+ ;; truncated to 32-bits and everything else is woven into place.
1039
+ (rule -1 (lower (has_type (multi_lane 32 4) (imul x y)))
1040
+ (let (
1041
+ (x Xmm x)
1042
+ (y Xmm y)
1043
+ (x_hi Xmm (x64_pshufd x 0b00_11_00_01))
1044
+ (y_hi Xmm (x64_pshufd y 0b00_11_00_01))
1045
+ (mul_lo Xmm (x64_pshufd (x64_pmuludq x y) 0b00_00_10_00))
1046
+ (mul_hi Xmm (x64_pshufd (x64_pmuludq x_hi y_hi) 0b00_00_10_00))
1047
+ )
1048
+ (x64_punpckldq mul_lo mul_hi)))
1049
+
1050
+ ;; With AVX-512 we can implement `i64x2` multiplication with a single
1051
+ ;; instruction.
1052
+ (rule 3 (lower (has_type (multi_lane 64 2) (imul x y)))
1053
+ (if-let $true (use_avx512vl))
1054
+ (if-let $true (use_avx512dq))
1055
+ (x64_vpmullq x y))
1056
+
1057
+ ;; Otherwise, for i64x2 multiplication we describe a lane A as being composed of
1058
+ ;; a 32-bit upper half "Ah" and a 32-bit lower half "Al". The 32-bit long hand
1059
+ ;; multiplication can then be written as:
1060
+ ;;
1061
+ ;; Ah Al
1062
+ ;; * Bh Bl
1063
+ ;; -----
1064
+ ;; Al * Bl
1065
+ ;; + (Ah * Bl) << 32
1066
+ ;; + (Al * Bh) << 32
1067
+ ;;
1068
+ ;; So for each lane we will compute:
1069
+ ;;
1070
+ ;; A * B = (Al * Bl) + ((Ah * Bl) + (Al * Bh)) << 32
1071
+ ;;
1072
+ ;; Note, the algorithm will use `pmuludq` which operates directly on the lower
1073
+ ;; 32-bit (`Al` or `Bl`) of a lane and writes the result to the full 64-bits of
1074
+ ;; the lane of the destination. For this reason we don't need shifts to isolate
1075
+ ;; the lower 32-bits, however, we will need to use shifts to isolate the high
1076
+ ;; 32-bits when doing calculations, i.e., `Ah == A >> 32`.
1077
+ (rule (lower (has_type (multi_lane 64 2)
1078
+ (imul a b)))
1079
+ (let ((a0 Xmm a)
1080
+ (b0 Xmm b)
1081
+ ;; a_hi = A >> 32
1082
+ (a_hi Xmm (x64_psrlq a0 (xmi_imm 32)))
1083
+ ;; ah_bl = Ah * Bl
1084
+ (ah_bl Xmm (x64_pmuludq a_hi b0))
1085
+ ;; b_hi = B >> 32
1086
+ (b_hi Xmm (x64_psrlq b0 (xmi_imm 32)))
1087
+ ;; al_bh = Al * Bh
1088
+ (al_bh Xmm (x64_pmuludq a0 b_hi))
1089
+ ;; aa_bb = ah_bl + al_bh
1090
+ (aa_bb Xmm (x64_paddq ah_bl al_bh))
1091
+ ;; aa_bb_shifted = aa_bb << 32
1092
+ (aa_bb_shifted Xmm (x64_psllq aa_bb (xmi_imm 32)))
1093
+ ;; al_bl = Al * Bl
1094
+ (al_bl Xmm (x64_pmuludq a0 b0)))
1095
+ ;; al_bl + aa_bb_shifted
1096
+ (x64_paddq al_bl aa_bb_shifted)))
1097
+
1098
+ ;; Special case for `i32x4.extmul_high_i16x8_s`.
1099
+ (rule 1 (lower (has_type (multi_lane 32 4)
1100
+ (imul (swiden_high (and (value_type (multi_lane 16 8))
1101
+ x))
1102
+ (swiden_high (and (value_type (multi_lane 16 8))
1103
+ y)))))
1104
+ (let ((x2 Xmm x)
1105
+ (y2 Xmm y)
1106
+ (lo Xmm (x64_pmullw x2 y2))
1107
+ (hi Xmm (x64_pmulhw x2 y2)))
1108
+ (x64_punpckhwd lo hi)))
1109
+
1110
+ ;; Special case for `i64x2.extmul_high_i32x4_s`.
1111
+ (rule 1 (lower (has_type (multi_lane 64 2)
1112
+ (imul (swiden_high (and (value_type (multi_lane 32 4))
1113
+ x))
1114
+ (swiden_high (and (value_type (multi_lane 32 4))
1115
+ y)))))
1116
+ (if-let $true (use_sse41))
1117
+ (let ((x2 Xmm (x64_pshufd x 0xFA))
1118
+ (y2 Xmm (x64_pshufd y 0xFA)))
1119
+ (x64_pmuldq x2 y2)))
1120
+
1121
+ ;; Special case for `i32x4.extmul_low_i16x8_s`.
1122
+ (rule 1 (lower (has_type (multi_lane 32 4)
1123
+ (imul (swiden_low (and (value_type (multi_lane 16 8))
1124
+ x))
1125
+ (swiden_low (and (value_type (multi_lane 16 8))
1126
+ y)))))
1127
+ (let ((x2 Xmm x)
1128
+ (y2 Xmm y)
1129
+ (lo Xmm (x64_pmullw x2 y2))
1130
+ (hi Xmm (x64_pmulhw x2 y2)))
1131
+ (x64_punpcklwd lo hi)))
1132
+
1133
+ ;; Special case for `i64x2.extmul_low_i32x4_s`.
1134
+ (rule 1 (lower (has_type (multi_lane 64 2)
1135
+ (imul (swiden_low (and (value_type (multi_lane 32 4))
1136
+ x))
1137
+ (swiden_low (and (value_type (multi_lane 32 4))
1138
+ y)))))
1139
+ (if-let $true (use_sse41))
1140
+ (let ((x2 Xmm (x64_pshufd x 0x50))
1141
+ (y2 Xmm (x64_pshufd y 0x50)))
1142
+ (x64_pmuldq x2 y2)))
1143
+
1144
+ ;; Special case for `i32x4.extmul_high_i16x8_u`.
1145
+ (rule 1 (lower (has_type (multi_lane 32 4)
1146
+ (imul (uwiden_high (and (value_type (multi_lane 16 8))
1147
+ x))
1148
+ (uwiden_high (and (value_type (multi_lane 16 8))
1149
+ y)))))
1150
+ (let ((x2 Xmm x)
1151
+ (y2 Xmm y)
1152
+ (lo Xmm (x64_pmullw x2 y2))
1153
+ (hi Xmm (x64_pmulhuw x2 y2)))
1154
+ (x64_punpckhwd lo hi)))
1155
+
1156
+ ;; Special case for `i64x2.extmul_high_i32x4_u`.
1157
+ (rule 1 (lower (has_type (multi_lane 64 2)
1158
+ (imul (uwiden_high (and (value_type (multi_lane 32 4))
1159
+ x))
1160
+ (uwiden_high (and (value_type (multi_lane 32 4))
1161
+ y)))))
1162
+ (let ((x2 Xmm (x64_pshufd x 0xFA))
1163
+ (y2 Xmm (x64_pshufd y 0xFA)))
1164
+ (x64_pmuludq x2 y2)))
1165
+
1166
+ ;; Special case for `i32x4.extmul_low_i16x8_u`.
1167
+ (rule 1 (lower (has_type (multi_lane 32 4)
1168
+ (imul (uwiden_low (and (value_type (multi_lane 16 8))
1169
+ x))
1170
+ (uwiden_low (and (value_type (multi_lane 16 8))
1171
+ y)))))
1172
+ (let ((x2 Xmm x)
1173
+ (y2 Xmm y)
1174
+ (lo Xmm (x64_pmullw x2 y2))
1175
+ (hi Xmm (x64_pmulhuw x2 y2)))
1176
+ (x64_punpcklwd lo hi)))
1177
+
1178
+ ;; Special case for `i64x2.extmul_low_i32x4_u`.
1179
+ (rule 1 (lower (has_type (multi_lane 64 2)
1180
+ (imul (uwiden_low (and (value_type (multi_lane 32 4))
1181
+ x))
1182
+ (uwiden_low (and (value_type (multi_lane 32 4))
1183
+ y)))))
1184
+ (let ((x2 Xmm (x64_pshufd x 0x50))
1185
+ (y2 Xmm (x64_pshufd y 0x50)))
1186
+ (x64_pmuludq x2 y2)))
1187
+
1188
+ ;;;; Rules for `iabs` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1189
+
1190
+ (rule 1 (lower (has_type $I8X16 (iabs x)))
1191
+ (if-let $true (use_ssse3))
1192
+ (x64_pabsb x))
1193
+
1194
+ ;; Note the use of `pminub` with signed inputs will produce the positive signed
1195
+ ;; result which is what is desired here. The `pmaxub` isn't available until
1196
+ ;; SSE4.1 in which case the single-instruction above lowering would apply.
1197
+ (rule (lower (has_type $I8X16 (iabs x)))
1198
+ (let (
1199
+ (x Xmm x)
1200
+ (negated Xmm (x64_psubb (xmm_zero $I8X16) x))
1201
+ )
1202
+ (x64_pminub x negated)))
1203
+
1204
+ (rule 1 (lower (has_type $I16X8 (iabs x)))
1205
+ (if-let $true (use_ssse3))
1206
+ (x64_pabsw x))
1207
+
1208
+ (rule (lower (has_type $I16X8 (iabs x)))
1209
+ (let (
1210
+ (x Xmm x)
1211
+ (negated Xmm (x64_psubw (xmm_zero $I16X8) x))
1212
+ )
1213
+ (x64_pmaxsw x negated)))
1214
+
1215
+ (rule 1 (lower (has_type $I32X4 (iabs x)))
1216
+ (if-let $true (use_ssse3))
1217
+ (x64_pabsd x))
1218
+
1219
+ ;; Generate a `negative_mask` which is either numerically -1 or 0 depending on
1220
+ ;; if the lane is negative. If the lane is positive then the xor operation
1221
+ ;; won't change the lane but otherwise it'll bit-flip everything. By then
1222
+ ;; subtracting the mask this subtracts 0 for positive lanes (does nothing) or
1223
+ ;; ends up adding one for negative lanes. This means that for a negative lane
1224
+ ;; `x` the result is `!x + 1` which is the result of negating it.
1225
+ (rule (lower (has_type $I32X4 (iabs x)))
1226
+ (let (
1227
+ (x Xmm x)
1228
+ (negative_mask Xmm (x64_psrad x (xmi_imm 31)))
1229
+ (flipped_if_negative Xmm (x64_pxor x negative_mask))
1230
+ )
1231
+ (x64_psubd flipped_if_negative negative_mask)))
1232
+
1233
+ ;; When AVX512 is available, we can use a single `vpabsq` instruction.
1234
+ (rule 2 (lower (has_type $I64X2 (iabs x)))
1235
+ (if-let $true (use_avx512vl))
1236
+ (if-let $true (use_avx512f))
1237
+ (x64_vpabsq x))
1238
+
1239
+ ;; Otherwise, we use a separate register, `neg`, to contain the results of `0 -
1240
+ ;; x` and then blend in those results with `blendvpd` if the MSB of `neg` was
1241
+ ;; set to 1 (i.e. if `neg` was negative or, conversely, if `x` was originally
1242
+ ;; positive).
1243
+ (rule 1 (lower (has_type $I64X2 (iabs x)))
1244
+ (if-let $true (use_sse41))
1245
+ (let ((rx Xmm x)
1246
+ (neg Xmm (x64_psubq (imm $I64X2 0) rx)))
1247
+ (x64_blendvpd neg rx neg)))
1248
+
1249
+ ;; and if `blendvpd` isn't available then perform a shift/shuffle to generate a
1250
+ ;; mask of which lanes are negative, followed by flipping bits/sub to make both
1251
+ ;; positive.
1252
+ (rule (lower (has_type $I64X2 (iabs x)))
1253
+ (let ((x Xmm x)
1254
+ (signs Xmm (x64_psrad x (RegMemImm.Imm 31)))
1255
+ (signs Xmm (x64_pshufd signs 0b11_11_01_01))
1256
+ (xor_if_negative Xmm (x64_pxor x signs)))
1257
+ (x64_psubq xor_if_negative signs)))
1258
+
1259
+ ;; `i64` and smaller.
1260
+
1261
+ (rule -1 (lower (has_type (fits_in_64 ty) (iabs x)))
1262
+ (let ((src Gpr x)
1263
+ (neg ProducesFlags (x64_neg_paired ty src))
1264
+ ;; Manually extract the result from the neg, then ignore
1265
+ ;; it below, since we need to pass it into the cmove
1266
+ ;; before we pass the cmove to with_flags_reg.
1267
+ (neg_result Gpr (produces_flags_get_reg neg))
1268
+ ;; When the neg instruction sets the sign flag,
1269
+ ;; takes the original (non-negative) value.
1270
+ (cmove ConsumesFlags (cmove ty (CC.S) src neg_result)))
1271
+ (with_flags_reg (produces_flags_ignore neg) cmove)))
1272
+
1273
+ ;; `i128`. Negate the low bits, `adc` to the higher bits, then negate high bits.
1274
+ (rule (lower (has_type $I128 (iabs x)))
1275
+ ;; Get the high/low registers for `x`.
1276
+ (let ((x_regs ValueRegs x)
1277
+ (x_lo Gpr (value_regs_get_gpr x_regs 0))
1278
+ (x_hi Gpr (value_regs_get_gpr x_regs 1))
1279
+ ; negate low bits, then add 0 with carry to high bits.
1280
+ (neg_lo ProducesFlags (x64_neg_paired $I64 x_lo))
1281
+ (adc_hi ConsumesFlags (x64_adc_paired $I64 x_hi (imm $I64 0)))
1282
+ (neg_adc_vals ValueRegs (with_flags neg_lo adc_hi))
1283
+ ; negate high bits.
1284
+ (neg_hi ProducesFlags (x64_neg_paired $I64 (value_regs_get neg_adc_vals 1)))
1285
+ (neg_hi_flag_only ProducesFlags (produces_flags_ignore neg_hi))
1286
+ ; cmove based on sign flag from hi negation.
1287
+ (cmove_lo ConsumesFlags (cmove $I64 (CC.S) x_lo
1288
+ (value_regs_get neg_adc_vals 0)))
1289
+ (cmove_hi ConsumesFlags (cmove $I64 (CC.S) x_hi
1290
+ (produces_flags_get_reg neg_hi)))
1291
+ (cmoves ConsumesFlags (consumes_flags_concat cmove_lo cmove_hi)))
1292
+ (with_flags neg_hi_flag_only cmoves)))
1293
+
1294
+ ;;;; Rules for `fabs` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1295
+
1296
+ (rule (lower (has_type $F32 (fabs x)))
1297
+ (x64_andps x (imm $F32 0x7fffffff)))
1298
+
1299
+ (rule (lower (has_type $F64 (fabs x)))
1300
+ (x64_andpd x (imm $F64 0x7fffffffffffffff)))
1301
+
1302
+ ;; Special case for `f32x4.abs`.
1303
+ (rule (lower (has_type $F32X4 (fabs x)))
1304
+ (x64_andps x
1305
+ (x64_psrld (vector_all_ones) (xmi_imm 1))))
1306
+
1307
+ ;; Special case for `f64x2.abs`.
1308
+ (rule (lower (has_type $F64X2 (fabs x)))
1309
+ (x64_andpd x
1310
+ (x64_psrlq (vector_all_ones) (xmi_imm 1))))
1311
+
1312
+ ;;;; Rules for `fneg` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1313
+
1314
+ (rule (lower (has_type $F32 (fneg x)))
1315
+ (x64_xorps x (imm $F32 0x80000000)))
1316
+
1317
+ (rule (lower (has_type $F64 (fneg x)))
1318
+ (x64_xorpd x (imm $F64 0x8000000000000000)))
1319
+
1320
+ (rule (lower (has_type $F32X4 (fneg x)))
1321
+ (x64_xorps x
1322
+ (x64_pslld (vector_all_ones) (xmi_imm 31))))
1323
+
1324
+ (rule (lower (has_type $F64X2 (fneg x)))
1325
+ (x64_xorpd x
1326
+ (x64_psllq (vector_all_ones) (xmi_imm 63))))
1327
+
1328
+ ;;;; Rules for `bmask` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1329
+
1330
+ (decl lower_bmask (Type Type ValueRegs) ValueRegs)
1331
+
1332
+ ;; Values that fit in a register
1333
+ ;;
1334
+ ;; Use the neg instruction on the input which sets the CF (carry) flag
1335
+ ;; to 0 if the input is 0 or 1 otherwise.
1336
+ ;; We then subtract the output register with itself, which always gives a 0,
1337
+ ;; however use the carry flag from the previous negate to generate a -1 if it
1338
+ ;; was nonzero.
1339
+ ;;
1340
+ ;; neg in_reg
1341
+ ;; sbb out_reg, out_reg
1342
+ (rule 0
1343
+ (lower_bmask (fits_in_64 out_ty) (fits_in_64 in_ty) val)
1344
+ (let ((reg Gpr (value_regs_get_gpr val 0))
1345
+ (out ValueRegs (with_flags
1346
+ (x64_neg_paired in_ty reg)
1347
+ (x64_sbb_paired out_ty reg reg))))
1348
+ ;; Extract only the output of the sbb instruction
1349
+ (value_reg (value_regs_get out 1))))
1350
+
1351
+
1352
+ ;; If the input type is I128 we can `or` the registers, and recurse to the general case.
1353
+ (rule 1
1354
+ (lower_bmask (fits_in_64 out_ty) $I128 val)
1355
+ (let ((lo Gpr (value_regs_get_gpr val 0))
1356
+ (hi Gpr (value_regs_get_gpr val 1))
1357
+ (mixed Gpr (x64_or $I64 lo hi)))
1358
+ (lower_bmask out_ty $I64 (value_reg mixed))))
1359
+
1360
+ ;; If the output type is I128 we just duplicate the result of the I64 lowering
1361
+ (rule 2
1362
+ (lower_bmask $I128 in_ty val)
1363
+ (let ((res ValueRegs (lower_bmask $I64 in_ty val))
1364
+ (res Gpr (value_regs_get_gpr res 0)))
1365
+ (value_regs res res)))
1366
+
1367
+
1368
+ ;; Call the lower_bmask rule that does all the procssing
1369
+ (rule (lower (has_type out_ty (bmask x @ (value_type in_ty))))
1370
+ (lower_bmask out_ty in_ty x))
1371
+
1372
+ ;;;; Rules for `bnot` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1373
+
1374
+ ;; `i64` and smaller.
1375
+
1376
+ (rule -2 (lower (has_type ty (bnot x)))
1377
+ (if (ty_int_ref_scalar_64 ty))
1378
+ (x64_not ty x))
1379
+
1380
+
1381
+ ;; `i128`.
1382
+
1383
+ (decl i128_not (Value) ValueRegs)
1384
+ (rule (i128_not x)
1385
+ (let ((x_regs ValueRegs x)
1386
+ (x_lo Gpr (value_regs_get_gpr x_regs 0))
1387
+ (x_hi Gpr (value_regs_get_gpr x_regs 1)))
1388
+ (value_gprs (x64_not $I64 x_lo)
1389
+ (x64_not $I64 x_hi))))
1390
+
1391
+ (rule (lower (has_type $I128 (bnot x)))
1392
+ (i128_not x))
1393
+
1394
+ ;; f32 and f64
1395
+
1396
+ (rule -3 (lower (has_type (ty_scalar_float ty) (bnot x)))
1397
+ (x64_xor_vector ty x (vector_all_ones)))
1398
+
1399
+ ;; Special case for vector-types where bit-negation is an xor against an
1400
+ ;; all-one value
1401
+ (rule -1 (lower (has_type ty @ (multi_lane _bits _lanes) (bnot x)))
1402
+ (x64_xor_vector ty x (vector_all_ones)))
1403
+
1404
+ ;;;; Rules for `bitselect` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1405
+
1406
+ (rule (lower (has_type ty @ (multi_lane _bits _lanes)
1407
+ (bitselect condition
1408
+ if_true
1409
+ if_false)))
1410
+ ;; a = and if_true, condition
1411
+ ;; b = and_not condition, if_false
1412
+ ;; or b, a
1413
+ (let ((cond_xmm Xmm condition)
1414
+ (a Xmm (sse_and ty if_true cond_xmm))
1415
+ (b Xmm (sse_and_not ty cond_xmm if_false)))
1416
+ (sse_or ty b a)))
1417
+
1418
+ ;; If every byte of the condition is guaranteed to be all ones or all zeroes,
1419
+ ;; we can use x64_blend.
1420
+ (rule 1 (lower (has_type ty @ (multi_lane _bits _lanes)
1421
+ (bitselect condition
1422
+ if_true
1423
+ if_false)))
1424
+ (if-let $true (use_sse41))
1425
+ (if (all_ones_or_all_zeros condition))
1426
+ (x64_pblendvb if_false if_true condition))
1427
+
1428
+ (decl pure partial all_ones_or_all_zeros (Value) bool)
1429
+ (rule (all_ones_or_all_zeros (and (icmp _ _ _) (value_type (multi_lane _ _)))) $true)
1430
+ (rule (all_ones_or_all_zeros (and (fcmp _ _ _) (value_type (multi_lane _ _)))) $true)
1431
+ (rule (all_ones_or_all_zeros (and (bitcast _ (fcmp _ _ _)) (value_type (multi_lane _ _)))) $true)
1432
+ (rule (all_ones_or_all_zeros (vconst (vconst_all_ones_or_all_zeros))) $true)
1433
+
1434
+ (decl pure vconst_all_ones_or_all_zeros () Constant)
1435
+ (extern extractor vconst_all_ones_or_all_zeros vconst_all_ones_or_all_zeros)
1436
+
1437
+ ;; Specializations for floating-pointer compares to generate a `minp*` or a
1438
+ ;; `maxp*` instruction. These are equivalent to the wasm `f32x4.{pmin,pmax}`
1439
+ ;; instructions and how they're lowered into CLIF. Note the careful ordering
1440
+ ;; of all the operands here to ensure that the input CLIF matched is implemented
1441
+ ;; by the corresponding x64 instruction.
1442
+ (rule 2 (lower (has_type $F32X4 (bitselect (bitcast _ (fcmp (FloatCC.LessThan) x y)) x y)))
1443
+ (x64_minps x y))
1444
+ (rule 2 (lower (has_type $F64X2 (bitselect (bitcast _ (fcmp (FloatCC.LessThan) x y)) x y)))
1445
+ (x64_minpd x y))
1446
+
1447
+ (rule 3 (lower (has_type $F32X4 (bitselect (bitcast _ (fcmp (FloatCC.LessThan) y x)) x y)))
1448
+ (x64_maxps x y))
1449
+ (rule 3 (lower (has_type $F64X2 (bitselect (bitcast _ (fcmp (FloatCC.LessThan) y x)) x y)))
1450
+ (x64_maxpd x y))
1451
+
1452
+ ;; Scalar rules
1453
+
1454
+ (rule 3 (lower (has_type $I128 (bitselect c t f)))
1455
+ (let ((a ValueRegs (and_i128 c t))
1456
+ (b ValueRegs (and_i128 (i128_not c) f)))
1457
+ (or_i128 a b)))
1458
+
1459
+ (rule 4 (lower (has_type (ty_int_ref_scalar_64 ty) (bitselect c t f)))
1460
+ (let ((a Gpr (x64_and ty c t))
1461
+ (b Gpr (x64_and ty (x64_not ty c) f)))
1462
+ (x64_or ty a b)))
1463
+
1464
+ (rule 5 (lower (has_type (ty_scalar_float ty) (bitselect c t f)))
1465
+ (let ((a Xmm (sse_and ty c t))
1466
+ (c_neg Xmm (x64_xor_vector ty c (vector_all_ones)))
1467
+ (b Xmm (sse_and ty c_neg f)))
1468
+ (sse_or ty a b)))
1469
+
1470
+ ;;;; Rules for `x86_blendv` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1471
+
1472
+ (rule (lower (has_type $I8X16
1473
+ (x86_blendv condition if_true if_false)))
1474
+ (if-let $true (use_sse41))
1475
+ (x64_pblendvb if_false if_true condition))
1476
+
1477
+ (rule (lower (has_type $I32X4
1478
+ (x86_blendv condition if_true if_false)))
1479
+ (if-let $true (use_sse41))
1480
+ (x64_blendvps if_false if_true condition))
1481
+
1482
+ (rule (lower (has_type $I64X2
1483
+ (x86_blendv condition if_true if_false)))
1484
+ (if-let $true (use_sse41))
1485
+ (x64_blendvpd if_false if_true condition))
1486
+
1487
+ ;;;; Rules for `insertlane` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1488
+
1489
+ (rule 1 (lower (insertlane vec @ (value_type $I8X16) val (u8_from_uimm8 idx)))
1490
+ (if-let $true (use_sse41))
1491
+ (x64_pinsrb vec val idx))
1492
+ (rule 2 (lower (insertlane vec @ (value_type $I8X16) (sinkable_load_exact val) (u8_from_uimm8 idx)))
1493
+ (if-let $true (use_sse41))
1494
+ (x64_pinsrb vec val idx))
1495
+
1496
+ ;; This lowering is particularly unoptimized and is mostly just here to work
1497
+ ;; rather than here to be fast. Requiring SSE 4.1 for the above lowering isn't
1498
+ ;; the end of the world hopefully as that's a pretty old instruction set, so
1499
+ ;; this is the "simplest" version that works on SSE2 for now.
1500
+ ;;
1501
+ ;; This lowering masks the original vector with a constant with all 1s except
1502
+ ;; for the "hole" where this value will get placed into, meaning the desired
1503
+ ;; lane is guaranteed as all 0s. Next the `val` is shuffled into this hole with
1504
+ ;; a few operations:
1505
+ ;;
1506
+ ;; 1. The `val` is zero-extended to 32-bits to guarantee the lower 32-bits
1507
+ ;; are all defined.
1508
+ ;; 2. An arithmetic shift-left is used with the low two bits of `n`, the
1509
+ ;; desired lane, to move the value into the right position within the 32-bit
1510
+ ;; register value.
1511
+ ;; 3. The 32-bit register is moved with `movd` into an XMM register
1512
+ ;; 4. The XMM register, where all lanes are 0 except for the first lane which
1513
+ ;; has the shifted value, is then shuffled with `pshufd` to move the
1514
+ ;; shifted value to the correct and final lane. This uses the upper two
1515
+ ;; bits of `n` to index the i32x4 lane that we're targeting.
1516
+ ;;
1517
+ ;; This all, laboriously, gets the `val` into the desired lane so it's then
1518
+ ;; `por`'d with the original vec-with-a-hole to produce the final result of the
1519
+ ;; insertion.
1520
+ (rule (lower (insertlane vec @ (value_type $I8X16) val (u8_from_uimm8 n)))
1521
+ (let ((vec_with_hole Xmm (x64_pand vec (insert_i8x16_lane_hole n)))
1522
+ (val Gpr (x64_movzx (ExtMode.BL) val))
1523
+ (val Gpr (x64_shl $I32 val (Imm8Reg.Imm8 (u8_shl (u8_and n 3) 3))))
1524
+ (val Xmm (x64_movd_to_xmm val))
1525
+ (val_at_hole Xmm (x64_pshufd val (insert_i8x16_lane_pshufd_imm (u8_shr n 2)))))
1526
+ (x64_por vec_with_hole val_at_hole)))
1527
+
1528
+ (decl insert_i8x16_lane_hole (u8) VCodeConstant)
1529
+ (extern constructor insert_i8x16_lane_hole insert_i8x16_lane_hole)
1530
+ (decl insert_i8x16_lane_pshufd_imm (u8) u8)
1531
+ (rule (insert_i8x16_lane_pshufd_imm 0) 0b01_01_01_00)
1532
+ (rule (insert_i8x16_lane_pshufd_imm 1) 0b01_01_00_01)
1533
+ (rule (insert_i8x16_lane_pshufd_imm 2) 0b01_00_01_01)
1534
+ (rule (insert_i8x16_lane_pshufd_imm 3) 0b00_01_01_01)
1535
+
1536
+
1537
+ ;; i16x8.replace_lane
1538
+ (rule (lower (insertlane vec @ (value_type $I16X8) val (u8_from_uimm8 idx)))
1539
+ (x64_pinsrw vec val idx))
1540
+ (rule 1 (lower (insertlane vec @ (value_type $I16X8) (sinkable_load_exact val) (u8_from_uimm8 idx)))
1541
+ (x64_pinsrw vec val idx))
1542
+
1543
+ ;; i32x4.replace_lane
1544
+ (rule 1 (lower (insertlane vec @ (value_type $I32X4) val (u8_from_uimm8 idx)))
1545
+ (if-let $true (use_sse41))
1546
+ (x64_pinsrd vec val idx))
1547
+
1548
+ (rule (lower (insertlane vec @ (value_type $I32X4) val (u8_from_uimm8 0)))
1549
+ (x64_movss_regmove vec (x64_movd_to_xmm val)))
1550
+
1551
+ ;; tmp = [ vec[1] vec[0] val[1] val[0] ]
1552
+ ;; result = [ vec[3] vec[2] tmp[0] tmp[2] ]
1553
+ (rule (lower (insertlane vec @ (value_type $I32X4) val (u8_from_uimm8 1)))
1554
+ (let ((val Xmm (x64_movd_to_xmm val))
1555
+ (vec Xmm vec))
1556
+ (x64_shufps (x64_punpcklqdq val vec) vec 0b11_10_00_10)))
1557
+
1558
+ ;; tmp = [ vec[0] vec[3] val[0] val[0] ]
1559
+ ;; result = [ tmp[2] tmp[0] vec[1] vec[0] ]
1560
+ (rule (lower (insertlane vec @ (value_type $I32X4) val (u8_from_uimm8 2)))
1561
+ (let ((val Xmm (x64_movd_to_xmm val))
1562
+ (vec Xmm vec))
1563
+ (x64_shufps vec (x64_shufps val vec 0b00_11_00_00) 0b10_00_01_00)))
1564
+
1565
+ ;; tmp = [ vec[3] vec[2] val[1] val[0] ]
1566
+ ;; result = [ tmp[0] tmp[2] vec[1] vec[0] ]
1567
+ (rule (lower (insertlane vec @ (value_type $I32X4) val (u8_from_uimm8 3)))
1568
+ (let ((val Xmm (x64_movd_to_xmm val))
1569
+ (vec Xmm vec))
1570
+ (x64_shufps vec (x64_shufps val vec 0b11_10_01_00) 0b00_10_01_00)))
1571
+
1572
+ ;; i64x2.replace_lane
1573
+ (rule 1 (lower (insertlane vec @ (value_type $I64X2) val (u8_from_uimm8 idx)))
1574
+ (if-let $true (use_sse41))
1575
+ (x64_pinsrq vec val idx))
1576
+ (rule (lower (insertlane vec @ (value_type $I64X2) val (u8_from_uimm8 0)))
1577
+ (x64_movsd_regmove vec (x64_movq_to_xmm val)))
1578
+ (rule (lower (insertlane vec @ (value_type $I64X2) val (u8_from_uimm8 1)))
1579
+ (x64_punpcklqdq vec (x64_movq_to_xmm val)))
1580
+
1581
+ ;; (i64x2.replace_lane 1) with a splat as source for lane 0 -- we can elide
1582
+ ;; the splat and just do a move. This turns out to be a common pattern when
1583
+ ;; constructing an i64x2 out of two i64s.
1584
+ (rule 3 (lower (insertlane (has_type $I64X2 (splat lane0))
1585
+ lane1
1586
+ (u8_from_uimm8 1)))
1587
+ (if-let $true (use_sse41))
1588
+ (x64_pinsrq (bitcast_gpr_to_xmm $I64 lane0) lane1 1))
1589
+
1590
+ (rule 1 (lower (insertlane vec @ (value_type $F32X4) (sinkable_load val) (u8_from_uimm8 idx)))
1591
+ (if-let $true (use_sse41))
1592
+ (x64_insertps vec val (sse_insertps_lane_imm idx)))
1593
+ (rule (lower (insertlane vec @ (value_type $F32X4) val (u8_from_uimm8 idx)))
1594
+ (f32x4_insertlane vec val idx))
1595
+
1596
+ ;; Helper function used below for `insertlane` but also here for other
1597
+ (decl f32x4_insertlane (Xmm Xmm u8) Xmm)
1598
+
1599
+ ;; f32x4.replace_lane
1600
+ (rule 1 (f32x4_insertlane vec val idx)
1601
+ (if-let $true (use_sse41))
1602
+ (x64_insertps vec val (sse_insertps_lane_imm idx)))
1603
+
1604
+ ;; External rust code used to calculate the immediate value to `insertps`.
1605
+ (decl sse_insertps_lane_imm (u8) u8)
1606
+ (extern constructor sse_insertps_lane_imm sse_insertps_lane_imm)
1607
+
1608
+ ;; f32x4.replace_lane 0
1609
+ (rule (f32x4_insertlane vec val 0)
1610
+ (x64_movss_regmove vec val))
1611
+
1612
+ ;; f32x4.replace_lane 1
1613
+ ;; tmp = [ vec[1] vec[0] val[1] val[0] ]
1614
+ ;; result = [ vec[3] vec[2] tmp[0] tmp[2] ]
1615
+ (rule (f32x4_insertlane vec val 1)
1616
+ (let ((tmp Xmm (x64_movlhps val vec)))
1617
+ (x64_shufps tmp vec 0b11_10_00_10)))
1618
+
1619
+ ;; f32x4.replace_lane 2
1620
+ ;; tmp = [ vec[0] vec[3] val[0] val[0] ]
1621
+ ;; result = [ tmp[2] tmp[0] vec[1] vec[0] ]
1622
+ (rule (f32x4_insertlane vec val 2)
1623
+ (let ((tmp Xmm (x64_shufps val vec 0b00_11_00_00)))
1624
+ (x64_shufps vec tmp 0b10_00_01_00)))
1625
+
1626
+ ;; f32x4.replace_lane 3
1627
+ ;; tmp = [ vec[3] vec[2] val[1] val[0] ]
1628
+ ;; result = [ tmp[0] tmp[2] vec[1] vec[0] ]
1629
+ (rule (f32x4_insertlane vec val 3)
1630
+ (let ((tmp Xmm (x64_shufps val vec 0b11_10_01_00)))
1631
+ (x64_shufps vec tmp 0b00_10_01_00)))
1632
+
1633
+ ;; f64x2.replace_lane 0
1634
+ ;;
1635
+ ;; Here the `movsd` instruction is used specifically to specialize moving
1636
+ ;; into the fist lane where unlike above cases we're not using the lane
1637
+ ;; immediate as an immediate to the instruction itself.
1638
+ (rule (lower (insertlane vec @ (value_type $F64X2) val (u8_from_uimm8 0)))
1639
+ (x64_movsd_regmove vec val))
1640
+
1641
+ ;; f64x2.replace_lane 1
1642
+ ;;
1643
+ ;; Here the `movlhps` instruction is used specifically to specialize moving
1644
+ ;; into the second lane where unlike above cases we're not using the lane
1645
+ ;; immediate as an immediate to the instruction itself.
1646
+ (rule (lower (insertlane vec @ (value_type $F64X2) val (u8_from_uimm8 1)))
1647
+ (x64_movlhps vec val))
1648
+
1649
+ ;;;; Rules for `smin`, `smax`, `umin`, `umax` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1650
+
1651
+ ;; `i64` and smaller.
1652
+
1653
+ (decl cmp_and_choose (Type CC Value Value) ValueRegs)
1654
+ (rule (cmp_and_choose (fits_in_64 ty) cc x y)
1655
+ (let ((size OperandSize (raw_operand_size_of_type ty))
1656
+ ;; We need to put x and y in registers explicitly because
1657
+ ;; we use the values more than once. Hence, even if these
1658
+ ;; are "unique uses" at the CLIF level and would otherwise
1659
+ ;; allow for load-op merging, here we cannot do that.
1660
+ (x_reg Reg x)
1661
+ (y_reg Reg y))
1662
+ (with_flags_reg (x64_cmp size y_reg x_reg)
1663
+ (cmove ty cc y_reg x_reg))))
1664
+
1665
+ (rule -1 (lower (has_type (fits_in_64 ty) (umin x y)))
1666
+ (cmp_and_choose ty (CC.B) x y))
1667
+
1668
+ (rule -1 (lower (has_type (fits_in_64 ty) (umax x y)))
1669
+ (cmp_and_choose ty (CC.NB) x y))
1670
+
1671
+ (rule -1 (lower (has_type (fits_in_64 ty) (smin x y)))
1672
+ (cmp_and_choose ty (CC.L) x y))
1673
+
1674
+ (rule -1 (lower (has_type (fits_in_64 ty) (smax x y)))
1675
+ (cmp_and_choose ty (CC.NL) x y))
1676
+
1677
+ ;; SSE helpers for determining if single-instruction lowerings are available.
1678
+
1679
+ (decl pure has_pmins (Type) bool)
1680
+ (rule 1 (has_pmins $I16X8) $true)
1681
+ (rule 1 (has_pmins $I64X2) $false)
1682
+ (rule (has_pmins _) (use_sse41))
1683
+
1684
+ (decl pure has_pmaxs (Type) bool)
1685
+ (rule 1 (has_pmaxs $I16X8) $true)
1686
+ (rule 1 (has_pmaxs $I64X2) $false)
1687
+ (rule (has_pmaxs _) (use_sse41))
1688
+
1689
+ (decl pure has_pmaxu (Type) bool)
1690
+ (rule 1 (has_pmaxu $I8X16) $true)
1691
+ (rule 1 (has_pmaxu $I64X2) $false)
1692
+ (rule (has_pmaxu _) (use_sse41))
1693
+
1694
+ (decl pure has_pminu (Type) bool)
1695
+ (rule 1 (has_pminu $I8X16) $true)
1696
+ (rule 1 (has_pminu $I64X2) $false)
1697
+ (rule (has_pminu _) (use_sse41))
1698
+
1699
+ ;; SSE `smax`.
1700
+
1701
+ (rule (lower (has_type (ty_vec128 ty) (smax x y)))
1702
+ (lower_vec_smax ty x y))
1703
+
1704
+ (decl lower_vec_smax (Type Xmm Xmm) Xmm)
1705
+ (rule 1 (lower_vec_smax ty x y)
1706
+ (if-let $true (has_pmaxs ty))
1707
+ (x64_pmaxs ty x y))
1708
+
1709
+ (rule (lower_vec_smax ty x y)
1710
+ (let (
1711
+ (x Xmm x)
1712
+ (y Xmm y)
1713
+ (cmp Xmm (x64_pcmpgt ty x y))
1714
+ (x_is_max Xmm (x64_pand cmp x))
1715
+ (y_is_max Xmm (x64_pandn cmp y))
1716
+ )
1717
+ (x64_por x_is_max y_is_max)))
1718
+
1719
+ ;; SSE `smin`.
1720
+
1721
+ (rule 1 (lower (has_type (ty_vec128 ty) (smin x y)))
1722
+ (if-let $true (has_pmins ty))
1723
+ (x64_pmins ty x y))
1724
+
1725
+ (rule (lower (has_type (ty_vec128 ty) (smin x y)))
1726
+ (let (
1727
+ (x Xmm x)
1728
+ (y Xmm y)
1729
+ (cmp Xmm (x64_pcmpgt ty y x))
1730
+ (x_is_min Xmm (x64_pand cmp x))
1731
+ (y_is_min Xmm (x64_pandn cmp y))
1732
+ )
1733
+ (x64_por x_is_min y_is_min)))
1734
+
1735
+ ;; SSE `umax`.
1736
+
1737
+ (rule 2 (lower (has_type (ty_vec128 ty) (umax x y)))
1738
+ (if-let $true (has_pmaxu ty))
1739
+ (x64_pmaxu ty x y))
1740
+
1741
+ ;; If y < x then the saturating subtraction will be zero, otherwise when added
1742
+ ;; back to x it'll return y.
1743
+ (rule 1 (lower (has_type $I16X8 (umax x y)))
1744
+ (let ((x Xmm x))
1745
+ (x64_paddw x (x64_psubusw y x))))
1746
+
1747
+ ;; Flip the upper bits of each lane so the signed comparison has the same
1748
+ ;; result as a signed comparison, and then select the results with the output
1749
+ ;; mask. See `pcmpgt` lowering for info on flipping the upper bit.
1750
+ (rule (lower (has_type (ty_vec128 ty) (umax x y)))
1751
+ (let (
1752
+ (x Xmm x)
1753
+ (y Xmm y)
1754
+ (mask Xmm (flip_high_bit_mask ty))
1755
+ (x_masked Xmm (x64_pxor x mask))
1756
+ (y_masked Xmm (x64_pxor y mask))
1757
+ (cmp Xmm (x64_pcmpgt ty x_masked y_masked))
1758
+ (x_is_max Xmm (x64_pand cmp x))
1759
+ (y_is_max Xmm (x64_pandn cmp y))
1760
+ )
1761
+ (x64_por x_is_max y_is_max)))
1762
+
1763
+ (decl flip_high_bit_mask (Type) Xmm)
1764
+ (rule (flip_high_bit_mask $I16X8)
1765
+ (x64_movdqu_load (emit_u128_le_const 0x8000_8000_8000_8000_8000_8000_8000_8000)))
1766
+ (rule (flip_high_bit_mask $I32X4)
1767
+ (x64_movdqu_load (emit_u128_le_const 0x80000000_80000000_80000000_80000000)))
1768
+ (rule (flip_high_bit_mask $I64X2)
1769
+ (x64_movdqu_load (emit_u128_le_const 0x8000000000000000_8000000000000000)))
1770
+
1771
+ ;; SSE `umin`.
1772
+
1773
+ (rule 2 (lower (has_type (ty_vec128 ty) (umin x y)))
1774
+ (if-let $true (has_pminu ty))
1775
+ (x64_pminu ty x y))
1776
+
1777
+ ;; If x < y then the saturating subtraction will be 0. Otherwise if x > y then
1778
+ ;; the saturated result, when subtracted again, will go back to `y`.
1779
+ (rule 1 (lower (has_type $I16X8 (umin x y)))
1780
+ (let ((x Xmm x))
1781
+ (x64_psubw x (x64_psubusw x y))))
1782
+
1783
+ ;; Same as `umax`, and see `pcmpgt` for docs on flipping the upper bit.
1784
+ (rule (lower (has_type (ty_vec128 ty) (umin x y)))
1785
+ (let (
1786
+ (x Xmm x)
1787
+ (y Xmm y)
1788
+ (mask Xmm (flip_high_bit_mask ty))
1789
+ (x_masked Xmm (x64_pxor x mask))
1790
+ (y_masked Xmm (x64_pxor y mask))
1791
+ (cmp Xmm (x64_pcmpgt ty y_masked x_masked))
1792
+ (x_is_max Xmm (x64_pand cmp x))
1793
+ (y_is_max Xmm (x64_pandn cmp y))
1794
+ )
1795
+ (x64_por x_is_max y_is_max)))
1796
+
1797
+ ;;;; Rules for `trap` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1798
+
1799
+ (rule (lower (trap code))
1800
+ (side_effect (x64_ud2 code)))
1801
+
1802
+ ;;;; Rules for `uadd_overflow_trap` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1803
+
1804
+ (rule (lower (has_type (fits_in_64 ty) (uadd_overflow_trap a b tc)))
1805
+ (with_flags
1806
+ (x64_add_with_flags_paired ty a b)
1807
+ (trap_if (CC.B) tc)))
1808
+
1809
+ ;; Handle lhs immediates/sinkable loads in addition to the automatic rhs
1810
+ ;; handling of above.
1811
+
1812
+ (rule 1 (lower (has_type (fits_in_64 ty)
1813
+ (uadd_overflow_trap (simm32_from_value a) b tc)))
1814
+ (with_flags
1815
+ (x64_add_with_flags_paired ty b a)
1816
+ (trap_if (CC.B) tc)))
1817
+
1818
+ (rule 2 (lower (has_type (fits_in_64 ty)
1819
+ (uadd_overflow_trap (sinkable_load a) b tc)))
1820
+ (with_flags
1821
+ (x64_add_with_flags_paired ty b a)
1822
+ (trap_if (CC.B) tc)))
1823
+
1824
+ ;;;; Rules for `resumable_trap` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1825
+
1826
+ (rule (lower (resumable_trap code))
1827
+ (side_effect (x64_ud2 code)))
1828
+
1829
+ ;;;; Rules for `return` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1830
+
1831
+ ;; N.B.: the Ret itself is generated by the ABI.
1832
+ (rule (lower (return args))
1833
+ (lower_return args))
1834
+
1835
+ ;;;; Rules for `icmp` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1836
+
1837
+ (rule -2 (lower (icmp cc a @ (value_type (fits_in_64 ty)) b))
1838
+ (lower_icmp_bool (emit_cmp cc a b)))
1839
+
1840
+ (rule -1 (lower (icmp cc a @ (value_type $I128) b))
1841
+ (lower_icmp_bool (emit_cmp cc a b)))
1842
+
1843
+ ;; Peephole optimization for `x < 0`, when x is a signed 64 bit value
1844
+ (rule 2 (lower (has_type $I8 (icmp (IntCC.SignedLessThan) x @ (value_type $I64) (u64_from_iconst 0))))
1845
+ (x64_shr $I64 x (Imm8Reg.Imm8 63)))
1846
+
1847
+ ;; Peephole optimization for `0 > x`, when x is a signed 64 bit value
1848
+ (rule 2 (lower (has_type $I8 (icmp (IntCC.SignedGreaterThan) (u64_from_iconst 0) x @ (value_type $I64))))
1849
+ (x64_shr $I64 x (Imm8Reg.Imm8 63)))
1850
+
1851
+ ;; Peephole optimization for `0 <= x`, when x is a signed 64 bit value
1852
+ (rule 2 (lower (has_type $I8 (icmp (IntCC.SignedLessThanOrEqual) (u64_from_iconst 0) x @ (value_type $I64))))
1853
+ (x64_shr $I64 (x64_not $I64 x) (Imm8Reg.Imm8 63)))
1854
+
1855
+ ;; Peephole optimization for `x >= 0`, when x is a signed 64 bit value
1856
+ (rule 2 (lower (has_type $I8 (icmp (IntCC.SignedGreaterThanOrEqual) x @ (value_type $I64) (u64_from_iconst 0))))
1857
+ (x64_shr $I64 (x64_not $I64 x) (Imm8Reg.Imm8 63)))
1858
+
1859
+ ;; Peephole optimization for `x < 0`, when x is a signed 32 bit value
1860
+ (rule 2 (lower (has_type $I8 (icmp (IntCC.SignedLessThan) x @ (value_type $I32) (u64_from_iconst 0))))
1861
+ (x64_shr $I32 x (Imm8Reg.Imm8 31)))
1862
+
1863
+ ;; Peephole optimization for `0 > x`, when x is a signed 32 bit value
1864
+ (rule 2 (lower (has_type $I8 (icmp (IntCC.SignedGreaterThan) (u64_from_iconst 0) x @ (value_type $I32))))
1865
+ (x64_shr $I32 x (Imm8Reg.Imm8 31)))
1866
+
1867
+ ;; Peephole optimization for `0 <= x`, when x is a signed 32 bit value
1868
+ (rule 2 (lower (has_type $I8 (icmp (IntCC.SignedLessThanOrEqual) (u64_from_iconst 0) x @ (value_type $I32))))
1869
+ (x64_shr $I32 (x64_not $I64 x) (Imm8Reg.Imm8 31)))
1870
+
1871
+ ;; Peephole optimization for `x >= 0`, when x is a signed 32 bit value
1872
+ (rule 2 (lower (has_type $I8 (icmp (IntCC.SignedGreaterThanOrEqual) x @ (value_type $I32) (u64_from_iconst 0))))
1873
+ (x64_shr $I32 (x64_not $I64 x) (Imm8Reg.Imm8 31)))
1874
+
1875
+ ;; For XMM-held values, we lower to `PCMP*` instructions, sometimes more than
1876
+ ;; one. To note: what is different here about the output values is that each
1877
+ ;; lane will be filled with all 1s or all 0s according to the comparison,
1878
+ ;; whereas for GPR-held values, the result will be simply 0 or 1 (upper bits
1879
+ ;; unset).
1880
+ (rule (lower (icmp (IntCC.Equal) a @ (value_type (ty_vec128 ty)) b))
1881
+ (x64_pcmpeq ty a b))
1882
+
1883
+ ;; To lower a not-equals comparison, we perform an equality comparison
1884
+ ;; (PCMPEQ*) and then invert the bits (PXOR with all 1s).
1885
+ (rule (lower (icmp (IntCC.NotEqual) a @ (value_type (ty_vec128 ty)) b))
1886
+ (let ((checked Xmm (x64_pcmpeq ty a b))
1887
+ (all_ones Xmm (vector_all_ones)))
1888
+ (x64_pxor checked all_ones)))
1889
+
1890
+ ;; SSE `sgt`
1891
+
1892
+ (rule (lower (icmp (IntCC.SignedGreaterThan) a @ (value_type (ty_vec128 ty)) b))
1893
+ (x64_pcmpgt ty a b))
1894
+
1895
+ ;; SSE `slt`
1896
+
1897
+ (rule (lower (icmp (IntCC.SignedLessThan) a @ (value_type (ty_vec128 ty)) b))
1898
+ (x64_pcmpgt ty b a))
1899
+
1900
+ ;; SSE `ugt`
1901
+
1902
+ ;; N.B.: we must manually prevent load coalescing operands; the
1903
+ ;; register allocator gets confused otherwise.
1904
+ (rule 1 (lower (icmp (IntCC.UnsignedGreaterThan) a @ (value_type (ty_vec128 ty)) b))
1905
+ (if-let $true (has_pmaxu ty))
1906
+ (let ((a Xmm a)
1907
+ (b Xmm b)
1908
+ (max Xmm (x64_pmaxu ty a b))
1909
+ (eq Xmm (x64_pcmpeq ty max b)))
1910
+ (x64_pxor eq (vector_all_ones))))
1911
+
1912
+ ;; Flip the upper bit of each lane so the result of a signed comparison is the
1913
+ ;; same as the result of an unsigned comparison (see docs on `pcmpgt` for more)
1914
+ (rule (lower (icmp (IntCC.UnsignedGreaterThan) a @ (value_type (ty_vec128 ty)) b))
1915
+ (let ((mask Xmm (flip_high_bit_mask ty))
1916
+ (a_masked Xmm (x64_pxor a mask))
1917
+ (b_masked Xmm (x64_pxor b mask)))
1918
+ (x64_pcmpgt ty a_masked b_masked)))
1919
+
1920
+ ;; SSE `ult`
1921
+
1922
+ (rule 1 (lower (icmp (IntCC.UnsignedLessThan) a @ (value_type (ty_vec128 ty)) b))
1923
+ (if-let $true (has_pminu ty))
1924
+ ;; N.B.: see note above.
1925
+ (let ((a Xmm a)
1926
+ (b Xmm b)
1927
+ (min Xmm (x64_pminu ty a b))
1928
+ (eq Xmm (x64_pcmpeq ty min b)))
1929
+ (x64_pxor eq (vector_all_ones))))
1930
+
1931
+ ;; Flip the upper bit of `a` and `b` so the signed comparison result will
1932
+ ;; be the same as the unsigned comparison result (see docs on `pcmpgt` for more).
1933
+ (rule (lower (icmp (IntCC.UnsignedLessThan) a @ (value_type (ty_vec128 ty)) b))
1934
+ (let ((mask Xmm (flip_high_bit_mask ty))
1935
+ (a_masked Xmm (x64_pxor a mask))
1936
+ (b_masked Xmm (x64_pxor b mask)))
1937
+ (x64_pcmpgt ty b_masked a_masked)))
1938
+
1939
+ ;; SSE `sge`
1940
+
1941
+ ;; Use `pmaxs*` and compare the result to `a` to see if it's `>= b`.
1942
+ (rule 1 (lower (icmp (IntCC.SignedGreaterThanOrEqual) a @ (value_type (ty_vec128 ty)) b))
1943
+ (if-let $true (has_pmaxs ty))
1944
+ (x64_pcmpeq ty a (x64_pmaxs ty a b)))
1945
+
1946
+ ;; Without `pmaxs*` use a `pcmpgt*` with reversed operands and invert the
1947
+ ;; result.
1948
+ (rule (lower (icmp (IntCC.SignedGreaterThanOrEqual) a @ (value_type (ty_vec128 ty)) b))
1949
+ (x64_pxor (x64_pcmpgt ty b a) (vector_all_ones)))
1950
+
1951
+ ;; SSE `sle`
1952
+
1953
+ ;; With `pmins*` use that and compare the result to `a`.
1954
+ (rule 1 (lower (icmp (IntCC.SignedLessThanOrEqual) a @ (value_type (ty_vec128 ty)) b))
1955
+ (if-let $true (has_pmins ty))
1956
+ (x64_pcmpeq ty a (x64_pmins ty a b)))
1957
+
1958
+ ;; Without `pmins*` perform a greater-than test and invert the result.
1959
+ (rule (lower (icmp (IntCC.SignedLessThanOrEqual) a @ (value_type (ty_vec128 ty)) b))
1960
+ (x64_pxor (x64_pcmpgt ty a b) (vector_all_ones)))
1961
+
1962
+ ;; SSE `uge`
1963
+
1964
+ (rule 2 (lower (icmp (IntCC.UnsignedGreaterThanOrEqual) a @ (value_type (ty_vec128 ty)) b))
1965
+ (if-let $true (has_pmaxu ty))
1966
+ (x64_pcmpeq ty a (x64_pmaxu ty a b)))
1967
+
1968
+ ;; Perform a saturating subtract of `a` from `b` and if the result is zero then
1969
+ ;; `a` is greater or equal.
1970
+ (rule 1 (lower (icmp (IntCC.UnsignedGreaterThanOrEqual) a @ (value_type $I16X8) b))
1971
+ (x64_pcmpeqw (x64_psubusw b a) (xmm_zero $I16X8)))
1972
+
1973
+ ;; Flip the upper bit of each lane so the signed comparison is the same as
1974
+ ;; an unsigned one and then invert the result. See docs on `pcmpgt` for why
1975
+ ;; flipping the upper bit works.
1976
+ (rule (lower (icmp (IntCC.UnsignedGreaterThanOrEqual) a @ (value_type (ty_vec128 ty)) b))
1977
+ (let (
1978
+ (mask Xmm (flip_high_bit_mask ty))
1979
+ (a_masked Xmm (x64_pxor a mask))
1980
+ (b_masked Xmm (x64_pxor b mask))
1981
+ (cmp Xmm (x64_pcmpgt ty b_masked a_masked))
1982
+ )
1983
+ (x64_pxor cmp (vector_all_ones))))
1984
+
1985
+ ;; SSE `ule`
1986
+
1987
+ (rule 2 (lower (icmp (IntCC.UnsignedLessThanOrEqual) a @ (value_type (ty_vec128 ty)) b))
1988
+ (if-let $true (has_pminu ty))
1989
+ (x64_pcmpeq ty a (x64_pminu ty a b)))
1990
+
1991
+ ;; A saturating subtraction will produce zeros if `a` is less than `b`, so
1992
+ ;; compare that result to an all-zeros result to figure out lanes of `a` that
1993
+ ;; are <= to the lanes in `b`
1994
+ (rule 1 (lower (icmp (IntCC.UnsignedLessThanOrEqual) a @ (value_type $I16X8) b))
1995
+ (let ((zeros_if_a_is_min Xmm (x64_psubusw a b)))
1996
+ (x64_pcmpeqw zeros_if_a_is_min (xmm_zero $I8X16))))
1997
+
1998
+ ;; Flip the upper bit of each lane in `a` and `b` so a signed comparison
1999
+ ;; produces the same result as an unsigned comparison. Then test test for `gt`
2000
+ ;; and invert the result to get the `le` that is desired here. See docs on
2001
+ ;; `pcmpgt` for why flipping the upper bit works.
2002
+ (rule (lower (icmp (IntCC.UnsignedLessThanOrEqual) a @ (value_type (ty_vec128 ty)) b))
2003
+ (let (
2004
+ (mask Xmm (flip_high_bit_mask ty))
2005
+ (a_masked Xmm (x64_pxor a mask))
2006
+ (b_masked Xmm (x64_pxor b mask))
2007
+ (cmp Xmm (x64_pcmpgt ty a_masked b_masked))
2008
+ )
2009
+ (x64_pxor cmp (vector_all_ones))))
2010
+
2011
+ ;;;; Rules for `fcmp` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2012
+
2013
+ ;; CLIF's `fcmp` instruction always operates on XMM registers--both scalar and
2014
+ ;; vector. For the scalar versions, we use the flag-setting behavior of the
2015
+ ;; `UCOMIS*` instruction to `SETcc` a 0 or 1 in a GPR register. Note that CLIF's
2016
+ ;; `select` uses the same kind of flag-setting behavior but chooses values other
2017
+ ;; than 0 or 1.
2018
+ ;;
2019
+ ;; Checking the result of `UCOMIS*` is unfortunately difficult in some cases
2020
+ ;; because we do not have `SETcc` instructions that explicitly check
2021
+ ;; simultaneously for the condition (i.e., `eq`, `le`, `gt`, etc.) *and*
2022
+ ;; orderedness. Instead, we must check the flags multiple times. The UCOMIS*
2023
+ ;; documentation (see Intel's Software Developer's Manual, volume 2, chapter 4)
2024
+ ;; is helpful:
2025
+ ;; - unordered assigns Z = 1, P = 1, C = 1
2026
+ ;; - greater than assigns Z = 0, P = 0, C = 0
2027
+ ;; - less than assigns Z = 0, P = 0, C = 1
2028
+ ;; - equal assigns Z = 1, P = 0, C = 0
2029
+
2030
+ (rule -1 (lower (fcmp cc a @ (value_type (ty_scalar_float ty)) b))
2031
+ (lower_fcmp_bool (emit_fcmp cc a b)))
2032
+
2033
+ ;; For vector lowerings, we use `CMPP*` instructions with a 3-bit operand that
2034
+ ;; determines the comparison to make. Note that comparisons that succeed will
2035
+ ;; fill the lane with 1s; comparisons that do not will fill the lane with 0s.
2036
+
2037
+ (rule (lower (fcmp (FloatCC.Equal) a @ (value_type (ty_vec128 ty)) b))
2038
+ (x64_cmpp ty a b (FcmpImm.Equal)))
2039
+ (rule (lower (fcmp (FloatCC.NotEqual) a @ (value_type (ty_vec128 ty)) b))
2040
+ (x64_cmpp ty a b (FcmpImm.NotEqual)))
2041
+ (rule (lower (fcmp (FloatCC.LessThan) a @ (value_type (ty_vec128 ty)) b))
2042
+ (x64_cmpp ty a b (FcmpImm.LessThan)))
2043
+ (rule (lower (fcmp (FloatCC.LessThanOrEqual) a @ (value_type (ty_vec128 ty)) b))
2044
+ (x64_cmpp ty a b (FcmpImm.LessThanOrEqual)))
2045
+ (rule (lower (fcmp (FloatCC.Ordered) a @ (value_type (ty_vec128 ty)) b))
2046
+ (x64_cmpp ty a b (FcmpImm.Ordered)))
2047
+ (rule (lower (fcmp (FloatCC.Unordered) a @ (value_type (ty_vec128 ty)) b))
2048
+ (x64_cmpp ty a b (FcmpImm.Unordered)))
2049
+ (rule (lower (fcmp (FloatCC.UnorderedOrGreaterThan) a @ (value_type (ty_vec128 ty)) b))
2050
+ (x64_cmpp ty a b (FcmpImm.UnorderedOrGreaterThan)))
2051
+ (rule (lower (fcmp (FloatCC.UnorderedOrGreaterThanOrEqual) a @ (value_type (ty_vec128 ty)) b))
2052
+ (x64_cmpp ty a b (FcmpImm.UnorderedOrGreaterThanOrEqual)))
2053
+
2054
+ ;; Some vector lowerings rely on flipping the operands and using a reversed
2055
+ ;; comparison code.
2056
+
2057
+ (rule (lower (fcmp (FloatCC.GreaterThan) a @ (value_type (ty_vec128 ty)) b))
2058
+ (x64_cmpp ty b a (FcmpImm.LessThan)))
2059
+ (rule (lower (fcmp (FloatCC.GreaterThanOrEqual) a @ (value_type (ty_vec128 ty)) b))
2060
+ (x64_cmpp ty b a (FcmpImm.LessThanOrEqual)))
2061
+ (rule (lower (fcmp (FloatCC.UnorderedOrLessThan) a @ (value_type (ty_vec128 ty)) b))
2062
+ (x64_cmpp ty b a (FcmpImm.UnorderedOrGreaterThan)))
2063
+ (rule (lower (fcmp (FloatCC.UnorderedOrLessThanOrEqual) a @ (value_type (ty_vec128 ty)) b))
2064
+ (x64_cmpp ty b a (FcmpImm.UnorderedOrGreaterThanOrEqual)))
2065
+
2066
+ ;; Some vector lowerings are simply not supported for certain codes:
2067
+ ;; - FloatCC::OrderedNotEqual
2068
+ ;; - FloatCC::UnorderedOrEqual
2069
+
2070
+ ;;;; Rules for `select` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2071
+
2072
+ ;; When a `select` has an `fcmp` as a condition then rely on `emit_fcmp` to
2073
+ ;; figure out how to perform the comparison.
2074
+ ;;
2075
+ ;; Note, though, that the `FloatCC.Equal` requires an "and" to happen for two
2076
+ ;; condition codes which isn't the easiest thing to lower to a `cmove`
2077
+ ;; instruction. For this reason a `select (fcmp eq ..) ..` is instead
2078
+ ;; flipped around to be `select (fcmp ne ..) ..` with all operands reversed.
2079
+ ;; This will produce a `FcmpCondResult.OrCondition` which is easier to codegen
2080
+ ;; for.
2081
+ (rule (lower (has_type ty (select (maybe_uextend (fcmp cc a b)) x y)))
2082
+ (lower_select_fcmp ty (emit_fcmp cc a b) x y))
2083
+ (rule 1 (lower (has_type ty (select (maybe_uextend (fcmp (FloatCC.Equal) a b)) x y)))
2084
+ (lower_select_fcmp ty (emit_fcmp (FloatCC.NotEqual) a b) y x))
2085
+
2086
+ (decl lower_select_fcmp (Type FcmpCondResult Value Value) InstOutput)
2087
+ (rule (lower_select_fcmp ty (FcmpCondResult.Condition flags cc) x y)
2088
+ (with_flags flags (cmove_from_values ty cc x y)))
2089
+ (rule (lower_select_fcmp ty (FcmpCondResult.OrCondition flags cc1 cc2) x y)
2090
+ (with_flags flags (cmove_or_from_values ty cc1 cc2 x y)))
2091
+
2092
+ ;; We also can lower `select`s that depend on an `icmp` test, but more simply
2093
+ ;; than the `fcmp` variants above. In these cases, we lower to a `CMP`
2094
+ ;; instruction plus a `CMOV`; recall that `cmove_from_values` here may emit more
2095
+ ;; than one instruction for certain types (e.g., XMM-held, I128).
2096
+
2097
+ (rule (lower (has_type ty (select (maybe_uextend (icmp cc a @ (value_type (fits_in_64 a_ty)) b)) x y)))
2098
+ (lower_select_icmp ty (emit_cmp cc a b) x y))
2099
+
2100
+ ;; Finally, we lower `select` from a condition value `c`. These rules are meant
2101
+ ;; to be the final, default lowerings if no other patterns matched above.
2102
+
2103
+ (rule -1 (lower (has_type ty (select c @ (value_type (fits_in_64 a_ty)) x y)))
2104
+ (let ((size OperandSize (raw_operand_size_of_type a_ty))
2105
+ ;; N.B.: disallow load-op fusion, see above. TODO:
2106
+ ;; https://github.com/bytecodealliance/wasmtime/issues/3953.
2107
+ (gpr_c Gpr (put_in_gpr c)))
2108
+ (with_flags (x64_test size gpr_c gpr_c) (cmove_from_values ty (CC.NZ) x y))))
2109
+
2110
+ (rule -2 (lower (has_type ty (select c @ (value_type $I128) x y)))
2111
+ (let ((cond_result IcmpCondResult (cmp_zero_i128 (CC.Z) c)))
2112
+ (select_icmp cond_result x y)))
2113
+
2114
+ (decl lower_select_icmp (Type IcmpCondResult Value Value) InstOutput)
2115
+ (rule (lower_select_icmp ty (IcmpCondResult.Condition flags cc) x y)
2116
+ (with_flags flags (cmove_from_values ty cc x y)))
2117
+
2118
+ ;; Specializations for floating-point compares to generate a `mins*` or a
2119
+ ;; `maxs*` instruction. These are equivalent to the "pseudo-m{in,ax}"
2120
+ ;; specializations for vectors.
2121
+ (rule 2 (lower (has_type $F32 (select (maybe_uextend (fcmp (FloatCC.LessThan) x y)) x y)))
2122
+ (x64_minss x y))
2123
+ (rule 2 (lower (has_type $F64 (select (maybe_uextend (fcmp (FloatCC.LessThan) x y)) x y)))
2124
+ (x64_minsd x y))
2125
+ (rule 3 (lower (has_type $F32 (select (maybe_uextend (fcmp (FloatCC.LessThan) y x)) x y)))
2126
+ (x64_maxss x y))
2127
+ (rule 3 (lower (has_type $F64 (select (maybe_uextend (fcmp (FloatCC.LessThan) y x)) x y)))
2128
+ (x64_maxsd x y))
2129
+
2130
+ ;; Rules for `clz` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2131
+
2132
+ ;; If available, we can use a plain lzcnt instruction here. Note no
2133
+ ;; special handling is required for zero inputs, because the machine
2134
+ ;; instruction does what the CLIF expects for zero, i.e. it returns
2135
+ ;; zero.
2136
+ (rule 3 (lower (has_type (ty_32_or_64 ty) (clz src)))
2137
+ (if-let $true (use_lzcnt))
2138
+ (x64_lzcnt ty src))
2139
+
2140
+ (rule 2 (lower (has_type (ty_32_or_64 ty) (clz src)))
2141
+ (do_clz ty ty src))
2142
+
2143
+ (rule 1 (lower
2144
+ (has_type (ty_8_or_16 ty)
2145
+ (clz src)))
2146
+ (do_clz $I32 ty (extend_to_gpr src $I32 (ExtendKind.Zero))))
2147
+
2148
+ (rule 0 (lower
2149
+ (has_type $I128
2150
+ (clz src)))
2151
+ (let ((upper Gpr (do_clz $I64 $I64 (value_regs_get_gpr src 1)))
2152
+ (lower Gpr (x64_add $I64
2153
+ (do_clz $I64 $I64 (value_regs_get_gpr src 0))
2154
+ (RegMemImm.Imm 64)))
2155
+ (result_lo Gpr
2156
+ (with_flags_reg
2157
+ (x64_cmp_imm (OperandSize.Size64) upper 64)
2158
+ (cmove $I64 (CC.NZ) upper lower))))
2159
+ (value_regs result_lo (imm $I64 0))))
2160
+
2161
+ ;; Implementation helper for clz; operates on 32 or 64-bit units.
2162
+ (decl do_clz (Type Type Gpr) Gpr)
2163
+ (rule (do_clz ty orig_ty src)
2164
+ (let ((highest_bit_index Reg (bsr_or_else ty src (imm_i64 $I64 -1)))
2165
+ (bits_minus_1 Reg (imm ty (u64_sub (ty_bits_u64 orig_ty) 1))))
2166
+ (x64_sub ty bits_minus_1 highest_bit_index)))
2167
+
2168
+ ;; Rules for `ctz` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2169
+
2170
+ ;; Analogous to `clz` cases above, but using mirror instructions
2171
+ ;; (tzcnt vs lzcnt, bsf vs bsr).
2172
+
2173
+ (rule 3 (lower (has_type (ty_32_or_64 ty) (ctz src)))
2174
+ (if-let $true (use_bmi1))
2175
+ (x64_tzcnt ty src))
2176
+
2177
+ (rule 2 (lower (has_type (ty_32_or_64 ty) (ctz src)))
2178
+ (do_ctz ty ty src))
2179
+
2180
+ (rule 1 (lower
2181
+ (has_type (ty_8_or_16 ty)
2182
+ (ctz src)))
2183
+ (do_ctz $I32 ty (extend_to_gpr src $I32 (ExtendKind.Zero))))
2184
+
2185
+ (rule 0 (lower
2186
+ (has_type $I128
2187
+ (ctz src)))
2188
+ (let ((lower Gpr (do_ctz $I64 $I64 (value_regs_get_gpr src 0)))
2189
+ (upper Gpr (x64_add $I64
2190
+ (do_ctz $I64 $I64 (value_regs_get_gpr src 1))
2191
+ (RegMemImm.Imm 64)))
2192
+ (result_lo Gpr
2193
+ (with_flags_reg
2194
+ (x64_cmp_imm (OperandSize.Size64) lower 64)
2195
+ (cmove $I64 (CC.Z) upper lower))))
2196
+ (value_regs result_lo (imm $I64 0))))
2197
+
2198
+ (decl do_ctz (Type Type Gpr) Gpr)
2199
+ (rule (do_ctz ty orig_ty src)
2200
+ (bsf_or_else ty src (imm $I64 (ty_bits_u64 orig_ty))))
2201
+
2202
+ ;; Rules for `popcnt` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2203
+
2204
+ (rule 4 (lower (has_type (ty_32_or_64 ty) (popcnt src)))
2205
+ (if-let $true (use_popcnt))
2206
+ (x64_popcnt ty src))
2207
+
2208
+ (rule 3 (lower (has_type (ty_8_or_16 ty) (popcnt src)))
2209
+ (if-let $true (use_popcnt))
2210
+ (x64_popcnt $I32 (extend_to_gpr src $I32 (ExtendKind.Zero))))
2211
+
2212
+ (rule 1 (lower (has_type $I128 (popcnt src)))
2213
+ (if-let $true (use_popcnt))
2214
+ (let ((lo_count Gpr (x64_popcnt $I64 (value_regs_get_gpr src 0)))
2215
+ (hi_count Gpr (x64_popcnt $I64 (value_regs_get_gpr src 1))))
2216
+ (value_regs (x64_add $I64 lo_count hi_count) (imm $I64 0))))
2217
+
2218
+ (rule -1 (lower
2219
+ (has_type (ty_32_or_64 ty)
2220
+ (popcnt src)))
2221
+ (do_popcnt ty src))
2222
+
2223
+ (rule -2 (lower
2224
+ (has_type (ty_8_or_16 ty)
2225
+ (popcnt src)))
2226
+ (do_popcnt $I32 (extend_to_gpr src $I32 (ExtendKind.Zero))))
2227
+
2228
+ (rule (lower
2229
+ (has_type $I128
2230
+ (popcnt src)))
2231
+ (let ((lo_count Gpr (do_popcnt $I64 (value_regs_get_gpr src 0)))
2232
+ (hi_count Gpr (do_popcnt $I64 (value_regs_get_gpr src 1))))
2233
+ (value_regs (x64_add $I64 lo_count hi_count) (imm $I64 0))))
2234
+
2235
+ ;; Implementation of popcount when we don't nave a native popcount
2236
+ ;; instruction.
2237
+ (decl do_popcnt (Type Gpr) Gpr)
2238
+ (rule (do_popcnt $I64 src)
2239
+ (let ((shifted1 Gpr (x64_shr $I64 src (Imm8Reg.Imm8 1)))
2240
+ (sevens Gpr (imm $I64 0x7777777777777777))
2241
+ (masked1 Gpr (x64_and $I64 shifted1 sevens))
2242
+ ;; diff1 := src - ((src >> 1) & 0b0111_0111_0111...)
2243
+ (diff1 Gpr (x64_sub $I64 src masked1))
2244
+ (shifted2 Gpr (x64_shr $I64 masked1 (Imm8Reg.Imm8 1)))
2245
+ (masked2 Gpr (x64_and $I64 shifted2 sevens))
2246
+ ;; diff2 := diff1 - ((diff1 >> 1) & 0b0111_0111_0111...)
2247
+ (diff2 Gpr (x64_sub $I64 diff1 masked2))
2248
+ (shifted3 Gpr (x64_shr $I64 masked2 (Imm8Reg.Imm8 1)))
2249
+ (masked3 Gpr (x64_and $I64 shifted3 sevens))
2250
+ ;; diff3 := diff2 - ((diff2 >> 1) & 0b0111_0111_0111...)
2251
+ ;;
2252
+ ;; At this point, each nibble of diff3 is the popcount of
2253
+ ;; that nibble. This works because at each step above, we
2254
+ ;; are basically subtracting floor(value / 2) from the
2255
+ ;; running value; the leftover remainder is 1 if the LSB
2256
+ ;; was 1. After three steps, we have (nibble / 8) -- 0 or
2257
+ ;; 1 for the MSB of the nibble -- plus three possible
2258
+ ;; additions for the three other bits.
2259
+ (diff3 Gpr (x64_sub $I64 diff2 masked3))
2260
+ ;; Add the two nibbles of each byte together.
2261
+ (sum1 Gpr (x64_add $I64
2262
+ (x64_shr $I64 diff3 (Imm8Reg.Imm8 4))
2263
+ diff3))
2264
+ ;; Mask the above sum to have the popcount for each byte
2265
+ ;; in the lower nibble of that byte.
2266
+ (ofof Gpr (imm $I64 0x0f0f0f0f0f0f0f0f))
2267
+ (masked4 Gpr (x64_and $I64 sum1 ofof))
2268
+ (ones Gpr (imm $I64 0x0101010101010101))
2269
+ ;; Use a multiply to sum all of the bytes' popcounts into
2270
+ ;; the top byte. Consider the binomial expansion for the
2271
+ ;; top byte: it is the sum of the bytes (masked4 >> 56) *
2272
+ ;; 0x01 + (masked4 >> 48) * 0x01 + (masked4 >> 40) * 0x01
2273
+ ;; + ... + (masked4 >> 0).
2274
+ (mul Gpr (x64_imul $I64 masked4 ones))
2275
+ ;; Now take that top byte and return it as the popcount.
2276
+ (final Gpr (x64_shr $I64 mul (Imm8Reg.Imm8 56))))
2277
+ final))
2278
+
2279
+ ;; This is the 32-bit version of the above; the steps for each nibble
2280
+ ;; are the same, we just use constants half as wide.
2281
+ (rule (do_popcnt $I32 src)
2282
+ (let ((shifted1 Gpr (x64_shr $I32 src (Imm8Reg.Imm8 1)))
2283
+ (sevens Gpr (imm $I32 0x77777777))
2284
+ (masked1 Gpr (x64_and $I32 shifted1 sevens))
2285
+ (diff1 Gpr (x64_sub $I32 src masked1))
2286
+ (shifted2 Gpr (x64_shr $I32 masked1 (Imm8Reg.Imm8 1)))
2287
+ (masked2 Gpr (x64_and $I32 shifted2 sevens))
2288
+ (diff2 Gpr (x64_sub $I32 diff1 masked2))
2289
+ (shifted3 Gpr (x64_shr $I32 masked2 (Imm8Reg.Imm8 1)))
2290
+ (masked3 Gpr (x64_and $I32 shifted3 sevens))
2291
+ (diff3 Gpr (x64_sub $I32 diff2 masked3))
2292
+ (sum1 Gpr (x64_add $I32
2293
+ (x64_shr $I32 diff3 (Imm8Reg.Imm8 4))
2294
+ diff3))
2295
+ (masked4 Gpr (x64_and $I32 sum1 (RegMemImm.Imm 0x0f0f0f0f)))
2296
+ (mul Gpr (x64_imul_imm $I32 masked4 0x01010101))
2297
+ (final Gpr (x64_shr $I32 mul (Imm8Reg.Imm8 24))))
2298
+ final))
2299
+
2300
+
2301
+ (rule 2 (lower (has_type $I8X16 (popcnt src)))
2302
+ (if-let $true (use_avx512vl))
2303
+ (if-let $true (use_avx512bitalg))
2304
+ (x64_vpopcntb src))
2305
+
2306
+
2307
+ ;; For SSE 4.2 we use Mula's algorithm (https://arxiv.org/pdf/1611.07612.pdf):
2308
+ ;;
2309
+ ;; __m128i count_bytes ( __m128i v) {
2310
+ ;; __m128i lookup = _mm_setr_epi8(0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4);
2311
+ ;; __m128i low_mask = _mm_set1_epi8 (0x0f);
2312
+ ;; __m128i lo = _mm_and_si128 (v, low_mask);
2313
+ ;; __m128i hi = _mm_and_si128 (_mm_srli_epi16 (v, 4), low_mask);
2314
+ ;; __m128i cnt1 = _mm_shuffle_epi8 (lookup, lo);
2315
+ ;; __m128i cnt2 = _mm_shuffle_epi8 (lookup, hi);
2316
+ ;; return _mm_add_epi8 (cnt1, cnt2);
2317
+ ;; }
2318
+ ;;
2319
+ ;; Details of the above algorithm can be found in the reference noted above, but the basics
2320
+ ;; are to create a lookup table that pre populates the popcnt values for each number [0,15].
2321
+ ;; The algorithm uses shifts to isolate 4 bit sections of the vector, pshufb as part of the
2322
+ ;; lookup process, and adds together the results.
2323
+ ;;
2324
+ ;; __m128i lookup = _mm_setr_epi8(0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4);
2325
+
2326
+
2327
+ (rule 1 (lower (has_type $I8X16 (popcnt src)))
2328
+ (if-let $true (use_ssse3))
2329
+ (let ((low_mask XmmMem (emit_u128_le_const 0x0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f))
2330
+ (low_nibbles Xmm (sse_and $I8X16 src low_mask))
2331
+ ;; Note that this is a 16x8 shift, but that's OK; we mask
2332
+ ;; off anything that traverses from one byte to the next
2333
+ ;; with the low_mask below.
2334
+ (shifted_src Xmm (x64_psrlw src (xmi_imm 4)))
2335
+ (high_nibbles Xmm (sse_and $I8X16 shifted_src low_mask))
2336
+ (lookup Xmm (x64_xmm_load_const $I8X16
2337
+ (emit_u128_le_const 0x04030302_03020201_03020201_02010100)))
2338
+ (bit_counts_low Xmm (x64_pshufb lookup low_nibbles))
2339
+ (bit_counts_high Xmm (x64_pshufb lookup high_nibbles)))
2340
+ (x64_paddb bit_counts_low bit_counts_high)))
2341
+
2342
+ ;; A modified version of the popcnt method from Hacker's Delight.
2343
+ (rule (lower (has_type $I8X16 (popcnt src)))
2344
+ (let ((mask1 XmmMem (emit_u128_le_const 0x77777777777777777777777777777777))
2345
+ (src Xmm src)
2346
+ (shifted Xmm (x64_pand (x64_psrlq src (xmi_imm 1)) mask1))
2347
+ (src Xmm (x64_psubb src shifted))
2348
+ (shifted Xmm (x64_pand (x64_psrlq shifted (xmi_imm 1)) mask1))
2349
+ (src Xmm (x64_psubb src shifted))
2350
+ (shifted Xmm (x64_pand (x64_psrlq shifted (xmi_imm 1)) mask1))
2351
+ (src Xmm (x64_psubb src shifted))
2352
+ (src Xmm (x64_paddb src (x64_psrlw src (xmi_imm 4)))))
2353
+ (x64_pand src (emit_u128_le_const 0x0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f))))
2354
+
2355
+ ;; Rules for `bitrev` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2356
+
2357
+ (rule (lower (has_type $I8 (bitrev src)))
2358
+ (do_bitrev8 $I32 src))
2359
+
2360
+ (rule (lower (has_type $I16 (bitrev src)))
2361
+ (do_bitrev16 $I32 src))
2362
+
2363
+ (rule (lower (has_type $I32 (bitrev src)))
2364
+ (do_bitrev32 $I32 src))
2365
+
2366
+ (rule (lower (has_type $I64 (bitrev src)))
2367
+ (do_bitrev64 $I64 src))
2368
+
2369
+ (rule (lower (has_type $I128 (bitrev src)))
2370
+ (value_regs
2371
+ (do_bitrev64 $I64 (value_regs_get_gpr src 1))
2372
+ (do_bitrev64 $I64 (value_regs_get_gpr src 0))))
2373
+
2374
+ (decl do_bitrev8 (Type Gpr) Gpr)
2375
+ (rule (do_bitrev8 ty src)
2376
+ (let ((tymask u64 (ty_mask ty))
2377
+ (mask1 Gpr (imm ty (u64_and tymask 0x5555555555555555)))
2378
+ (lo1 Gpr (x64_and ty src mask1))
2379
+ (hi1 Gpr (x64_and ty (x64_shr ty src (Imm8Reg.Imm8 1)) mask1))
2380
+ (swap1 Gpr (x64_or ty
2381
+ (x64_shl ty lo1 (Imm8Reg.Imm8 1))
2382
+ hi1))
2383
+ (mask2 Gpr (imm ty (u64_and tymask 0x3333333333333333)))
2384
+ (lo2 Gpr (x64_and ty swap1 mask2))
2385
+ (hi2 Gpr (x64_and ty (x64_shr ty swap1 (Imm8Reg.Imm8 2)) mask2))
2386
+ (swap2 Gpr (x64_or ty
2387
+ (x64_shl ty lo2 (Imm8Reg.Imm8 2))
2388
+ hi2))
2389
+ (mask4 Gpr (imm ty (u64_and tymask 0x0f0f0f0f0f0f0f0f)))
2390
+ (lo4 Gpr (x64_and ty swap2 mask4))
2391
+ (hi4 Gpr (x64_and ty (x64_shr ty swap2 (Imm8Reg.Imm8 4)) mask4))
2392
+ (swap4 Gpr (x64_or ty
2393
+ (x64_shl ty lo4 (Imm8Reg.Imm8 4))
2394
+ hi4)))
2395
+ swap4))
2396
+
2397
+ (decl do_bitrev16 (Type Gpr) Gpr)
2398
+ (rule (do_bitrev16 ty src)
2399
+ (let ((src_ Gpr (do_bitrev8 ty src))
2400
+ (tymask u64 (ty_mask ty))
2401
+ (mask8 Gpr (imm ty (u64_and tymask 0x00ff00ff00ff00ff)))
2402
+ (lo8 Gpr (x64_and ty src_ mask8))
2403
+ (hi8 Gpr (x64_and ty (x64_shr ty src_ (Imm8Reg.Imm8 8)) mask8))
2404
+ (swap8 Gpr (x64_or ty
2405
+ (x64_shl ty lo8 (Imm8Reg.Imm8 8))
2406
+ hi8)))
2407
+ swap8))
2408
+
2409
+ (decl do_bitrev32 (Type Gpr) Gpr)
2410
+ (rule (do_bitrev32 ty src)
2411
+ (let ((src_ Gpr (do_bitrev16 ty src))
2412
+ (tymask u64 (ty_mask ty))
2413
+ (mask16 Gpr (imm ty (u64_and tymask 0x0000ffff0000ffff)))
2414
+ (lo16 Gpr (x64_and ty src_ mask16))
2415
+ (hi16 Gpr (x64_and ty (x64_shr ty src_ (Imm8Reg.Imm8 16)) mask16))
2416
+ (swap16 Gpr (x64_or ty
2417
+ (x64_shl ty lo16 (Imm8Reg.Imm8 16))
2418
+ hi16)))
2419
+ swap16))
2420
+
2421
+ (decl do_bitrev64 (Type Gpr) Gpr)
2422
+ (rule (do_bitrev64 ty @ $I64 src)
2423
+ (let ((src_ Gpr (do_bitrev32 ty src))
2424
+ (mask32 Gpr (imm ty 0xffffffff))
2425
+ (lo32 Gpr (x64_and ty src_ mask32))
2426
+ (hi32 Gpr (x64_shr ty src_ (Imm8Reg.Imm8 32)))
2427
+ (swap32 Gpr (x64_or ty
2428
+ (x64_shl ty lo32 (Imm8Reg.Imm8 32))
2429
+ hi32)))
2430
+ swap32))
2431
+
2432
+ ;; Rules for `bswap` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2433
+
2434
+ ;; x64 bswap instruction is only for 32- or 64-bit swaps
2435
+ ;; implement the 16-bit swap as a rotl by 8
2436
+ (rule (lower (has_type $I16 (bswap src)))
2437
+ (x64_rotl $I16 src (Imm8Reg.Imm8 8)))
2438
+
2439
+ (rule (lower (has_type $I32 (bswap src)))
2440
+ (x64_bswap $I32 src))
2441
+
2442
+ (rule (lower (has_type $I64 (bswap src)))
2443
+ (x64_bswap $I64 src))
2444
+
2445
+ (rule (lower (has_type $I128 (bswap src)))
2446
+ (value_regs
2447
+ (x64_bswap $I64 (value_regs_get_gpr src 1))
2448
+ (x64_bswap $I64 (value_regs_get_gpr src 0))))
2449
+
2450
+ ;; Rules for `is_null` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2451
+
2452
+ ;; Null references are represented by the constant value `0`.
2453
+ (rule (lower (is_null src @ (value_type $R64)))
2454
+ (with_flags
2455
+ (x64_cmp_imm (OperandSize.Size64) src 0)
2456
+ (x64_setcc (CC.Z))))
2457
+
2458
+ ;; Rules for `is_invalid` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2459
+
2460
+ ;; Invalid references are represented by the constant value `-1`.
2461
+ (rule (lower (is_invalid src @ (value_type $R64)))
2462
+ (with_flags
2463
+ (x64_cmp_imm (OperandSize.Size64) src 0xffffffff) ;; simm32 0xffff_ffff is sign-extended to -1.
2464
+ (x64_setcc (CC.Z))))
2465
+
2466
+
2467
+ ;; Rules for `uextend` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2468
+
2469
+ ;; I{8,16,32,64} -> I128.
2470
+ (rule (lower (has_type $I128 (uextend src)))
2471
+ (value_regs (extend_to_gpr src $I64 (ExtendKind.Zero)) (imm $I64 0)))
2472
+
2473
+ ;; I{8,16,32} -> I64.
2474
+ (rule (lower (has_type $I64 (uextend src)))
2475
+ (extend_to_gpr src $I64 (ExtendKind.Zero)))
2476
+
2477
+ ;; I{8,16} -> I32
2478
+ ;; I8 -> I16
2479
+ (rule -1 (lower (has_type (fits_in_32 _) (uextend src)))
2480
+ (extend_to_gpr src $I32 (ExtendKind.Zero)))
2481
+
2482
+ ;; Rules for `sextend` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2483
+
2484
+ ;; I{8,16,32} -> I128.
2485
+ ;;
2486
+ ;; Produce upper 64 bits sign-extended from lower 64: shift right by
2487
+ ;; 63 bits to spread the sign bit across the result.
2488
+ (rule (lower (has_type $I128 (sextend src)))
2489
+ (let ((lo Gpr (extend_to_gpr src $I64 (ExtendKind.Sign)))
2490
+ (hi Gpr (x64_sar $I64 lo (Imm8Reg.Imm8 63))))
2491
+ (value_regs lo hi)))
2492
+
2493
+ ;; I{8,16,32} -> I64.
2494
+ (rule (lower (has_type $I64 (sextend src)))
2495
+ (extend_to_gpr src $I64 (ExtendKind.Sign)))
2496
+
2497
+ ;; I{8,16} -> I32
2498
+ ;; I8 -> I16
2499
+ (rule -1 (lower (has_type (fits_in_32 _) (sextend src)))
2500
+ (extend_to_gpr src $I32 (ExtendKind.Sign)))
2501
+
2502
+ ;; Rules for `ireduce` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2503
+
2504
+ ;; T -> T is always a no-op, even I128 -> I128.
2505
+ (rule (lower (has_type ty (ireduce src @ (value_type ty))))
2506
+ src)
2507
+
2508
+ ;; T -> I{64,32,16,8}: We can simply pass through the value: values
2509
+ ;; are always stored with high bits undefined, so we can just leave
2510
+ ;; them be.
2511
+ (rule 1 (lower (has_type (fits_in_64 ty) (ireduce src)))
2512
+ (value_regs_get_gpr src 0))
2513
+
2514
+ ;; Rules for `debugtrap` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2515
+
2516
+ (rule (lower (debugtrap))
2517
+ (side_effect (x64_hlt)))
2518
+
2519
+ ;; Rules for `x86_pmaddubsw` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2520
+
2521
+ (rule (lower (has_type $I16X8 (x86_pmaddubsw x y)))
2522
+ (if-let $true (use_ssse3))
2523
+ (x64_pmaddubsw y x))
2524
+
2525
+ ;; Rules for `fadd` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2526
+
2527
+ (rule (lower (has_type $F32 (fadd x y)))
2528
+ (x64_addss x y))
2529
+ (rule (lower (has_type $F64 (fadd x y)))
2530
+ (x64_addsd x y))
2531
+ (rule (lower (has_type $F32X4 (fadd x y)))
2532
+ (x64_addps x y))
2533
+ (rule (lower (has_type $F64X2 (fadd x y)))
2534
+ (x64_addpd x y))
2535
+
2536
+ ;; The above rules automatically sink loads for rhs operands, so additionally
2537
+ ;; add rules for sinking loads with lhs operands.
2538
+ (rule 1 (lower (has_type $F32 (fadd (sinkable_load x) y)))
2539
+ (x64_addss y x))
2540
+ (rule 1 (lower (has_type $F64 (fadd (sinkable_load x) y)))
2541
+ (x64_addsd y x))
2542
+ (rule 1 (lower (has_type $F32X4 (fadd (sinkable_load x) y)))
2543
+ (x64_addps y x))
2544
+ (rule 1 (lower (has_type $F64X2 (fadd (sinkable_load x) y)))
2545
+ (x64_addpd y x))
2546
+
2547
+ ;; Rules for `fsub` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2548
+
2549
+ (rule (lower (has_type $F32 (fsub x y)))
2550
+ (x64_subss x y))
2551
+ (rule (lower (has_type $F64 (fsub x y)))
2552
+ (x64_subsd x y))
2553
+ (rule (lower (has_type $F32X4 (fsub x y)))
2554
+ (x64_subps x y))
2555
+ (rule (lower (has_type $F64X2 (fsub x y)))
2556
+ (x64_subpd x y))
2557
+
2558
+ ;; Rules for `fmul` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2559
+
2560
+ (rule (lower (has_type $F32 (fmul x y)))
2561
+ (x64_mulss x y))
2562
+ (rule (lower (has_type $F64 (fmul x y)))
2563
+ (x64_mulsd x y))
2564
+ (rule (lower (has_type $F32X4 (fmul x y)))
2565
+ (x64_mulps x y))
2566
+ (rule (lower (has_type $F64X2 (fmul x y)))
2567
+ (x64_mulpd x y))
2568
+
2569
+ ;; The above rules automatically sink loads for rhs operands, so additionally
2570
+ ;; add rules for sinking loads with lhs operands.
2571
+ (rule 1 (lower (has_type $F32 (fmul (sinkable_load x) y)))
2572
+ (x64_mulss y x))
2573
+ (rule 1 (lower (has_type $F64 (fmul (sinkable_load x) y)))
2574
+ (x64_mulsd y x))
2575
+ (rule 1 (lower (has_type $F32X4 (fmul (sinkable_load x) y)))
2576
+ (x64_mulps y x))
2577
+ (rule 1 (lower (has_type $F64X2 (fmul (sinkable_load x) y)))
2578
+ (x64_mulpd y x))
2579
+
2580
+ ;; Rules for `fdiv` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2581
+
2582
+ (rule (lower (has_type $F32 (fdiv x y)))
2583
+ (x64_divss x y))
2584
+ (rule (lower (has_type $F64 (fdiv x y)))
2585
+ (x64_divsd x y))
2586
+ (rule (lower (has_type $F32X4 (fdiv x y)))
2587
+ (x64_divps x y))
2588
+ (rule (lower (has_type $F64X2 (fdiv x y)))
2589
+ (x64_divpd x y))
2590
+
2591
+ ;; Rules for `sqrt` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2592
+ (rule (lower (has_type $F32 (sqrt x)))
2593
+ (x64_sqrtss (xmm_zero $F32X4) x))
2594
+ (rule (lower (has_type $F64 (sqrt x)))
2595
+ (x64_sqrtsd (xmm_zero $F64X2) x))
2596
+ (rule (lower (has_type $F32X4 (sqrt x)))
2597
+ (x64_sqrtps x))
2598
+ (rule (lower (has_type $F64X2 (sqrt x)))
2599
+ (x64_sqrtpd x))
2600
+
2601
+ ;; Rules for `fpromote` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2602
+ (rule (lower (has_type $F64 (fpromote x)))
2603
+ (x64_cvtss2sd (xmm_zero $F64X2) x))
2604
+
2605
+ ;; Rules for `fvpromote` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2606
+ (rule (lower (has_type $F64X2 (fvpromote_low x)))
2607
+ (x64_cvtps2pd (put_in_xmm x)))
2608
+
2609
+ ;; Rules for `fdemote` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2610
+ (rule (lower (has_type $F32 (fdemote x)))
2611
+ (x64_cvtsd2ss (xmm_zero $F32X4) x))
2612
+
2613
+ ;; Rules for `fvdemote` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2614
+ (rule (lower (has_type $F32X4 (fvdemote x)))
2615
+ (x64_cvtpd2ps x))
2616
+
2617
+ ;; Rules for `fmin` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2618
+
2619
+ (rule (lower (has_type $F32 (fmin x y)))
2620
+ (xmm_min_max_seq $F32 $true x y))
2621
+ (rule (lower (has_type $F64 (fmin x y)))
2622
+ (xmm_min_max_seq $F64 $true x y))
2623
+
2624
+ ;; Vector-typed version. We don't use single pseudoinstructions as
2625
+ ;; above, because we don't need to generate a mini-CFG. Instead, we
2626
+ ;; perform a branchless series of operations.
2627
+ ;;
2628
+ ;; We cannot simply use native min instructions (minps, minpd) because
2629
+ ;; NaN handling is different per CLIF semantics than on
2630
+ ;; x86. Specifically, if an argument is NaN, or the arguments are both
2631
+ ;; zero but of opposite signs, then the x86 instruction always
2632
+ ;; produces the second argument. However, per CLIF semantics, we
2633
+ ;; require that fmin(NaN, _) = fmin(_, NaN) = NaN, and fmin(+0, -0) =
2634
+ ;; fmin(-0, +0) = -0.
2635
+
2636
+ (rule (lower (has_type $F32X4 (fmin x y)))
2637
+ ;; Compute min(x, y) and min(y, x) with native
2638
+ ;; instructions. These will differ in one of the edge cases
2639
+ ;; above that we have to handle properly. (Conversely, if they
2640
+ ;; don't differ, then the native instruction's answer is the
2641
+ ;; right one per CLIF semantics.)
2642
+ (let ((min1 Xmm (x64_minps x y))
2643
+ (min2 Xmm (x64_minps y x))
2644
+ ;; Compute the OR of the two. Note that NaNs have an
2645
+ ;; exponent field of all-ones (0xFF for F32), so if either
2646
+ ;; result is a NaN, this OR will be. And if either is a
2647
+ ;; zero (which has an exponent of 0 and mantissa of 0),
2648
+ ;; this captures a sign-bit of 1 (negative) if either
2649
+ ;; input is negative.
2650
+ ;;
2651
+ ;; In the case where we don't have a +/-0 mismatch or
2652
+ ;; NaNs, then `min1` and `min2` are equal and `min_or` is
2653
+ ;; the correct minimum.
2654
+ (min_or Xmm (x64_orps min1 min2))
2655
+ ;; "compare unordered" produces a true mask (all ones) in
2656
+ ;; a given lane if the min is a NaN. We use this to
2657
+ ;; generate a mask to ensure quiet NaNs.
2658
+ (is_nan_mask Xmm (x64_cmpps min_or min2 (FcmpImm.Unordered)))
2659
+ ;; OR in the NaN mask.
2660
+ (min_or_2 Xmm (x64_orps min_or is_nan_mask))
2661
+ ;; Shift the NaN mask down so that it covers just the
2662
+ ;; fraction below the NaN signalling bit; we'll use this
2663
+ ;; to mask off non-canonical NaN payloads.
2664
+ ;;
2665
+ ;; All-ones for NaN, shifted down to leave 10 top bits (1
2666
+ ;; sign, 8 exponent, 1 QNaN bit that must remain set)
2667
+ ;; cleared.
2668
+ (nan_fraction_mask Xmm (x64_psrld is_nan_mask (xmi_imm 10)))
2669
+ ;; Do a NAND, so that we retain every bit not set in
2670
+ ;; `nan_fraction_mask`. This mask will be all zeroes (so
2671
+ ;; we retain every bit) in non-NaN cases, and will have
2672
+ ;; ones (so we clear those bits) in NaN-payload bits
2673
+ ;; otherwise.
2674
+ (final Xmm (x64_andnps nan_fraction_mask min_or_2)))
2675
+ final))
2676
+
2677
+ ;; Likewise for F64 lanes, except that the right-shift is by 13 bits
2678
+ ;; (1 sign, 11 exponent, 1 QNaN bit).
2679
+ (rule (lower (has_type $F64X2 (fmin x y)))
2680
+ (let ((min1 Xmm (x64_minpd x y))
2681
+ (min2 Xmm (x64_minpd y x))
2682
+ (min_or Xmm (x64_orpd min1 min2))
2683
+ (is_nan_mask Xmm (x64_cmppd min1 min2 (FcmpImm.Unordered)))
2684
+ (min_or_2 Xmm (x64_orpd min_or is_nan_mask))
2685
+ (nan_fraction_mask Xmm (x64_psrlq is_nan_mask (xmi_imm 13)))
2686
+ (final Xmm (x64_andnpd nan_fraction_mask min_or_2)))
2687
+ final))
2688
+
2689
+ ;; Rules for `fmax` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2690
+
2691
+ (rule (lower (has_type $F32 (fmax x y)))
2692
+ (xmm_min_max_seq $F32 $false x y))
2693
+ (rule (lower (has_type $F64 (fmax x y)))
2694
+ (xmm_min_max_seq $F64 $false x y))
2695
+
2696
+ ;; The vector version of fmax here is a dual to the fmin sequence
2697
+ ;; above, almost, with a few differences.
2698
+
2699
+ (rule (lower (has_type $F32X4 (fmax x y)))
2700
+ ;; Compute max(x, y) and max(y, x) with native
2701
+ ;; instructions. These will differ in one of the edge cases
2702
+ ;; above that we have to handle properly. (Conversely, if they
2703
+ ;; don't differ, then the native instruction's answer is the
2704
+ ;; right one per CLIF semantics.)
2705
+ (let ((max1 Xmm (x64_maxps x y))
2706
+ (max2 Xmm (x64_maxps y x))
2707
+ ;; Compute the XOR of the two maxima. In the case
2708
+ ;; where we don't have a +/-0 mismatch or NaNs, then
2709
+ ;; `min1` and `min2` are equal and this XOR is zero.
2710
+ (max_xor Xmm (x64_xorps max1 max2))
2711
+ ;; OR the XOR into one of the original maxima. If they are
2712
+ ;; equal, this does nothing. If max2 was NaN, its exponent
2713
+ ;; bits were all-ones, so the xor's exponent bits were the
2714
+ ;; complement of max1, and the OR of max1 and max_xor has
2715
+ ;; an all-ones exponent (is a NaN). If max1 was NaN, then
2716
+ ;; its exponent bits were already all-ones, so the OR will
2717
+ ;; be a NaN as well.
2718
+ (max_blended_nan Xmm (x64_orps max1 max_xor))
2719
+ ;; Subtract the XOR. This ensures that if we had +0 and
2720
+ ;; -0, we end up with +0.
2721
+ (max_blended_nan_positive Xmm (x64_subps max_blended_nan max_xor))
2722
+ ;; "compare unordered" produces a true mask (all ones) in
2723
+ ;; a given lane if the min is a NaN. We use this to
2724
+ ;; generate a mask to ensure quiet NaNs.
2725
+ (is_nan_mask Xmm (x64_cmpps max_blended_nan max_blended_nan (FcmpImm.Unordered)))
2726
+ ;; Shift the NaN mask down so that it covers just the
2727
+ ;; fraction below the NaN signalling bit; we'll use this
2728
+ ;; to mask off non-canonical NaN payloads.
2729
+ ;;
2730
+ ;; All-ones for NaN, shifted down to leave 10 top bits (1
2731
+ ;; sign, 8 exponent, 1 QNaN bit that must remain set)
2732
+ ;; cleared.
2733
+ (nan_fraction_mask Xmm (x64_psrld is_nan_mask (xmi_imm 10)))
2734
+ ;; Do a NAND, so that we retain every bit not set in
2735
+ ;; `nan_fraction_mask`. This mask will be all zeroes (so
2736
+ ;; we retain every bit) in non-NaN cases, and will have
2737
+ ;; ones (so we clear those bits) in NaN-payload bits
2738
+ ;; otherwise.
2739
+ (final Xmm (x64_andnps nan_fraction_mask max_blended_nan_positive)))
2740
+ final))
2741
+
2742
+ (rule (lower (has_type $F64X2 (fmax x y)))
2743
+ ;; Compute max(x, y) and max(y, x) with native
2744
+ ;; instructions. These will differ in one of the edge cases
2745
+ ;; above that we have to handle properly. (Conversely, if they
2746
+ ;; don't differ, then the native instruction's answer is the
2747
+ ;; right one per CLIF semantics.)
2748
+ (let ((max1 Xmm (x64_maxpd x y))
2749
+ (max2 Xmm (x64_maxpd y x))
2750
+ ;; Compute the XOR of the two maxima. In the case
2751
+ ;; where we don't have a +/-0 mismatch or NaNs, then
2752
+ ;; `min1` and `min2` are equal and this XOR is zero.
2753
+ (max_xor Xmm (x64_xorpd max1 max2))
2754
+ ;; OR the XOR into one of the original maxima. If they are
2755
+ ;; equal, this does nothing. If max2 was NaN, its exponent
2756
+ ;; bits were all-ones, so the xor's exponent bits were the
2757
+ ;; complement of max1, and the OR of max1 and max_xor has
2758
+ ;; an all-ones exponent (is a NaN). If max1 was NaN, then
2759
+ ;; its exponent bits were already all-ones, so the OR will
2760
+ ;; be a NaN as well.
2761
+ (max_blended_nan Xmm (x64_orpd max1 max_xor))
2762
+ ;; Subtract the XOR. This ensures that if we had +0 and
2763
+ ;; -0, we end up with +0.
2764
+ (max_blended_nan_positive Xmm (x64_subpd max_blended_nan max_xor))
2765
+ ;; `cmpps` with predicate index `3` is `cmpunordps`, or
2766
+ ;; "compare unordered": it produces a true mask (all ones)
2767
+ ;; in a given lane if the min is a NaN. We use this to
2768
+ ;; generate a mask to ensure quiet NaNs.
2769
+ (is_nan_mask Xmm (x64_cmppd max_blended_nan max_blended_nan (FcmpImm.Unordered)))
2770
+ ;; Shift the NaN mask down so that it covers just the
2771
+ ;; fraction below the NaN signalling bit; we'll use this
2772
+ ;; to mask off non-canonical NaN payloads.
2773
+ ;;
2774
+ ;; All-ones for NaN, shifted down to leave 13 top bits (1
2775
+ ;; sign, 11 exponent, 1 QNaN bit that must remain set)
2776
+ ;; cleared.
2777
+ (nan_fraction_mask Xmm (x64_psrlq is_nan_mask (xmi_imm 13)))
2778
+ ;; Do a NAND, so that we retain every bit not set in
2779
+ ;; `nan_fraction_mask`. This mask will be all zeroes (so
2780
+ ;; we retain every bit) in non-NaN cases, and will have
2781
+ ;; ones (so we clear those bits) in NaN-payload bits
2782
+ ;; otherwise.
2783
+ (final Xmm (x64_andnpd nan_fraction_mask max_blended_nan_positive)))
2784
+ final))
2785
+
2786
+ ;; Rules for `fma` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2787
+
2788
+ ;; Base case for fma is to call out to one of two libcalls. For vectors they
2789
+ ;; need to be decomposed, handle each element individually, and then recomposed.
2790
+
2791
+ (rule (lower (has_type $F32 (fma x y z)))
2792
+ (libcall_3 (LibCall.FmaF32) x y z))
2793
+ (rule (lower (has_type $F64 (fma x y z)))
2794
+ (libcall_3 (LibCall.FmaF64) x y z))
2795
+
2796
+ (rule (lower (has_type $F32X4 (fma x y z)))
2797
+ (let (
2798
+ (x Xmm (put_in_xmm x))
2799
+ (y Xmm (put_in_xmm y))
2800
+ (z Xmm (put_in_xmm z))
2801
+ (x0 Xmm (libcall_3 (LibCall.FmaF32) x y z))
2802
+ (x1 Xmm (libcall_3 (LibCall.FmaF32)
2803
+ (x64_pshufd x 1)
2804
+ (x64_pshufd y 1)
2805
+ (x64_pshufd z 1)))
2806
+ (x2 Xmm (libcall_3 (LibCall.FmaF32)
2807
+ (x64_pshufd x 2)
2808
+ (x64_pshufd y 2)
2809
+ (x64_pshufd z 2)))
2810
+ (x3 Xmm (libcall_3 (LibCall.FmaF32)
2811
+ (x64_pshufd x 3)
2812
+ (x64_pshufd y 3)
2813
+ (x64_pshufd z 3)))
2814
+
2815
+ (tmp Xmm (f32x4_insertlane x0 x1 1))
2816
+ (tmp Xmm (f32x4_insertlane tmp x2 2))
2817
+ (tmp Xmm (f32x4_insertlane tmp x3 3))
2818
+ )
2819
+ tmp))
2820
+ (rule (lower (has_type $F64X2 (fma x y z)))
2821
+ (let (
2822
+ (x Xmm (put_in_xmm x))
2823
+ (y Xmm (put_in_xmm y))
2824
+ (z Xmm (put_in_xmm z))
2825
+ (x0 Xmm (libcall_3 (LibCall.FmaF64) x y z))
2826
+ (x1 Xmm (libcall_3 (LibCall.FmaF64)
2827
+ (x64_pshufd x 0xee)
2828
+ (x64_pshufd y 0xee)
2829
+ (x64_pshufd z 0xee)))
2830
+ )
2831
+ (x64_movlhps x0 x1)))
2832
+
2833
+
2834
+ ;; Special case for when the `fma` feature is active and a native instruction
2835
+ ;; can be used.
2836
+ (rule 1 (lower (has_type ty (fma x y z)))
2837
+ (if-let $true (use_fma))
2838
+ (fmadd ty x y z))
2839
+
2840
+ (decl fmadd (Type Value Value Value) Xmm)
2841
+ (decl fnmadd (Type Value Value Value) Xmm)
2842
+
2843
+ ;; Base case. Note that this will automatically sink a load with `z`, the value
2844
+ ;; to add.
2845
+ (rule (fmadd ty x y z) (x64_vfmadd213 ty x y z))
2846
+
2847
+ ;; Allow sinking loads with one of the two values being multiplied in addition
2848
+ ;; to the value being added. Note that both x and y can be sunk here due to
2849
+ ;; multiplication being commutative.
2850
+ (rule 1 (fmadd ty (sinkable_load x) y z) (x64_vfmadd132 ty y z x))
2851
+ (rule 2 (fmadd ty x (sinkable_load y) z) (x64_vfmadd132 ty x z y))
2852
+
2853
+ ;; If one of the values being multiplied is negated then use a `vfnmadd*`
2854
+ ;; instruction instead
2855
+ (rule 3 (fmadd ty (fneg x) y z) (fnmadd ty x y z))
2856
+ (rule 4 (fmadd ty x (fneg y) z) (fnmadd ty x y z))
2857
+
2858
+ (rule (fnmadd ty x y z) (x64_vfnmadd213 ty x y z))
2859
+ (rule 1 (fnmadd ty (sinkable_load x) y z) (x64_vfnmadd132 ty y z x))
2860
+ (rule 2 (fnmadd ty x (sinkable_load y) z) (x64_vfnmadd132 ty x z y))
2861
+
2862
+ ;; Like `fmadd` if one argument is negated switch which one is being codegen'd
2863
+ (rule 3 (fnmadd ty (fneg x) y z) (fmadd ty x y z))
2864
+ (rule 4 (fnmadd ty x (fneg y) z) (fmadd ty x y z))
2865
+
2866
+ ;; Rules for `load*` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2867
+
2868
+ ;; In order to load a value from memory to a GPR register, we may need to extend
2869
+ ;; the loaded value from 8-, 16-, or 32-bits to this backend's expected GPR
2870
+ ;; width: 64 bits. Note that `ext_mode` will load 1-bit types (booleans) as
2871
+ ;; 8-bit loads.
2872
+ ;;
2873
+ ;; By default, we zero-extend all sub-64-bit loads to a GPR.
2874
+ (rule -4 (lower (has_type (and (fits_in_32 ty) (is_gpr_type _)) (load flags address offset)))
2875
+ (x64_movzx (ext_mode (ty_bits_u16 ty) 64) (to_amode flags address offset)))
2876
+ ;; But if we know that both the `from` and `to` are 64 bits, we simply load with
2877
+ ;; no extension.
2878
+ (rule -1 (lower (has_type (ty_int_ref_64 ty) (load flags address offset)))
2879
+ (x64_mov (to_amode flags address offset)))
2880
+ ;; Also, certain scalar loads have a specific `from` width and extension kind
2881
+ ;; (signed -> `sx`, zeroed -> `zx`). We overwrite the high bits of the 64-bit
2882
+ ;; GPR even if the `to` type is smaller (e.g., 16-bits).
2883
+ (rule (lower (has_type (is_gpr_type ty) (uload8 flags address offset)))
2884
+ (x64_movzx (ExtMode.BQ) (to_amode flags address offset)))
2885
+ (rule (lower (has_type (is_gpr_type ty) (sload8 flags address offset)))
2886
+ (x64_movsx (ExtMode.BQ) (to_amode flags address offset)))
2887
+ (rule (lower (has_type (is_gpr_type ty) (uload16 flags address offset)))
2888
+ (x64_movzx (ExtMode.WQ) (to_amode flags address offset)))
2889
+ (rule (lower (has_type (is_gpr_type ty) (sload16 flags address offset)))
2890
+ (x64_movsx (ExtMode.WQ) (to_amode flags address offset)))
2891
+ (rule (lower (has_type (is_gpr_type ty) (uload32 flags address offset)))
2892
+ (x64_movzx (ExtMode.LQ) (to_amode flags address offset)))
2893
+ (rule (lower (has_type (is_gpr_type ty) (sload32 flags address offset)))
2894
+ (x64_movsx (ExtMode.LQ) (to_amode flags address offset)))
2895
+
2896
+ ;; To load to XMM registers, we use the x64-specific instructions for each type.
2897
+ ;; For `$F32` and `$F64` this is important--we only want to load 32 or 64 bits.
2898
+ ;; But for the 128-bit types, this is not strictly necessary for performance but
2899
+ ;; might help with clarity during disassembly.
2900
+ (rule (lower (has_type $F32 (load flags address offset)))
2901
+ (x64_movss_load (to_amode flags address offset)))
2902
+ (rule (lower (has_type $F64 (load flags address offset)))
2903
+ (x64_movsd_load (to_amode flags address offset)))
2904
+ (rule (lower (has_type $F32X4 (load flags address offset)))
2905
+ (x64_movups_load (to_amode flags address offset)))
2906
+ (rule (lower (has_type $F64X2 (load flags address offset)))
2907
+ (x64_movupd_load (to_amode flags address offset)))
2908
+ (rule -2 (lower (has_type (ty_vec128 ty) (load flags address offset)))
2909
+ (x64_movdqu_load (to_amode flags address offset)))
2910
+
2911
+ ;; We can load an I128 by doing two 64-bit loads.
2912
+ (rule -3 (lower (has_type $I128
2913
+ (load flags address offset)))
2914
+ (let ((addr_lo Amode (to_amode flags address offset))
2915
+ (addr_hi Amode (amode_offset addr_lo 8))
2916
+ (value_lo Reg (x64_mov addr_lo))
2917
+ (value_hi Reg (x64_mov addr_hi)))
2918
+ (value_regs value_lo value_hi)))
2919
+
2920
+ ;; We also include widening vector loads; these sign- or zero-extend each lane
2921
+ ;; to the next wider width (e.g., 16x4 -> 32x4).
2922
+ (rule 1 (lower (has_type $I16X8 (sload8x8 flags address offset)))
2923
+ (if-let $true (use_sse41))
2924
+ (x64_pmovsxbw (to_amode flags address offset)))
2925
+ (rule 1 (lower (has_type $I16X8 (uload8x8 flags address offset)))
2926
+ (if-let $true (use_sse41))
2927
+ (x64_pmovzxbw (to_amode flags address offset)))
2928
+ (rule 1 (lower (has_type $I32X4 (sload16x4 flags address offset)))
2929
+ (if-let $true (use_sse41))
2930
+ (x64_pmovsxwd (to_amode flags address offset)))
2931
+ (rule 1 (lower (has_type $I32X4 (uload16x4 flags address offset)))
2932
+ (if-let $true (use_sse41))
2933
+ (x64_pmovzxwd (to_amode flags address offset)))
2934
+ (rule 1 (lower (has_type $I64X2 (sload32x2 flags address offset)))
2935
+ (if-let $true (use_sse41))
2936
+ (x64_pmovsxdq (to_amode flags address offset)))
2937
+ (rule 1 (lower (has_type $I64X2 (uload32x2 flags address offset)))
2938
+ (if-let $true (use_sse41))
2939
+ (x64_pmovzxdq (to_amode flags address offset)))
2940
+
2941
+ (rule (lower (has_type $I16X8 (sload8x8 flags address offset)))
2942
+ (lower_swiden_low $I16X8 (x64_movq_to_xmm (to_amode flags address offset))))
2943
+ (rule (lower (has_type $I16X8 (uload8x8 flags address offset)))
2944
+ (lower_uwiden_low $I16X8 (x64_movq_to_xmm (to_amode flags address offset))))
2945
+ (rule (lower (has_type $I32X4 (sload16x4 flags address offset)))
2946
+ (lower_swiden_low $I32X4 (x64_movq_to_xmm (to_amode flags address offset))))
2947
+ (rule (lower (has_type $I32X4 (uload16x4 flags address offset)))
2948
+ (lower_uwiden_low $I32X4 (x64_movq_to_xmm (to_amode flags address offset))))
2949
+ (rule (lower (has_type $I64X2 (sload32x2 flags address offset)))
2950
+ (lower_swiden_low $I64X2 (x64_movq_to_xmm (to_amode flags address offset))))
2951
+ (rule (lower (has_type $I64X2 (uload32x2 flags address offset)))
2952
+ (lower_uwiden_low $I64X2 (x64_movq_to_xmm (to_amode flags address offset))))
2953
+
2954
+ ;; Rules for `store*` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2955
+
2956
+ ;; 8-, 16-, 32- and 64-bit GPR stores.
2957
+ (rule -2 (lower (store flags
2958
+ value @ (value_type (is_gpr_type ty))
2959
+ address
2960
+ offset))
2961
+ (side_effect
2962
+ (x64_movrm ty (to_amode flags address offset) value)))
2963
+
2964
+ ;; Explicit 8/16/32-bit opcodes.
2965
+ (rule (lower (istore8 flags value address offset))
2966
+ (side_effect
2967
+ (x64_movrm $I8 (to_amode flags address offset) value)))
2968
+ (rule (lower (istore16 flags value address offset))
2969
+ (side_effect
2970
+ (x64_movrm $I16 (to_amode flags address offset) value)))
2971
+ (rule (lower (istore32 flags value address offset))
2972
+ (side_effect
2973
+ (x64_movrm $I32 (to_amode flags address offset) value)))
2974
+
2975
+ ;; IMM stores
2976
+ (rule 2 (lower (store flags (has_type (fits_in_64 ty) (iconst (simm32 value))) address offset))
2977
+ (side_effect
2978
+ (x64_movimm_m ty (to_amode flags address offset) value)))
2979
+
2980
+ ;; F32 stores of values in XMM registers.
2981
+ (rule 1 (lower (store flags
2982
+ value @ (value_type $F32)
2983
+ address
2984
+ offset))
2985
+ (side_effect
2986
+ (x64_movss_store (to_amode flags address offset) value)))
2987
+
2988
+ ;; F64 stores of values in XMM registers.
2989
+ (rule 1 (lower (store flags
2990
+ value @ (value_type $F64)
2991
+ address
2992
+ offset))
2993
+ (side_effect
2994
+ (x64_movsd_store (to_amode flags address offset) value)))
2995
+
2996
+ ;; Stores of F32X4 vectors.
2997
+ (rule 1 (lower (store flags
2998
+ value @ (value_type $F32X4)
2999
+ address
3000
+ offset))
3001
+ (side_effect
3002
+ (x64_movups_store (to_amode flags address offset) value)))
3003
+
3004
+ ;; Stores of F64X2 vectors.
3005
+ (rule 1 (lower (store flags
3006
+ value @ (value_type $F64X2)
3007
+ address
3008
+ offset))
3009
+ (side_effect
3010
+ (x64_movupd_store (to_amode flags address offset) value)))
3011
+
3012
+ ;; Stores of all other 128-bit vector types with integer lanes.
3013
+ (rule -1 (lower (store flags
3014
+ value @ (value_type (ty_vec128_int _))
3015
+ address
3016
+ offset))
3017
+ (side_effect
3018
+ (x64_movdqu_store (to_amode flags address offset) value)))
3019
+
3020
+ ;; Stores of I128 values: store the two 64-bit halves separately.
3021
+ (rule 0 (lower (store flags
3022
+ value @ (value_type $I128)
3023
+ address
3024
+ offset))
3025
+ (let ((value_reg ValueRegs value)
3026
+ (value_lo Gpr (value_regs_get_gpr value_reg 0))
3027
+ (value_hi Gpr (value_regs_get_gpr value_reg 1))
3028
+ (addr_lo Amode (to_amode flags address offset))
3029
+ (addr_hi Amode (amode_offset addr_lo 8)))
3030
+ (side_effect
3031
+ (side_effect_concat
3032
+ (x64_movrm $I64 addr_lo value_lo)
3033
+ (x64_movrm $I64 addr_hi value_hi)))))
3034
+
3035
+ ;; Slightly optimize the extraction of the first lane from a vector which is
3036
+ ;; stored in memory. In the case the first lane specifically is selected the
3037
+ ;; standard `movss` and `movsd` instructions can be used as-if we're storing a
3038
+ ;; f32 or f64 despite the source perhaps being an integer vector since the
3039
+ ;; result of the instruction is the same.
3040
+ (rule 2 (lower (store flags
3041
+ (has_type $F32 (extractlane value (u8_from_uimm8 0)))
3042
+ address
3043
+ offset))
3044
+ (side_effect
3045
+ (x64_movss_store (to_amode flags address offset) value)))
3046
+ (rule 2 (lower (store flags
3047
+ (has_type $F64 (extractlane value (u8_from_uimm8 0)))
3048
+ address
3049
+ offset))
3050
+ (side_effect
3051
+ (x64_movsd_store (to_amode flags address offset) value)))
3052
+ (rule 2 (lower (store flags
3053
+ (has_type $I8 (extractlane value (u8_from_uimm8 n)))
3054
+ address
3055
+ offset))
3056
+ (if-let $true (use_sse41))
3057
+ (side_effect
3058
+ (x64_pextrb_store (to_amode flags address offset) value n)))
3059
+ (rule 2 (lower (store flags
3060
+ (has_type $I16 (extractlane value (u8_from_uimm8 n)))
3061
+ address
3062
+ offset))
3063
+ (if-let $true (use_sse41))
3064
+ (side_effect
3065
+ (x64_pextrw_store (to_amode flags address offset) value n)))
3066
+ (rule 2 (lower (store flags
3067
+ (has_type $I32 (extractlane value (u8_from_uimm8 n)))
3068
+ address
3069
+ offset))
3070
+ (if-let $true (use_sse41))
3071
+ (side_effect
3072
+ (x64_pextrd_store (to_amode flags address offset) value n)))
3073
+ (rule 2 (lower (store flags
3074
+ (has_type $I64 (extractlane value (u8_from_uimm8 n)))
3075
+ address
3076
+ offset))
3077
+ (if-let $true (use_sse41))
3078
+ (side_effect
3079
+ (x64_pextrq_store (to_amode flags address offset) value n)))
3080
+
3081
+ ;; Rules for `load*` + ALU op + `store*` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3082
+
3083
+ ;; Add mem, reg
3084
+ (rule 3 (lower
3085
+ (store flags
3086
+ (has_type (ty_32_or_64 ty)
3087
+ (iadd (and
3088
+ (sinkable_load sink)
3089
+ (load flags addr offset))
3090
+ src2))
3091
+ addr
3092
+ offset))
3093
+ (let ((_ RegMemImm sink))
3094
+ (side_effect
3095
+ (x64_add_mem ty (to_amode flags addr offset) src2))))
3096
+
3097
+ ;; Add mem, reg with args swapped
3098
+ (rule 2 (lower
3099
+ (store flags
3100
+ (has_type (ty_32_or_64 ty)
3101
+ (iadd src2
3102
+ (and
3103
+ (sinkable_load sink)
3104
+ (load flags addr offset))))
3105
+ addr
3106
+ offset))
3107
+ (let ((_ RegMemImm sink))
3108
+ (side_effect
3109
+ (x64_add_mem ty (to_amode flags addr offset) src2))))
3110
+
3111
+ ;; Sub mem, reg
3112
+ (rule 2 (lower
3113
+ (store flags
3114
+ (has_type (ty_32_or_64 ty)
3115
+ (isub (and
3116
+ (sinkable_load sink)
3117
+ (load flags addr offset))
3118
+ src2))
3119
+ addr
3120
+ offset))
3121
+ (let ((_ RegMemImm sink))
3122
+ (side_effect
3123
+ (x64_sub_mem ty (to_amode flags addr offset) src2))))
3124
+
3125
+ ;; And mem, reg
3126
+ (rule 3 (lower
3127
+ (store flags
3128
+ (has_type (ty_32_or_64 ty)
3129
+ (band (and
3130
+ (sinkable_load sink)
3131
+ (load flags addr offset))
3132
+ src2))
3133
+ addr
3134
+ offset))
3135
+ (let ((_ RegMemImm sink))
3136
+ (side_effect
3137
+ (x64_and_mem ty (to_amode flags addr offset) src2))))
3138
+
3139
+ ;; And mem, reg with args swapped
3140
+ (rule 2 (lower
3141
+ (store flags
3142
+ (has_type (ty_32_or_64 ty)
3143
+ (band src2
3144
+ (and
3145
+ (sinkable_load sink)
3146
+ (load flags addr offset))))
3147
+ addr
3148
+ offset))
3149
+ (let ((_ RegMemImm sink))
3150
+ (side_effect
3151
+ (x64_and_mem ty (to_amode flags addr offset) src2))))
3152
+
3153
+ ;; Or mem, reg
3154
+ (rule 3 (lower
3155
+ (store flags
3156
+ (has_type (ty_32_or_64 ty)
3157
+ (bor (and
3158
+ (sinkable_load sink)
3159
+ (load flags addr offset))
3160
+ src2))
3161
+ addr
3162
+ offset))
3163
+ (let ((_ RegMemImm sink))
3164
+ (side_effect
3165
+ (x64_or_mem ty (to_amode flags addr offset) src2))))
3166
+
3167
+ ;; Or mem, reg with args swapped
3168
+ (rule 2 (lower
3169
+ (store flags
3170
+ (has_type (ty_32_or_64 ty)
3171
+ (bor src2
3172
+ (and
3173
+ (sinkable_load sink)
3174
+ (load flags addr offset))))
3175
+ addr
3176
+ offset))
3177
+ (let ((_ RegMemImm sink))
3178
+ (side_effect
3179
+ (x64_or_mem ty (to_amode flags addr offset) src2))))
3180
+
3181
+ ;; Xor mem, reg
3182
+ (rule 3 (lower
3183
+ (store flags
3184
+ (has_type (ty_32_or_64 ty)
3185
+ (bxor (and
3186
+ (sinkable_load sink)
3187
+ (load flags addr offset))
3188
+ src2))
3189
+ addr
3190
+ offset))
3191
+ (let ((_ RegMemImm sink))
3192
+ (side_effect
3193
+ (x64_xor_mem ty (to_amode flags addr offset) src2))))
3194
+
3195
+ ;; Xor mem, reg with args swapped
3196
+ (rule 2 (lower
3197
+ (store flags
3198
+ (has_type (ty_32_or_64 ty)
3199
+ (bxor src2
3200
+ (and
3201
+ (sinkable_load sink)
3202
+ (load flags addr offset))))
3203
+ addr
3204
+ offset))
3205
+ (let ((_ RegMemImm sink))
3206
+ (side_effect
3207
+ (x64_xor_mem ty (to_amode flags addr offset) src2))))
3208
+
3209
+ ;; Rules for `fence` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3210
+
3211
+ (rule (lower (fence))
3212
+ (side_effect (x64_mfence)))
3213
+
3214
+ ;; Rules for `func_addr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3215
+
3216
+ (rule (lower (func_addr (func_ref_data _ extname dist)))
3217
+ (load_ext_name extname 0 dist))
3218
+
3219
+ ;; Rules for `symbol_value` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3220
+
3221
+ (rule (lower (symbol_value (symbol_value_data extname dist offset)))
3222
+ (load_ext_name extname offset dist))
3223
+
3224
+ ;; Rules for `atomic_load` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3225
+
3226
+ ;; This is a normal load. The x86-TSO memory model provides sufficient
3227
+ ;; sequencing to satisfy the CLIF synchronisation requirements for `AtomicLoad`
3228
+ ;; without the need for any fence instructions.
3229
+ ;;
3230
+ ;; As described in the `atomic_load` documentation, this lowering is only valid
3231
+ ;; for I8, I16, I32, and I64. The sub-64-bit types are zero extended, as with a
3232
+ ;; normal load.
3233
+ (rule 1 (lower (has_type $I64 (atomic_load flags address)))
3234
+ (x64_mov (to_amode flags address (zero_offset))))
3235
+ (rule (lower (has_type (and (fits_in_32 ty) (ty_int _)) (atomic_load flags address)))
3236
+ (x64_movzx (ext_mode (ty_bits_u16 ty) 64) (to_amode flags address (zero_offset))))
3237
+
3238
+ ;; Rules for `atomic_store` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3239
+
3240
+ ;; This is a normal store followed by an `mfence` instruction. As described in
3241
+ ;; the `atomic_load` documentation, this lowering is only valid for I8, I16,
3242
+ ;; I32, and I64.
3243
+ (rule (lower (atomic_store flags
3244
+ value @ (value_type (and (fits_in_64 ty) (ty_int _)))
3245
+ address))
3246
+ (side_effect (side_effect_concat
3247
+ (x64_movrm ty (to_amode flags address (zero_offset)) value)
3248
+ (x64_mfence))))
3249
+
3250
+ ;; Rules for `atomic_cas` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3251
+
3252
+ (rule (lower (has_type (and (fits_in_64 ty) (ty_int _))
3253
+ (atomic_cas flags address expected replacement)))
3254
+ (x64_cmpxchg ty expected replacement (to_amode flags address (zero_offset))))
3255
+
3256
+ ;; Rules for `atomic_rmw` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3257
+
3258
+ ;; This is a simple, general-case atomic update, based on a loop involving
3259
+ ;; `cmpxchg`. Note that we could do much better than this in the case where the
3260
+ ;; old value at the location (that is to say, the SSA `Value` computed by this
3261
+ ;; CLIF instruction) is not required. In that case, we could instead implement
3262
+ ;; this using a single `lock`-prefixed x64 read-modify-write instruction. Also,
3263
+ ;; even in the case where the old value is required, for the `add` and `sub`
3264
+ ;; cases, we can use the single instruction `lock xadd`. However, those
3265
+ ;; improvements have been left for another day. TODO: filed as
3266
+ ;; https://github.com/bytecodealliance/wasmtime/issues/2153.
3267
+
3268
+ (rule (lower (has_type (and (fits_in_64 ty) (ty_int _))
3269
+ (atomic_rmw flags op address input)))
3270
+ (x64_atomic_rmw_seq ty op (to_amode flags address (zero_offset)) input))
3271
+
3272
+ ;; Rules for `call` and `call_indirect` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3273
+
3274
+ (rule (lower (call (func_ref_data sig_ref extname dist) inputs))
3275
+ (gen_call sig_ref extname dist inputs))
3276
+
3277
+ (rule (lower (call_indirect sig_ref val inputs))
3278
+ (gen_call_indirect sig_ref val inputs))
3279
+
3280
+ ;;;; Rules for `return_call` and `return_call_indirect` ;;;;;;;;;;;;;;;;;;;;;;;;
3281
+
3282
+ (rule (lower (return_call (func_ref_data sig_ref extname dist) args))
3283
+ (gen_return_call sig_ref extname dist args))
3284
+
3285
+ (rule (lower (return_call_indirect sig_ref callee args))
3286
+ (gen_return_call_indirect sig_ref callee args))
3287
+
3288
+ ;;;; Rules for `get_{frame,stack}_pointer` and `get_return_address` ;;;;;;;;;;;;
3289
+
3290
+ (rule (lower (get_frame_pointer))
3291
+ (x64_rbp))
3292
+
3293
+ (rule (lower (get_stack_pointer))
3294
+ (x64_rsp))
3295
+
3296
+ (rule (lower (get_return_address))
3297
+ (x64_load $I64
3298
+ (Amode.ImmReg 8 (x64_rbp) (mem_flags_trusted))
3299
+ (ExtKind.None)))
3300
+
3301
+ ;; Rules for `jump` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3302
+
3303
+ (rule (lower_branch (jump _) (single_target target))
3304
+ (emit_side_effect (jmp_known target)))
3305
+
3306
+ ;; Rules for `brif` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3307
+
3308
+ (rule 2 (lower_branch (brif (maybe_uextend (icmp cc a b)) _ _) (two_targets then else))
3309
+ (emit_side_effect (jmp_cond_icmp (emit_cmp cc a b) then else)))
3310
+
3311
+ (rule 2 (lower_branch (brif (maybe_uextend (fcmp cc a b)) _ _) (two_targets then else))
3312
+ (emit_side_effect (jmp_cond_fcmp (emit_fcmp cc a b) then else)))
3313
+
3314
+ (rule 1 (lower_branch (brif val @ (value_type $I128) _ _)
3315
+ (two_targets then else))
3316
+ (emit_side_effect (jmp_cond_icmp (cmp_zero_i128 (CC.Z) val) then else)))
3317
+
3318
+ (rule (lower_branch (brif val @ (value_type (ty_int_bool_or_ref)) _ _)
3319
+ (two_targets then else))
3320
+ (emit_side_effect (with_flags_side_effect
3321
+ (cmp_zero_int_bool_ref val)
3322
+ (jmp_cond (CC.NZ) then else))))
3323
+
3324
+
3325
+ ;; Compare an I128 value to zero, returning a flags result suitable for making a
3326
+ ;; jump decision. The comparison is implemented as `(hi | low) == 0`,
3327
+ ;; and the result can be interpreted as follows
3328
+ ;; * CC.Z indicates that the value was non-zero, as one or both of the halves of
3329
+ ;; the value were non-zero
3330
+ ;; * CC.NZ indicates that both halves of the value were 0
3331
+ (decl cmp_zero_i128 (CC ValueRegs) IcmpCondResult)
3332
+ (rule (cmp_zero_i128 (cc_nz_or_z cc) val)
3333
+ (let ((lo Gpr (value_regs_get_gpr val 0))
3334
+ (hi Gpr (value_regs_get_gpr val 1)))
3335
+ (icmp_cond_result
3336
+ (x64_alurmi_flags_side_effect (AluRmiROpcode.Or) $I64 lo hi)
3337
+ (cc_invert cc))))
3338
+
3339
+
3340
+ (decl cmp_zero_int_bool_ref (Value) ProducesFlags)
3341
+ (rule (cmp_zero_int_bool_ref val @ (value_type ty))
3342
+ (let ((size OperandSize (raw_operand_size_of_type ty))
3343
+ (src Gpr val))
3344
+ (x64_test size src src)))
3345
+
3346
+ ;; Rules for `br_table` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3347
+
3348
+ (rule (lower_branch (br_table idx @ (value_type ty) _) (jump_table_targets default_target jt_targets))
3349
+ (let ((size OperandSize (raw_operand_size_of_type ty))
3350
+ (jt_size u32 (jump_table_size jt_targets))
3351
+ (size_reg Reg (imm ty (u32_as_u64 jt_size)))
3352
+ (idx_reg Gpr (extend_to_gpr idx $I64 (ExtendKind.Zero)))
3353
+ (clamped_idx Reg (with_flags_reg
3354
+ (x64_cmp size idx_reg size_reg)
3355
+ (cmove ty (CC.B) idx_reg size_reg))))
3356
+ (emit_side_effect (jmp_table_seq ty clamped_idx default_target jt_targets))))
3357
+
3358
+ ;; Rules for `select_spectre_guard` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3359
+
3360
+ (rule (lower (select_spectre_guard (icmp cc a b) x y))
3361
+ (select_icmp (emit_cmp cc a b) x y))
3362
+
3363
+ (rule -1 (lower (has_type ty (select_spectre_guard c @ (value_type (fits_in_64 a_ty)) x y)))
3364
+ (let ((size OperandSize (raw_operand_size_of_type a_ty))
3365
+ (gpr_c Gpr (put_in_gpr c)))
3366
+ (with_flags (x64_test size gpr_c gpr_c) (cmove_from_values ty (CC.NZ) x y))))
3367
+
3368
+ (rule -2 (lower (has_type ty (select_spectre_guard c @ (value_type $I128) x y)))
3369
+ (let ((cond_result IcmpCondResult (cmp_zero_i128 (CC.Z) c)))
3370
+ (select_icmp cond_result x y)))
3371
+
3372
+ ;; Rules for `fcvt_from_sint` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3373
+
3374
+ ;; Note that the `cvtsi2s{s,d}` instruction is not just an int-to-float
3375
+ ;; conversion instruction in isolation, it also takes the upper 64-bits of an
3376
+ ;; xmm register and places it into the destination. We don't actually want that
3377
+ ;; to happen as it could accidentally create a false dependency with a
3378
+ ;; previous instruction defining the register's upper 64-bits. See #7085 for
3379
+ ;; an instance of this.
3380
+ ;;
3381
+ ;; This means that the first operand to all of the int-to-float conversions here
3382
+ ;; are `(xmm_zero)` operands which is a guaranteed zero register that has no
3383
+ ;; dependencies on other instructions.
3384
+ ;;
3385
+ ;; Ideally this would be lifted out to a higher level to get deduplicated
3386
+ ;; between consecutive int-to-float operations but that's not easy
3387
+ ;; to do at this time. One possibility would be a mid-end rule which rewrites
3388
+ ;; `fcvt_from_sint` to an x86-specific opcode using a zero constant which would
3389
+ ;; be subject to normal LICM, but that's not feasible today.
3390
+
3391
+ (rule 2 (lower (has_type $F32 (fcvt_from_sint a @ (value_type $I8))))
3392
+ (x64_cvtsi2ss $I32 (xmm_zero $F32X4) (extend_to_gpr a $I32 (ExtendKind.Sign))))
3393
+
3394
+ (rule 2 (lower (has_type $F32 (fcvt_from_sint a @ (value_type $I16))))
3395
+ (x64_cvtsi2ss $I32 (xmm_zero $F32X4) (extend_to_gpr a $I32 (ExtendKind.Sign))))
3396
+
3397
+ (rule 1 (lower (has_type $F32 (fcvt_from_sint a @ (value_type (ty_int (fits_in_64 ty))))))
3398
+ (x64_cvtsi2ss ty (xmm_zero $F32X4) a))
3399
+
3400
+ (rule 2 (lower (has_type $F64 (fcvt_from_sint a @ (value_type $I8))))
3401
+ (x64_cvtsi2sd $I32 (xmm_zero $F64X2) (extend_to_gpr a $I32 (ExtendKind.Sign))))
3402
+
3403
+ (rule 2 (lower (has_type $F64 (fcvt_from_sint a @ (value_type $I16))))
3404
+ (x64_cvtsi2sd $I32 (xmm_zero $F64X2) (extend_to_gpr a $I32 (ExtendKind.Sign))))
3405
+
3406
+ (rule 1 (lower (has_type $F64 (fcvt_from_sint a @ (value_type (ty_int (fits_in_64 ty))))))
3407
+ (x64_cvtsi2sd ty (xmm_zero $F64X2) a))
3408
+
3409
+ (rule 0 (lower (fcvt_from_sint a @ (value_type $I32X4)))
3410
+ (x64_cvtdq2ps a))
3411
+
3412
+ ;; Base case: decompose the i64x2 input into two scalar registers and convert
3413
+ ;; each of those into a float. Afterwards re-pack the two results into the final
3414
+ ;; destination.
3415
+ (rule 0 (lower (fcvt_from_sint a @ (value_type $I64X2)))
3416
+ (let (
3417
+ (a Xmm a)
3418
+ (zero Xmm (xmm_zero $F64X2))
3419
+ (f0 Xmm (x64_cvtsi2sd $I64 zero (x64_movq_to_gpr a)))
3420
+ (f1 Xmm (x64_cvtsi2sd $I64 zero (x64_movq_to_gpr (x64_pshufd a 0b11_10_11_10))))
3421
+ )
3422
+ (x64_unpcklpd f0 f1)))
3423
+
3424
+ (rule 1 (lower (has_type $F64X2 (fcvt_from_sint (swiden_low a @ (value_type $I32X4)))))
3425
+ (x64_cvtdq2pd a))
3426
+
3427
+ ;; Rules for `fcvt_from_uint` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3428
+
3429
+ (rule 1 (lower (has_type $F32 (fcvt_from_uint val @ (value_type (fits_in_32 (ty_int ty))))))
3430
+ (x64_cvtsi2ss $I64 (xmm_zero $F32X4) (extend_to_gpr val $I64 (ExtendKind.Zero))))
3431
+
3432
+ (rule 1 (lower (has_type $F64 (fcvt_from_uint val @ (value_type (fits_in_32 (ty_int ty))))))
3433
+ (x64_cvtsi2sd $I64 (xmm_zero $F64X2) (extend_to_gpr val $I64 (ExtendKind.Zero))))
3434
+
3435
+ (rule (lower (has_type ty (fcvt_from_uint val @ (value_type $I64))))
3436
+ (cvt_u64_to_float_seq ty val))
3437
+
3438
+ ;; Base case of u64x2 being converted to f64x2. No native instruction for this
3439
+ ;; is available so it's emulated through a series of instructions that exploit
3440
+ ;; the binary representation of 64-bit floats. This sequence of instructions is
3441
+ ;; copied from LLVM and my understanding of the general idea is to roughly:
3442
+ ;;
3443
+ ;; * For each bullet below operate in parallel on the left and right lanes.
3444
+ ;; * Move the low 32 bits of the input into one register and the upper
3445
+ ;; 32-bits into a different register, where both have all 0s for the upper
3446
+ ;; 32-bits. (e.g. split the 64-bit input into two locations)
3447
+ ;; * For the low bits, create `1.<twenty-zeros><low32>p52` via bit tricks.
3448
+ ;; * For the high bits, create `1.<twenty-zeros><high32>p84` via bit tricks.
3449
+ ;; * Create the constant `1.0p84 + 1.0p52`
3450
+ ;; * Add the two high halves and subtract the constant.
3451
+ ;;
3452
+ ;; Apply some math and this should produce the same result as the native
3453
+ ;; conversion.
3454
+ ;;
3455
+ ;; As for the bit tricks a float is represented where the low 53 bits are the
3456
+ ;; decimal of the float, basically:
3457
+ ;;
3458
+ ;; f = 1.<fraction> ^ (<exponent> - 1023)
3459
+ ;;
3460
+ ;; where `<fraction>` is the low 53 bits. By placing the 32-bit halves from
3461
+ ;; the original integer into the low 53 bits and setting the exponent right it
3462
+ ;; means that each 32-bit half can become part of a 64-bit floating point
3463
+ ;; number. The final step in combining via float arithmetic will chop off the
3464
+ ;; leading `1.` at the start of the float that we constructed, one for the low
3465
+ ;; half and one for the upper half.
3466
+ (rule -1 (lower (has_type $F64X2 (fcvt_from_uint val @ (value_type $I64X2))))
3467
+ (let ((low32_mask XmmMem (emit_u128_le_const 0x00000000ffffffff_00000000ffffffff))
3468
+ (float_1p52 XmmMem (emit_u128_le_const 0x4330000000000000_4330000000000000))
3469
+ (float_1p84 XmmMem (emit_u128_le_const 0x4530000000000000_4530000000000000))
3470
+ (float_1p84_plus_1p52 XmmMem (emit_u128_le_const 0x4530000000100000_4530000000100000))
3471
+ (low32 Xmm (x64_pand val low32_mask))
3472
+ (low32_as_float Xmm (x64_por low32 float_1p52))
3473
+ (high32 Xmm (x64_psrlq val (xmi_imm 32)))
3474
+ (high32_as_float Xmm (x64_por high32 float_1p84)))
3475
+ (x64_addpd low32_as_float (x64_subpd high32_as_float float_1p84_plus_1p52))))
3476
+
3477
+ ;; Algorithm uses unpcklps to help create a float that is equivalent
3478
+ ;; 0x1.0p52 + double(src). 0x1.0p52 is unique because at this exponent
3479
+ ;; every value of the mantissa represents a corresponding uint32 number.
3480
+ ;; When we subtract 0x1.0p52 we are left with double(src).
3481
+ (rule 1 (lower (has_type $F64X2 (fcvt_from_uint (uwiden_low val @ (value_type $I32X4)))))
3482
+ (let ((uint_mask XmmMem (emit_u128_le_const 0x43300000_43300000))
3483
+ (res Xmm (x64_unpcklps val uint_mask))
3484
+ (uint_mask_high XmmMem (emit_u128_le_const 0x4330000000000000_4330000000000000)))
3485
+ (x64_subpd res uint_mask_high)))
3486
+
3487
+ ;; When AVX512VL and AVX512F are available,
3488
+ ;; `fcvt_from_uint` can be lowered to a single instruction.
3489
+ (rule 2 (lower (has_type $F32X4 (fcvt_from_uint src)))
3490
+ (if-let $true (use_avx512vl))
3491
+ (if-let $true (use_avx512f))
3492
+ (x64_vcvtudq2ps src))
3493
+
3494
+ ;; Converting packed unsigned integers to packed floats
3495
+ ;; requires a few steps. There is no single instruction
3496
+ ;; lowering for converting unsigned floats but there is for
3497
+ ;; converting packed signed integers to float (cvtdq2ps). In
3498
+ ;; the steps below we isolate the upper half (16 bits) and
3499
+ ;; lower half (16 bits) of each lane and then we convert
3500
+ ;; each half separately using cvtdq2ps meant for signed
3501
+ ;; integers. In order for this to work for the upper half
3502
+ ;; bits we must shift right by 1 (divide by 2) these bits in
3503
+ ;; order to ensure the most significant bit is 0 not signed,
3504
+ ;; and then after the conversion we double the value.
3505
+ ;; Finally we add the converted values where addition will
3506
+ ;; correctly round.
3507
+ ;;
3508
+ ;; Sequence:
3509
+ ;; -> A = 0xffffffff
3510
+ ;; -> Ah = 0xffff0000
3511
+ ;; -> Al = 0x0000ffff
3512
+ ;; -> Convert(Al) // Convert int to float
3513
+ ;; -> Ah = Ah >> 1 // Shift right 1 to assure Ah conversion isn't treated as signed
3514
+ ;; -> Convert(Ah) // Convert .. with no loss of significant digits from previous shift
3515
+ ;; -> Ah = Ah + Ah // Double Ah to account for shift right before the conversion.
3516
+ ;; -> dst = Ah + Al // Add the two floats together
3517
+ (rule 1 (lower (has_type $F32X4 (fcvt_from_uint val)))
3518
+ (let ((a Xmm val)
3519
+
3520
+ ;; get the low 16 bits
3521
+ (a_lo Xmm (x64_pslld a (xmi_imm 16)))
3522
+ (a_lo Xmm (x64_psrld a_lo (xmi_imm 16)))
3523
+
3524
+ ;; get the high 16 bits
3525
+ (a_hi Xmm (x64_psubd a a_lo))
3526
+
3527
+ ;; convert the low 16 bits
3528
+ (a_lo Xmm (x64_cvtdq2ps a_lo))
3529
+
3530
+ ;; shift the high bits by 1, convert, and double to get the correct
3531
+ ;; value
3532
+ (a_hi Xmm (x64_psrld a_hi (xmi_imm 1)))
3533
+ (a_hi Xmm (x64_cvtdq2ps a_hi))
3534
+ (a_hi Xmm (x64_addps a_hi a_hi)))
3535
+
3536
+ ;; add together the two converted values
3537
+ (x64_addps a_hi a_lo)))
3538
+
3539
+ ;; Rules for `fcvt_to_uint` and `fcvt_to_sint` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3540
+
3541
+ (rule (lower (has_type out_ty (fcvt_to_uint val @ (value_type (ty_scalar_float _)))))
3542
+ (cvt_float_to_uint_seq out_ty val $false))
3543
+
3544
+ (rule (lower (has_type out_ty (fcvt_to_uint_sat val @ (value_type (ty_scalar_float _)))))
3545
+ (cvt_float_to_uint_seq out_ty val $true))
3546
+
3547
+ (rule (lower (has_type out_ty (fcvt_to_sint val @ (value_type (ty_scalar_float _)))))
3548
+ (cvt_float_to_sint_seq out_ty val $false))
3549
+
3550
+ (rule (lower (has_type out_ty (fcvt_to_sint_sat val @ (value_type (ty_scalar_float _)))))
3551
+ (cvt_float_to_sint_seq out_ty val $true))
3552
+
3553
+ ;; The x64 backend currently only supports these two type combinations.
3554
+ (rule 1 (lower (has_type $I32X4 (fcvt_to_sint_sat val @ (value_type $F32X4))))
3555
+ (let ((src Xmm val)
3556
+
3557
+ ;; Sets tmp to zero if float is NaN
3558
+ (tmp Xmm (x64_cmpps src src (FcmpImm.Equal)))
3559
+ (dst Xmm (x64_andps src tmp))
3560
+
3561
+ ;; Sets top bit of tmp if float is positive
3562
+ ;; Setting up to set top bit on negative float values
3563
+ (tmp Xmm (x64_pxor tmp dst))
3564
+
3565
+ ;; Convert the packed float to packed doubleword.
3566
+ (dst Xmm (x64_cvttps2dq dst))
3567
+
3568
+ ;; Set top bit only if < 0
3569
+ (tmp Xmm (x64_pand dst tmp))
3570
+ (tmp Xmm (x64_psrad tmp (xmi_imm 31))))
3571
+
3572
+ ;; On overflow 0x80000000 is returned to a lane.
3573
+ ;; Below sets positive overflow lanes to 0x7FFFFFFF
3574
+ ;; Keeps negative overflow lanes as is.
3575
+ (x64_pxor tmp dst)))
3576
+
3577
+ ;; The algorithm for converting floats to unsigned ints is a little tricky. The
3578
+ ;; complication arises because we are converting from a signed 64-bit int with a positive
3579
+ ;; integer range from 1..INT_MAX (0x1..0x7FFFFFFF) to an unsigned integer with an extended
3580
+ ;; range from (INT_MAX+1)..UINT_MAX. It's this range from (INT_MAX+1)..UINT_MAX
3581
+ ;; (0x80000000..0xFFFFFFFF) that needs to be accounted for as a special case since our
3582
+ ;; conversion instruction (cvttps2dq) only converts as high as INT_MAX (0x7FFFFFFF), but
3583
+ ;; which conveniently setting underflows and overflows (smaller than MIN_INT or larger than
3584
+ ;; MAX_INT) to be INT_MAX+1 (0x80000000). Nothing that the range (INT_MAX+1)..UINT_MAX includes
3585
+ ;; precisely INT_MAX values we can correctly account for and convert every value in this range
3586
+ ;; if we simply subtract INT_MAX+1 before doing the cvttps2dq conversion. After the subtraction
3587
+ ;; every value originally (INT_MAX+1)..UINT_MAX is now the range (0..INT_MAX).
3588
+ ;; After the conversion we add INT_MAX+1 back to this converted value, noting again that
3589
+ ;; values we are trying to account for were already set to INT_MAX+1 during the original conversion.
3590
+ ;; We simply have to create a mask and make sure we are adding together only the lanes that need
3591
+ ;; to be accounted for. Digesting it all the steps then are:
3592
+ ;;
3593
+ ;; Step 1 - Account for NaN and negative floats by setting these src values to zero.
3594
+ ;; Step 2 - Make a copy (tmp1) of the src value since we need to convert twice for
3595
+ ;; reasons described above.
3596
+ ;; Step 3 - Convert the original src values. This will convert properly all floats up to INT_MAX
3597
+ ;; Step 4 - Subtract INT_MAX from the copy set (tmp1). Note, all zero and negative values are those
3598
+ ;; values that were originally in the range (0..INT_MAX). This will come in handy during
3599
+ ;; step 7 when we zero negative lanes.
3600
+ ;; Step 5 - Create a bit mask for tmp1 that will correspond to all lanes originally less than
3601
+ ;; UINT_MAX that are now less than INT_MAX thanks to the subtraction.
3602
+ ;; Step 6 - Convert the second set of values (tmp1)
3603
+ ;; Step 7 - Prep the converted second set by zeroing out negative lanes (these have already been
3604
+ ;; converted correctly with the first set) and by setting overflow lanes to 0x7FFFFFFF
3605
+ ;; as this will allow us to properly saturate overflow lanes when adding to 0x80000000
3606
+ ;; Step 8 - Add the orginal converted src and the converted tmp1 where float values originally less
3607
+ ;; than and equal to INT_MAX will be unchanged, float values originally between INT_MAX+1 and
3608
+ ;; UINT_MAX will add together (INT_MAX) + (SRC - INT_MAX), and float values originally
3609
+ ;; greater than UINT_MAX will be saturated to UINT_MAX (0xFFFFFFFF) after adding (0x8000000 + 0x7FFFFFFF).
3610
+ ;;
3611
+ ;;
3612
+ ;; The table below illustrates the result after each step where it matters for the converted set.
3613
+ ;; Note the original value range (original src set) is the final dst in Step 8:
3614
+ ;;
3615
+ ;; Original src set:
3616
+ ;; | Original Value Range | Step 1 | Step 3 | Step 8 |
3617
+ ;; | -FLT_MIN..FLT_MAX | 0.0..FLT_MAX | 0..INT_MAX(w/overflow) | 0..UINT_MAX(w/saturation) |
3618
+ ;;
3619
+ ;; Copied src set (tmp1):
3620
+ ;; | Step 2 | Step 4 |
3621
+ ;; | 0.0..FLT_MAX | (0.0-(INT_MAX+1))..(FLT_MAX-(INT_MAX+1)) |
3622
+ ;;
3623
+ ;; | Step 6 | Step 7 |
3624
+ ;; | (0-(INT_MAX+1))..(UINT_MAX-(INT_MAX+1))(w/overflow) | ((INT_MAX+1)-(INT_MAX+1))..(INT_MAX+1) |
3625
+ (rule 1 (lower (has_type $I32X4 (fcvt_to_uint_sat val @ (value_type $F32X4))))
3626
+ (let ((src Xmm val)
3627
+
3628
+ ;; Converting to unsigned int so if float src is negative or NaN
3629
+ ;; will first set to zero.
3630
+ (tmp2 Xmm (xmm_zero $F32X4))
3631
+ (dst Xmm (x64_maxps src tmp2))
3632
+
3633
+ ;; Set tmp2 to INT_MAX+1. It is important to note here that after it looks
3634
+ ;; like we are only converting INT_MAX (0x7FFFFFFF) but in fact because
3635
+ ;; single precision IEEE-754 floats can only accurately represent contingous
3636
+ ;; integers up to 2^23 and outside of this range it rounds to the closest
3637
+ ;; integer that it can represent. In the case of INT_MAX, this value gets
3638
+ ;; represented as 0x4f000000 which is the integer value (INT_MAX+1).
3639
+ (tmp2 Xmm (x64_pcmpeqd tmp2 tmp2))
3640
+ (tmp2 Xmm (x64_psrld tmp2 (xmi_imm 1)))
3641
+ (tmp2 Xmm (x64_cvtdq2ps tmp2))
3642
+
3643
+ ;; Make a copy of these lanes and then do the first conversion.
3644
+ ;; Overflow lanes greater than the maximum allowed signed value will
3645
+ ;; set to 0x80000000. Negative and NaN lanes will be 0x0
3646
+ (tmp1 Xmm dst)
3647
+ (dst Xmm (x64_cvttps2dq dst))
3648
+
3649
+ ;; Set lanes to src - max_signed_int
3650
+ (tmp1 Xmm (x64_subps tmp1 tmp2))
3651
+
3652
+ ;; Create mask for all positive lanes to saturate (i.e. greater than
3653
+ ;; or equal to the maxmimum allowable unsigned int).
3654
+ (tmp2 Xmm (x64_cmpps tmp2 tmp1 (FcmpImm.LessThanOrEqual)))
3655
+
3656
+ ;; Convert those set of lanes that have the max_signed_int factored out.
3657
+ (tmp1 Xmm (x64_cvttps2dq tmp1))
3658
+
3659
+ ;; Prepare converted lanes by zeroing negative lanes and prepping lanes
3660
+ ;; that have positive overflow (based on the mask) by setting these lanes
3661
+ ;; to 0x7FFFFFFF
3662
+ (tmp1 Xmm (x64_pxor tmp1 tmp2))
3663
+ (tmp2 Xmm (xmm_zero $I32X4))
3664
+ (tmp1 Xmm (lower_vec_smax $I32X4 tmp1 tmp2)))
3665
+
3666
+ ;; Add this second set of converted lanes to the original to properly handle
3667
+ ;; values greater than max signed int.
3668
+ (x64_paddd tmp1 dst)))
3669
+
3670
+ ;; Rules for `x86_cvtt2dq` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3671
+
3672
+ (rule (lower (has_type $I32X4 (x86_cvtt2dq val @ (value_type $F32X4))))
3673
+ (x64_cvttps2dq val))
3674
+
3675
+ ;; Rules for `iadd_pairwise` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3676
+
3677
+ (rule (lower (has_type $I8X16 (iadd_pairwise x y)))
3678
+ (let (
3679
+ ;; Shuffle all the even lanes of `x` and `y` into one register
3680
+ (even_lane_mask Xmm (x64_movdqu_load (emit_u128_le_const 0x00ff_00ff_00ff_00ff_00ff_00ff_00ff_00ff)))
3681
+ (x_evens Xmm (x64_pand x even_lane_mask))
3682
+ (y_evens Xmm (x64_pand y even_lane_mask))
3683
+ (evens Xmm (x64_packuswb x_evens y_evens))
3684
+
3685
+ ;; Shuffle all the odd lanes of `x` and `y` into one register
3686
+ (x_odds Xmm (x64_psrlw x (xmi_imm 8)))
3687
+ (y_odds Xmm (x64_psrlw y (xmi_imm 8)))
3688
+ (odds Xmm (x64_packuswb x_odds y_odds))
3689
+ )
3690
+ (x64_paddb evens odds)))
3691
+
3692
+
3693
+ (rule 1 (lower (has_type $I16X8 (iadd_pairwise x y)))
3694
+ (if-let $true (use_ssse3))
3695
+ (x64_phaddw x y))
3696
+
3697
+ (rule (lower (has_type $I16X8 (iadd_pairwise x y)))
3698
+ (let (
3699
+ (x Xmm x)
3700
+ (y Xmm y)
3701
+
3702
+ ;; Shuffle the even-numbered 16-bit lanes into low four lanes of each
3703
+ ;; vector by shuffling 16-bit lanes then shuffling 32-bit lanes.
3704
+ ;; With these in place generate a new vector from the two low 64-bits
3705
+ ;; of each vector (the low four 16-bit lanes).
3706
+ ;;
3707
+ ;; 0xe8 == 0b11_10_10_00
3708
+ (x_evens Xmm (x64_pshufd (x64_pshufhw (x64_pshuflw x 0xe8) 0xe8) 0xe8))
3709
+ (y_evens Xmm (x64_pshufd (x64_pshufhw (x64_pshuflw y 0xe8) 0xe8) 0xe8))
3710
+ (evens Xmm (x64_punpcklqdq x_evens y_evens))
3711
+
3712
+ ;; Shuffle the odd-numbered 16-bit lanes into the low 8 lanes by
3713
+ ;; performing `sshr` operation on 32-bit lanes, effectively moving the
3714
+ ;; odd lanes into even lanes while leaving their sign bits in the
3715
+ ;; odd lanes. The `packssdw` instruction then conveniently will
3716
+ ;; put everything into one vector for us.
3717
+ (x_shifted Xmm (x64_psrad x (xmi_imm 16)))
3718
+ (y_shifted Xmm (x64_psrad y (xmi_imm 16)))
3719
+ (odds Xmm (x64_packssdw x_shifted y_shifted))
3720
+ )
3721
+ (x64_paddw evens odds)))
3722
+
3723
+ (rule 1 (lower (has_type $I32X4 (iadd_pairwise x y)))
3724
+ (if-let $true (use_ssse3))
3725
+ (x64_phaddd x y))
3726
+
3727
+ (rule (lower (has_type $I32X4 (iadd_pairwise x y)))
3728
+ (let (
3729
+ (x Xmm x)
3730
+ (y Xmm y)
3731
+ ;; evens = [ x[0] x[2] y[0] y[2] ]
3732
+ (evens Xmm (x64_shufps x y 0b10_00_10_00))
3733
+ ;; odds = [ x[1] x[3] y[1] y[3] ]
3734
+ (odds Xmm (x64_shufps x y 0b11_01_11_01))
3735
+ )
3736
+ (x64_paddd evens odds)))
3737
+
3738
+ ;; special case for the `i16x8.extadd_pairwise_i8x16_s` wasm instruction
3739
+ (rule 2 (lower
3740
+ (has_type $I16X8 (iadd_pairwise
3741
+ (swiden_low val @ (value_type $I8X16))
3742
+ (swiden_high val))))
3743
+ (if-let $true (use_ssse3))
3744
+ (let ((mul_const Xmm (x64_xmm_load_const $I8X16
3745
+ (emit_u128_le_const 0x01010101010101010101010101010101))))
3746
+ (x64_pmaddubsw mul_const val)))
3747
+
3748
+ ;; special case for the `i32x4.extadd_pairwise_i16x8_s` wasm instruction
3749
+ (rule 2 (lower
3750
+ (has_type $I32X4 (iadd_pairwise
3751
+ (swiden_low val @ (value_type $I16X8))
3752
+ (swiden_high val))))
3753
+ (let ((mul_const XmmMem (emit_u128_le_const 0x0001_0001_0001_0001_0001_0001_0001_0001)))
3754
+ (x64_pmaddwd val mul_const)))
3755
+
3756
+ ;; special case for the `i16x8.extadd_pairwise_i8x16_u` wasm instruction
3757
+ (rule 2 (lower
3758
+ (has_type $I16X8 (iadd_pairwise
3759
+ (uwiden_low val @ (value_type $I8X16))
3760
+ (uwiden_high val))))
3761
+ (if-let $true (use_ssse3))
3762
+ (let ((mul_const XmmMem (emit_u128_le_const 0x01010101010101010101010101010101)))
3763
+ (x64_pmaddubsw val mul_const)))
3764
+
3765
+ ;; special case for the `i32x4.extadd_pairwise_i16x8_u` wasm instruction
3766
+ (rule 2 (lower
3767
+ (has_type $I32X4 (iadd_pairwise
3768
+ (uwiden_low val @ (value_type $I16X8))
3769
+ (uwiden_high val))))
3770
+ (let ((xor_const XmmMem (emit_u128_le_const 0x8000_8000_8000_8000_8000_8000_8000_8000))
3771
+ (dst Xmm (x64_pxor val xor_const))
3772
+
3773
+ (madd_const XmmMem (emit_u128_le_const 0x0001_0001_0001_0001_0001_0001_0001_0001))
3774
+ (dst Xmm (x64_pmaddwd dst madd_const))
3775
+
3776
+ (addd_const XmmMem (emit_u128_le_const 0x00010000_00010000_00010000_00010000)))
3777
+ (x64_paddd dst addd_const)))
3778
+
3779
+ ;; special case for the `i32x4.dot_i16x8_s` wasm instruction
3780
+ (rule 2 (lower
3781
+ (has_type $I32X4 (iadd_pairwise
3782
+ (imul (swiden_low x) (swiden_low y))
3783
+ (imul (swiden_high x) (swiden_high y)))))
3784
+ (x64_pmaddwd x y))
3785
+
3786
+ ;; Rules for `swiden_low` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3787
+
3788
+ ;; With SSE4.1 use the `pmovsx*` instructions for this
3789
+ (rule 1 (lower (has_type $I16X8 (swiden_low val @ (value_type $I8X16))))
3790
+ (if-let $true (use_sse41))
3791
+ (x64_pmovsxbw val))
3792
+ (rule 1 (lower (has_type $I32X4 (swiden_low val @ (value_type $I16X8))))
3793
+ (if-let $true (use_sse41))
3794
+ (x64_pmovsxwd val))
3795
+ (rule 1 (lower (has_type $I64X2 (swiden_low val @ (value_type $I32X4))))
3796
+ (if-let $true (use_sse41))
3797
+ (x64_pmovsxdq val))
3798
+
3799
+ (rule (lower (has_type ty (swiden_low val))) (lower_swiden_low ty val))
3800
+
3801
+ (decl lower_swiden_low (Type Xmm) Xmm)
3802
+
3803
+ ;; Duplicate the low lanes next to each other, then perform a wider shift-right
3804
+ ;; by the low lane width to move the upper of each pair back into the lower lane
3805
+ ;; of each pair, achieving the widening of the lower lanes.
3806
+ (rule (lower_swiden_low $I16X8 val)
3807
+ (x64_psraw (x64_punpcklbw val val) (xmi_imm 8)))
3808
+ (rule (lower_swiden_low $I32X4 val)
3809
+ (x64_psrad (x64_punpcklwd val val) (xmi_imm 16)))
3810
+
3811
+ ;; Generate the sign-extended halves with a `val < 0` comparison (expressed
3812
+ ;; reversed here), then interleave the low 32-bit halves to create the full
3813
+ ;; 64-bit results.
3814
+ (rule (lower_swiden_low $I64X2 val)
3815
+ (let ((tmp Xmm (x64_pcmpgtd (xmm_zero $I32X4) val)))
3816
+ (x64_punpckldq val tmp)))
3817
+
3818
+ ;; Rules for `swiden_high` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3819
+
3820
+ ;; Similar to `swiden_low` with SSE4.1 except that the upper lanes are moved
3821
+ ;; to the lower lanes first.
3822
+ (rule 1 (lower (has_type $I16X8 (swiden_high val @ (value_type $I8X16))))
3823
+ (if-let $true (use_sse41))
3824
+ (if-let $true (use_ssse3))
3825
+ (let ((x Xmm val))
3826
+ (x64_pmovsxbw (x64_palignr x x 8))))
3827
+ (rule 1 (lower (has_type $I32X4 (swiden_high val @ (value_type $I16X8))))
3828
+ (if-let $true (use_sse41))
3829
+ (if-let $true (use_ssse3))
3830
+ (let ((x Xmm val))
3831
+ (x64_pmovsxwd (x64_palignr x x 8))))
3832
+ (rule 1 (lower (has_type $I64X2 (swiden_high val @ (value_type $I32X4))))
3833
+ (if-let $true (use_sse41))
3834
+ (x64_pmovsxdq (x64_pshufd val 0b11_10_11_10)))
3835
+
3836
+ ;; Similar to `swiden_low` versions but using `punpckh*` instructions to
3837
+ ;; pair the high lanes next to each other.
3838
+ (rule (lower (has_type $I16X8 (swiden_high val @ (value_type $I8X16))))
3839
+ (let ((val Xmm val))
3840
+ (x64_psraw (x64_punpckhbw val val) (xmi_imm 8))))
3841
+ (rule (lower (has_type $I32X4 (swiden_high val @ (value_type $I16X8))))
3842
+ (let ((val Xmm val))
3843
+ (x64_psrad (x64_punpckhwd val val) (xmi_imm 16))))
3844
+
3845
+ ;; Same as `swiden_low`, but `val` has its high lanes moved down.
3846
+ (rule (lower (has_type $I64X2 (swiden_high val @ (value_type $I32X4))))
3847
+ (let ((val Xmm (x64_pshufd val 0b00_00_11_10))
3848
+ (tmp Xmm (x64_pcmpgtd (xmm_zero $I32X4) val)))
3849
+ (x64_punpckldq val tmp)))
3850
+
3851
+ ;; Rules for `uwiden_low` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3852
+
3853
+ ;; With SSE4.1 use the `pmovzx*` instructions for this
3854
+ (rule 1 (lower (has_type $I16X8 (uwiden_low val @ (value_type $I8X16))))
3855
+ (if-let $true (use_sse41))
3856
+ (x64_pmovzxbw val))
3857
+ (rule 1 (lower (has_type $I32X4 (uwiden_low val @ (value_type $I16X8))))
3858
+ (if-let $true (use_sse41))
3859
+ (x64_pmovzxwd val))
3860
+ (rule 1 (lower (has_type $I64X2 (uwiden_low val @ (value_type $I32X4))))
3861
+ (if-let $true (use_sse41))
3862
+ (x64_pmovzxdq val))
3863
+
3864
+ (rule (lower (has_type ty (uwiden_low val))) (lower_uwiden_low ty val))
3865
+
3866
+ ;; Interleave an all-zero register with the low lanes to produce zero-extended
3867
+ ;; results.
3868
+ (decl lower_uwiden_low (Type Xmm) Xmm)
3869
+ (rule (lower_uwiden_low $I16X8 val) (x64_punpcklbw val (xmm_zero $I8X16)))
3870
+ (rule (lower_uwiden_low $I32X4 val) (x64_punpcklwd val (xmm_zero $I8X16)))
3871
+ (rule (lower_uwiden_low $I64X2 val) (x64_unpcklps val (xmm_zero $F32X4)))
3872
+
3873
+ ;; Rules for `uwiden_high` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3874
+
3875
+ ;; Same as `uwiden_high`, but interleaving high lanes instead.
3876
+ ;;
3877
+ ;; Note that according to `llvm-mca` at least these instructions are faster
3878
+ ;; than using `pmovzx*` in terms of cycles, even if SSE4.1 is available.
3879
+ (rule (lower (has_type $I16X8 (uwiden_high val @ (value_type $I8X16))))
3880
+ (x64_punpckhbw val (xmm_zero $I8X16)))
3881
+ (rule (lower (has_type $I32X4 (uwiden_high val @ (value_type $I16X8))))
3882
+ (x64_punpckhwd val (xmm_zero $I8X16)))
3883
+ (rule (lower (has_type $I64X2 (uwiden_high val @ (value_type $I32X4))))
3884
+ (x64_unpckhps val (xmm_zero $F32X4)))
3885
+
3886
+ ;; Rules for `snarrow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3887
+
3888
+ (rule (lower (has_type $I8X16 (snarrow a @ (value_type $I16X8) b)))
3889
+ (x64_packsswb a b))
3890
+
3891
+ (rule (lower (has_type $I16X8 (snarrow a @ (value_type $I32X4) b)))
3892
+ (x64_packssdw a b))
3893
+
3894
+ ;; We're missing a `snarrow` case for $I64X2
3895
+ ;; https://github.com/bytecodealliance/wasmtime/issues/4734
3896
+
3897
+ ;; This rule is a special case for handling the translation of the wasm op
3898
+ ;; `i32x4.trunc_sat_f64x2_s_zero`. It can be removed once we have an
3899
+ ;; implementation of `snarrow` for `I64X2`.
3900
+ (rule (lower (has_type $I32X4 (snarrow (has_type $I64X2 (fcvt_to_sint_sat val))
3901
+ (vconst (u128_from_constant 0)))))
3902
+ (let ((a Xmm val)
3903
+
3904
+ ;; y = i32x4.trunc_sat_f64x2_s_zero(x) is lowered to:
3905
+ ;; MOVE xmm_tmp, xmm_x
3906
+ ;; CMPEQPD xmm_tmp, xmm_x
3907
+ ;; MOVE xmm_y, xmm_x
3908
+ ;; ANDPS xmm_tmp, [wasm_f64x2_splat(2147483647.0)]
3909
+ ;; MINPD xmm_y, xmm_tmp
3910
+ ;; CVTTPD2DQ xmm_y, xmm_y
3911
+
3912
+ (tmp1 Xmm (x64_cmppd a a (FcmpImm.Equal)))
3913
+
3914
+ ;; 2147483647.0 is equivalent to 0x41DFFFFFFFC00000
3915
+ (umax_mask XmmMem (emit_u128_le_const 0x41DFFFFFFFC00000_41DFFFFFFFC00000))
3916
+
3917
+ ;; ANDPD xmm_y, [wasm_f64x2_splat(2147483647.0)]
3918
+ (tmp1 Xmm (x64_andps tmp1 umax_mask))
3919
+ (dst Xmm (x64_minpd a tmp1)))
3920
+ (x64_cvttpd2dq dst)))
3921
+
3922
+ ;; This rule is a special case for handling the translation of the wasm op
3923
+ ;; `i32x4.relaxed_trunc_f64x2_s_zero`.
3924
+ (rule (lower (has_type $I32X4 (snarrow (has_type $I64X2 (x86_cvtt2dq val))
3925
+ (vconst (u128_from_constant 0)))))
3926
+ (x64_cvttpd2dq val))
3927
+
3928
+ ;; Rules for `unarrow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3929
+
3930
+ (rule (lower (has_type $I8X16 (unarrow a @ (value_type $I16X8) b)))
3931
+ (x64_packuswb a b))
3932
+
3933
+ (rule 1 (lower (has_type $I16X8 (unarrow a @ (value_type $I32X4) b)))
3934
+ (if-let $true (use_sse41))
3935
+ (x64_packusdw a b))
3936
+
3937
+ ;; For each input `a` and `b` take the four 32-bit lanes and compress them to
3938
+ ;; the low 64-bits of the vector as four 16-bit lanes. Then these are woven
3939
+ ;; into one final vector with a `punpcklqdq`.
3940
+ ;;
3941
+ ;; If this is performance sensitive then it's probably best to upgrade the CPU
3942
+ ;; to get the above single-instruction lowering.
3943
+ (rule (lower (has_type $I16X8 (unarrow a @ (value_type $I32X4) b)))
3944
+ (let (
3945
+ (a Xmm (unarrow_i32x4_lanes_to_low_u16_lanes a))
3946
+ (b Xmm (unarrow_i32x4_lanes_to_low_u16_lanes b))
3947
+ )
3948
+ (x64_punpcklqdq a b)))
3949
+
3950
+ (decl unarrow_i32x4_lanes_to_low_u16_lanes (Xmm) Xmm)
3951
+ (rule (unarrow_i32x4_lanes_to_low_u16_lanes val)
3952
+ (let (
3953
+ ;; First convert all negative values in `val` to zero lanes.
3954
+ (val_gt_zero Xmm (x64_pcmpgtd val (xmm_zero $I32X4)))
3955
+ (val Xmm (x64_pand val val_gt_zero))
3956
+
3957
+ ;; Next clamp all larger-than-u16-max lanes to u16::MAX.
3958
+ (max Xmm (x64_movdqu_load (emit_u128_le_const 0x0000ffff_0000ffff_0000ffff_0000ffff)))
3959
+ (cmp Xmm (x64_pcmpgtd max val))
3960
+ (valid_lanes Xmm (x64_pand val cmp))
3961
+ (clamped_lanes Xmm (x64_pandn cmp max))
3962
+ (val Xmm (x64_por valid_lanes clamped_lanes))
3963
+
3964
+ ;; Within each 64-bit half of the 32x4 vector move the first 16 bits
3965
+ ;; and the third 16 bits to the bottom of the half. Afterwards
3966
+ ;; for the 32x4 vector move the first and third lanes to the bottom
3967
+ ;; lanes, which finishes up the conversion here as all the lanes
3968
+ ;; are now converted to 16-bit values in the low 4 lanes.
3969
+ (val Xmm (x64_pshuflw val 0b00_00_10_00))
3970
+ (val Xmm (x64_pshufhw val 0b00_00_10_00))
3971
+ )
3972
+ (x64_pshufd val 0b00_00_10_00)))
3973
+
3974
+
3975
+ ;; We're missing a `unarrow` case for $I64X2
3976
+ ;; https://github.com/bytecodealliance/wasmtime/issues/4734
3977
+
3978
+ ;; Rules for `bitcast` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3979
+
3980
+ (rule (lower (has_type $I32 (bitcast _ src @ (value_type $F32))))
3981
+ (bitcast_xmm_to_gpr $F32 src))
3982
+
3983
+ (rule (lower (has_type $F32 (bitcast _ src @ (value_type $I32))))
3984
+ (bitcast_gpr_to_xmm $I32 src))
3985
+
3986
+ (rule (lower (has_type $I64 (bitcast _ src @ (value_type $F64))))
3987
+ (bitcast_xmm_to_gpr $F64 src))
3988
+
3989
+ (rule (lower (has_type $F64 (bitcast _ src @ (value_type $I64))))
3990
+ (bitcast_gpr_to_xmm $I64 src))
3991
+
3992
+ ;; Bitcast between types residing in GPR registers is a no-op.
3993
+ (rule 1 (lower (has_type (is_gpr_type _)
3994
+ (bitcast _ x @ (value_type (is_gpr_type _)))))
3995
+ x)
3996
+
3997
+ ;; Bitcasts between `r{32,64}` and `i{32,64}` need to be a copy to avoid
3998
+ ;; conflicting regalloc constraints on reference type values that both need to
3999
+ ;; be in some register but also some safepoint stack slot at the same time.
4000
+ (rule 2 (lower (has_type (is_gpr_type dst_ty)
4001
+ (bitcast _ x @ (value_type (is_gpr_type src_ty)))))
4002
+ (if-let $true (is_ref_type src_ty))
4003
+ (if-let $false (is_ref_type dst_ty))
4004
+ (copy_gpr dst_ty x))
4005
+ (rule 2 (lower (has_type (is_gpr_type dst_ty)
4006
+ (bitcast _ x @ (value_type (is_gpr_type src_ty)))))
4007
+ (if-let $false (is_ref_type src_ty))
4008
+ (if-let $true (is_ref_type dst_ty))
4009
+ (copy_gpr dst_ty x))
4010
+
4011
+ ;; Bitcast between types residing in XMM registers is a no-op.
4012
+ (rule 3 (lower (has_type (is_xmm_type _)
4013
+ (bitcast _ x @ (value_type (is_xmm_type _)))))
4014
+ x)
4015
+
4016
+ ;; Rules for `fcopysign` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4017
+
4018
+ (rule (lower (has_type $F32 (fcopysign a @ (value_type $F32) b)))
4019
+ (let ((sign_bit Xmm (imm $F32 0x80000000)))
4020
+ (x64_orps
4021
+ (x64_andnps sign_bit a)
4022
+ (x64_andps sign_bit b))))
4023
+
4024
+ (rule (lower (has_type $F64 (fcopysign a @ (value_type $F64) b)))
4025
+ (let ((sign_bit Xmm (imm $F64 0x8000000000000000)))
4026
+ (x64_orpd
4027
+ (x64_andnpd sign_bit a)
4028
+ (x64_andpd sign_bit b))))
4029
+
4030
+ ;; Helper for the `ceil`/`floor`/`nearest`/`trunc` instructions ;;;;;;;;;;;;;;;;
4031
+
4032
+ ;; Emits either a `round{ss,sd,ps,pd}` instruction, as appropriate, or generates
4033
+ ;; the appropriate libcall and sequence to call that.
4034
+ (decl x64_round (Type RegMem RoundImm) Xmm)
4035
+ (rule 1 (x64_round $F32 a imm)
4036
+ (if-let $true (use_sse41))
4037
+ (x64_roundss a imm))
4038
+ (rule 1 (x64_round $F64 a imm)
4039
+ (if-let $true (use_sse41))
4040
+ (x64_roundsd a imm))
4041
+ (rule 1 (x64_round $F32X4 a imm)
4042
+ (if-let $true (use_sse41))
4043
+ (x64_roundps a imm))
4044
+ (rule 1 (x64_round $F64X2 a imm)
4045
+ (if-let $true (use_sse41))
4046
+ (x64_roundpd a imm))
4047
+
4048
+ (rule (x64_round $F32 (RegMem.Reg a) imm) (libcall_1 (round_libcall $F32 imm) a))
4049
+ (rule (x64_round $F64 (RegMem.Reg a) imm) (libcall_1 (round_libcall $F64 imm) a))
4050
+ (rule (x64_round $F32X4 (RegMem.Reg a) imm)
4051
+ (let (
4052
+ (libcall LibCall (round_libcall $F32 imm))
4053
+ (result Xmm (libcall_1 libcall a))
4054
+ (a1 Xmm (libcall_1 libcall (x64_pshufd a 1)))
4055
+ (result Xmm (f32x4_insertlane result a1 1))
4056
+ (a2 Xmm (libcall_1 libcall (x64_pshufd a 2)))
4057
+ (result Xmm (f32x4_insertlane result a2 2))
4058
+ (a3 Xmm (libcall_1 libcall (x64_pshufd a 3)))
4059
+ (result Xmm (f32x4_insertlane result a3 3))
4060
+ )
4061
+ result))
4062
+ (rule (x64_round $F64X2 (RegMem.Reg a) imm)
4063
+ (let (
4064
+ (libcall LibCall (round_libcall $F64 imm))
4065
+ (result Xmm (libcall_1 libcall a))
4066
+ (a1 Xmm (libcall_1 libcall (x64_pshufd a 0b00_00_11_10)))
4067
+ )
4068
+ (x64_movlhps result a1)))
4069
+ (rule (x64_round ty (RegMem.Mem addr) imm)
4070
+ (x64_round ty (RegMem.Reg (x64_load ty addr (ExtKind.ZeroExtend))) imm))
4071
+
4072
+ (decl round_libcall (Type RoundImm) LibCall)
4073
+ (rule (round_libcall $F32 (RoundImm.RoundUp)) (LibCall.CeilF32))
4074
+ (rule (round_libcall $F64 (RoundImm.RoundUp)) (LibCall.CeilF64))
4075
+ (rule (round_libcall $F32 (RoundImm.RoundDown)) (LibCall.FloorF32))
4076
+ (rule (round_libcall $F64 (RoundImm.RoundDown)) (LibCall.FloorF64))
4077
+ (rule (round_libcall $F32 (RoundImm.RoundNearest)) (LibCall.NearestF32))
4078
+ (rule (round_libcall $F64 (RoundImm.RoundNearest)) (LibCall.NearestF64))
4079
+ (rule (round_libcall $F32 (RoundImm.RoundZero)) (LibCall.TruncF32))
4080
+ (rule (round_libcall $F64 (RoundImm.RoundZero)) (LibCall.TruncF64))
4081
+
4082
+ ;; Rules for `ceil` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4083
+
4084
+ (rule (lower (ceil a @ (value_type ty)))
4085
+ (x64_round ty a (RoundImm.RoundUp)))
4086
+
4087
+ ;; Rules for `floor` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4088
+
4089
+ (rule (lower (floor a @ (value_type ty)))
4090
+ (x64_round ty a (RoundImm.RoundDown)))
4091
+
4092
+ ;; Rules for `nearest` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4093
+
4094
+ (rule (lower (nearest a @ (value_type ty)))
4095
+ (x64_round ty a (RoundImm.RoundNearest)))
4096
+
4097
+ ;; Rules for `trunc` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4098
+
4099
+ (rule (lower (trunc a @ (value_type ty)))
4100
+ (x64_round ty a (RoundImm.RoundZero)))
4101
+
4102
+ ;; Rules for `stack_addr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4103
+
4104
+ (rule (lower (stack_addr stack_slot offset))
4105
+ (stack_addr_impl stack_slot offset))
4106
+
4107
+ ;; Rules for `udiv` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4108
+
4109
+ ;; NB: a `RegMem` divisor, while allowed in the instruction encoding, isn't
4110
+ ;; used right now to prevent a possibly-trapping load getting folded into the
4111
+ ;; `div` instruction. Ideally non-trapping loads would get folded, however, or
4112
+ ;; alternatively Wasmtime/Cranelift would grow support for multiple traps on
4113
+ ;; a single opcode and the signal kind would differentiate at runtime.
4114
+
4115
+ ;; The inputs to the `div` instruction are different for 8-bit division so
4116
+ ;; it needs a special case here since the instruction being crafted has a
4117
+ ;; different shape.
4118
+ (rule 2 (lower (udiv a @ (value_type $I8) b))
4119
+ (x64_div8 (extend_to_gpr a $I32 (ExtendKind.Zero))
4120
+ (put_in_gpr b)
4121
+ (DivSignedness.Unsigned)
4122
+ (TrapCode.IntegerDivisionByZero)))
4123
+
4124
+ ;; 16-to-64-bit division is all done with a similar instruction and the only
4125
+ ;; tricky requirement here is that when div traps are disallowed the divisor
4126
+ ;; must not be zero.
4127
+ (rule 1 (lower (udiv a @ (value_type (fits_in_64 ty)) b))
4128
+ (x64_div_quotient a
4129
+ (imm $I64 0)
4130
+ (put_in_gpr b)
4131
+ (raw_operand_size_of_type ty)
4132
+ (DivSignedness.Unsigned)
4133
+ (TrapCode.IntegerDivisionByZero)))
4134
+
4135
+ ;; Rules for `sdiv` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4136
+
4137
+ (rule 2 (lower (sdiv a @ (value_type $I8) b))
4138
+ (x64_div8 (x64_sign_extend_data a (OperandSize.Size8))
4139
+ (nonzero_sdiv_divisor $I8 b)
4140
+ (DivSignedness.Signed)
4141
+ (TrapCode.IntegerOverflow)))
4142
+
4143
+ (rule 1 (lower (sdiv a @ (value_type (fits_in_64 ty)) b))
4144
+ (let (
4145
+ (a Gpr a)
4146
+ (size OperandSize (raw_operand_size_of_type ty))
4147
+ )
4148
+ (x64_div_quotient a
4149
+ (x64_sign_extend_data a size)
4150
+ (nonzero_sdiv_divisor ty b)
4151
+ size
4152
+ (DivSignedness.Signed)
4153
+ (TrapCode.IntegerOverflow))))
4154
+
4155
+ ;; Checks to make sure that the input `Value` is a non-zero value for `sdiv`.
4156
+ ;;
4157
+ ;; This is required to differentiate the divide-by-zero trap from the
4158
+ ;; integer-overflow trap, the two trapping conditions of signed division.
4159
+ (decl nonzero_sdiv_divisor (Type Value) Reg)
4160
+ (rule 1 (nonzero_sdiv_divisor ty (iconst imm))
4161
+ (if-let n (safe_divisor_from_imm64 ty imm))
4162
+ (imm ty n))
4163
+ (rule 0 (nonzero_sdiv_divisor ty val)
4164
+ (let (
4165
+ (val Reg val)
4166
+ (_ InstOutput (side_effect (with_flags_side_effect
4167
+ (x64_test (raw_operand_size_of_type ty) val val)
4168
+ (trap_if (CC.Z) (TrapCode.IntegerDivisionByZero)))))
4169
+ )
4170
+ val))
4171
+
4172
+ ;; Rules for `urem` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4173
+
4174
+ ;; The remainder is in AH, so take the result of the division and right-shift
4175
+ ;; by 8.
4176
+ (rule 2 (lower (urem a @ (value_type $I8) b))
4177
+ (let (
4178
+ (result Gpr (x64_div8 (extend_to_gpr a $I32 (ExtendKind.Zero))
4179
+ (put_in_gpr b) ;; see `udiv` for why not `gpr_mem`
4180
+ (DivSignedness.Unsigned)
4181
+ (TrapCode.IntegerDivisionByZero)))
4182
+ )
4183
+ (x64_shr $I64 result (Imm8Reg.Imm8 8))))
4184
+
4185
+ (rule 1 (lower (urem a @ (value_type (fits_in_64 ty)) b))
4186
+ (x64_div_remainder a
4187
+ (imm $I64 0)
4188
+ (put_in_gpr b) ;; see `udiv` for why not `gpr_mem`
4189
+ (raw_operand_size_of_type ty)
4190
+ (DivSignedness.Unsigned)
4191
+ (TrapCode.IntegerDivisionByZero)))
4192
+
4193
+ ;; Rules for `srem` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4194
+
4195
+ ;; Special-cases first for constant `srem` where the checks for 0 and -1 aren't
4196
+ ;; applicable.
4197
+ ;;
4198
+ ;; Note that like `urem` for i8 types the result is in AH so to get the result
4199
+ ;; it's right-shifted down.
4200
+ (rule 3 (lower (srem a @ (value_type $I8) (iconst imm)))
4201
+ (if-let n (safe_divisor_from_imm64 $I8 imm))
4202
+ (let (
4203
+ (a Gpr (x64_sign_extend_data a (OperandSize.Size8)))
4204
+ (result Gpr (x64_div8 a (imm $I8 n) (DivSignedness.Signed) (TrapCode.IntegerDivisionByZero)))
4205
+ )
4206
+ (x64_shr $I64 result (Imm8Reg.Imm8 8))))
4207
+
4208
+ ;; Same as the above rule but for 16-to-64 bit types.
4209
+ (rule 2 (lower (srem a @ (value_type ty) (iconst imm)))
4210
+ (if-let n (safe_divisor_from_imm64 ty imm))
4211
+ (let (
4212
+ (a Gpr a)
4213
+ (size OperandSize (raw_operand_size_of_type ty))
4214
+ )
4215
+ (x64_div_remainder a
4216
+ (x64_sign_extend_data a size)
4217
+ (imm ty n)
4218
+ size
4219
+ (DivSignedness.Signed)
4220
+ (TrapCode.IntegerDivisionByZero))))
4221
+
4222
+ (rule 1 (lower (srem a @ (value_type $I8) b))
4223
+ (let (
4224
+ (a Gpr (x64_sign_extend_data a (OperandSize.Size8)))
4225
+ )
4226
+ (x64_shr $I64 (x64_checked_srem_seq8 a b) (Imm8Reg.Imm8 8))))
4227
+
4228
+ (rule (lower (srem a @ (value_type ty) b))
4229
+ (let (
4230
+ (a Gpr a)
4231
+ (size OperandSize (raw_operand_size_of_type ty))
4232
+ (hi Gpr (x64_sign_extend_data a size))
4233
+ (tmp ValueRegs (x64_checked_srem_seq size a hi b))
4234
+ )
4235
+ (value_regs_get tmp 1)))
4236
+
4237
+ ;; Rules for `umulhi` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4238
+
4239
+ (rule 0 (lower (umulhi a @ (value_type $I8) b))
4240
+ (x64_shr $I16 (x64_mul8 $false a b) (imm8_to_imm8_gpr 8)))
4241
+
4242
+ (rule 1 (lower (umulhi a @ (value_type (ty_int_ref_16_to_64 ty)) b))
4243
+ (value_regs_get_gpr (x64_mul ty $false a b) 1))
4244
+
4245
+ ;; Rules for `smulhi` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4246
+
4247
+ (rule 0 (lower (smulhi a @ (value_type $I8) b))
4248
+ (x64_sar $I16 (x64_mul8 $true a b) (imm8_to_imm8_gpr 8)))
4249
+
4250
+ (rule 1 (lower (smulhi a @ (value_type (ty_int_ref_16_to_64 ty)) b))
4251
+ (value_regs_get_gpr (x64_mul ty $true a b) 1))
4252
+
4253
+ ;; Rules for `get_pinned_reg` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4254
+
4255
+ (rule (lower (get_pinned_reg))
4256
+ (read_pinned_gpr))
4257
+
4258
+ ;; Rules for `set_pinned_reg` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4259
+
4260
+ (rule (lower (set_pinned_reg a @ (value_type ty)))
4261
+ (side_effect (write_pinned_gpr a)))
4262
+
4263
+ ;; Rules for `vconst` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4264
+
4265
+ (rule (lower (has_type ty (vconst const)))
4266
+ ;; TODO use Inst::gen_constant() instead.
4267
+ (x64_xmm_load_const ty (const_to_vconst const)))
4268
+
4269
+ ;; Special case for a zero-vector: don't load, xor instead.
4270
+ (rule 1 (lower (has_type ty (vconst (u128_from_constant 0))))
4271
+ (let ((dst Xmm (xmm_uninit_value)))
4272
+ (x64_pxor dst dst)))
4273
+
4274
+ ;; Rules for `shuffle` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4275
+
4276
+ ;; Special case for `pblendw` which takes an 8-bit immediate where each bit
4277
+ ;; indicates which lane of the two operands is chosen for the output. A bit of
4278
+ ;; 0 chooses the corresponding 16-it lane from `a` and a bit of 1 chooses the
4279
+ ;; corresponding 16-bit lane from `b`.
4280
+ (rule 14 (lower (shuffle a b (pblendw_imm n)))
4281
+ (if-let $true (use_sse41))
4282
+ (x64_pblendw a b n))
4283
+ (decl pblendw_imm (u8) Immediate)
4284
+ (extern extractor pblendw_imm pblendw_imm)
4285
+
4286
+ ;; When the shuffle looks like "concatenate `a` and `b` and shift right by n*8
4287
+ ;; bytes", that's a `palignr` instruction. Note that the order of operands are
4288
+ ;; swapped in the instruction here. The `palignr` instruction uses the second
4289
+ ;; operand as the low-order bytes and the first operand as high-order bytes,
4290
+ ;; so put `a` second.
4291
+ (rule 13 (lower (shuffle a b (palignr_imm_from_immediate n)))
4292
+ (if-let $true (use_ssse3))
4293
+ (x64_palignr b a n))
4294
+ (decl palignr_imm_from_immediate (u8) Immediate)
4295
+ (extern extractor palignr_imm_from_immediate palignr_imm_from_immediate)
4296
+
4297
+ ;; Special case the `pshuf{l,h}w` instruction which shuffles four 16-bit
4298
+ ;; integers within one value, preserving the other four 16-bit integers in that
4299
+ ;; value (either the high or low half). The complicated logic is in the
4300
+ ;; extractors here implemented in Rust and note that there's two cases for each
4301
+ ;; instruction here to match when either the first or second shuffle operand is
4302
+ ;; used.
4303
+ (rule 12 (lower (shuffle x y (pshuflw_lhs_imm imm)))
4304
+ (x64_pshuflw x imm))
4305
+ (rule 11 (lower (shuffle x y (pshuflw_rhs_imm imm)))
4306
+ (x64_pshuflw y imm))
4307
+ (rule 10 (lower (shuffle x y (pshufhw_lhs_imm imm)))
4308
+ (x64_pshufhw x imm))
4309
+ (rule 9 (lower (shuffle x y (pshufhw_rhs_imm imm)))
4310
+ (x64_pshufhw y imm))
4311
+
4312
+ (decl pshuflw_lhs_imm (u8) Immediate)
4313
+ (extern extractor pshuflw_lhs_imm pshuflw_lhs_imm)
4314
+ (decl pshuflw_rhs_imm (u8) Immediate)
4315
+ (extern extractor pshuflw_rhs_imm pshuflw_rhs_imm)
4316
+ (decl pshufhw_lhs_imm (u8) Immediate)
4317
+ (extern extractor pshufhw_lhs_imm pshufhw_lhs_imm)
4318
+ (decl pshufhw_rhs_imm (u8) Immediate)
4319
+ (extern extractor pshufhw_rhs_imm pshufhw_rhs_imm)
4320
+
4321
+ ;; Special case for the `pshufd` instruction which will permute 32-bit values
4322
+ ;; within a single register. This is only applicable if the `imm` specified
4323
+ ;; selects 32-bit values from either `x` or `y`, but not both. This means
4324
+ ;; there's one rule for selecting from `x` and another rule for selecting from
4325
+ ;; `y`.
4326
+ (rule 8 (lower (shuffle x y (pshufd_lhs_imm imm)))
4327
+ (x64_pshufd x imm))
4328
+ (rule 7 (lower (shuffle x y (pshufd_rhs_imm imm)))
4329
+ (x64_pshufd y imm))
4330
+
4331
+ (decl pshufd_lhs_imm (u8) Immediate)
4332
+ (extern extractor pshufd_lhs_imm pshufd_lhs_imm)
4333
+ (decl pshufd_rhs_imm (u8) Immediate)
4334
+ (extern extractor pshufd_rhs_imm pshufd_rhs_imm)
4335
+
4336
+ ;; Special case for i8-level interleaving of upper/low bytes.
4337
+ (rule 6 (lower (shuffle a b (u128_from_immediate 0x1f0f_1e0e_1d0d_1c0c_1b0b_1a0a_1909_1808)))
4338
+ (x64_punpckhbw a b))
4339
+ (rule 6 (lower (shuffle a b (u128_from_immediate 0x1707_1606_1505_1404_1303_1202_1101_1000)))
4340
+ (x64_punpcklbw a b))
4341
+
4342
+ ;; Special case for i16-level interleaving of upper/low bytes.
4343
+ (rule 6 (lower (shuffle a b (u128_from_immediate 0x1f1e_0f0e_1d1c_0d0c_1b1a_0b0a_1918_0908)))
4344
+ (x64_punpckhwd a b))
4345
+ (rule 6 (lower (shuffle a b (u128_from_immediate 0x1716_0706_1514_0504_1312_0302_1110_0100)))
4346
+ (x64_punpcklwd a b))
4347
+
4348
+ ;; Special case for i32-level interleaving of upper/low bytes.
4349
+ (rule 6 (lower (shuffle a b (u128_from_immediate 0x1f1e1d1c_0f0e0d0c_1b1a1918_0b0a0908)))
4350
+ (x64_punpckhdq a b))
4351
+ (rule 6 (lower (shuffle a b (u128_from_immediate 0x17161514_07060504_13121110_03020100)))
4352
+ (x64_punpckldq a b))
4353
+
4354
+ ;; Special case for i64-level interleaving of upper/low bytes.
4355
+ (rule 6 (lower (shuffle a b (u128_from_immediate 0x1f1e1d1c1b1a1918_0f0e0d0c0b0a0908)))
4356
+ (x64_punpckhqdq a b))
4357
+ (rule 6 (lower (shuffle a b (u128_from_immediate 0x1716151413121110_0706050403020100)))
4358
+ (x64_punpcklqdq a b))
4359
+
4360
+ ;; If the vector shift mask is all 0s then that means the first byte of the
4361
+ ;; first operand is broadcast to all bytes. Falling through would load an
4362
+ ;; all-zeros constant from a rip-relative location but it should be slightly
4363
+ ;; more efficient to execute the `pshufb` here-and-now with an xor'd-to-be-zero
4364
+ ;; register.
4365
+ (rule 6 (lower (shuffle a _ (u128_from_immediate 0)))
4366
+ (if-let $true (use_ssse3))
4367
+ (x64_pshufb a (xmm_zero $I8X16)))
4368
+
4369
+ ;; Special case for the `shufps` instruction which will select two 32-bit values
4370
+ ;; from the first operand and two 32-bit values from the second operand. Note
4371
+ ;; that there is a second case here as well for when the operands can be
4372
+ ;; swapped.
4373
+ ;;
4374
+ ;; Note that the priority of this instruction is currently lower than the above
4375
+ ;; special cases since `shufps` handles many of them and for now it's
4376
+ ;; hypothesized that the dedicated instructions are better than `shufps`.
4377
+ ;; Someone with more knowledge about x86 timings should perhaps reorder the
4378
+ ;; rules here eventually though.
4379
+ (rule 5 (lower (shuffle x y (shufps_imm imm)))
4380
+ (x64_shufps x y imm))
4381
+ (rule 4 (lower (shuffle x y (shufps_rev_imm imm)))
4382
+ (x64_shufps y x imm))
4383
+
4384
+ (decl shufps_imm(u8) Immediate)
4385
+ (extern extractor shufps_imm shufps_imm)
4386
+ (decl shufps_rev_imm(u8) Immediate)
4387
+ (extern extractor shufps_rev_imm shufps_rev_imm)
4388
+
4389
+
4390
+ ;; If `lhs` and `rhs` are the same we can use a single PSHUFB to shuffle the XMM
4391
+ ;; register. We statically build `constructed_mask` to zero out any unknown lane
4392
+ ;; indices (may not be completely necessary: verification could fail incorrect
4393
+ ;; mask values) and fix the indexes to all point to the `dst` vector.
4394
+ (rule 3 (lower (shuffle a a (vec_mask_from_immediate mask)))
4395
+ (if-let $true (use_ssse3))
4396
+ (x64_pshufb a (shuffle_0_31_mask mask)))
4397
+
4398
+ ;; For the case where the shuffle mask contains out-of-bounds values (values
4399
+ ;; greater than 31) we must mask off those resulting values in the result of
4400
+ ;; `vpermi2b`.
4401
+ (rule 2 (lower (shuffle a b (vec_mask_from_immediate (perm_from_mask_with_zeros mask zeros))))
4402
+ (if-let $true (use_avx512vl))
4403
+ (if-let $true (use_avx512vbmi))
4404
+ (x64_andps (x64_vpermi2b (x64_xmm_load_const $I8X16 mask) a b) zeros))
4405
+
4406
+ ;; However, if the shuffle mask contains no out-of-bounds values, we can use
4407
+ ;; `vpermi2b` without any masking.
4408
+ (rule 1 (lower (shuffle a b (vec_mask_from_immediate mask)))
4409
+ (if-let $true (use_avx512vl))
4410
+ (if-let $true (use_avx512vbmi))
4411
+ (x64_vpermi2b (x64_xmm_load_const $I8X16 (perm_from_mask mask)) a b))
4412
+
4413
+ ;; If `lhs` and `rhs` are different, we must shuffle each separately and then OR
4414
+ ;; them together. This is necessary due to PSHUFB semantics. As in the case
4415
+ ;; above, we build the `constructed_mask` for each case statically.
4416
+ (rule (lower (shuffle a b (vec_mask_from_immediate mask)))
4417
+ (x64_por
4418
+ (lower_pshufb a (shuffle_0_15_mask mask))
4419
+ (lower_pshufb b (shuffle_16_31_mask mask))))
4420
+
4421
+ ;; Rules for `swizzle` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4422
+
4423
+ ;; SIMD swizzle; the following inefficient implementation is due to the Wasm
4424
+ ;; SIMD spec requiring mask indexes greater than 15 to have the same semantics
4425
+ ;; as a 0 index. For the spec discussion, see
4426
+ ;; https://github.com/WebAssembly/simd/issues/93. The CLIF semantics match the
4427
+ ;; Wasm SIMD semantics for this instruction. The instruction format maps to
4428
+ ;; variables like: %dst = swizzle %src, %mask
4429
+ (rule (lower (swizzle src mask))
4430
+ (let ((mask Xmm (x64_paddusb mask (emit_u128_le_const 0x70707070707070707070707070707070))))
4431
+ (lower_pshufb src mask)))
4432
+
4433
+ ;; Rules for `x86_pshufb` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4434
+
4435
+ (rule (lower (x86_pshufb src mask))
4436
+ (if-let $true (use_ssse3))
4437
+ (x64_pshufb src mask))
4438
+
4439
+ ;; A helper function to generate either the `pshufb` instruction or a libcall to
4440
+ ;; the `X86Pshufb` libcall. Note that the libcall is not exactly the most
4441
+ ;; performant thing in the world so this is primarily here for completeness
4442
+ ;; of lowerings on all x86 cpus but if rules are ideally gated on the presence
4443
+ ;; of SSSE3 to use the `pshufb` instruction itself.
4444
+ (decl lower_pshufb (Xmm RegMem) Xmm)
4445
+ (rule 1 (lower_pshufb src mask)
4446
+ (if-let $true (use_ssse3))
4447
+ (x64_pshufb src mask))
4448
+ (rule (lower_pshufb src (RegMem.Reg mask))
4449
+ (libcall_2 (LibCall.X86Pshufb) src mask))
4450
+ (rule (lower_pshufb src (RegMem.Mem addr))
4451
+ (lower_pshufb src (x64_movdqu_load addr)))
4452
+
4453
+ ;; Rules for `extractlane` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4454
+
4455
+ ;; Remove the extractlane instruction, leaving the float where it is. The upper
4456
+ ;; bits will remain unchanged; for correctness, this relies on Cranelift type
4457
+ ;; checking to avoid using those bits.
4458
+ (rule 3 (lower (has_type (ty_scalar_float _) (extractlane val 0)))
4459
+ val)
4460
+
4461
+ ;; `f32x4.extract_lane N` where `N != 0`
4462
+ (rule 1 (lower (extractlane val @ (value_type $F32X4) (u8_from_uimm8 lane)))
4463
+ (x64_pshufd val lane))
4464
+
4465
+ ;; `f64x2.extract_lane N` where `N != 0` (aka N == 1)
4466
+ (rule (lower (extractlane val @ (value_type $F64X2) 1))
4467
+ (x64_pshufd val 0b11_10_11_10))
4468
+
4469
+ ;; `i8x16.extract_lane N`
4470
+ ;;
4471
+ ;; Note that without SSE4.1 a 16-bit lane extraction is performed and then
4472
+ ;; the result is updated if the desired index is either odd or even.
4473
+ (rule 2 (lower (extractlane val @ (value_type ty @ $I8X16) (u8_from_uimm8 lane)))
4474
+ (if-let $true (use_sse41))
4475
+ (x64_pextrb val lane))
4476
+ ;; extracting an odd lane has an extra shift-right
4477
+ (rule 1 (lower (extractlane val @ (value_type ty @ $I8X16) (u8_from_uimm8 lane)))
4478
+ (if-let 1 (u8_and lane 1))
4479
+ (x64_shr $I16 (x64_pextrw val (u8_shr lane 1)) (Imm8Reg.Imm8 8)))
4480
+ ;; Extracting an even lane already has the desired lane in the lower bits. Note
4481
+ ;; that having arbitrary upper bits in the returned register should be ok since
4482
+ ;; all operators on the resulting `i8` type should work correctly regardless of
4483
+ ;; the bits in the rest of the register.
4484
+ (rule (lower (extractlane val @ (value_type ty @ $I8X16) (u8_from_uimm8 lane)))
4485
+ (if-let 0 (u8_and lane 1))
4486
+ (x64_pextrw val (u8_shr lane 1)))
4487
+
4488
+ ;; `i16x8.extract_lane N`
4489
+ (rule (lower (extractlane val @ (value_type ty @ $I16X8) (u8_from_uimm8 lane)))
4490
+ (x64_pextrw val lane))
4491
+
4492
+ ;; `i32x4.extract_lane N`
4493
+ (rule 2 (lower (extractlane val @ (value_type ty @ $I32X4) (u8_from_uimm8 lane)))
4494
+ (if-let $true (use_sse41))
4495
+ (x64_pextrd val lane))
4496
+ (rule 1 (lower (extractlane val @ (value_type $I32X4) 0))
4497
+ (x64_movd_to_gpr val))
4498
+ (rule (lower (extractlane val @ (value_type $I32X4) (u8_from_uimm8 n)))
4499
+ (x64_movd_to_gpr (x64_pshufd val n)))
4500
+
4501
+ ;; `i64x2.extract_lane N`
4502
+ (rule 1 (lower (extractlane val @ (value_type $I64X2) (u8_from_uimm8 lane)))
4503
+ (if-let $true (use_sse41))
4504
+ (x64_pextrq val lane))
4505
+ (rule (lower (extractlane val @ (value_type $I64X2) 0))
4506
+ (x64_movq_to_gpr val))
4507
+ (rule (lower (extractlane val @ (value_type $I64X2) 1))
4508
+ (x64_movq_to_gpr (x64_pshufd val 0b00_00_11_10)))
4509
+
4510
+ ;; Rules for `scalar_to_vector` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4511
+
4512
+ ;; Case 1: when moving a scalar float, we simply move from one XMM register
4513
+ ;; to another, expecting the register allocator to elide this. Here we
4514
+ ;; assume that the upper bits of a scalar float have not been munged with
4515
+ ;; (the same assumption the old backend makes).
4516
+ (rule 1 (lower (scalar_to_vector src @ (value_type (ty_scalar_float _))))
4517
+ src)
4518
+
4519
+ ;; Case 2: when moving a scalar value of any other type, use MOVD to zero
4520
+ ;; the upper lanes.
4521
+ (rule (lower (scalar_to_vector src @ (value_type ty)))
4522
+ (bitcast_gpr_to_xmm ty src))
4523
+
4524
+ ;; Case 3: when presented with `load + scalar_to_vector`, coalesce into a single
4525
+ ;; MOVSS/MOVSD instruction.
4526
+ (rule 2 (lower (scalar_to_vector (and (sinkable_load src) (value_type (ty_32 _)))))
4527
+ (x64_movss_load src))
4528
+ (rule 3 (lower (scalar_to_vector (and (sinkable_load src) (value_type (ty_64 _)))))
4529
+ (x64_movsd_load src))
4530
+
4531
+ ;; Rules for `splat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4532
+
4533
+ ;; For all the splat rules below one of the goals is that splatting a value
4534
+ ;; doesn't end up accidentally depending on the previous value in a register.
4535
+ ;; This means that instructions are chosen to avoid false dependencies where
4536
+ ;; new values are created fresh or otherwise overwrite previous register
4537
+ ;; contents where possible.
4538
+ ;;
4539
+ ;; Additionally splats are specialized to special-case load-and-splat which
4540
+ ;; has a number of micro-optimizations available.
4541
+
4542
+ ;; i8x16 splats: use `vpbroadcastb` on AVX2 and otherwise `pshufb` broadcasts
4543
+ ;; with a mask of zero which is calculated with an xor-against-itself register.
4544
+ (rule 0 (lower (has_type $I8X16 (splat src)))
4545
+ (let ((src Xmm (x64_movd_to_xmm src)))
4546
+ (x64_pshufd (x64_pshuflw (x64_punpcklbw src src) 0) 0)))
4547
+ (rule 1 (lower (has_type $I8X16 (splat src)))
4548
+ (if-let $true (use_ssse3))
4549
+ (x64_pshufb (bitcast_gpr_to_xmm $I32 src) (xmm_zero $I8X16)))
4550
+ (rule 2 (lower (has_type $I8X16 (splat src)))
4551
+ (if-let $true (use_avx2))
4552
+ (x64_vpbroadcastb (bitcast_gpr_to_xmm $I32 src)))
4553
+ (rule 3 (lower (has_type $I8X16 (splat (sinkable_load_exact addr))))
4554
+ (if-let $true (use_sse41))
4555
+ (if-let $true (use_ssse3))
4556
+ (x64_pshufb (x64_pinsrb (xmm_uninit_value) addr 0) (xmm_zero $I8X16)))
4557
+ (rule 4 (lower (has_type $I8X16 (splat (sinkable_load_exact addr))))
4558
+ (if-let $true (use_avx2))
4559
+ (x64_vpbroadcastb addr))
4560
+
4561
+ ;; i16x8 splats: use `vpbroadcastw` on AVX2 and otherwise a 16-bit value is
4562
+ ;; loaded into an xmm register, `pshuflw` broadcasts the low 16-bit lane
4563
+ ;; to the low four lanes, and `pshufd` broadcasts the low 32-bit lane (which
4564
+ ;; at that point is two of the 16-bit values we want to broadcast) to all the
4565
+ ;; lanes.
4566
+ (rule 0 (lower (has_type $I16X8 (splat src)))
4567
+ (x64_pshufd (x64_pshuflw (bitcast_gpr_to_xmm $I32 src) 0) 0))
4568
+ (rule 1 (lower (has_type $I16X8 (splat src)))
4569
+ (if-let $true (use_avx2))
4570
+ (x64_vpbroadcastw (bitcast_gpr_to_xmm $I32 src)))
4571
+ (rule 2 (lower (has_type $I16X8 (splat (sinkable_load_exact addr))))
4572
+ (x64_pshufd (x64_pshuflw (x64_pinsrw (xmm_uninit_value) addr 0) 0) 0))
4573
+ (rule 3 (lower (has_type $I16X8 (splat (sinkable_load_exact addr))))
4574
+ (if-let $true (use_avx2))
4575
+ (x64_vpbroadcastw addr))
4576
+
4577
+ ;; i32x4.splat - use `vpbroadcastd` on AVX2 and otherwise `pshufd` can be
4578
+ ;; used to broadcast the low lane to all other lanes.
4579
+ ;;
4580
+ ;; Note that sinkable-load cases come later
4581
+ (rule 0 (lower (has_type $I32X4 (splat src)))
4582
+ (x64_pshufd (bitcast_gpr_to_xmm $I32 src) 0))
4583
+ (rule 1 (lower (has_type $I32X4 (splat src)))
4584
+ (if-let $true (use_avx2))
4585
+ (x64_vpbroadcastd (bitcast_gpr_to_xmm $I32 src)))
4586
+
4587
+ ;; f32x4.splat - the source is already in an xmm register so `shufps` is all
4588
+ ;; that's necessary to complete the splat. This is specialized to `vbroadcastss`
4589
+ ;; on AVX2 to leverage that specific instruction for this operation.
4590
+ (rule 0 (lower (has_type $F32X4 (splat src)))
4591
+ (let ((tmp Xmm src))
4592
+ (x64_shufps src src 0)))
4593
+ (rule 1 (lower (has_type $F32X4 (splat src)))
4594
+ (if-let $true (use_avx2))
4595
+ (x64_vbroadcastss src))
4596
+
4597
+ ;; t32x4.splat of a load - use a `movss` to load into an xmm register and then
4598
+ ;; `shufps` broadcasts to the other lanes. Note that this is used for both i32
4599
+ ;; and f32 splats.
4600
+ ;;
4601
+ ;; With AVX the `vbroadcastss` instruction suits this purpose precisely. Note
4602
+ ;; that the memory-operand encoding of `vbroadcastss` is usable with AVX, but
4603
+ ;; the register-based encoding is only available with AVX2. With the
4604
+ ;; `sinkable_load` extractor this should be guaranteed to use the memory-based
4605
+ ;; encoding hence the `use_avx` test.
4606
+ (rule 5 (lower (has_type (multi_lane 32 4) (splat (sinkable_load addr))))
4607
+ (let ((tmp Xmm (x64_movss_load addr)))
4608
+ (x64_shufps tmp tmp 0)))
4609
+ (rule 6 (lower (has_type (multi_lane 32 4) (splat (sinkable_load addr))))
4610
+ (if-let $true (use_avx))
4611
+ (x64_vbroadcastss addr))
4612
+
4613
+ ;; t64x2.splat - use `pshufd` to broadcast the lower 64-bit lane to the upper
4614
+ ;; lane. A minor specialization for sinkable loads to avoid going through a gpr
4615
+ ;; for i64 splats is used as well when `movddup` is available.
4616
+ (rule 0 (lower (has_type $I64X2 (splat src)))
4617
+ (x64_pshufd (bitcast_gpr_to_xmm $I64 src) 0b01_00_01_00))
4618
+ (rule 0 (lower (has_type $F64X2 (splat src)))
4619
+ (x64_pshufd src 0b01_00_01_00))
4620
+ (rule 6 (lower (has_type (multi_lane 64 2) (splat (sinkable_load addr))))
4621
+ (if-let $true (use_ssse3))
4622
+ (x64_movddup addr))
4623
+
4624
+ ;; Rules for `vany_true` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4625
+
4626
+ (rule 1 (lower (vany_true val))
4627
+ (if-let $true (use_sse41))
4628
+ (let ((val Xmm val))
4629
+ (with_flags (x64_ptest val val) (x64_setcc (CC.NZ)))))
4630
+
4631
+ ;; Any nonzero byte in `val` means that any lane is true. Compare `val` with a
4632
+ ;; zeroed register and extract the high bits to a gpr mask. If the mask is
4633
+ ;; 0xffff then every byte was equal to zero, so test if the comparison is
4634
+ ;; not-equal or NZ.
4635
+ (rule (lower (vany_true val))
4636
+ (let (
4637
+ (any_byte_zero Xmm (x64_pcmpeqb val (xmm_zero $I8X16)))
4638
+ (mask Gpr (x64_pmovmskb (OperandSize.Size32) any_byte_zero))
4639
+ )
4640
+ (with_flags (x64_cmp_imm (OperandSize.Size32) mask 0xffff)
4641
+ (x64_setcc (CC.NZ)))))
4642
+
4643
+ ;; Rules for `vall_true` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4644
+
4645
+ (rule 1 (lower (vall_true val @ (value_type ty)))
4646
+ (if-let $true (use_sse41))
4647
+ (let ((src Xmm val)
4648
+ (zeros Xmm (xmm_zero ty))
4649
+ (cmp Xmm (x64_pcmpeq (vec_int_type ty) src zeros)))
4650
+ (with_flags (x64_ptest cmp cmp) (x64_setcc (CC.Z)))))
4651
+
4652
+ ;; Perform an appropriately-sized lane-wise comparison with zero. If the
4653
+ ;; result is all 0s then all of them are true because nothing was equal to
4654
+ ;; zero.
4655
+ (rule (lower (vall_true val @ (value_type ty)))
4656
+ (let ((lanes_with_zero Xmm (x64_pcmpeq (vec_int_type ty) val (xmm_zero ty)))
4657
+ (mask Gpr (x64_pmovmskb (OperandSize.Size32) lanes_with_zero)))
4658
+ (with_flags (x64_test (OperandSize.Size32) mask mask)
4659
+ (x64_setcc (CC.Z)))))
4660
+
4661
+ ;; Rules for `vhigh_bits` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4662
+
4663
+ ;; The Intel specification allows using both 32-bit and 64-bit GPRs as
4664
+ ;; destination for the "move mask" instructions. This is controlled by the REX.R
4665
+ ;; bit: "In 64-bit mode, the instruction can access additional registers when
4666
+ ;; used with a REX.R prefix. The default operand size is 64-bit in 64-bit mode"
4667
+ ;; (PMOVMSKB in IA Software Development Manual, vol. 2). This being the case, we
4668
+ ;; will always clear REX.W since its use is unnecessary (`OperandSize` is used
4669
+ ;; for setting/clearing REX.W) as we need at most 16 bits of output for
4670
+ ;; `vhigh_bits`.
4671
+
4672
+ (rule (lower (vhigh_bits val @ (value_type (multi_lane 8 16))))
4673
+ (x64_pmovmskb (OperandSize.Size32) val))
4674
+
4675
+ (rule (lower (vhigh_bits val @ (value_type (multi_lane 32 4))))
4676
+ (x64_movmskps (OperandSize.Size32) val))
4677
+
4678
+ (rule (lower (vhigh_bits val @ (value_type (multi_lane 64 2))))
4679
+ (x64_movmskpd (OperandSize.Size32) val))
4680
+
4681
+ ;; There is no x86 instruction for extracting the high bit of 16-bit lanes so
4682
+ ;; here we:
4683
+ ;; - duplicate the 16-bit lanes of `src` into 8-bit lanes:
4684
+ ;; PACKSSWB([x1, x2, ...], [x1, x2, ...]) = [x1', x2', ..., x1', x2', ...]
4685
+ ;; - use PMOVMSKB to gather the high bits; now we have duplicates, though
4686
+ ;; - shift away the bottom 8 high bits to remove the duplicates.
4687
+ (rule (lower (vhigh_bits val @ (value_type (multi_lane 16 8))))
4688
+ (let ((src Xmm val)
4689
+ (tmp Xmm (x64_packsswb src src))
4690
+ (tmp Gpr (x64_pmovmskb (OperandSize.Size32) tmp)))
4691
+ (x64_shr $I64 tmp (Imm8Reg.Imm8 8))))
4692
+
4693
+ ;; Rules for `iconcat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4694
+
4695
+ (rule (lower (iconcat lo @ (value_type $I64) hi))
4696
+ (value_regs lo hi))
4697
+
4698
+ ;; Rules for `isplit` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4699
+
4700
+ (rule (lower (isplit val @ (value_type $I128)))
4701
+ (let ((regs ValueRegs val)
4702
+ (lo Reg (value_regs_get regs 0))
4703
+ (hi Reg (value_regs_get regs 1)))
4704
+ (output_pair lo hi)))
4705
+
4706
+ ;; Rules for `tls_value` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4707
+
4708
+ (rule (lower (has_type (tls_model (TlsModel.ElfGd)) (tls_value (symbol_value_data name _ _))))
4709
+ (elf_tls_get_addr name))
4710
+
4711
+ (rule (lower (has_type (tls_model (TlsModel.Macho)) (tls_value (symbol_value_data name _ _))))
4712
+ (macho_tls_get_addr name))
4713
+
4714
+ (rule (lower (has_type (tls_model (TlsModel.Coff)) (tls_value (symbol_value_data name _ _))))
4715
+ (coff_tls_get_addr name))
4716
+
4717
+ ;; Rules for `sqmul_round_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4718
+
4719
+ (rule 1 (lower (sqmul_round_sat qx @ (value_type $I16X8) qy))
4720
+ (if-let $true (use_ssse3))
4721
+ (let ((src1 Xmm qx)
4722
+ (src2 Xmm qy)
4723
+
4724
+ (mask XmmMem (emit_u128_le_const 0x8000_8000_8000_8000_8000_8000_8000_8000))
4725
+ (dst Xmm (x64_pmulhrsw src1 src2))
4726
+ (cmp Xmm (x64_pcmpeqw dst mask)))
4727
+ (x64_pxor dst cmp)))
4728
+
4729
+ ;; This operation is defined in wasm as:
4730
+ ;;
4731
+ ;; S.SignedSaturate((x * y + 0x4000) >> 15)
4732
+ ;;
4733
+ ;; so perform all those operations here manually with a lack of the native
4734
+ ;; instruction.
4735
+ (rule (lower (sqmul_round_sat qx @ (value_type $I16X8) qy))
4736
+ (let (
4737
+ (qx Xmm qx)
4738
+ (qy Xmm qy)
4739
+ ;; Multiply `qx` and `qy` generating 32-bit intermediate results. The
4740
+ ;; 32-bit results have their low-halves stored in `mul_lsb` and the
4741
+ ;; high halves are stored in `mul_msb`. These are then shuffled into
4742
+ ;; `mul_lo` and `mul_hi` which represent the low 4 multiplications
4743
+ ;; and the upper 4 multiplications.
4744
+ (mul_lsb Xmm (x64_pmullw qx qy))
4745
+ (mul_msb Xmm (x64_pmulhw qx qy))
4746
+ (mul_lo Xmm (x64_punpcklwd mul_lsb mul_msb))
4747
+ (mul_hi Xmm (x64_punpckhwd mul_lsb mul_msb))
4748
+ ;; Add the 0x4000 constant to all multiplications
4749
+ (val Xmm (x64_movdqu_load (emit_u128_le_const 0x00004000_00004000_00004000_00004000)))
4750
+ (mul_lo Xmm (x64_paddd mul_lo val))
4751
+ (mul_hi Xmm (x64_paddd mul_hi val))
4752
+ ;; Perform the right-shift by 15 to all multiplications
4753
+ (lo Xmm (x64_psrad mul_lo (xmi_imm 15)))
4754
+ (hi Xmm (x64_psrad mul_hi (xmi_imm 15)))
4755
+ )
4756
+ ;; And finally perform a saturating 32-to-16-bit conversion.
4757
+ (x64_packssdw lo hi)))
4758
+
4759
+ ;; Rules for `x86_pmulhrsw` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4760
+
4761
+ (rule (lower (x86_pmulhrsw qx @ (value_type $I16X8) qy))
4762
+ (if-let $true (use_ssse3))
4763
+ (x64_pmulhrsw qx qy))
4764
+
4765
+ ;; Rules for `uunarrow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4766
+
4767
+ ;; TODO: currently we only lower a special case of `uunarrow` needed to support
4768
+ ;; the translation of wasm's i32x4.trunc_sat_f64x2_u_zero operation.
4769
+ ;; https://github.com/bytecodealliance/wasmtime/issues/4791
4770
+ ;;
4771
+ ;; y = i32x4.trunc_sat_f64x2_u_zero(x) is lowered to:
4772
+ ;; MOVAPD xmm_y, xmm_x
4773
+ ;; XORPD xmm_tmp, xmm_tmp
4774
+ ;; MAXPD xmm_y, xmm_tmp
4775
+ ;; MINPD xmm_y, [wasm_f64x2_splat(4294967295.0)]
4776
+ ;; ROUNDPD xmm_y, xmm_y, 0x0B
4777
+ ;; ADDPD xmm_y, [wasm_f64x2_splat(0x1.0p+52)]
4778
+ ;; SHUFPS xmm_y, xmm_xmp, 0x88
4779
+ (rule (lower (uunarrow (fcvt_to_uint_sat src @ (value_type $F64X2))
4780
+ (vconst (u128_from_constant 0))))
4781
+ (let ((src Xmm src)
4782
+
4783
+ ;; MOVAPD xmm_y, xmm_x
4784
+ ;; XORPD xmm_tmp, xmm_tmp
4785
+ (zeros Xmm (xmm_zero $F64X2))
4786
+ (dst Xmm (x64_maxpd src zeros))
4787
+
4788
+ ;; 4294967295.0 is equivalent to 0x41EFFFFFFFE00000
4789
+ (umax_mask XmmMem (emit_u128_le_const 0x41EFFFFFFFE00000_41EFFFFFFFE00000))
4790
+
4791
+ ;; MINPD xmm_y, [wasm_f64x2_splat(4294967295.0)]
4792
+ (dst Xmm (x64_minpd dst umax_mask))
4793
+
4794
+ ;; ROUNDPD xmm_y, xmm_y, 0x0B
4795
+ (dst Xmm (x64_round $F64X2 dst (RoundImm.RoundZero)))
4796
+
4797
+ ;; ADDPD xmm_y, [wasm_f64x2_splat(0x1.0p+52)]
4798
+ (uint_mask XmmMem (emit_u128_le_const 0x4330000000000000_4330000000000000))
4799
+
4800
+ (dst Xmm (x64_addpd dst uint_mask)))
4801
+
4802
+ ;; SHUFPS xmm_y, xmm_xmp, 0x88
4803
+ (x64_shufps dst zeros 0x88)))
4804
+
4805
+ ;; Rules for `nop` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4806
+
4807
+ (rule (lower (nop))
4808
+ (invalid_reg))