vertigo_vhdl 0.8.2

data/tests/parser_tests/test_MUST_fail.vhd

@@ -0,0 +1 @@
+error

data/tests/parser_tests/test_accelerator.vhd

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+library ieee,std;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.accelerator_pkg.all;
+
+entity accelerator is
+  port(
+    clk          : in  std_logic;
+    reset_n      : in  std_logic;
+    bus_addr     : in  std_logic_vector(31 downto 0);
+    bus_data_p2a : in  std_logic_vector(31 downto 0);
+    bus_data_a2p : out std_logic_vector(31 downto 0);
+    bus_rd       : in  std_logic;
+    bus_wr       : in  std_logic
+    );
+end accelerator;
+
+architecture rtl of accelerator is
+
+  type regs_t is record
+    a, b, res : std_logic_vector(31 downto 0);
+    ctrl      : std_logic;
+    status    : std_logic_vector(1 downto 0);  --busy,done
+  end record;
+
+  constant INIT_REGS : regs_t := (
+    (others => '0'),
+    (others => '0'),
+    (others => '0'),
+    '0',
+    "00"
+    );
+
+  signal ifregs : regs_t;
+
+  type   state_t is (idle, running);
+  signal state, state_c : state_t;
+
+  type vars_t is record
+    go   : std_logic;
+    a, b : unsigned(31 downto 0);
+    done : std_logic;
+  end record;
+
+  -- constant VARS_INIT : vars_t := (
+  --   '0',
+  --   to_unsigned(0, 32),
+  --   to_unsigned(0, 32),
+  --   '0');
+
+  signal vars, vars_c : vars_t;
+
+begin
+  --========================================
+  -- Bus interface
+  --========================================
+  bus_wr_proc : process(clk, reset_n)
+  begin
+    if reset_n = '0' then
+      ifregs <= INIT_REGS;
+    elsif rising_edge(clk) then
+      ifregs.ctrl <= '0';                               --autoreset
+      if bus_wr = '1' then
+        case bus_addr is
+          when ADDR_A =>
+            ifregs.a <= bus_data_p2a;
+          when ADDR_B =>
+            ifregs.b <= bus_data_p2a;
+          when ADDR_CTRL =>
+            ifregs.ctrl <= bus_data_p2a(0);             --write/clear a go
+          when ADDR_STATUS =>
+            ifregs.status <= bus_data_p2a(1 downto 0);  --clear rdy
+          when others => null;
+        end case;
+      elsif vars.done = '1' then
+        ifregs.res       <= std_logic_vector(vars.a);  --BUG : vars.a ne passait pas
+                                                       --=> FIX lexer : selected_name
+        --ifregs.status(0) <= vars.done;  --BUG : (0) ne passe pas
+        ifregs.status <= vars.done;  --BUG : (0) ne passe pas
+      end if;
+    end if;
+  end process;
+
+  bus_rd_proc : process(reset_n, clk)
+  begin
+    if reset_n = '0' then
+      bus_data_a2p <= (others => '0');
+    elsif rising_edge(clk) then
+      if bus_rd = '1' then
+        case bus_addr is
+          when ADDR_A =>
+            bus_data_a2p <= ifregs.a;
+          when ADDR_B =>
+            bus_data_a2p <= ifregs.b;
+          when ADDR_CTRL =>
+            null;
+            --bus_data_a2p <= X"0000000" & "000" & ifregs.ctrl;  --write/clear a go
+          when ADDR_STATUS =>
+            null;
+            bus_data_a2p <= X"0000000" & "00" & ifregs.status;
+          when ADDR_RES =>
+            bus_data_a2p <= ifregs.res;
+          when others => null;
+        end case;
+      end if;
+    end if;
+  end process;
+
+--=============================================
+-- BUG
+--=============================================
+
+  reg : process(clk, reset_n)
+  begin
+    if reset_n = '0' then
+      state <= idle;
+      vars  <= VARS_INIT;
+    elsif rising_edge(clk) then
+      state <= state_c;
+      vars  <= vars_c;
+      if ifregs.ctrl = '1' then
+        vars.a  <= unsigned(ifregs.a);
+        vars.b  <= unsigned(ifregs.b);
+        vars.go <= '1';
+      end if;
+    end if;
+  end process;
+
+  comb : process (state, vars)
+    variable state_v : state_t;
+    variable vars_v  : vars_t;
+  begin
+    state_v := state;
+    vars_v  := vars;
+    case state_v is
+      when idle =>
+        if vars_v.go = '1' then
+          state_v   := running;
+          vars_v.go := '0';
+        else
+          vars_v := VARS_INIT;
+        end if;
+      when running =>
+        if vars_v.a /= vars_v.b then
+          if vars_v.a > vars_v.b then
+            vars_v.a := vars_v.a-vars_v.b;
+          else
+            vars_v.b := vars_v.b-vars_v.a;
+          end if;
+        else
+          vars_v.done := '1';
+          state_v     := idle;
+        end if;
+      when others => null;
+    end case;
+    state_c <= state_v;
+    vars_c  <= vars_v;
+  end process;
+
+end rtl;

data/tests/parser_tests/test_accelerator_pp.vhd

@@ -0,0 +1,144 @@
+-- generated by Vertigo VHDL tool
+library ieee;
+library std;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.accelerator_pkg.all;
+ 
+entity accelerator is
+  port(
+    clk : in std_logic;
+    reset_n : in std_logic;
+    bus_addr : in std_logic_vector(31 downto 0);
+    bus_data_p2a : in std_logic_vector(31 downto 0);
+    bus_data_a2p : out std_logic_vector(31 downto 0);
+    bus_rd : in std_logic;
+    bus_wr : in std_logic);
+end entity accelerator;
+ 
+architecture rtl of accelerator is
+   
+  type regs_t is record
+    a : std_logic_vector(31 downto 0);
+    b : std_logic_vector(31 downto 0);
+    res : std_logic_vector(31 downto 0);
+    ctrl : std_logic;
+    status : std_logic_vector(1 downto 0);
+  end record;
+  constant init_regs : regs_t := ((others => '0'),(others => '0'),(others => '0'),'0',"00");
+  signal ifregs : regs_t;
+   
+  type state_t is (idle,running);
+  signal state : state_t;
+  signal state_c : state_t;
+   
+  type vars_t is record
+    go : std_logic;
+    a : unsigned(31 downto 0);
+    b : unsigned(31 downto 0);
+    done : std_logic;
+  end record;
+  signal vars : vars_t;
+  signal vars_c : vars_t;
+begin
+ 
+   
+  bus_wr_proc : process(clk,reset_n)
+  begin
+    if reset_n = '0' then
+      ifregs <= init_regs;
+    elsif rising_edge(clk) then
+      ifregs.ctrl <= '0';
+      if bus_wr = '1' then
+        case bus_addr is
+          when addr_a =>
+            ifregs.a <= bus_data_p2a;
+          when addr_b =>
+            ifregs.b <= bus_data_p2a;
+          when addr_ctrl =>
+            ifregs.ctrl <= bus_data_p2a(0);
+          when addr_status =>
+            ifregs.status <= bus_data_p2a(1 downto 0);
+          when others =>
+            null;
+        end case;
+      elsif vars.done = '1' then
+        ifregs.res <= std_logic_vector(vars.a);
+        ifregs.status <= vars.done;
+      end if;
+    end if;
+  end process;
+   
+  bus_rd_proc : process(reset_n,clk)
+  begin
+    if reset_n = '0' then
+      bus_data_a2p <= (others => '0');
+    elsif rising_edge(clk) then
+      if bus_rd = '1' then
+        case bus_addr is
+          when addr_a =>
+            bus_data_a2p <= ifregs.a;
+          when addr_b =>
+            bus_data_a2p <= ifregs.b;
+          when addr_ctrl =>
+            null;
+          when addr_status =>
+            null;
+            bus_data_a2p <= x"0000000" & "00" & ifregs.status;
+          when addr_res =>
+            bus_data_a2p <= ifregs.res;
+          when others =>
+            null;
+        end case;
+      end if;
+    end if;
+  end process;
+   
+  reg : process(clk,reset_n)
+  begin
+    if reset_n = '0' then
+      state <= idle;
+      vars <= vars_init;
+    elsif rising_edge(clk) then
+      state <= state_c;
+      vars <= vars_c;
+      if ifregs.ctrl = '1' then
+        vars.a <= unsigned(ifregs.a);
+        vars.b <= unsigned(ifregs.b);
+        vars.go <= '1';
+      end if;
+    end if;
+  end process;
+   
+  comb : process(state,vars)
+    variable state_v : state_t;
+    variable vars_v : vars_t;
+  begin
+    state_v := state;
+    vars_v := vars;
+    case state_v is
+      when idle =>
+        if vars_v.go = '1' then
+          state_v := running;
+          vars_v.go := '0';
+        else
+          vars_v := vars_init;
+        end if;
+      when running =>
+        if vars_v.a /= vars_v.b then
+          if vars_v.a > vars_v.b then
+            vars_v.a := vars_v.a - vars_v.b;
+          else
+            vars_v.b := vars_v.b - vars_v.a;
+          end if;
+        else
+          vars_v.done := '1';
+          state_v := idle;
+        end if;
+      when others =>
+        null;
+    end case;
+    state_c <= state_v;
+    vars_c <= vars_v;
+  end process;
+end rtl;

data/tests/parser_tests/test_aggregate.vhd

@@ -0,0 +1,17 @@
+entity test is
+end entity;
+
+architecture bhv of test is
+begin
+
+  reg_ctrl_out <= (63 downto 11 => '0', 10 downto  0 => reg_ctrl);
+
+  -- from microwatt_dcache.vhd
+  req_laddr <= r0.addr(63 downto LINE_OFF_BITS) & (LINE_OFF_BITS-1 downto 0 => '0');
+
+  regs_t <= (1,2,3);
+  regs_t <= (others => '0');
+  regs_t <= ( (others => '0'), '0',"00" );
+  regs_t <= ( (others => '0'), (others => '0'), '0',"00" );
+
+end bhv;

data/tests/parser_tests/test_aggregate_pp.vhd

@@ -0,0 +1,15 @@
+-- generated by Vertigo VHDL tool
+ 
+entity test is
+end entity test;
+ 
+architecture bhv of test is
+begin
+ 
+  reg_ctrl_out <= (63 downto 11 => '0',10 downto 0 => reg_ctrl);
+  req_laddr <= r0.addr(63 downto line_off_bits) & (line_off_bits - 1 downto 0 => '0');
+  regs_t <= (1,2,3);
+  regs_t <= (others => '0');
+  regs_t <= ((others => '0'),'0',"00");
+  regs_t <= ((others => '0'),(others => '0'),'0',"00");
+end bhv;

data/tests/parser_tests/test_archi_1.vhd

@@ -0,0 +1,45 @@
+library ieee,std;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity accelerator is
+  port(
+    reset_n : in std_logic;
+    clk     : in std_logic;
+    a1      : in std_logic_vector(31 downto 0);
+    f1      : out std_logic_vector(31 downto 0)
+  );
+end entity accelerator;
+
+architecture rtl of accelerator is
+  signal a,b,c : std_logic;
+  signal s : integer;
+  signal d,e,f: std_logic_vector(31 downto 0);
+begin
+
+  c <= '0','1' after 15 ns;
+
+  a <= b;
+
+  s <= 1 when a='1' else
+       2 when a='0' else
+       3;
+
+  -- absurd code
+  label_1:process(s,reset_n,clk)
+  begin
+
+    if s > 32 then
+      s <= 1;
+    end if;
+
+    if reset_n='0' then
+      s <= 2;
+    elsif rising_edge(clk) then
+      s <= 1;
+    end if;
+
+    wait;
+  end process;
+
+end rtl;

data/tests/parser_tests/test_archi_1_pp.vhd

@@ -0,0 +1,41 @@
+-- generated by Vertigo VHDL tool
+library ieee;
+library std;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+ 
+entity accelerator is
+  port(
+    reset_n : in std_logic;
+    clk : in std_logic;
+    a1 : in std_logic_vector(31 downto 0);
+    f1 : out std_logic_vector(31 downto 0));
+end entity accelerator;
+ 
+architecture rtl of accelerator is
+  signal a : std_logic;
+  signal b : std_logic;
+  signal c : std_logic;
+  signal s : integer;
+  signal d : std_logic_vector(31 downto 0);
+  signal e : std_logic_vector(31 downto 0);
+  signal f : std_logic_vector(31 downto 0);
+begin
+ 
+  c <= '0','1' after 15 ns;
+  a <= b;
+  s <= 1 when a = '1' else 2 when a = '0' else  3;
+   
+  label_1 : process(s,reset_n,clk)
+  begin
+    if s > 32 then
+      s <= 1;
+    end if;
+    if reset_n = '0' then
+      s <= 2;
+    elsif rising_edge(clk) then
+      s <= 1;
+    end if;
+    wait ;
+  end process;
+end rtl;

data/tests/parser_tests/test_array_array_00.vhd

@@ -0,0 +1,25 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture test_var of test is
+
+
+begin  -- test_var
+
+  test : process
+    type TestIt is array(natural range <>) of boolean;
+    type     Mem is array (natural range <>, natural range <>) of std_logic;
+    variable TempCond : boolean              := true;
+    variable RAM2     : Mem (0 to 7, 0 to 7) :=
+      (('0', '0', '0', '0', '0', '0', '0', '0'),
+       ('0', '0', '0', '0', '0', '0', '0', '0'),
+       ('0', '0', '0', '0', '0', '0', '0', '0'),
+       ('0', '0', '0', '0', '0', '0', '0', '0'),
+       ('0', '0', '0', '0', '0', '0', '0', '0'),
+       ('0', '0', '0', '0', '0', '0', '0', '0'),
+       ('0', '0', '0', '0', '0', '0', '0', '0'),
+       ('0', '0', '0', '0', '0', '0', '0', '0'));
+  begin  -- process test
+  end process test;
+
+end test_var;