vertigo_vhdl 0.8.2

data/lib/vertigo/runner.rb

@@ -0,0 +1,115 @@
+require "optparse"
+
+require_relative "compiler"
+
+module Vertigo
+
+  class Runner
+
+    def self.run *arguments
+      new.run(arguments)
+    end
+
+    def run arguments
+      compiler=Compiler.new
+      compiler.options = args = parse_options(arguments)
+      begin
+        if args[:parse_only]
+          filename=args[:vhdl_file]
+          ok=compiler.parse(filename)
+        elsif args[:gen_tb]
+          filename=args[:vhdl_file]
+          ok=compiler.gen_tb(filename)
+        elsif filename=args[:vhdl_file]
+          ok=compiler.compile(filename)
+        else
+          raise "need a VHDL file : vhdl_tb [options] <file.vhd>"
+        end
+        return ok
+      rescue Exception => e
+        puts e unless compiler.options[:mute]
+        return false
+      end
+    end
+
+    def header
+      puts "Vertigo -- VHDL utilities (#{VERSION})- (c) JC Le Lann 2016-20"
+    end
+
+    private
+    def parse_options(arguments)
+
+      parser = OptionParser.new
+
+      no_arguments=arguments.empty?
+
+      options = {}
+
+      parser.on("-h", "--help", "Show help message") do
+        puts parser
+        exit(true)
+      end
+
+      parser.on("-p", "--parse", "parse only") do
+        options[:parse_only]=true
+      end
+
+      parser.on("--dump", "dump ast") do
+        options[:dump_ast]=true
+      end
+
+      parser.on("--pp", "pretty print back source code, in the console") do
+        options[:pp] = true
+      end
+
+      parser.on("--pp_to_file", "pretty print back source code, to a _pp.vhd file") do
+        options[:pp_to_file] = true
+      end
+
+      parser.on("--ast", "abstract syntax tree (AST)") do
+        options[:ast] = true
+      end
+
+      parser.on("--check", "elaborate and check types") do
+        options[:check] = true
+      end
+
+      parser.on("--draw_ast", "draw abstract syntax tree (AST)") do
+        options[:draw_ast] = true
+      end
+
+      parser.on("--gen_tb", "generates a testbench for the first entity/arch pair found") do
+        options[:gen_tb] = true
+      end
+
+      parser.on("--dummy_transform", "dummy ast transform") do
+        options[:dummy_transform] = true
+      end
+
+      parser.on("--vv", "verbose") do
+        options[:verbose] = true
+      end
+
+      parser.on("--mute","mute") do
+        options[:mute]=true
+      end
+
+      parser.on("-v", "--version", "Show version number") do
+        puts VERSION
+        exit(true)
+      end
+
+      parser.parse!(arguments)
+
+      header unless options[:mute]
+
+      options[:vhdl_file]=arguments.shift #the remaining c file
+
+      if no_arguments
+        puts parser
+      end
+
+      options
+    end
+  end
+end

data/lib/vertigo/tb_generator.rb

@@ -0,0 +1,81 @@
+require 'erb'
+
+module Vertigo
+
+  class TestBenchGenerator
+    attr_accessor :ast
+    attr_accessor :entity,:arch
+    attr_accessor :clk,:rst
+    def initialize options={}
+      @options=options
+      @supplemental_libs_h=options[:supplemental_libs_h]||{}
+    end
+
+    def generate_from ast
+      @ast=ast
+      entity_arch=find_entity_arch
+      detecting_clk_and_reset entity_arch
+      @tb_name=entity_arch.first.name.str+'_tb'
+      erb=ERB.new(IO.read "#{__dir__}/template.tb.vhd")
+      vhdl_tb=erb.result(binding)
+      tb_filename=@tb_name+".vhd"
+      File.open(tb_filename,'w'){|f| f.puts vhdl_tb}
+      puts "=> generated testbench : #{tb_filename}"
+    end
+
+    private
+    def find_entity_arch
+      @entity=ast.design_units.find{|du| du.is_a? Entity}
+      if @entity.nil?
+        puts msg="ERROR : no entity found"
+        raise msg
+      end
+      puts "=> found entity '#{entity.name.str}'"
+      @arch=ast.design_units.find{|du| du.is_a? Architecture}
+      if @arch.nil?
+        puts msg="ERROR : no architecture found"
+        raise msg
+      end
+
+      puts "=> found architecture '#{arch.name.str}'"
+      [@entity,@arch]
+    end
+
+    def detecting_clk_and_reset entity_arch
+      puts "=> detecting clock and reset"
+      entity,arch=entity_arch
+      inputs=entity.ports.select{|port| port.is_a?(Input)}
+      @clk = inputs.sort_by{|input| levenshtein_distance(input.name.str,"clk")}.first
+      @rst = inputs.sort_by{|input| levenshtein_distance(input.name.str,"reset")}.first
+      puts "\t-most probable clk   : #{@clk.name.str}"
+      puts "\t-most probable reset : #{@rst.name.str}"
+      @max_length_str=entity.ports.map{|port| port.name.str.size}.max
+      @excluded=[@clk,@rst]
+    end
+
+    def levenshtein_distance(s, t)
+      m = s.length
+      n = t.length
+      return m if n == 0
+      return n if m == 0
+      d = Array.new(m+1) {Array.new(n+1)}
+
+      (0..m).each {|i| d[i][0] = i}
+      (0..n).each {|j| d[0][j] = j}
+      (1..n).each do |j|
+        (1..m).each do |i|
+          d[i][j] = if s[i-1] == t[j-1] # adjust index into string
+                      d[i-1][j-1]       # no operation required
+                    else
+                      [ d[i-1][j]+1,    # deletion
+                        d[i][j-1]+1,    # insertion
+                        d[i-1][j-1]+1,  # substitution
+                      ].min
+                    end
+        end
+      end
+      d[m][n]
+    end
+  end
+
+end

data/lib/vertigo/template.tb.vhd

@@ -0,0 +1,72 @@
+-----------------------------------------------------------------
+-- This file was generated automatically by Vertigo Ruby utility
+-- date : <%=Time.now.strftime("(d/m/y) %d/%m/%Y %H:%M")%>
+-- Author : Jean-Christophe Le Lann - 2014
+-----------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+<%@supplemental_libs_h.each do |lib,packages|%>
+library <%=lib%>;
+<%packages.each do |package|%>
+use <%=lib%>.<%=package%>.all;
+<%end%>
+<%end%>
+
+entity <%=@tb_name%> is
+end entity;
+
+architecture bhv of <%=@tb_name%> is
+
+  constant HALF_PERIOD : time := 5 ns;
+
+  signal <%=clk.name.str%> : std_logic := '0';
+  signal <%=rst.name.str%> : std_logic := '0';
+
+  signal running : boolean   := true;
+
+  procedure wait_cycles(n : natural) is
+   begin
+     for i in 1 to n loop
+       wait until rising_edge(clk);
+     end loop;
+   end procedure;
+
+<%=@entity.ports.collect do |port|
+  "  signal #{port.name.str.ljust(@max_length_str)} : #{port.type.str}" if not @excluded.include?(port)
+  end.compact.join(";\n")%>;
+
+begin
+  -------------------------------------------------------------------
+  -- clock and reset
+  -------------------------------------------------------------------
+  reset_n <= '0','1' after 666 ns;
+
+  clk <= not(clk) after HALF_PERIOD when running else clk;
+
+  --------------------------------------------------------------------
+  -- Design Under Test
+  --------------------------------------------------------------------
+  dut : entity work.<%=@entity.name.str%>(<%=@arch.name.str%>)
+        <%=@generics%>
+        port map ( <%map=@entity.ports.collect do |port| "\t  #{port.name.str} => #{port.name.str}" end%>
+<%=map.join(",\n")%>
+        );
+
+  --------------------------------------------------------------------
+  -- sequential stimuli
+  --------------------------------------------------------------------
+  stim : process
+   begin
+     report "running testbench for <%=@entity.name.str%>(<%=@arch.name.str%>)";
+     report "waiting for asynchronous reset";
+     wait until reset_n='1';
+     wait_cycles(100);
+     report "applying stimuli...";
+     wait_cycles(100);
+     report "end of simulation";
+     running <=false;
+     wait;
+   end process;
+
+end bhv;

data/lib/vertigo/token.rb

@@ -0,0 +1,67 @@
+module Vertigo
+
+  class Token
+    attr_accessor :kind,:val,:pos
+    def initialize tab
+      @kind,@val,@pos=*tab
+    end
+
+    def is_a? kind
+      case kind
+      when Symbol
+        return @kind==kind
+      when Array
+        for sym in kind
+          return true if @kind==sym
+        end
+        return false
+      else
+        raise "wrong type during lookahead"
+      end
+    end
+
+    def not_a? kind
+      result=self.is_a? kind
+      !result
+    end
+
+    def is_not_a? kind
+      case kind
+      when Symbol
+        return @kind!=kind
+      when Array
+        ret=true
+        for sym in kind
+          ret=false if @kind==sym
+        end
+        return ret
+      else
+        raise "wrong type during lookahead"
+      end
+    end
+
+    def accept visitor,args=nil
+      visitor.visitToken(self)
+    end
+
+    def self.create kind,str
+      Token.new [kind,str,[0,0]]
+    end
+
+    # def inspect
+    #   "(#{@kind.to_s.ljust(15,' ')},'#{@val}',#{@pos})"
+    # end
+
+    def str
+      val
+    end
+
+    def clone
+      Token.new([@kind,@val,@pos])
+    end
+
+    def line
+      pos.first
+    end
+  end
+end

data/lib/vertigo/version.rb

@@ -0,0 +1,3 @@
+module Vertigo
+  VERSION="0.8.2"
+end

data/lib/vertigo/vertigo.rkg

@@ -0,0 +1,354 @@
+
+- Root:
+  - design_unitS
+
+- Comment:
+  - str
+
+- Library:
+  - name
+
+- Use:
+  - library
+  - package
+  - element
+
+- Entity:
+  - name
+  - genericS
+  - portS
+
+- Generic:
+  - name
+  - type
+  - init
+
+- Input:
+  - name
+  - type
+  - init
+
+- Output:
+  - name
+  - type
+  - init
+
+- InOut:
+  - name
+  - type
+  - init
+#===================
+- Package:
+  - name
+  - declS
+
+- PackageBody:
+  - name
+  - declS
+
+- ProcedureDecl:
+  - name
+  - formal_argS
+  - declS
+  - body
+
+- FormalArg:
+  - signal
+  - direction
+  - name
+  - type
+
+- ProcedureCall:
+  - name
+  - actual_argS
+#====================
+- Architecture:
+  - name
+  - entity_name
+  - declS
+  - body
+
+- Body:
+  - elementS
+
+- Process:
+  - sensitivity
+  - declS
+  - body
+
+- Sensitivity:
+  - elementS
+
+- EntityInstance:
+  - full_name
+  - arch_name
+  - generic_map
+  - port_map
+
+- ComponentDecl:
+  - name
+  - genericS
+  - portS
+
+- ComponentInstance:
+  - name
+  - generic_map
+  - port_map
+
+- PortMap:
+  - elementS
+
+- GenericMap:
+  - elementS
+
+- Map:
+  - lhs
+  - rhs
+
+- AttributeDecl:
+  - name
+  - type
+
+- AttributeSpec:
+  - name
+  - entity_spec
+  - expr
+
+- EntitySpec:
+  - elementS
+  - entity_class
+
+#======= statements =====
+
+- SigAssign:
+  - lhs
+  - rhs
+
+- varAssign:
+  - lhs
+  - rhs
+
+- wait:
+  - until_
+  - for_
+
+- If:
+  - cond
+  - body
+  - elsifS
+  - else_
+
+- Elsif:
+  - cond
+  - body
+
+- Else:
+  - body
+
+- Case:
+  - expr
+  - whenS
+
+- CaseWhen:
+  - expr
+  - body
+
+- Alternative:
+  - elementS
+
+- NullStmt:
+  - dummy
+
+- Assert:
+  - cond
+  - report
+  - severity
+
+- Report:
+  - expr
+  - severity
+
+- Severity:
+  - type
+
+- Return:
+  - expr
+
+- WithSelect:
+  - with_expr
+  - assigned
+  - selected_whenS
+
+- SelectedWhen:
+  - lhs
+  - rhs
+
+- IfGenerate:
+  - cond
+  - body
+
+- ForGenerate:
+  - index
+  - range
+  - declS
+  - body
+
+- IsolatedRange:
+  - lhs
+  - rhs
+
+#====================
+- TypeDecl:
+  - name
+  - spec
+
+- SubTypeDecl:
+  - name
+  - spec
+
+- EnumDecl:
+  - elementS
+
+- RecordDecl:
+  - elementS
+
+- RecordItem:
+  - name
+  - type
+
+- ArrayDecl:
+  - dim_declS
+  - type
+
+- ArrayDimDecl:
+  - type_mark
+  - range
+
+- Constant:
+  - name
+  - type
+  - expr
+
+- Signal:
+  - name
+  - type
+  - init
+
+- Variable:
+  - name
+  - type
+  - init
+
+- Alias:
+  - designator
+  - type
+  - name
+  - signature
+
+- StdType:
+  - ident
+
+- RangedType:
+  - type
+  - range
+
+- NamedType:
+  - ident
+
+- ArrayType:
+  - name
+  - discrete_rangeS
+
+- DiscreteRange:
+  - lhs
+  - dir
+  - rhs
+
+# === expressions
+- Parenth:
+  - expr
+
+- Waveform:
+  - elementS
+
+- CondExpr:
+  - whenS
+  - else_
+
+- When:
+  - expr
+  - cond
+
+- Binary:
+  - lhs
+  - op
+  - rhs
+
+- After:
+  - lhs
+  - rhs
+
+- Timed:
+  - lhs
+  - rhs
+
+- Attributed:
+  - lhs
+  - rhs
+
+- Concat:
+  - lhs
+  - rhs
+
+- Qualified:
+  - lhs
+  - rhs
+
+- Sliced:
+  - expr
+  - lhs
+  - dir
+  - rhs
+
+# === terms
+- ident:
+  - tok
+
+- IntLit:
+  - tok
+
+- CharLit:
+  - tok
+
+- BoolLit:
+  - tok
+
+- selectedName:
+  - lhs
+  - rhs
+
+- FuncProtoDecl:
+  - name
+  - formal_argS
+  - return_type
+
+- FuncDecl:
+  - name
+  - formal_argS
+  - return_type
+  - decls
+  - body
+
+- FuncCall:
+  - name
+  - actual_argS
+
+- Aggregate:
+  - elementS
+
+- Label:
+  - ident
+
+- Assoc:
+  - lhs
+  - rhs