vertigo_vhdl 0.8.2
Sign up to get free protection for your applications and to get access to all the features.
- checksums.yaml +7 -0
- data/bin/vertigo +7 -0
- data/lib/vertigo.rb +4 -0
- data/lib/vertigo/ast.rb +87 -0
- data/lib/vertigo/ast_vertigo_rkgen.rb +607 -0
- data/lib/vertigo/code.rb +57 -0
- data/lib/vertigo/compiler.rb +61 -0
- data/lib/vertigo/generic_lexer.rb +61 -0
- data/lib/vertigo/generic_parser.rb +44 -0
- data/lib/vertigo/indent.rb +20 -0
- data/lib/vertigo/lexer.rb +172 -0
- data/lib/vertigo/parser.rb +1458 -0
- data/lib/vertigo/pretty_printer.rb +749 -0
- data/lib/vertigo/runner.rb +115 -0
- data/lib/vertigo/tb_generator.rb +81 -0
- data/lib/vertigo/template.tb.vhd +72 -0
- data/lib/vertigo/token.rb +67 -0
- data/lib/vertigo/version.rb +3 -0
- data/lib/vertigo/vertigo.rkg +354 -0
- data/lib/vertigo/visitor_vertigo_rkgen.rb +447 -0
- data/tests/ghdl_tests/fsm.vhd +98 -0
- data/tests/ghdl_tests/fsm_synth.vhd +248 -0
- data/tests/ghdl_tests/test_fsm.vhd +162 -0
- data/tests/parser_tests/else.vhd +64 -0
- data/tests/parser_tests/test_MUST_fail.vhd +1 -0
- data/tests/parser_tests/test_accelerator.vhd +160 -0
- data/tests/parser_tests/test_accelerator_pp.vhd +144 -0
- data/tests/parser_tests/test_aggregate.vhd +17 -0
- data/tests/parser_tests/test_aggregate_pp.vhd +15 -0
- data/tests/parser_tests/test_archi_1.vhd +45 -0
- data/tests/parser_tests/test_archi_1_pp.vhd +41 -0
- data/tests/parser_tests/test_array_array_00.vhd +25 -0
- data/tests/parser_tests/test_array_array_00_pp.vhd +25 -0
- data/tests/parser_tests/test_array_urange.vhd +25 -0
- data/tests/parser_tests/test_array_urange_pp.vhd +25 -0
- data/tests/parser_tests/test_chu-1.vhd +80 -0
- data/tests/parser_tests/test_chu-1_pp.vhd +104 -0
- data/tests/parser_tests/test_concat.vhd +11 -0
- data/tests/parser_tests/test_concat_pp.vhd +14 -0
- data/tests/parser_tests/test_counter.vhd +35 -0
- data/tests/parser_tests/test_counter_pp.vhd +35 -0
- data/tests/parser_tests/test_de2.vhd +358 -0
- data/tests/parser_tests/test_de2_pp.vhd +274 -0
- data/tests/parser_tests/test_encode.vhd +2679 -0
- data/tests/parser_tests/test_encode_pp.vhd +2549 -0
- data/tests/parser_tests/test_fsm.vhd +162 -0
- data/tests/parser_tests/test_fsm_pp.vhd +125 -0
- data/tests/parser_tests/test_fsm_synth.vhd +248 -0
- data/tests/parser_tests/test_fsm_synth_pp.vhd +197 -0
- data/tests/parser_tests/test_function-01.vhd +33 -0
- data/tests/parser_tests/test_function-01_pp.vhd +18 -0
- data/tests/parser_tests/test_lfsr.vhd +75 -0
- data/tests/parser_tests/test_lfsr_pp.vhd +44 -0
- data/tests/parser_tests/test_microwatt_cache_ram.vhd +1 -0
- data/tests/parser_tests/test_microwatt_cache_ram_pp.vhd +68 -0
- data/tests/parser_tests/test_microwatt_common.vhd +1 -0
- data/tests/parser_tests/test_microwatt_common_pp.vhd +336 -0
- data/tests/parser_tests/test_microwatt_control.vhd +1 -0
- data/tests/parser_tests/test_microwatt_control_pp.vhd +187 -0
- data/tests/parser_tests/test_microwatt_core.vhd +1 -0
- data/tests/parser_tests/test_microwatt_core_debug.vhd +1 -0
- data/tests/parser_tests/test_microwatt_core_debug_pp.vhd +104 -0
- data/tests/parser_tests/test_microwatt_core_pp.vhd +231 -0
- data/tests/parser_tests/test_microwatt_core_tb.vhd +1 -0
- data/tests/parser_tests/test_microwatt_core_tb_pp.vhd +43 -0
- data/tests/parser_tests/test_microwatt_countzero.vhd +1 -0
- data/tests/parser_tests/test_microwatt_countzero_pp.vhd +120 -0
- data/tests/parser_tests/test_microwatt_countzero_tb.vhd +1 -0
- data/tests/parser_tests/test_microwatt_countzero_tb_pp.vhd +70 -0
- data/tests/parser_tests/test_microwatt_cr_file.vhd +1 -0
- data/tests/parser_tests/test_microwatt_cr_file_pp.vhd +74 -0
- data/tests/parser_tests/test_microwatt_cr_hazard.vhd +1 -0
- data/tests/parser_tests/test_microwatt_cr_hazard_pp.vhd +51 -0
- data/tests/parser_tests/test_microwatt_crhelpers.vhd +1 -0
- data/tests/parser_tests/test_microwatt_crhelpers_pp.vhd +48 -0
- data/tests/parser_tests/test_microwatt_dcache.vhd +1 -0
- data/tests/parser_tests/test_microwatt_dcache_pp.vhd +481 -0
- data/tests/parser_tests/test_microwatt_dcache_tb.vhd +1 -0
- data/tests/parser_tests/test_microwatt_dcache_tb_pp.vhd +98 -0
- data/tests/parser_tests/test_microwatt_decode1.vhd +1 -0
- data/tests/parser_tests/test_microwatt_decode1_pp.vhd +138 -0
- data/tests/parser_tests/test_microwatt_decode2.vhd +1 -0
- data/tests/parser_tests/test_microwatt_decode2_pp.vhd +300 -0
- data/tests/parser_tests/test_microwatt_decode_types.vhd +1 -0
- data/tests/parser_tests/test_microwatt_decode_types_pp.vhd +67 -0
- data/tests/parser_tests/test_microwatt_divider.vhd +1 -0
- data/tests/parser_tests/test_microwatt_divider_pp.vhd +132 -0
- data/tests/parser_tests/test_microwatt_divider_tb.vhd +1 -0
- data/tests/parser_tests/test_microwatt_divider_tb_pp.vhd +95 -0
- data/tests/parser_tests/test_microwatt_dmi_dtm_dummy.vhd +1 -0
- data/tests/parser_tests/test_microwatt_dmi_dtm_dummy_pp.vhd +29 -0
- data/tests/parser_tests/test_microwatt_dmi_dtm_tb.vhd +1 -0
- data/tests/parser_tests/test_microwatt_dmi_dtm_tb_pp.vhd +197 -0
- data/tests/parser_tests/test_microwatt_dmi_dtm_xilinx.vhd +1 -0
- data/tests/parser_tests/test_microwatt_dmi_dtm_xilinx_pp.vhd +139 -0
- data/tests/parser_tests/test_microwatt_execute1.vhd +1 -0
- data/tests/parser_tests/test_microwatt_execute1_pp.vhd +689 -0
- data/tests/parser_tests/test_microwatt_fetch1.vhd +1 -0
- data/tests/parser_tests/test_microwatt_fetch1_pp.vhd +88 -0
- data/tests/parser_tests/test_microwatt_fetch2.vhd +1 -0
- data/tests/parser_tests/test_microwatt_fetch2_pp.vhd +79 -0
- data/tests/parser_tests/test_microwatt_glibc_random.vhd +1 -0
- data/tests/parser_tests/test_microwatt_glibc_random_helpers.vhd +1 -0
- data/tests/parser_tests/test_microwatt_glibc_random_helpers_pp.vhd +25 -0
- data/tests/parser_tests/test_microwatt_glibc_random_pp.vhd +41 -0
- data/tests/parser_tests/test_microwatt_gpr_hazard.vhd +1 -0
- data/tests/parser_tests/test_microwatt_gpr_hazard_pp.vhd +68 -0
- data/tests/parser_tests/test_microwatt_helpers.vhd +1 -0
- data/tests/parser_tests/test_microwatt_helpers_pp.vhd +153 -0
- data/tests/parser_tests/test_microwatt_icache.vhd +1 -0
- data/tests/parser_tests/test_microwatt_icache_pp.vhd +337 -0
- data/tests/parser_tests/test_microwatt_icache_tb.vhd +1 -0
- data/tests/parser_tests/test_microwatt_icache_tb_pp.vhd +104 -0
- data/tests/parser_tests/test_microwatt_insn_helpers.vhd +1 -0
- data/tests/parser_tests/test_microwatt_insn_helpers_pp.vhd +208 -0
- data/tests/parser_tests/test_microwatt_loadstore1.vhd +1 -0
- data/tests/parser_tests/test_microwatt_loadstore1_pp.vhd +222 -0
- data/tests/parser_tests/test_microwatt_logical.vhd +1 -0
- data/tests/parser_tests/test_microwatt_logical_pp.vhd +87 -0
- data/tests/parser_tests/test_microwatt_multiply.vhd +1 -0
- data/tests/parser_tests/test_microwatt_multiply_pp.vhd +84 -0
- data/tests/parser_tests/test_microwatt_multiply_tb.vhd +1 -0
- data/tests/parser_tests/test_microwatt_multiply_tb_pp.vhd +75 -0
- data/tests/parser_tests/test_microwatt_plru.vhd +1 -0
- data/tests/parser_tests/test_microwatt_plru_pp.vhd +46 -0
- data/tests/parser_tests/test_microwatt_plru_tb.vhd +1 -0
- data/tests/parser_tests/test_microwatt_plru_tb_pp.vhd +93 -0
- data/tests/parser_tests/test_microwatt_ppc_fx_insns.vhd +1 -0
- data/tests/parser_tests/test_microwatt_ppc_fx_insns_pp.vhd +665 -0
- data/tests/parser_tests/test_microwatt_register_file.vhd +1 -0
- data/tests/parser_tests/test_microwatt_register_file_pp.vhd +86 -0
- data/tests/parser_tests/test_microwatt_rotator.vhd +1 -0
- data/tests/parser_tests/test_microwatt_rotator_pp.vhd +149 -0
- data/tests/parser_tests/test_microwatt_rotator_tb.vhd +1 -0
- data/tests/parser_tests/test_microwatt_rotator_tb_pp.vhd +134 -0
- data/tests/parser_tests/test_microwatt_sim_bram.vhd +1 -0
- data/tests/parser_tests/test_microwatt_sim_bram_helpers.vhd +1 -0
- data/tests/parser_tests/test_microwatt_sim_bram_helpers_pp.vhd +52 -0
- data/tests/parser_tests/test_microwatt_sim_bram_pp.vhd +53 -0
- data/tests/parser_tests/test_microwatt_sim_console.vhd +1 -0
- data/tests/parser_tests/test_microwatt_sim_console_pp.vhd +43 -0
- data/tests/parser_tests/test_microwatt_sim_jtag.vhd +1 -0
- data/tests/parser_tests/test_microwatt_sim_jtag_pp.vhd +64 -0
- data/tests/parser_tests/test_microwatt_sim_jtag_socket.vhd +1 -0
- data/tests/parser_tests/test_microwatt_sim_jtag_socket_pp.vhd +36 -0
- data/tests/parser_tests/test_microwatt_sim_uart.vhd +1 -0
- data/tests/parser_tests/test_microwatt_sim_uart_pp.vhd +90 -0
- data/tests/parser_tests/test_microwatt_soc.vhd +1 -0
- data/tests/parser_tests/test_microwatt_soc_pp.vhd +195 -0
- data/tests/parser_tests/test_microwatt_utils.vhd +1 -0
- data/tests/parser_tests/test_microwatt_utils_pp.vhd +39 -0
- data/tests/parser_tests/test_microwatt_wishbone_arbiter.vhd +1 -0
- data/tests/parser_tests/test_microwatt_wishbone_arbiter_pp.vhd +54 -0
- data/tests/parser_tests/test_microwatt_wishbone_bram_tb.vhd +1 -0
- data/tests/parser_tests/test_microwatt_wishbone_bram_tb_pp.vhd +157 -0
- data/tests/parser_tests/test_microwatt_wishbone_bram_wrapper.vhd +1 -0
- data/tests/parser_tests/test_microwatt_wishbone_bram_wrapper_pp.vhd +62 -0
- data/tests/parser_tests/test_microwatt_wishbone_debug_master.vhd +1 -0
- data/tests/parser_tests/test_microwatt_wishbone_debug_master_pp.vhd +124 -0
- data/tests/parser_tests/test_microwatt_wishbone_types.vhd +1 -0
- data/tests/parser_tests/test_microwatt_wishbone_types_pp.vhd +38 -0
- data/tests/parser_tests/test_microwatt_writeback.vhd +1 -0
- data/tests/parser_tests/test_microwatt_writeback_pp.vhd +87 -0
- data/tests/parser_tests/test_package-1.vhd +68 -0
- data/tests/parser_tests/test_package-1_pp.vhd +53 -0
- data/tests/parser_tests/test_precedence.vhd +13 -0
- data/tests/parser_tests/test_precedence_pp.vhd +16 -0
- data/tests/parser_tests/test_selected_sig.vhd +14 -0
- data/tests/parser_tests/test_selected_sig_pp.vhd +10 -0
- data/tests/parser_tests/test_slice.vhd +15 -0
- data/tests/parser_tests/test_slice_pp.vhd +16 -0
- data/tests/parser_tests/test_tb-00.vhd +94 -0
- data/tests/parser_tests/test_tb-00_pp.vhd +71 -0
- data/tests/parser_tests/test_type_decl_02.vhd +9 -0
- data/tests/parser_tests/test_type_decl_02_pp.vhd +11 -0
- data/tests/parser_tests/test_use.vhd +7 -0
- data/tests/parser_tests/test_use_pp.vhd +10 -0
- data/tests/parser_tests/test_while_1.vhd +38 -0
- data/tests/parser_tests/test_while_1_pp.vhd +26 -0
- data/tests/parser_tests/test_with-00.vhd +21 -0
- data/tests/parser_tests/test_with-00_pp.vhd +12 -0
- data/tests/tb_gen_tests/test_accelerator.vhd +160 -0
- metadata +224 -0
@@ -0,0 +1,162 @@
|
|
1
|
+
library ieee;
|
2
|
+
use ieee.std_logic_1164.all;
|
3
|
+
use ieee.numeric_std.all;
|
4
|
+
entity fsm is
|
5
|
+
port (
|
6
|
+
reset_n: in std_logic;
|
7
|
+
clk: in std_logic;
|
8
|
+
switches: in std_logic_vector (7 downto 0);
|
9
|
+
leds: out std_logic_vector (7 downto 0)
|
10
|
+
);
|
11
|
+
end entity;
|
12
|
+
|
13
|
+
library ieee;
|
14
|
+
use ieee.std_logic_1164.all;
|
15
|
+
use ieee.numeric_std.all;
|
16
|
+
|
17
|
+
architecture rtl of fsm is
|
18
|
+
signal wrap_reset_n: std_logic;
|
19
|
+
signal wrap_clk: std_logic;
|
20
|
+
signal wrap_switches: std_logic_vector (7 downto 0);
|
21
|
+
signal wrap_leds: std_logic_vector (7 downto 0);
|
22
|
+
signal state : std_logic_vector (2 downto 0);
|
23
|
+
signal state_c : std_logic_vector (2 downto 0);
|
24
|
+
signal n4_o : std_logic;
|
25
|
+
signal n9_q : std_logic_vector (2 downto 0);
|
26
|
+
signal n12_o : std_logic;
|
27
|
+
signal n14_o : std_logic_vector (2 downto 0);
|
28
|
+
signal n15_o : std_logic;
|
29
|
+
signal n17_o : std_logic_vector (2 downto 0);
|
30
|
+
signal n18_o : std_logic;
|
31
|
+
signal n20_o : std_logic_vector (2 downto 0);
|
32
|
+
signal n21_o : std_logic;
|
33
|
+
signal n23_o : std_logic_vector (2 downto 0);
|
34
|
+
signal n24_o : std_logic;
|
35
|
+
signal n26_o : std_logic_vector (2 downto 0);
|
36
|
+
signal n27_o : std_logic;
|
37
|
+
signal n29_o : std_logic_vector (2 downto 0);
|
38
|
+
signal n30_o : std_logic;
|
39
|
+
signal n32_o : std_logic_vector (2 downto 0);
|
40
|
+
signal n33_o : std_logic;
|
41
|
+
signal n35_o : std_logic_vector (2 downto 0);
|
42
|
+
signal n36_o : std_logic_vector (1 downto 0);
|
43
|
+
signal n37_o : std_logic_vector (2 downto 0);
|
44
|
+
signal n38_o : std_logic_vector (2 downto 0);
|
45
|
+
signal n39_o : std_logic;
|
46
|
+
signal n40_o : std_logic_vector (2 downto 0);
|
47
|
+
signal n44_o : std_logic;
|
48
|
+
signal n45_o : std_logic_vector (7 downto 0);
|
49
|
+
signal n48_o : std_logic;
|
50
|
+
signal n49_o : std_logic_vector (7 downto 0);
|
51
|
+
signal n52_o : std_logic;
|
52
|
+
signal n53_o : std_logic_vector (7 downto 0);
|
53
|
+
signal n56_o : std_logic;
|
54
|
+
signal n57_o : std_logic_vector (7 downto 0);
|
55
|
+
signal n60_o : std_logic;
|
56
|
+
signal n61_o : std_logic_vector (7 downto 0);
|
57
|
+
signal n64_o : std_logic;
|
58
|
+
signal n65_o : std_logic_vector (7 downto 0);
|
59
|
+
signal n68_o : std_logic;
|
60
|
+
signal n69_o : std_logic_vector (7 downto 0);
|
61
|
+
begin
|
62
|
+
wrap_reset_n <= reset_n;
|
63
|
+
wrap_clk <= clk;
|
64
|
+
wrap_switches <= switches;
|
65
|
+
leds <= wrap_leds;
|
66
|
+
wrap_leds <= n45_o;
|
67
|
+
-- fsm.vhd:16:10
|
68
|
+
state <= n9_q; -- (signal)
|
69
|
+
-- fsm.vhd:16:16
|
70
|
+
state_c <= n40_o; -- (signal)
|
71
|
+
-- fsm.vhd:20:15
|
72
|
+
n4_o <= not wrap_reset_n;
|
73
|
+
-- fsm.vhd:22:5
|
74
|
+
process (wrap_clk, n4_o)
|
75
|
+
begin
|
76
|
+
if n4_o = '1' then
|
77
|
+
n9_q <= "000";
|
78
|
+
elsif rising_edge (wrap_clk) then
|
79
|
+
n9_q <= state_c;
|
80
|
+
end if;
|
81
|
+
end process;
|
82
|
+
-- fsm.vhd:33:20
|
83
|
+
n12_o <= wrap_switches (0);
|
84
|
+
-- fsm.vhd:33:9
|
85
|
+
n14_o <= state when n12_o = '0' else "001";
|
86
|
+
-- fsm.vhd:37:20
|
87
|
+
n15_o <= wrap_switches (1);
|
88
|
+
-- fsm.vhd:37:9
|
89
|
+
n17_o <= state when n15_o = '0' else "010";
|
90
|
+
-- fsm.vhd:41:20
|
91
|
+
n18_o <= wrap_switches (2);
|
92
|
+
-- fsm.vhd:41:9
|
93
|
+
n20_o <= state when n18_o = '0' else "011";
|
94
|
+
-- fsm.vhd:45:20
|
95
|
+
n21_o <= wrap_switches (3);
|
96
|
+
-- fsm.vhd:45:9
|
97
|
+
n23_o <= state when n21_o = '0' else "100";
|
98
|
+
-- fsm.vhd:49:20
|
99
|
+
n24_o <= wrap_switches (4);
|
100
|
+
-- fsm.vhd:49:9
|
101
|
+
n26_o <= state when n24_o = '0' else "101";
|
102
|
+
-- fsm.vhd:53:20
|
103
|
+
n27_o <= wrap_switches (5);
|
104
|
+
-- fsm.vhd:53:9
|
105
|
+
n29_o <= state when n27_o = '0' else "110";
|
106
|
+
-- fsm.vhd:57:20
|
107
|
+
n30_o <= wrap_switches (6);
|
108
|
+
-- fsm.vhd:57:9
|
109
|
+
n32_o <= state when n30_o = '0' else "111";
|
110
|
+
-- fsm.vhd:61:20
|
111
|
+
n33_o <= wrap_switches (7);
|
112
|
+
-- fsm.vhd:61:9
|
113
|
+
n35_o <= state when n33_o = '0' else "000";
|
114
|
+
-- fsm.vhd:31:10
|
115
|
+
n36_o <= state (1 downto 0);
|
116
|
+
-- fsm.vhd:31:10
|
117
|
+
with n36_o select n37_o <=
|
118
|
+
n14_o when "00",
|
119
|
+
n17_o when "01",
|
120
|
+
n20_o when "10",
|
121
|
+
n23_o when "11",
|
122
|
+
"XXX" when others;
|
123
|
+
-- fsm.vhd:31:10
|
124
|
+
with n36_o select n38_o <=
|
125
|
+
n26_o when "00",
|
126
|
+
n29_o when "01",
|
127
|
+
n32_o when "10",
|
128
|
+
n35_o when "11",
|
129
|
+
"XXX" when others;
|
130
|
+
-- fsm.vhd:31:10
|
131
|
+
n39_o <= state (2);
|
132
|
+
-- fsm.vhd:31:10
|
133
|
+
n40_o <= n37_o when n39_o = '0' else n38_o;
|
134
|
+
-- fsm.vhd:71:56
|
135
|
+
n44_o <= '1' when state = "000" else '0';
|
136
|
+
-- fsm.vhd:71:46
|
137
|
+
n45_o <= n49_o when n44_o = '0' else "00000000";
|
138
|
+
-- fsm.vhd:72:56
|
139
|
+
n48_o <= '1' when state = "001" else '0';
|
140
|
+
-- fsm.vhd:71:60
|
141
|
+
n49_o <= n53_o when n48_o = '0' else "00000001";
|
142
|
+
-- fsm.vhd:73:56
|
143
|
+
n52_o <= '1' when state = "010" else '0';
|
144
|
+
-- fsm.vhd:72:60
|
145
|
+
n53_o <= n57_o when n52_o = '0' else "00000010";
|
146
|
+
-- fsm.vhd:74:56
|
147
|
+
n56_o <= '1' when state = "011" else '0';
|
148
|
+
-- fsm.vhd:73:60
|
149
|
+
n57_o <= n61_o when n56_o = '0' else "00000011";
|
150
|
+
-- fsm.vhd:75:56
|
151
|
+
n60_o <= '1' when state = "100" else '0';
|
152
|
+
-- fsm.vhd:74:60
|
153
|
+
n61_o <= n65_o when n60_o = '0' else "00000100";
|
154
|
+
-- fsm.vhd:76:56
|
155
|
+
n64_o <= '1' when state = "101" else '0';
|
156
|
+
-- fsm.vhd:75:60
|
157
|
+
n65_o <= n69_o when n64_o = '0' else "00000101";
|
158
|
+
-- fsm.vhd:77:56
|
159
|
+
n68_o <= '1' when state = "110" else '0';
|
160
|
+
-- fsm.vhd:76:60
|
161
|
+
n69_o <= "00000111" when n68_o = '0' else "00000110";
|
162
|
+
end rtl;
|
@@ -0,0 +1,125 @@
|
|
1
|
+
-- generated by Vertigo VHDL tool
|
2
|
+
library ieee;
|
3
|
+
use ieee.std_logic_1164.all;
|
4
|
+
use ieee.numeric_std.all;
|
5
|
+
|
6
|
+
entity fsm is
|
7
|
+
port(
|
8
|
+
reset_n : in std_logic;
|
9
|
+
clk : in std_logic;
|
10
|
+
switches : in std_logic_vector(7 downto 0);
|
11
|
+
leds : out std_logic_vector(7 downto 0));
|
12
|
+
end entity fsm;
|
13
|
+
|
14
|
+
library ieee;
|
15
|
+
use ieee.std_logic_1164.all;
|
16
|
+
use ieee.numeric_std.all;
|
17
|
+
architecture rtl of fsm is
|
18
|
+
signal wrap_reset_n : std_logic;
|
19
|
+
signal wrap_clk : std_logic;
|
20
|
+
signal wrap_switches : std_logic_vector(7 downto 0);
|
21
|
+
signal wrap_leds : std_logic_vector(7 downto 0);
|
22
|
+
signal state : std_logic_vector(2 downto 0);
|
23
|
+
signal state_c : std_logic_vector(2 downto 0);
|
24
|
+
signal n4_o : std_logic;
|
25
|
+
signal n9_q : std_logic_vector(2 downto 0);
|
26
|
+
signal n12_o : std_logic;
|
27
|
+
signal n14_o : std_logic_vector(2 downto 0);
|
28
|
+
signal n15_o : std_logic;
|
29
|
+
signal n17_o : std_logic_vector(2 downto 0);
|
30
|
+
signal n18_o : std_logic;
|
31
|
+
signal n20_o : std_logic_vector(2 downto 0);
|
32
|
+
signal n21_o : std_logic;
|
33
|
+
signal n23_o : std_logic_vector(2 downto 0);
|
34
|
+
signal n24_o : std_logic;
|
35
|
+
signal n26_o : std_logic_vector(2 downto 0);
|
36
|
+
signal n27_o : std_logic;
|
37
|
+
signal n29_o : std_logic_vector(2 downto 0);
|
38
|
+
signal n30_o : std_logic;
|
39
|
+
signal n32_o : std_logic_vector(2 downto 0);
|
40
|
+
signal n33_o : std_logic;
|
41
|
+
signal n35_o : std_logic_vector(2 downto 0);
|
42
|
+
signal n36_o : std_logic_vector(1 downto 0);
|
43
|
+
signal n37_o : std_logic_vector(2 downto 0);
|
44
|
+
signal n38_o : std_logic_vector(2 downto 0);
|
45
|
+
signal n39_o : std_logic;
|
46
|
+
signal n40_o : std_logic_vector(2 downto 0);
|
47
|
+
signal n44_o : std_logic;
|
48
|
+
signal n45_o : std_logic_vector(7 downto 0);
|
49
|
+
signal n48_o : std_logic;
|
50
|
+
signal n49_o : std_logic_vector(7 downto 0);
|
51
|
+
signal n52_o : std_logic;
|
52
|
+
signal n53_o : std_logic_vector(7 downto 0);
|
53
|
+
signal n56_o : std_logic;
|
54
|
+
signal n57_o : std_logic_vector(7 downto 0);
|
55
|
+
signal n60_o : std_logic;
|
56
|
+
signal n61_o : std_logic_vector(7 downto 0);
|
57
|
+
signal n64_o : std_logic;
|
58
|
+
signal n65_o : std_logic_vector(7 downto 0);
|
59
|
+
signal n68_o : std_logic;
|
60
|
+
signal n69_o : std_logic_vector(7 downto 0);
|
61
|
+
begin
|
62
|
+
|
63
|
+
wrap_reset_n <= reset_n;
|
64
|
+
wrap_clk <= clk;
|
65
|
+
wrap_switches <= switches;
|
66
|
+
leds <= wrap_leds;
|
67
|
+
wrap_leds <= n45_o;
|
68
|
+
state <= n9_q;
|
69
|
+
state_c <= n40_o;
|
70
|
+
n4_o <= wrap_reset_n;
|
71
|
+
|
72
|
+
process(wrap_clk,n4_o)
|
73
|
+
begin
|
74
|
+
if n4_o = '1' then
|
75
|
+
n9_q <= "000";
|
76
|
+
elsif rising_edge(wrap_clk) then
|
77
|
+
n9_q <= state_c;
|
78
|
+
end if;
|
79
|
+
end process;
|
80
|
+
n12_o <= wrap_switches(0);
|
81
|
+
n14_o <= state when n12_o = '0' else "001";
|
82
|
+
n15_o <= wrap_switches(1);
|
83
|
+
n17_o <= state when n15_o = '0' else "010";
|
84
|
+
n18_o <= wrap_switches(2);
|
85
|
+
n20_o <= state when n18_o = '0' else "011";
|
86
|
+
n21_o <= wrap_switches(3);
|
87
|
+
n23_o <= state when n21_o = '0' else "100";
|
88
|
+
n24_o <= wrap_switches(4);
|
89
|
+
n26_o <= state when n24_o = '0' else "101";
|
90
|
+
n27_o <= wrap_switches(5);
|
91
|
+
n29_o <= state when n27_o = '0' else "110";
|
92
|
+
n30_o <= wrap_switches(6);
|
93
|
+
n32_o <= state when n30_o = '0' else "111";
|
94
|
+
n33_o <= wrap_switches(7);
|
95
|
+
n35_o <= state when n33_o = '0' else "000";
|
96
|
+
n36_o <= state(1 downto 0);
|
97
|
+
with n36_o select n37_o <=
|
98
|
+
n14_o when "00",
|
99
|
+
n17_o when "01",
|
100
|
+
n20_o when "10",
|
101
|
+
n23_o when "11",
|
102
|
+
"xxx" when others,;
|
103
|
+
with n36_o select n38_o <=
|
104
|
+
n26_o when "00",
|
105
|
+
n29_o when "01",
|
106
|
+
n32_o when "10",
|
107
|
+
n35_o when "11",
|
108
|
+
"xxx" when others,;
|
109
|
+
n39_o <= state(2);
|
110
|
+
n40_o <= n37_o when n39_o = '0' else n38_o;
|
111
|
+
n44_o <= '1' when state = "000" else '0';
|
112
|
+
n45_o <= n49_o when n44_o = '0' else "00000000";
|
113
|
+
n48_o <= '1' when state = "001" else '0';
|
114
|
+
n49_o <= n53_o when n48_o = '0' else "00000001";
|
115
|
+
n52_o <= '1' when state = "010" else '0';
|
116
|
+
n53_o <= n57_o when n52_o = '0' else "00000010";
|
117
|
+
n56_o <= '1' when state = "011" else '0';
|
118
|
+
n57_o <= n61_o when n56_o = '0' else "00000011";
|
119
|
+
n60_o <= '1' when state = "100" else '0';
|
120
|
+
n61_o <= n65_o when n60_o = '0' else "00000100";
|
121
|
+
n64_o <= '1' when state = "101" else '0';
|
122
|
+
n65_o <= n69_o when n64_o = '0' else "00000101";
|
123
|
+
n68_o <= '1' when state = "110" else '0';
|
124
|
+
n69_o <= "00000111" when n68_o = '0' else "00000110";
|
125
|
+
end rtl;
|
@@ -0,0 +1,248 @@
|
|
1
|
+
library ieee;
|
2
|
+
use ieee.std_logic_1164.all;
|
3
|
+
use ieee.numeric_std.all;
|
4
|
+
entity fsm is
|
5
|
+
port (
|
6
|
+
reset_n: in std_logic;
|
7
|
+
clk: in std_logic;
|
8
|
+
switches: in std_logic_vector (7 downto 0);
|
9
|
+
leds: out std_logic_vector (7 downto 0);
|
10
|
+
o1, o2: out std_logic;
|
11
|
+
o3: out unsigned (3 downto 0)
|
12
|
+
);
|
13
|
+
end entity;
|
14
|
+
|
15
|
+
library ieee;
|
16
|
+
use ieee.std_logic_1164.all;
|
17
|
+
use ieee.numeric_std.all;
|
18
|
+
|
19
|
+
architecture rtl of fsm is
|
20
|
+
signal wrap_reset_n: std_logic;
|
21
|
+
signal wrap_clk: std_logic;
|
22
|
+
signal wrap_switches: std_logic_vector (7 downto 0);
|
23
|
+
signal wrap_leds: std_logic_vector (7 downto 0);
|
24
|
+
signal wrap_o1: std_logic;
|
25
|
+
signal wrap_o2: std_logic;
|
26
|
+
signal wrap_o3: std_logic_vector (3 downto 0);
|
27
|
+
signal state : std_logic_vector (2 downto 0);
|
28
|
+
signal state_c : std_logic_vector (2 downto 0);
|
29
|
+
signal c3 : std_logic_vector (3 downto 0);
|
30
|
+
signal n7_o : std_logic;
|
31
|
+
signal n12_q : std_logic_vector (2 downto 0);
|
32
|
+
signal n17_o : std_logic;
|
33
|
+
signal n19_o : std_logic_vector (2 downto 0);
|
34
|
+
signal n20_o : std_logic;
|
35
|
+
signal n22_o : std_logic_vector (2 downto 0);
|
36
|
+
signal n23_o : std_logic;
|
37
|
+
signal n25_o : std_logic_vector (2 downto 0);
|
38
|
+
signal n26_o : std_logic;
|
39
|
+
signal n28_o : std_logic_vector (2 downto 0);
|
40
|
+
signal n29_o : std_logic;
|
41
|
+
signal n31_o : std_logic_vector (2 downto 0);
|
42
|
+
signal n32_o : std_logic;
|
43
|
+
signal n35_o : std_logic;
|
44
|
+
signal n36_o : std_logic_vector (2 downto 0);
|
45
|
+
signal n37_o : std_logic;
|
46
|
+
signal n40_o : std_logic;
|
47
|
+
signal n41_o : std_logic_vector (2 downto 0);
|
48
|
+
signal n42_o : std_logic;
|
49
|
+
signal n44_o : std_logic_vector (2 downto 0);
|
50
|
+
signal n45_o : std_logic_vector (1 downto 0);
|
51
|
+
signal n46_o : std_logic;
|
52
|
+
signal n47_o : std_logic;
|
53
|
+
signal n48_o : std_logic;
|
54
|
+
signal n49_o : std_logic;
|
55
|
+
signal n50_o : std_logic_vector (1 downto 0);
|
56
|
+
signal n51_o : std_logic;
|
57
|
+
signal n52_o : std_logic;
|
58
|
+
signal n53_o : std_logic;
|
59
|
+
signal n54_o : std_logic;
|
60
|
+
signal n55_o : std_logic_vector (1 downto 0);
|
61
|
+
signal n56_o : std_logic_vector (2 downto 0);
|
62
|
+
signal n57_o : std_logic_vector (2 downto 0);
|
63
|
+
signal n58_o : std_logic;
|
64
|
+
signal n59_o : std_logic_vector (2 downto 0);
|
65
|
+
signal n63_o : std_logic;
|
66
|
+
signal n64_o : std_logic_vector (7 downto 0);
|
67
|
+
signal n67_o : std_logic;
|
68
|
+
signal n68_o : std_logic_vector (7 downto 0);
|
69
|
+
signal n71_o : std_logic;
|
70
|
+
signal n72_o : std_logic_vector (7 downto 0);
|
71
|
+
signal n75_o : std_logic;
|
72
|
+
signal n76_o : std_logic_vector (7 downto 0);
|
73
|
+
signal n79_o : std_logic;
|
74
|
+
signal n80_o : std_logic_vector (7 downto 0);
|
75
|
+
signal n83_o : std_logic;
|
76
|
+
signal n84_o : std_logic_vector (7 downto 0);
|
77
|
+
signal n87_o : std_logic;
|
78
|
+
signal n88_o : std_logic_vector (7 downto 0);
|
79
|
+
signal n92_o : std_logic;
|
80
|
+
signal n96_o : std_logic_vector (3 downto 0);
|
81
|
+
signal n99_q : std_logic_vector (3 downto 0);
|
82
|
+
begin
|
83
|
+
wrap_reset_n <= reset_n;
|
84
|
+
wrap_clk <= clk;
|
85
|
+
wrap_switches <= switches;
|
86
|
+
leds <= wrap_leds;
|
87
|
+
o1 <= wrap_o1;
|
88
|
+
o2 <= wrap_o2;
|
89
|
+
o3 <= unsigned(wrap_o3);
|
90
|
+
wrap_leds <= n64_o;
|
91
|
+
wrap_o1 <= n49_o;
|
92
|
+
wrap_o2 <= n54_o;
|
93
|
+
wrap_o3 <= c3;
|
94
|
+
-- fsm.vhd:18:10
|
95
|
+
state <= n12_q; -- (signal)
|
96
|
+
-- fsm.vhd:18:16
|
97
|
+
state_c <= n59_o; -- (signal)
|
98
|
+
-- fsm.vhd:20:10
|
99
|
+
c3 <= n99_q; -- (signal)
|
100
|
+
-- fsm.vhd:24:15
|
101
|
+
n7_o <= not wrap_reset_n;
|
102
|
+
-- fsm.vhd:26:5
|
103
|
+
process (wrap_clk, n7_o)
|
104
|
+
begin
|
105
|
+
if n7_o = '1' then
|
106
|
+
n12_q <= "000";
|
107
|
+
elsif rising_edge (wrap_clk) then
|
108
|
+
n12_q <= state_c;
|
109
|
+
end if;
|
110
|
+
end process;
|
111
|
+
-- fsm.vhd:39:20
|
112
|
+
n17_o <= wrap_switches (0);
|
113
|
+
-- fsm.vhd:39:9
|
114
|
+
n19_o <= state when n17_o = '0' else "001";
|
115
|
+
-- fsm.vhd:43:20
|
116
|
+
n20_o <= wrap_switches (1);
|
117
|
+
-- fsm.vhd:43:9
|
118
|
+
n22_o <= state when n20_o = '0' else "010";
|
119
|
+
-- fsm.vhd:47:20
|
120
|
+
n23_o <= wrap_switches (2);
|
121
|
+
-- fsm.vhd:47:9
|
122
|
+
n25_o <= state when n23_o = '0' else "011";
|
123
|
+
-- fsm.vhd:51:20
|
124
|
+
n26_o <= wrap_switches (3);
|
125
|
+
-- fsm.vhd:51:9
|
126
|
+
n28_o <= state when n26_o = '0' else "100";
|
127
|
+
-- fsm.vhd:55:20
|
128
|
+
n29_o <= wrap_switches (4);
|
129
|
+
-- fsm.vhd:55:9
|
130
|
+
n31_o <= state when n29_o = '0' else "101";
|
131
|
+
-- fsm.vhd:59:20
|
132
|
+
n32_o <= wrap_switches (5);
|
133
|
+
-- fsm.vhd:59:9
|
134
|
+
n35_o <= '0' when n32_o = '0' else '1';
|
135
|
+
-- fsm.vhd:59:9
|
136
|
+
n36_o <= state when n32_o = '0' else "110";
|
137
|
+
-- fsm.vhd:64:20
|
138
|
+
n37_o <= wrap_switches (6);
|
139
|
+
-- fsm.vhd:64:9
|
140
|
+
n40_o <= '1' when n37_o = '0' else '1';
|
141
|
+
-- fsm.vhd:64:9
|
142
|
+
n41_o <= state when n37_o = '0' else "111";
|
143
|
+
-- fsm.vhd:69:20
|
144
|
+
n42_o <= wrap_switches (7);
|
145
|
+
-- fsm.vhd:69:9
|
146
|
+
n44_o <= state when n42_o = '0' else "000";
|
147
|
+
-- fsm.vhd:37:10
|
148
|
+
n45_o <= state (1 downto 0);
|
149
|
+
-- fsm.vhd:37:10
|
150
|
+
with n45_o select n46_o <=
|
151
|
+
'0' when "00",
|
152
|
+
'0' when "01",
|
153
|
+
'0' when "10",
|
154
|
+
'0' when "11",
|
155
|
+
'X' when others;
|
156
|
+
-- fsm.vhd:37:10
|
157
|
+
with n45_o select n47_o <=
|
158
|
+
'0' when "00",
|
159
|
+
n35_o when "01",
|
160
|
+
'0' when "10",
|
161
|
+
'0' when "11",
|
162
|
+
'X' when others;
|
163
|
+
-- fsm.vhd:37:10
|
164
|
+
n48_o <= state (2);
|
165
|
+
-- fsm.vhd:37:10
|
166
|
+
n49_o <= n46_o when n48_o = '0' else n47_o;
|
167
|
+
-- fsm.vhd:37:10
|
168
|
+
n50_o <= state (1 downto 0);
|
169
|
+
-- fsm.vhd:37:10
|
170
|
+
with n50_o select n51_o <=
|
171
|
+
'1' when "00",
|
172
|
+
'1' when "01",
|
173
|
+
'1' when "10",
|
174
|
+
'1' when "11",
|
175
|
+
'X' when others;
|
176
|
+
-- fsm.vhd:37:10
|
177
|
+
with n50_o select n52_o <=
|
178
|
+
'1' when "00",
|
179
|
+
'1' when "01",
|
180
|
+
n40_o when "10",
|
181
|
+
'1' when "11",
|
182
|
+
'X' when others;
|
183
|
+
-- fsm.vhd:37:10
|
184
|
+
n53_o <= state (2);
|
185
|
+
-- fsm.vhd:37:10
|
186
|
+
n54_o <= n51_o when n53_o = '0' else n52_o;
|
187
|
+
-- fsm.vhd:37:10
|
188
|
+
n55_o <= state (1 downto 0);
|
189
|
+
-- fsm.vhd:37:10
|
190
|
+
with n55_o select n56_o <=
|
191
|
+
n19_o when "00",
|
192
|
+
n22_o when "01",
|
193
|
+
n25_o when "10",
|
194
|
+
n28_o when "11",
|
195
|
+
"XXX" when others;
|
196
|
+
-- fsm.vhd:37:10
|
197
|
+
with n55_o select n57_o <=
|
198
|
+
n31_o when "00",
|
199
|
+
n36_o when "01",
|
200
|
+
n41_o when "10",
|
201
|
+
n44_o when "11",
|
202
|
+
"XXX" when others;
|
203
|
+
-- fsm.vhd:37:10
|
204
|
+
n58_o <= state (2);
|
205
|
+
-- fsm.vhd:37:10
|
206
|
+
n59_o <= n56_o when n58_o = '0' else n57_o;
|
207
|
+
-- fsm.vhd:79:56
|
208
|
+
n63_o <= '1' when state = "000" else '0';
|
209
|
+
-- fsm.vhd:79:46
|
210
|
+
n64_o <= n68_o when n63_o = '0' else "00000000";
|
211
|
+
-- fsm.vhd:80:56
|
212
|
+
n67_o <= '1' when state = "001" else '0';
|
213
|
+
-- fsm.vhd:79:60
|
214
|
+
n68_o <= n72_o when n67_o = '0' else "00000001";
|
215
|
+
-- fsm.vhd:81:56
|
216
|
+
n71_o <= '1' when state = "010" else '0';
|
217
|
+
-- fsm.vhd:80:60
|
218
|
+
n72_o <= n76_o when n71_o = '0' else "00000010";
|
219
|
+
-- fsm.vhd:82:56
|
220
|
+
n75_o <= '1' when state = "011" else '0';
|
221
|
+
-- fsm.vhd:81:60
|
222
|
+
n76_o <= n80_o when n75_o = '0' else "00000011";
|
223
|
+
-- fsm.vhd:83:56
|
224
|
+
n79_o <= '1' when state = "100" else '0';
|
225
|
+
-- fsm.vhd:82:60
|
226
|
+
n80_o <= n84_o when n79_o = '0' else "00000100";
|
227
|
+
-- fsm.vhd:84:56
|
228
|
+
n83_o <= '1' when state = "101" else '0';
|
229
|
+
-- fsm.vhd:83:60
|
230
|
+
n84_o <= n88_o when n83_o = '0' else "00000101";
|
231
|
+
-- fsm.vhd:85:56
|
232
|
+
n87_o <= '1' when state = "110" else '0';
|
233
|
+
-- fsm.vhd:84:60
|
234
|
+
n88_o <= "00000111" when n87_o = '0' else "00000110";
|
235
|
+
-- fsm.vhd:90:15
|
236
|
+
n92_o <= not wrap_reset_n;
|
237
|
+
-- fsm.vhd:93:16
|
238
|
+
n96_o <= std_logic_vector (unsigned (c3) + unsigned'("0001"));
|
239
|
+
-- fsm.vhd:92:5
|
240
|
+
process (wrap_clk, n92_o)
|
241
|
+
begin
|
242
|
+
if n92_o = '1' then
|
243
|
+
n99_q <= "0000";
|
244
|
+
elsif rising_edge (wrap_clk) then
|
245
|
+
n99_q <= n96_o;
|
246
|
+
end if;
|
247
|
+
end process;
|
248
|
+
end rtl;
|