vertigo_vhdl 0.8.2

data/tests/parser_tests/test_microwatt_multiply.vhd

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+../microwatt/multiply.vhdl

data/tests/parser_tests/test_microwatt_multiply_pp.vhd

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+-- generated by Vertigo VHDL tool
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.common.all;
+use work.decode_types.all;
+ 
+entity multiply is
+  generic(
+    pipeline_depth : natural16 := 16);
+  port(
+    clk : in std_logic;
+    m_in : in execute1tomultiplytype;
+    m_out : out multiplytoexecute1type);
+end entity multiply;
+ 
+architecture behaviour of multiply is
+  signal m : execute1tomultiplytype;
+   
+  type multiply_pipeline_stage is record
+    valid : std_ulogic;
+    insn_type : insn_type_t;
+    data : signed(129 downto 0);
+    is_32bit : std_ulogic;
+  end record;
+  constant multiplypipelinestageinit : multiply_pipeline_stage := (valid => '0',insn_type => op_illegal,is_32bit => '0',data => (others => '0'));
+   
+  type multiply_pipeline_type is array(range 0 to pipeline_depth - 1) of multiply_pipeline_stage;
+  constant multiplypipelineinit : multiply_pipeline_type := (others => multiplypipelinestageinit);
+   
+  type reg_type is record
+    multiply_pipeline : multiply_pipeline_type;
+  end record;
+  signal r : reg_type;
+  signal rin : reg_type := (multiply_pipeline => multiplypipelineinit);
+begin
+ 
+   
+  multiply_0 : process(clk)
+  begin
+    if rising_edge(clk) then
+      m <= m_in;
+      r <= rin;
+    end if;
+  end process;
+   
+  multiply_1 : process(all)
+    variable v : reg_type;
+    variable d : std_ulogic_vector(129 downto 0);
+    variable d2 : std_ulogic_vector(63 downto 0);
+    variable ov : std_ulogic;
+  begin
+    v := r;
+    m_out <= multiplytoexecute1init;
+    v.multiply_pipeline(0).valid := m.valid;
+    v.multiply_pipeline(0).insn_type := m.insn_type;
+    v.multiply_pipeline(0).data := signed(m.data1) * signed(m.data2);
+    v.multiply_pipeline(0).is_32bit := m.is_32bit;
+    d := std_ulogic_vector(v.multiply_pipeline(pipeline_depth - 1).data);
+    ov := '0';
+    case v.multiply_pipeline(pipeline_depth - 1).insn_type is
+      when op_mul_l64 =>
+        d2 := d(63 downto 0);
+        if v.multiply_pipeline(pipeline_depth - 1).is_32bit = '1' then
+          ov := (or(d(63 downto 31))) and (and(d(63 downto 31)));
+        else
+          ov := (or(d(127 downto 63))) and (and(d(127 downto 63)));
+        end if;
+      when op_mul_h32 =>
+        d2 := d(63 downto 32) & d(63 downto 32);
+      when op_mul_h64 =>
+        d2 := d(127 downto 64);
+      when others =>
+        d2 := (others => '0');
+    end case;
+    m_out.write_reg_data <= d2;
+    m_out.overflow <= ov;
+    if v.multiply_pipeline(pipeline_depth - 1).valid = '1' then
+      m_out.valid <= '1';
+    end if;
+    rin <= v;
+  end process;
+end behaviour;

data/tests/parser_tests/test_microwatt_multiply_tb.vhd

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+../microwatt/multiply_tb.vhdl

data/tests/parser_tests/test_microwatt_multiply_tb_pp.vhd

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+-- generated by Vertigo VHDL tool
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.decode_types.all;
+use work.common.all;
+use work.glibc_random.all;
+use work.ppc_fx_insns.all;
+ 
+entity multiply_tb is
+end entity multiply_tb;
+ 
+architecture behave of multiply_tb is
+  signal clk : std_ulogic;
+  constant clk_period : time := 10 ns;
+  constant pipeline_depth : integer := 4;
+  signal m1 : execute1tomultiplytype;
+  signal m2 : multiplytoexecute1type;
+begin
+ 
+  multiply_0 : entity work.multiply
+    port map(
+      clk => clk,
+      m_in => m1,
+      m_out => m2);
+   
+   
+  clk_process : process
+  begin
+    clk <= '0';
+    wait clk_period / 2;
+    clk <= '1';
+    wait clk_period / 2;
+  end process;
+   
+  stim_process : process
+    variable ra : std_ulogic_vector(63 downto 0);
+    variable rb : std_ulogic_vector(63 downto 0);
+    variable rt : std_ulogic_vector(63 downto 0);
+    variable behave_rt : std_ulogic_vector(63 downto 0);
+    variable si : std_ulogic_vector(15 downto 0);
+  begin
+    wait clk_period;
+    m1.valid <= '1';
+    m1.insn_type <= op_mul_l64;
+    m1.data1 <= '0' & x"0000000000001000";
+    m1.data2 <= '0' & x"0000000000001111";
+    wait clk_period;
+    assert m2.valid = '0';
+    m1.valid <= '0';
+    wait clk_period;
+    assert m2.valid = '0';
+    wait clk_period;
+    assert m2.valid = '0';
+    wait clk_period;
+    assert m2.valid = '1';
+    assert m2.write_reg_data = x"0000000001111000";
+    wait clk_period;
+    assert m2.valid = '0';
+    m1.valid <= '1';
+    wait clk_period;
+    assert m2.valid = '0';
+    m1.valid <= '0';
+    wait clk_period * (pipeline_depth - 1);
+    assert m2.valid = '1';
+    assert m2.write_reg_data = x"0000000001111000";
+    ;
+    ;
+    ;
+    assert false
+      report "end of test" severity failure;
+    wait ;
+  end process;
+end behave;

data/tests/parser_tests/test_microwatt_plru.vhd

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+../microwatt/plru.vhdl

data/tests/parser_tests/test_microwatt_plru_pp.vhd

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+-- generated by Vertigo VHDL tool
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+ 
+entity plru is
+  generic(
+    bits : positive2 := 2);
+  port(
+    clk : in std_ulogic;
+    rst : in std_ulogic;
+    acc : in std_ulogic_vector(bits - 1 downto 0);
+    acc_en : in std_ulogic;
+    lru : out std_ulogic_vector(bits - 1 downto 0));
+end entity plru;
+ 
+architecture rtl of plru is
+  constant count : positive := 2 ** bits - 1;
+   
+  subtype node_t is integer range 0 to count;
+   
+  type tree_t is array(range node_t) of std_ulogic;
+  signal tree : tree_t;
+begin
+ 
+   
+  get_lru : process(tree)
+    variable node : node_t;
+  begin
+    node := 0;
+  end process;
+   
+  update_lru : process(clk)
+    variable node : node_t;
+    variable abit : std_ulogic;
+  begin
+    if rising_edge(clk) then
+      if rst = '1' then
+        tree <= (others => '0');
+      elsif acc_en = '1' then
+        node := 0;
+      end if;
+    end if;
+  end process;
+end rtl;

data/tests/parser_tests/test_microwatt_plru_tb.vhd

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+../microwatt/plru_tb.vhdl

data/tests/parser_tests/test_microwatt_plru_tb_pp.vhd

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+-- generated by Vertigo VHDL tool
+library ieee;
+use ieee.std_logic_1164.all;
+library work;
+use work.common.all;
+use work.wishbone_types.all;
+ 
+entity plru_tb is
+end entity plru_tb;
+ 
+architecture behave of plru_tb is
+  signal clk : std_ulogic;
+  signal rst : std_ulogic;
+  constant clk_period : time := 10 ns;
+  signal acc_en : std_ulogic;
+  signal acc : std_ulogic_vector(2 downto 0);
+  signal lru : std_ulogic_vector(2 downto 0);
+begin
+ 
+  plru0 : entity work.plru
+    port map(
+      clk => clk,
+      rst => rst,
+      acc => acc,
+      acc_en => acc_en,
+      lru => lru);
+   
+   
+  clk_process : process
+  begin
+    clk <= '0';
+    wait clk_period / 2;
+    clk <= '1';
+    wait clk_period / 2;
+  end process;
+   
+  rst_process : process
+  begin
+    rst <= '1';
+    wait 2 * clk_period;
+    rst <= '0';
+    wait ;
+  end process;
+   
+  stim : process
+  begin
+    wait 4 * clk_period;
+    report "accessing 1:";
+    acc <= "001";
+    acc_en <= '1';
+    wait clk_period;
+    report "lru:" & to_hstring(lru);
+    report "accessing 2:";
+    acc <= "010";
+    wait clk_period;
+    report "lru:" & to_hstring(lru);
+    report "accessing 7:";
+    acc <= "111";
+    wait clk_period;
+    report "lru:" & to_hstring(lru);
+    report "accessing 4:";
+    acc <= "100";
+    wait clk_period;
+    report "lru:" & to_hstring(lru);
+    report "accessing 3:";
+    acc <= "011";
+    wait clk_period;
+    report "lru:" & to_hstring(lru);
+    report "accessing 5:";
+    acc <= "101";
+    wait clk_period;
+    report "lru:" & to_hstring(lru);
+    report "accessing 3:";
+    acc <= "011";
+    wait clk_period;
+    report "lru:" & to_hstring(lru);
+    report "accessing 5:";
+    acc <= "101";
+    wait clk_period;
+    report "lru:" & to_hstring(lru);
+    report "accessing 6:";
+    acc <= "110";
+    wait clk_period;
+    report "lru:" & to_hstring(lru);
+    report "accessing 0:";
+    acc <= "000";
+    wait clk_period;
+    report "lru:" & to_hstring(lru);
+    assert false
+      report "end of test" severity failure;
+    wait ;
+  end process;
+end behave;

data/tests/parser_tests/test_microwatt_ppc_fx_insns.vhd

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+../microwatt/ppc_fx_insns.vhdl

data/tests/parser_tests/test_microwatt_ppc_fx_insns_pp.vhd

@@ -0,0 +1,665 @@
+-- generated by Vertigo VHDL tool
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.helpers.all;
+ 
+package ppc_fx_insns is
+  function ppc_addi(ra : std_ulogic_vector(63 downto 0);si : std_ulogic_vector(15 downto 0)) return std_ulogic_vector
+  function ppc_addis(ra : std_ulogic_vector(63 downto 0);si : std_ulogic_vector(15 downto 0)) return std_ulogic_vector
+  function ppc_add(ra : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
+  function ppc_subf(ra : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
+  function ppc_neg(ra : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
+  function ppc_addic(ra : std_ulogic_vector(63 downto 0);si : std_ulogic_vector(15 downto 0)) return std_ulogic_vector
+  function ppc_adde(ra : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0);carry : std_ulogic) return std_ulogic_vector
+  function ppc_subfic(ra : std_ulogic_vector(63 downto 0);si : std_ulogic_vector(15 downto 0)) return std_ulogic_vector
+  function ppc_subfc(ra : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
+  function ppc_subfe(ra : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0);carry : std_ulogic) return std_ulogic_vector
+  function ppc_addze(ra : std_ulogic_vector(63 downto 0);carry : std_ulogic) return std_ulogic_vector
+  function ppc_andi(rs : std_ulogic_vector(63 downto 0);ui : std_ulogic_vector(15 downto 0)) return std_ulogic_vector
+  function ppc_andis(rs : std_ulogic_vector(63 downto 0);ui : std_ulogic_vector(15 downto 0)) return std_ulogic_vector
+  function ppc_ori(rs : std_ulogic_vector(63 downto 0);ui : std_ulogic_vector(15 downto 0)) return std_ulogic_vector
+  function ppc_oris(rs : std_ulogic_vector(63 downto 0);ui : std_ulogic_vector(15 downto 0)) return std_ulogic_vector
+  function ppc_xori(rs : std_ulogic_vector(63 downto 0);ui : std_ulogic_vector(15 downto 0)) return std_ulogic_vector
+  function ppc_xoris(rs : std_ulogic_vector(63 downto 0);ui : std_ulogic_vector(15 downto 0)) return std_ulogic_vector
+  function ppc_and(rs : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
+  function ppc_xor(rs : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
+  function ppc_nand(rs : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
+  function ppc_or(rs : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
+  function ppc_nor(rs : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
+  function ppc_andc(rs : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
+  function ppc_eqv(rs : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
+  function ppc_orc(rs : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
+  function ppc_extsb(rs : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
+  function ppc_extsh(rs : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
+  function ppc_extsw(rs : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
+  function ppc_cntlzw(rs : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
+  function ppc_cnttzw(rs : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
+  function ppc_cntlzd(rs : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
+  function ppc_cnttzd(rs : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
+  function ppc_popcntb(rs : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
+  function ppc_popcntw(rs : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
+  function ppc_popcntd(rs : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
+  function ppc_prtyd(rs : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
+  function ppc_prtyw(rs : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
+  function ppc_rlwinm(rs : std_ulogic_vector(63 downto 0);sh : std_ulogic_vector(4 downto 0);mb : std_ulogic_vector(4 downto 0);me : std_ulogic_vector(4 downto 0)) return std_ulogic_vector
+  function ppc_rlwnm(rs : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0);mb : std_ulogic_vector(4 downto 0);me : std_ulogic_vector(4 downto 0)) return std_ulogic_vector
+  function ppc_rlwimi(ra : std_ulogic_vector(63 downto 0);rs : std_ulogic_vector(63 downto 0);sh : std_ulogic_vector(4 downto 0);mb : std_ulogic_vector(4 downto 0);me : std_ulogic_vector(4 downto 0)) return std_ulogic_vector
+  function ppc_rldicl(rs : std_ulogic_vector(63 downto 0);sh : std_ulogic_vector(5 downto 0);mb : std_ulogic_vector(5 downto 0)) return std_ulogic_vector
+  function ppc_rldicr(rs : std_ulogic_vector(63 downto 0);sh : std_ulogic_vector(5 downto 0);me : std_ulogic_vector(5 downto 0)) return std_ulogic_vector
+  function ppc_rldic(rs : std_ulogic_vector(63 downto 0);sh : std_ulogic_vector(5 downto 0);mb : std_ulogic_vector(5 downto 0)) return std_ulogic_vector
+  function ppc_rldcl(rs : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0);mb : std_ulogic_vector(5 downto 0)) return std_ulogic_vector
+  function ppc_rldcr(rs : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0);me : std_ulogic_vector(5 downto 0)) return std_ulogic_vector
+  function ppc_rldimi(ra : std_ulogic_vector(63 downto 0);rs : std_ulogic_vector(63 downto 0);sh : std_ulogic_vector(5 downto 0);mb : std_ulogic_vector(5 downto 0)) return std_ulogic_vector
+  function ppc_slw(rs : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
+  function ppc_srw(rs : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
+  function ppc_srawi(rs : std_ulogic_vector(63 downto 0);sh : std_ulogic_vector(5 downto 0)) return std_ulogic_vector
+  function ppc_sraw(rs : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
+  function ppc_sld(rs : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
+  function ppc_srd(rs : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
+  function ppc_sradi(rs : std_ulogic_vector(63 downto 0);sh : std_ulogic_vector(5 downto 0)) return std_ulogic_vector
+  function ppc_srad(rs : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
+  function ppc_mulld(ra : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
+  function ppc_mulhd(ra : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
+  function ppc_mulhdu(ra : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
+  function ppc_mulli(ra : std_ulogic_vector(63 downto 0);si : std_ulogic_vector(15 downto 0)) return std_ulogic_vector
+  function ppc_mullw(ra : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
+  function ppc_mulhw(ra : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
+  function ppc_mulhwu(ra : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
+  function ppc_cmpi(l : std_ulogic;ra : std_ulogic_vector(63 downto 0);si : std_ulogic_vector(15 downto 0);so : std_ulogic) return std_ulogic_vector
+  function ppc_cmp(l : std_ulogic;ra : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0);so : std_ulogic) return std_ulogic_vector
+  function ppc_cmpli(l : std_ulogic;ra : std_ulogic_vector(63 downto 0);si : std_ulogic_vector(15 downto 0);so : std_ulogic) return std_ulogic_vector
+  function ppc_cmpl(l : std_ulogic;ra : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0);so : std_ulogic) return std_ulogic_vector
+  function ppc_cmpb(rs : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
+  function ppc_divw(ra : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
+  function ppc_divdu(ra : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
+  function ppc_divd(ra : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
+  function ppc_divwu(ra : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
+  function ppc_bc_taken(bo : std_ulogic_vector(4 downto 0);bi : std_ulogic_vector(4 downto 0);cr : std_ulogic_vector(31 downto 0);ctr : std_ulogic_vector(63 downto 0)) return integer
+ 
+end ppc_fx_insns;
+ 
+package body ppc_fx_insns is
+   
+  function ppc_addi(ra : std_ulogic_vector(63 downto 0);si : std_ulogic_vector(15 downto 0)) return std_ulogic_vector is
+  begin
+    return std_ulogic_vector(signed(ra) + signed(si));
+  end function ppc_addi;
+   
+  function ppc_addic(ra : std_ulogic_vector(63 downto 0);si : std_ulogic_vector(15 downto 0)) return std_ulogic_vector is
+  begin
+    return std_logic_vector(resize(unsigned(ra),65) + unsigned(resize(signed(si),64)));
+  end function ppc_addic;
+   
+  function ppc_adde(ra : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0);carry : std_ulogic) return std_ulogic_vector is
+  begin
+    return std_logic_vector(resize(unsigned(ra),65) + resize(unsigned(rb),65) + carry);
+  end function ppc_adde;
+   
+  function ppc_subfic(ra : std_ulogic_vector(63 downto 0);si : std_ulogic_vector(15 downto 0)) return std_ulogic_vector is
+  begin
+    return std_logic_vector(unsigned(resize(signed(si),64)) + resize(unsigned((ra)),65) + 1);
+  end function ppc_subfic;
+   
+  function ppc_subfc(ra : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
+  begin
+    return std_logic_vector(resize(unsigned(rb),65) + resize(unsigned((ra)),65) + 1);
+  end function ppc_subfc;
+   
+  function ppc_subfe(ra : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0);carry : std_ulogic) return std_ulogic_vector is
+  begin
+    return std_logic_vector(resize(unsigned(rb),65) + resize(unsigned((ra)),65) + carry);
+  end function ppc_subfe;
+   
+  function ppc_addze(ra : std_ulogic_vector(63 downto 0);carry : std_ulogic) return std_ulogic_vector is
+  begin
+    return std_logic_vector(resize(unsigned(ra),65) + carry);
+  end function ppc_addze;
+   
+  function ppc_addis(ra : std_ulogic_vector(63 downto 0);si : std_ulogic_vector(15 downto 0)) return std_ulogic_vector is
+  begin
+    return std_ulogic_vector(signed(ra) + shift_left(resize(signed(si),32),16));
+  end function ppc_addis;
+   
+  function ppc_add(ra : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
+  begin
+    return std_ulogic_vector(signed(ra) + signed(rb));
+  end function ppc_add;
+   
+  function ppc_subf(ra : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
+  begin
+    return std_ulogic_vector(signed(rb) - signed(ra));
+  end function ppc_subf;
+   
+  function ppc_neg(ra : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
+  begin
+    return std_ulogic_vector(signed(ra));
+  end function ppc_neg;
+   
+  function ppc_andi(rs : std_ulogic_vector(63 downto 0);ui : std_ulogic_vector(15 downto 0)) return std_ulogic_vector is
+  begin
+    return rs and std_ulogic_vector(resize(unsigned(ui),64));
+  end function ppc_andi;
+   
+  function ppc_andis(rs : std_ulogic_vector(63 downto 0);ui : std_ulogic_vector(15 downto 0)) return std_ulogic_vector is
+  begin
+    return rs and std_ulogic_vector(shift_left(resize(unsigned(ui),64),16));
+  end function ppc_andis;
+   
+  function ppc_ori(rs : std_ulogic_vector(63 downto 0);ui : std_ulogic_vector(15 downto 0)) return std_ulogic_vector is
+  begin
+    return rs or std_ulogic_vector(resize(unsigned(ui),64));
+  end function ppc_ori;
+   
+  function ppc_oris(rs : std_ulogic_vector(63 downto 0);ui : std_ulogic_vector(15 downto 0)) return std_ulogic_vector is
+  begin
+    return rs or std_ulogic_vector(shift_left(resize(unsigned(ui),64),16));
+  end function ppc_oris;
+   
+  function ppc_xori(rs : std_ulogic_vector(63 downto 0);ui : std_ulogic_vector(15 downto 0)) return std_ulogic_vector is
+  begin
+    return rs xor std_ulogic_vector(resize(unsigned(ui),64));
+  end function ppc_xori;
+   
+  function ppc_xoris(rs : std_ulogic_vector(63 downto 0);ui : std_ulogic_vector(15 downto 0)) return std_ulogic_vector is
+  begin
+    return rs xor std_ulogic_vector(shift_left(resize(unsigned(ui),64),16));
+  end function ppc_xoris;
+   
+  function ppc_and(rs : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
+  begin
+    return rs and rb;
+  end function ppc_and;
+   
+  function ppc_xor(rs : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
+  begin
+    return rs xor rb;
+  end function ppc_xor;
+   
+  function ppc_nand(rs : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
+  begin
+    return rs nand rb;
+  end function ppc_nand;
+   
+  function ppc_or(rs : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
+  begin
+    return rs or rb;
+  end function ppc_or;
+   
+  function ppc_nor(rs : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
+  begin
+    return rs nor rb;
+  end function ppc_nor;
+   
+  function ppc_andc(rs : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
+  begin
+    return rs and (rb);
+  end function ppc_andc;
+   
+  function ppc_eqv(rs : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
+  begin
+    return (rs xor rb);
+  end function ppc_eqv;
+   
+  function ppc_orc(rs : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
+  begin
+    return rs or (rb);
+  end function ppc_orc;
+   
+  function ppc_extsb(rs : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
+  begin
+    return std_ulogic_vector(resize(signed(rs(7 downto 0)),rs'length));
+  end function ppc_extsb;
+   
+  function ppc_extsh(rs : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
+  begin
+    return std_ulogic_vector(resize(signed(rs(15 downto 0)),rs'length));
+  end function ppc_extsh;
+   
+  function ppc_extsw(rs : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
+  begin
+    return std_ulogic_vector(resize(signed(rs(31 downto 0)),rs'length));
+  end function ppc_extsw;
+   
+  function ppc_cntlzw(rs : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
+  begin
+    return std_ulogic_vector(to_unsigned(fls_32(rs(31 downto 0)),rs'length));
+  end function ppc_cntlzw;
+   
+  function ppc_cnttzw(rs : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
+  begin
+    return std_ulogic_vector(to_unsigned(ffs_32(rs(31 downto 0)),rs'length));
+  end function ppc_cnttzw;
+   
+  function ppc_cntlzd(rs : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
+  begin
+    return std_ulogic_vector(to_unsigned(fls_64(rs),rs'length));
+  end function ppc_cntlzd;
+   
+  function ppc_cnttzd(rs : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
+  begin
+    return std_ulogic_vector(to_unsigned(ffs_64(rs),rs'length));
+  end function ppc_cnttzd;
+   
+  function ppc_popcntb(rs : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
+    variable ret : std_ulogic_vector(rs'range);
+    variable hi : integer;
+    variable lo : integer;
+  begin
+    ret := (others => '0');
+    return ret;
+  end function ppc_popcntb;
+   
+  function ppc_popcntw(rs : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
+    variable ret : std_ulogic_vector(rs'range);
+    variable hi : integer;
+    variable lo : integer;
+  begin
+    ret := (others => '0');
+    return ret;
+  end function ppc_popcntw;
+   
+  function ppc_popcntd(rs : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
+  begin
+    return popcnt64(rs);
+  end function ppc_popcntd;
+   
+  function ppc_prtyd(rs : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
+    variable tmp : std_ulogic;
+    variable ret : std_ulogic_vector(63 downto 0);
+  begin
+    ret := (others => '0');
+    tmp := '0';
+    ret(0) := tmp;
+    return ret;
+  end function ppc_prtyd;
+   
+  function ppc_prtyw(rs : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
+    variable tmp : std_ulogic;
+    variable ret : std_ulogic_vector(63 downto 0);
+  begin
+    ret := (others => '0');
+    tmp := '0';
+    ret(0) := tmp;
+    tmp := '0';
+    ret(32) := tmp;
+    return ret;
+  end function ppc_prtyw;
+   
+  function ppc_rlwinm(rs : std_ulogic_vector(63 downto 0);sh : std_ulogic_vector(4 downto 0);mb : std_ulogic_vector(4 downto 0);me : std_ulogic_vector(4 downto 0)) return std_ulogic_vector is
+    variable hi : integer;
+    variable lo : integer;
+    variable tmp1 : std_ulogic_vector(63 downto 0);
+    variable tmp2 : std_ulogic_vector(63 downto 0);
+  begin
+    hi := 31 - to_integer(unsigned(mb));
+    lo := 31 - to_integer(unsigned(me));
+    tmp1 := rs(31 downto 0) & rs(31 downto 0);
+    tmp1 := std_ulogic_vector(rotate_left(unsigned(tmp1),to_integer(unsigned(sh))));
+    tmp2 := (others => '0');
+    if hi < lo then
+      ;
+    else
+      ;
+    end if;
+    return tmp2;
+  end function ppc_rlwinm;
+   
+  function ppc_rlwnm(rs : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0);mb : std_ulogic_vector(4 downto 0);me : std_ulogic_vector(4 downto 0)) return std_ulogic_vector is
+    variable hi : integer;
+    variable lo : integer;
+    variable tmp1 : std_ulogic_vector(63 downto 0);
+    variable tmp2 : std_ulogic_vector(63 downto 0);
+    variable n : integer;
+  begin
+    hi := 31 - to_integer(unsigned(mb));
+    lo := 31 - to_integer(unsigned(me));
+    n := to_integer(unsigned(rb(4 downto 0)));
+    tmp1 := rs(31 downto 0) & rs(31 downto 0);
+    tmp1 := std_ulogic_vector(rotate_left(unsigned(tmp1),n));
+    tmp2 := (others => '0');
+    if hi < lo then
+      ;
+    else
+      ;
+    end if;
+    return tmp2;
+  end function ppc_rlwnm;
+   
+  function ppc_rlwimi(ra : std_ulogic_vector(63 downto 0);rs : std_ulogic_vector(63 downto 0);sh : std_ulogic_vector(4 downto 0);mb : std_ulogic_vector(4 downto 0);me : std_ulogic_vector(4 downto 0)) return std_ulogic_vector is
+    variable hi : integer;
+    variable lo : integer;
+    variable tmp1 : std_ulogic_vector(63 downto 0);
+    variable tmp2 : std_ulogic_vector(63 downto 0);
+  begin
+    hi := 31 - to_integer(unsigned(mb));
+    lo := 31 - to_integer(unsigned(me));
+    tmp1 := rs(31 downto 0) & rs(31 downto 0);
+    tmp1 := std_ulogic_vector(rotate_left(unsigned(tmp1),to_integer(unsigned(sh))));
+    tmp2 := ra;
+    if hi < lo then
+      ;
+    else
+      ;
+    end if;
+    return tmp2;
+  end function ppc_rlwimi;
+   
+  function ppc_rldicl(rs : std_ulogic_vector(63 downto 0);sh : std_ulogic_vector(5 downto 0);mb : std_ulogic_vector(5 downto 0)) return std_ulogic_vector is
+    variable hi : integer;
+    variable tmp1 : std_ulogic_vector(63 downto 0);
+    variable tmp2 : std_ulogic_vector(63 downto 0);
+  begin
+    hi := 63 - to_integer(unsigned(mb));
+    tmp1 := std_ulogic_vector(rotate_left(unsigned(rs),to_integer(unsigned(sh))));
+    tmp2 := (others => '0');
+    return tmp2;
+  end function ppc_rldicl;
+   
+  function ppc_rldicr(rs : std_ulogic_vector(63 downto 0);sh : std_ulogic_vector(5 downto 0);me : std_ulogic_vector(5 downto 0)) return std_ulogic_vector is
+    variable lo : integer;
+    variable tmp1 : std_ulogic_vector(63 downto 0);
+    variable tmp2 : std_ulogic_vector(63 downto 0);
+  begin
+    lo := 63 - to_integer(unsigned(me));
+    tmp1 := std_ulogic_vector(rotate_left(unsigned(rs),to_integer(unsigned(sh))));
+    tmp2 := (others => '0');
+    return tmp2;
+  end function ppc_rldicr;
+   
+  function ppc_rldic(rs : std_ulogic_vector(63 downto 0);sh : std_ulogic_vector(5 downto 0);mb : std_ulogic_vector(5 downto 0)) return std_ulogic_vector is
+    variable hi : integer;
+    variable lo : integer;
+    variable tmp1 : std_ulogic_vector(63 downto 0);
+    variable tmp2 : std_ulogic_vector(63 downto 0);
+  begin
+    hi := 63 - to_integer(unsigned(mb));
+    lo := to_integer(unsigned(sh));
+    tmp1 := std_ulogic_vector(rotate_left(unsigned(rs),to_integer(unsigned(sh))));
+    tmp2 := (others => '0');
+    if hi < lo then
+      ;
+    else
+      ;
+    end if;
+    return tmp2;
+  end function ppc_rldic;
+   
+  function ppc_rldcl(rs : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0);mb : std_ulogic_vector(5 downto 0)) return std_ulogic_vector is
+    variable hi : integer;
+    variable tmp1 : std_ulogic_vector(63 downto 0);
+    variable tmp2 : std_ulogic_vector(63 downto 0);
+  begin
+    hi := 63 - to_integer(unsigned(mb));
+    tmp1 := std_ulogic_vector(rotate_left(unsigned(rs),to_integer(unsigned(rb(5 downto 0)))));
+    tmp2 := (others => '0');
+    return tmp2;
+  end function ppc_rldcl;
+   
+  function ppc_rldcr(rs : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0);me : std_ulogic_vector(5 downto 0)) return std_ulogic_vector is
+    variable lo : integer;
+    variable tmp1 : std_ulogic_vector(63 downto 0);
+    variable tmp2 : std_ulogic_vector(63 downto 0);
+  begin
+    lo := 63 - to_integer(unsigned(me));
+    tmp1 := std_ulogic_vector(rotate_left(unsigned(rs),to_integer(unsigned(rb(5 downto 0)))));
+    tmp2 := (others => '0');
+    return tmp2;
+  end function ppc_rldcr;
+   
+  function ppc_rldimi(ra : std_ulogic_vector(63 downto 0);rs : std_ulogic_vector(63 downto 0);sh : std_ulogic_vector(5 downto 0);mb : std_ulogic_vector(5 downto 0)) return std_ulogic_vector is
+    variable hi : integer;
+    variable lo : integer;
+    variable tmp1 : std_ulogic_vector(rs'range);
+    variable tmp2 : std_ulogic_vector(rs'range);
+  begin
+    hi := 63 - to_integer(unsigned(mb));
+    lo := to_integer(unsigned(sh));
+    tmp1 := std_ulogic_vector(rotate_left(unsigned(rs),lo));
+    tmp2 := ra;
+    if hi < lo then
+      ;
+    else
+      ;
+    end if;
+    return tmp2;
+  end function ppc_rldimi;
+   
+  function ppc_slw(rs : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
+    variable n : integer;
+    variable tmp : unsigned(31 downto 0);
+  begin
+    n := to_integer(unsigned(rb(5 downto 0)));
+    tmp := shift_left(unsigned(rs(31 downto 0)),n);
+    return (63 downto 32 => '0') & std_ulogic_vector(tmp);
+  end function ppc_slw;
+   
+  function ppc_srw(rs : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
+    variable n : integer;
+    variable tmp : unsigned(31 downto 0);
+  begin
+    n := to_integer(unsigned(rb(5 downto 0)));
+    tmp := shift_right(unsigned(rs(31 downto 0)),n);
+    return (63 downto 32 => '0') & std_ulogic_vector(tmp);
+  end function ppc_srw;
+   
+  function ppc_srawi(rs : std_ulogic_vector(63 downto 0);sh : std_ulogic_vector(5 downto 0)) return std_ulogic_vector is
+    variable n : integer;
+    variable tmp : signed(31 downto 0);
+    variable mask : std_ulogic_vector(63 downto 0);
+    variable carry : std_ulogic;
+  begin
+    n := to_integer(unsigned(sh));
+    tmp := shift_right(signed(rs(31 downto 0)),n);
+    mask := (others => '0');
+    carry := '0' when (rs and mask) = (63 downto 0 => '0') else  rs(31);
+    return carry & std_ulogic_vector(resize(tmp,rs'length));
+  end function ppc_srawi;
+   
+  function ppc_sraw(rs : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
+    variable n : natural;
+    variable tmp : signed(31 downto 0);
+    variable mask : std_ulogic_vector(63 downto 0);
+    variable carry : std_ulogic;
+  begin
+    n := to_integer(unsigned(rb(5 downto 0)));
+    tmp := shift_right(signed(rs(31 downto 0)),n);
+    mask := (others => '0');
+    carry := or((rs and mask) and rs(31));
+    return carry & std_ulogic_vector(resize(tmp,rs'length));
+  end function ppc_sraw;
+   
+  function ppc_sld(rs : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
+    variable n : integer;
+  begin
+    n := to_integer(unsigned(rb(6 downto 0)));
+    return std_ulogic_vector(shift_left(unsigned(rs),n));
+  end function ppc_sld;
+   
+  function ppc_srd(rs : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
+    variable n : integer;
+  begin
+    n := to_integer(unsigned(rb(6 downto 0)));
+    return std_ulogic_vector(shift_right(unsigned(rs),n));
+  end function ppc_srd;
+   
+  function ppc_sradi(rs : std_ulogic_vector(63 downto 0);sh : std_ulogic_vector(5 downto 0)) return std_ulogic_vector is
+    variable n : integer;
+    variable carry : std_ulogic;
+    variable mask : std_ulogic_vector(63 downto 0);
+  begin
+    n := to_integer(unsigned(sh));
+    mask := (others => '0');
+    carry := '0' when (rs and mask) = (63 downto 0 => '0') else  rs(63);
+    return carry & std_ulogic_vector(shift_right(signed(rs),n));
+  end function ppc_sradi;
+   
+  function ppc_srad(rs : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
+    variable n : integer;
+    variable carry : std_ulogic;
+    variable mask : std_ulogic_vector(63 downto 0);
+  begin
+    n := to_integer(unsigned(rb(6 downto 0)));
+    mask := (others => '0');
+    carry := '0' when (rs and mask) = (63 downto 0 => '0') else  rs(63);
+    return carry & std_ulogic_vector(shift_right(signed(rs),n));
+  end function ppc_srad;
+   
+  function ppc_mulld(ra : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
+    variable tmp : signed(127 downto 0);
+  begin
+    tmp := signed(ra) * signed(rb);
+    return std_ulogic_vector(tmp(63 downto 0));
+  end function ppc_mulld;
+   
+  function ppc_mulhd(ra : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
+    variable tmp : signed(127 downto 0);
+  begin
+    tmp := signed(ra) * signed(rb);
+    return std_ulogic_vector(tmp(127 downto 64));
+  end function ppc_mulhd;
+   
+  function ppc_mulhdu(ra : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
+    variable tmp : unsigned(127 downto 0);
+  begin
+    tmp := unsigned(ra) * unsigned(rb);
+    return std_ulogic_vector(tmp(127 downto 64));
+  end function ppc_mulhdu;
+   
+  function ppc_mulli(ra : std_ulogic_vector(63 downto 0);si : std_ulogic_vector(15 downto 0)) return std_ulogic_vector is
+    variable tmp : signed(79 downto 0);
+  begin
+    tmp := signed(ra) * signed(si);
+    return std_ulogic_vector(tmp(63 downto 0));
+  end function ppc_mulli;
+   
+  function ppc_mullw(ra : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
+  begin
+    return std_ulogic_vector(signed(ra(31 downto 0)) * signed(rb(31 downto 0)));
+  end function ppc_mullw;
+   
+  function ppc_mulhw(ra : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
+    variable tmp : signed(63 downto 0);
+  begin
+    tmp := signed(ra(31 downto 0)) * signed(rb(31 downto 0));
+    return std_ulogic_vector(tmp(63 downto 32)) & std_ulogic_vector(tmp(63 downto 32));
+  end function ppc_mulhw;
+   
+  function ppc_mulhwu(ra : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
+    variable tmp : unsigned(63 downto 0);
+  begin
+    tmp := unsigned(ra(31 downto 0)) * unsigned(rb(31 downto 0));
+    return std_ulogic_vector(tmp(63 downto 32)) & std_ulogic_vector(tmp(63 downto 32));
+  end function ppc_mulhwu;
+   
+  function ppc_cmpi(l : std_ulogic;ra : std_ulogic_vector(63 downto 0);si : std_ulogic_vector(15 downto 0);so : std_ulogic) return std_ulogic_vector is
+    variable tmp : signed(ra'range);
+  begin
+    tmp := signed(ra);
+    if l = '0' then
+      tmp := resize(signed(ra(31 downto 0)),tmp'length);
+    end if;
+    return ppc_signed_compare(tmp,resize(signed(si),tmp'length),so);
+  end function ppc_cmpi;
+   
+  function ppc_cmp(l : std_ulogic;ra : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0);so : std_ulogic) return std_ulogic_vector is
+    variable tmpa : signed(ra'range);
+    variable tmpb : signed(ra'range);
+  begin
+    tmpa := signed(ra);
+    tmpb := signed(rb);
+    if l = '0' then
+      tmpa := resize(signed(ra(31 downto 0)),ra'length);
+      tmpb := resize(signed(rb(31 downto 0)),ra'length);
+    end if;
+    return ppc_signed_compare(tmpa,tmpb,so);
+  end function ppc_cmp;
+   
+  function ppc_cmpli(l : std_ulogic;ra : std_ulogic_vector(63 downto 0);si : std_ulogic_vector(15 downto 0);so : std_ulogic) return std_ulogic_vector is
+    variable tmp : unsigned(ra'range);
+  begin
+    tmp := unsigned(ra);
+    if l = '0' then
+      tmp := resize(unsigned(ra(31 downto 0)),tmp'length);
+    end if;
+    return ppc_unsigned_compare(tmp,resize(unsigned(si),tmp'length),so);
+  end function ppc_cmpli;
+   
+  function ppc_cmpl(l : std_ulogic;ra : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0);so : std_ulogic) return std_ulogic_vector is
+    variable tmpa : unsigned(ra'range);
+    variable tmpb : unsigned(ra'range);
+  begin
+    tmpa := unsigned(ra);
+    tmpb := unsigned(rb);
+    if l = '0' then
+      tmpa := resize(unsigned(ra(31 downto 0)),ra'length);
+      tmpb := resize(unsigned(rb(31 downto 0)),ra'length);
+    end if;
+    return ppc_unsigned_compare(tmpa,tmpb,so);
+  end function ppc_cmpl;
+   
+  function ppc_cmpb(rs : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
+    variable ret : std_ulogic_vector(rs'range);
+    variable hi : integer;
+    variable lo : integer;
+  begin
+    ;
+    return ret;
+  end function ppc_cmpb;
+   
+  function ppc_divw(ra : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
+    variable tmp : signed(31 downto 0);
+  begin
+    tmp := signed(ra(31 downto 0)) / signed(rb(31 downto 0));
+    return (63 downto 32 => '0') & std_ulogic_vector(tmp);
+  end function ppc_divw;
+   
+  function ppc_divdu(ra : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
+    variable tmp : unsigned(63 downto 0) := (others => '0');
+  begin
+    if unsigned(rb) /= 0 then
+      tmp := unsigned(ra) / unsigned(rb);
+    end if;
+    return std_ulogic_vector(tmp);
+  end function ppc_divdu;
+   
+  function ppc_divd(ra : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
+    variable tmp : signed(63 downto 0) := (others => '0');
+  begin
+    if signed(rb) /= 0 then
+      tmp := signed(ra) / signed(rb);
+    end if;
+    return std_ulogic_vector(tmp);
+  end function ppc_divd;
+   
+  function ppc_divwu(ra : std_ulogic_vector(63 downto 0);rb : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
+    variable tmp : unsigned(31 downto 0) := (others => '0');
+  begin
+    if unsigned(rb(31 downto 0)) /= 0 then
+      tmp := unsigned(ra(31 downto 0)) / unsigned(rb(31 downto 0));
+    end if;
+    return std_ulogic_vector(resize(tmp,ra'length));
+  end function ppc_divwu;
+   
+  function ppc_bc_taken(bo : std_ulogic_vector(4 downto 0);bi : std_ulogic_vector(4 downto 0);cr : std_ulogic_vector(31 downto 0);ctr : std_ulogic_vector(63 downto 0)) return integer is
+    variable crfield : integer;
+    variable crbit_match : std_ulogic;
+    variable ctr_not_zero : std_ulogic;
+    variable ctr_ok : std_ulogic;
+    variable cond_ok : std_ulogic;
+    variable ret : integer;
+  begin
+    crfield := to_integer(unsigned(bi));
+    crbit_match := '1' when cr(31 - crfield) = bo(4 - 1) else  '0';
+    ctr_not_zero := '1' when ctr /= x"0000000000000001" else  '0';
+    ctr_ok := bo(4 - 2) or (ctr_not_zero xor bo(4 - 3));
+    cond_ok := bo(4 - 0) or crbit_match;
+    if ctr_ok = '1' and cond_ok = '1' then
+      ret := 1;
+    else
+      ret := 0;
+    end if;
+    return ret;
+  end function ppc_bc_taken;
+end ppc_fx_insns;