vertigo_vhdl 0.8.2

data/tests/parser_tests/test_microwatt_utils.vhd

@@ -0,0 +1 @@
+../microwatt/utils.vhdl

data/tests/parser_tests/test_microwatt_utils_pp.vhd

@@ -0,0 +1,39 @@
+-- generated by Vertigo VHDL tool
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+ 
+package utils is
+  function log2(i : natural) return integer
+  function log2ceil(i : natural) return integer
+  function ispow2(i : integer) return boolean
+ 
+end utils;
+ 
+package body utils is
+   
+  function log2(i : natural) return integer is
+    variable tmp : integer := i;
+    variable ret : integer := 0;
+  begin
+    ;
+    return ret;
+  end function log2;
+   
+  function log2ceil(i : natural) return integer is
+    variable tmp : integer := i;
+    variable ret : integer := 0;
+  begin
+    ;
+    return ret;
+  end function log2ceil;
+   
+  function ispow2(i : integer) return boolean is
+  begin
+    if to_integer(to_unsigned(i,32) and to_unsigned(i - 1,32)) = 0 then
+      return true;
+    else
+      return false;
+    end if;
+  end function ispow2;
+end utils;

data/tests/parser_tests/test_microwatt_wishbone_arbiter.vhd

@@ -0,0 +1 @@
+../microwatt/wishbone_arbiter.vhdl

data/tests/parser_tests/test_microwatt_wishbone_arbiter_pp.vhd

@@ -0,0 +1,54 @@
+-- generated by Vertigo VHDL tool
+library ieee;
+use ieee.std_logic_1164.all;
+library work;
+use work.wishbone_types.all;
+ 
+entity wishbone_arbiter is
+  generic(
+    num_masters : positive3 := 3);
+  port(
+    clk : in std_ulogic;
+    rst : in std_ulogic;
+    wb_masters_in : in wishbone_master_out_vector(0 to num_masters - 1);
+    wb_masters_out : out wishbone_slave_out_vector(0 to num_masters - 1);
+    wb_slave_out : out wishbone_master_out;
+    wb_slave_in : in wishbone_slave_out);
+end entity wishbone_arbiter;
+ 
+architecture behave of wishbone_arbiter is
+   
+  subtype wb_arb_master_t is integer range 0 to num_masters - 1;
+  signal candidate : wb_arb_master_t;
+  signal selected : wb_arb_master_t;
+  signal busy : std_ulogic;
+begin
+ 
+  busy <= wb_masters_in(selected).cyc;
+   
+  wishbone_muxes : process(selected,candidate,busy,wb_slave_in,wb_masters_in)
+    variable early_sel : wb_arb_master_t;
+  begin
+    early_sel := selected;
+    if busy = '0' then
+      early_sel := candidate;
+    end if;
+    wb_slave_out <= wb_masters_in(early_sel);
+  end process;
+   
+  wishbone_candidate : process(all)
+  begin
+    candidate <= selected;
+  end process;
+   
+  wishbone_arbiter_process : process(clk)
+  begin
+    if rising_edge(clk) then
+      if rst = '1' then
+        selected <= 0;
+      elsif busy = '0' then
+        selected <= candidate;
+      end if;
+    end if;
+  end process;
+end behave;

data/tests/parser_tests/test_microwatt_wishbone_bram_tb.vhd

@@ -0,0 +1 @@
+../microwatt/wishbone_bram_tb.vhdl

data/tests/parser_tests/test_microwatt_wishbone_bram_tb_pp.vhd

@@ -0,0 +1,157 @@
+-- generated by Vertigo VHDL tool
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.wishbone_types.all;
+ 
+entity wishbone_bram_tb is
+end entity wishbone_bram_tb;
+ 
+architecture behave of wishbone_bram_tb is
+  signal clk : std_ulogic;
+  signal rst : std_ulogic := '1';
+  constant clk_period : time := 10 ns;
+  signal w_in : wishbone_slave_out;
+  signal w_out : wishbone_master_out;
+   
+  function to_adr(a : integer) return std_ulogic_vector is
+  begin
+    return std_ulogic_vector(to_unsigned(a,w_out.adr'length));
+  end function to_adr;
+begin
+ 
+  simple_ram_0 : entity work.wishbone_bram_wrapper
+    port map(
+      clk => clk,
+      rst => rst,
+      wishbone_out => w_in,
+      wishbone_in => w_out);
+   
+   
+  clock : process
+  begin
+    clk <= '1';
+    wait clk_period / 2;
+    clk <= '0';
+    wait clk_period / 2;
+  end process;
+   
+  stim : process
+  begin
+    w_out.adr <= (others => '0');
+    w_out.dat <= (others => '0');
+    w_out.cyc <= '0';
+    w_out.stb <= '0';
+    w_out.sel <= (others => '0');
+    w_out.we <= '0';
+    wait rising_edge(clk);
+    rst <= '0';
+    wait rising_edge(clk);
+    w_out.cyc <= '1';
+    w_out.stb <= '1';
+    w_out.sel <= "11111111";
+    w_out.adr <= to_adr(0);
+    assert w_in.ack = '0';
+    wait rising_edge(clk);
+    w_out.stb <= '0';
+    wait rising_edge(clk);
+    wait rising_edge(clk);
+    assert w_in.ack = '1';
+    assert w_in.dat(63 downto 0) = x"0706050403020100"
+      report to_hstring(w_in.dat);
+    wait rising_edge(clk);
+    assert w_in.ack = '0';
+    w_out.stb <= '1';
+    w_out.sel <= "11111111";
+    w_out.adr <= to_adr(8);
+    assert w_in.ack = '0';
+    wait rising_edge(clk);
+    w_out.stb <= '0';
+    wait rising_edge(clk);
+    wait rising_edge(clk);
+    assert w_in.ack = '1';
+    assert w_in.dat(63 downto 0) = x"0f0e0d0c0b0a0908"
+      report to_hstring(w_in.dat);
+    wait rising_edge(clk);
+    assert w_in.ack = '0';
+    w_out.stb <= '1';
+    w_out.sel <= "00000001";
+    w_out.adr <= to_adr(0);
+    w_out.we <= '1';
+    w_out.dat(7 downto 0) <= x"0f";
+    assert w_in.ack = '0';
+    wait rising_edge(clk);
+    w_out.stb <= '0';
+    wait rising_edge(clk) and w_in.ack = '1';
+    wait rising_edge(clk);
+    assert w_in.ack = '0';
+    w_out.stb <= '1';
+    w_out.sel <= "11111111";
+    w_out.adr <= to_adr(0);
+    w_out.we <= '0';
+    assert w_in.ack = '0';
+    wait rising_edge(clk);
+    w_out.stb <= '0';
+    wait rising_edge(clk);
+    wait rising_edge(clk);
+    assert w_in.ack = '1';
+    assert w_in.dat(63 downto 0) = x"070605040302010f"
+      report to_hstring(w_in.dat);
+    wait rising_edge(clk);
+    assert w_in.ack = '0';
+    w_out.stb <= '1';
+    w_out.sel <= "11110000";
+    w_out.adr <= to_adr(0);
+    w_out.we <= '1';
+    w_out.dat(63 downto 32) <= x"baadfeed";
+    assert w_in.ack = '0';
+    wait rising_edge(clk);
+    w_out.stb <= '0';
+    wait rising_edge(clk) and w_in.ack = '1';
+    wait rising_edge(clk);
+    assert w_in.ack = '0';
+    w_out.stb <= '1';
+    w_out.sel <= "11111111";
+    w_out.adr <= to_adr(0);
+    w_out.we <= '0';
+    assert w_in.ack = '0';
+    wait rising_edge(clk);
+    w_out.stb <= '0';
+    wait rising_edge(clk);
+    wait rising_edge(clk);
+    assert w_in.ack = '1';
+    assert w_in.dat(63 downto 0) = x"baadfeed0302010f"
+      report to_hstring(w_in.dat);
+    wait rising_edge(clk);
+    assert w_in.ack = '0';
+    w_out.stb <= '1';
+    w_out.sel <= "11111111";
+    w_out.adr <= to_adr(8);
+    w_out.we <= '1';
+    w_out.dat(63 downto 0) <= x"0001020304050607";
+    assert w_in.ack = '0';
+    wait rising_edge(clk);
+    w_out.stb <= '0';
+    wait rising_edge(clk) and w_in.ack = '1';
+    wait rising_edge(clk);
+    assert w_in.ack = '0';
+    w_out.stb <= '1';
+    w_out.sel <= "11111111";
+    w_out.adr <= to_adr(8);
+    w_out.we <= '0';
+    assert w_in.ack = '0';
+    wait rising_edge(clk);
+    w_out.stb <= '0';
+    wait rising_edge(clk);
+    wait rising_edge(clk);
+    assert w_in.ack = '1';
+    assert w_in.dat(63 downto 0) = x"0001020304050607"
+      report to_hstring(w_in.dat);
+    wait rising_edge(clk);
+    assert w_in.ack = '0';
+    assert false
+      report "end of test" severity failure;
+    wait ;
+  end process;
+end behave;

data/tests/parser_tests/test_microwatt_wishbone_bram_wrapper.vhd

@@ -0,0 +1 @@
+../microwatt/wishbone_bram_wrapper.vhdl

data/tests/parser_tests/test_microwatt_wishbone_bram_wrapper_pp.vhd

@@ -0,0 +1,62 @@
+-- generated by Vertigo VHDL tool
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+library work;
+use work.utils.all;
+use work.wishbone_types.all;
+ 
+entity wishbone_bram_wrapper is
+  generic(
+    memory_size : natural4096 := 4096;
+    ram_init_file : string);
+  port(
+    clk : in std_logic;
+    rst : in std_logic;
+    wishbone_in : in wishbone_master_out;
+    wishbone_out : out wishbone_slave_out);
+end entity wishbone_bram_wrapper;
+ 
+architecture behaviour of wishbone_bram_wrapper is
+  constant ram_addr_bits : integer := log2ceil(memory_size) - 3;
+  signal ram_addr : std_logic_vector(ram_addr_bits - 1 downto 0);
+  signal ram_we : std_ulogic;
+  signal ram_re : std_ulogic;
+  signal ack : std_ulogic;
+  signal ack_buf : std_ulogic;
+begin
+ 
+  ram_0 : entity work.main_bram
+    port map(
+      clk => clk,
+      addr => ram_addr,
+      di => wishbone_in.dat,
+      do => wishbone_out.dat,
+      sel => wishbone_in.sel,
+      re => ram_re,
+      we => ram_we);
+   
+  ram_addr <= wishbone_in.adr(ram_addr_bits + 2 downto 3);
+  ram_we <= wishbone_in.stb and wishbone_in.cyc and wishbone_in.we;
+  ram_re <= wishbone_in.stb and wishbone_in.cyc and wishbone_in.we;
+  wishbone_out.stall <= '0';
+  wishbone_out.ack <= ack_buf;
+   
+  wb_0 : process(clk)
+  begin
+    if rising_edge(clk) then
+      if rst = '1' or wishbone_in.cyc = '0' then
+        ack_buf <= '0';
+        ack <= '0';
+      else
+        if ram_we = '1' and ack = '0' then
+          ack_buf <= '1';
+        else
+          ack <= wishbone_in.stb;
+          ack_buf <= ack;
+        end if;
+      end if;
+    end if;
+  end process;
+end behaviour;

data/tests/parser_tests/test_microwatt_wishbone_debug_master.vhd

@@ -0,0 +1 @@
+../microwatt/wishbone_debug_master.vhdl

data/tests/parser_tests/test_microwatt_wishbone_debug_master_pp.vhd

@@ -0,0 +1,124 @@
+-- generated by Vertigo VHDL tool
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.wishbone_types.all;
+ 
+entity wishbone_debug_master is
+  port(
+    clk : in std_ulogic;
+    rst : in std_ulogic;
+    dmi_addr : in std_ulogic_vector(1 downto 0);
+    dmi_din : in std_ulogic_vector(63 downto 0);
+    dmi_dout : out std_ulogic_vector(63 downto 0);
+    dmi_req : in std_ulogic;
+    dmi_wr : in std_ulogic;
+    dmi_ack : out std_ulogic;
+    wb_out : out wishbone_master_out;
+    wb_in : in wishbone_slave_out);
+end entity wishbone_debug_master;
+ 
+architecture behaviour of wishbone_debug_master is
+  constant dbg_wb_addr : std_ulogic_vector(1 downto 0) := "00";
+  constant dbg_wb_data : std_ulogic_vector(1 downto 0) := "01";
+  constant dbg_wb_ctrl : std_ulogic_vector(1 downto 0) := "10";
+  constant dbg_wb_rsvd : std_ulogic_vector(1 downto 0) := "11";
+  signal reg_addr : std_ulogic_vector(63 downto 0);
+  signal reg_ctrl_out : std_ulogic_vector(63 downto 0);
+  signal reg_ctrl : std_ulogic_vector(10 downto 0);
+  signal data_latch : std_ulogic_vector(63 downto 0);
+   
+  type state_t is (idle,wb_cycle,dmi_wait);
+  signal state : state_t;
+begin
+ 
+  with dmi_addr select dmi_dout <=
+    reg_addr when dbg_wb_addr,
+    data_latch when dbg_wb_data,
+    reg_ctrl_out when dbg_wb_ctrl,
+    (others => '0') when others,;
+   
+  reg_write : process(clk)
+     
+    subtype autoinc_inc_t is integer range 1 to 8;
+     
+    function decode_autoinc(c : std_ulogic_vector(1 downto 0)) return autoinc_inc_t is
+    begin
+      case c is
+        when "00" =>
+          return 1;
+        when "01" =>
+          return 2;
+        when "10" =>
+          return 4;
+        when "11" =>
+          return 8;
+        when others =>
+          return 8;
+      end case;
+    end function decode_autoinc;
+  begin
+    if rising_edge(clk) then
+      if (rst) then
+        reg_addr <= (others => '0');
+        reg_ctrl <= (others => '0');
+      else
+        if dmi_req and dmi_wr then
+          if dmi_addr = dbg_wb_addr then
+            reg_addr <= dmi_din;
+          elsif dmi_addr = dbg_wb_ctrl then
+            reg_ctrl <= dmi_din(10 downto 0);
+          end if;
+        elsif state = wb_cycle and (wb_in.ack and reg_ctrl(8)) = '1' then
+          reg_addr <= std_ulogic_vector(unsigned(reg_addr) + decode_autoinc(reg_ctrl(10 downto 9)));
+        end if;
+      end if;
+    end if;
+  end process;
+  dmi_ack <= dmi_req when (dmi_addr /= dbg_wb_data or state = dmi_wait) else  '0';
+  wb_out.adr <= reg_addr(wb_out.adr'left downto 0);
+  wb_out.dat <= dmi_din;
+  wb_out.sel <= reg_ctrl(7 downto 0);
+  wb_out.we <= dmi_wr;
+  wb_out.cyc <= '1' when state = wb_cycle else  '0';
+   
+  latch_reads : process(clk)
+  begin
+    if rising_edge(clk) then
+      if state = wb_cycle and wb_in.ack = '1' and dmi_wr = '0' then
+        data_latch <= wb_in.dat;
+      end if;
+    end if;
+  end process;
+   
+  wb_trigger : process(clk)
+  begin
+    if rising_edge(clk) then
+      if (rst) then
+        state <= idle;
+        wb_out.stb <= '0';
+      else
+        case state is
+          when idle =>
+            if dmi_req = '1' and dmi_addr = dbg_wb_data then
+              state <= wb_cycle;
+              wb_out.stb <= '1';
+            end if;
+          when wb_cycle =>
+            if wb_in.stall = '0' then
+              wb_out.stb <= '0';
+            end if;
+            if wb_in.ack then
+              wb_out.stb <= '0';
+              state <= dmi_wait;
+            end if;
+          when dmi_wait =>
+            if dmi_req = '0' then
+              state <= idle;
+            end if;
+        end case;
+      end if;
+    end if;
+  end process;
+end behaviour;