vertigo_vhdl 0.8.2

data/tests/parser_tests/test_microwatt_sim_console.vhd

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+../microwatt/sim_console.vhdl

data/tests/parser_tests/test_microwatt_sim_console_pp.vhd

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+-- generated by Vertigo VHDL tool
+library ieee;
+use ieee.std_logic_1164.all;
+ 
+package sim_console is
+   
+  procedure sim_console_read(
+    val : out std_ulogic_vector(63 downto 0));
+  attribute foreign of sim_console_read : procedure is "vhpidirect sim_console_read";
+   
+  procedure sim_console_poll(
+    val : out std_ulogic_vector(63 downto 0));
+  attribute foreign of sim_console_poll : procedure is "vhpidirect sim_console_poll";
+   
+  procedure sim_console_write(
+    val : std_ulogic_vector(63 downto 0));
+  attribute foreign of sim_console_write : procedure is "vhpidirect sim_console_write";
+ 
+end sim_console;
+ 
+package body sim_console is
+   
+  procedure sim_console_read(
+    val : out std_ulogic_vector(63 downto 0)) is
+  begin
+    assert false
+      report "vhpi" severity failure;
+  end sim_console_read;
+   
+  procedure sim_console_poll(
+    val : out std_ulogic_vector(63 downto 0)) is
+  begin
+    assert false
+      report "vhpi" severity failure;
+  end sim_console_poll;
+   
+  procedure sim_console_write(
+    val : std_ulogic_vector(63 downto 0)) is
+  begin
+    assert false
+      report "vhpi" severity failure;
+  end sim_console_write;
+end sim_console;

data/tests/parser_tests/test_microwatt_sim_jtag.vhd

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+../microwatt/sim_jtag.vhdl

data/tests/parser_tests/test_microwatt_sim_jtag_pp.vhd

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+-- generated by Vertigo VHDL tool
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.sim_jtag_socket.all;
+library unisim;
+use unisim.vcomponents.all;
+ 
+entity sim_jtag is
+end entity sim_jtag;
+ 
+architecture behaviour of sim_jtag is
+begin
+ 
+   
+  jtag : process
+    alias j : glob_jtag_t is glob_jtag ;
+    constant jclk_period : time := 1 ns;
+    constant poll_period : time := 100 ns;
+    constant dummy_clocks : integer := 80;
+     
+    procedure clock(
+      count : in integer) is
+    begin
+      ;
+    end clock;
+     
+    procedure clock_command(
+      cmd : in std_ulogic_vector;
+      rsp : out std_ulogic_vector) is
+    begin
+      j.capture <= '1';
+      ()
+      j.capture <= '0';
+      ()
+      j.shift <= '1';
+      j.shift <= '0';
+      j.update <= '1';
+      ()
+      j.update <= '0';
+      ()
+    end clock_command;
+    variable cmd : std_ulogic_vector(0 to 247);
+    variable rsp : std_ulogic_vector(0 to 247);
+    variable msize : std_ulogic_vector(7 downto 0);
+    variable size : integer;
+  begin
+    j.reset <= '1';
+    j.sel <= "0000";
+    j.capture <= '0';
+    j.update <= '0';
+    j.shift <= '0';
+    j.tdi <= '0';
+    j.tms <= '0';
+    j.runtest <= '0';
+    ()
+    j.reset <= '0';
+    ()
+    j.sel <= "0010";
+    ()
+    rsp := (others => '0');
+  end process;
+end behaviour;

data/tests/parser_tests/test_microwatt_sim_jtag_socket.vhd

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+../microwatt/sim_jtag_socket.vhdl

data/tests/parser_tests/test_microwatt_sim_jtag_socket_pp.vhd

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+-- generated by Vertigo VHDL tool
+library ieee;
+use ieee.std_logic_1164.all;
+ 
+package sim_jtag_socket is
+   
+  procedure sim_jtag_read_msg(
+    out_msg : out std_ulogic_vector(247 downto 0);
+    out_size : out std_ulogic_vector(7 downto 0));
+  attribute foreign of sim_jtag_read_msg : procedure is "vhpidirect sim_jtag_read_msg";
+   
+  procedure sim_jtag_write_msg(
+    in_msg : in std_ulogic_vector(247 downto 0);
+    in_size : in std_ulogic_vector(7 downto 0));
+  attribute foreign of sim_jtag_write_msg : procedure is "vhpidirect sim_jtag_write_msg";
+ 
+end sim_jtag_socket;
+ 
+package body sim_jtag_socket is
+   
+  procedure sim_jtag_read_msg(
+    out_msg : out std_ulogic_vector(247 downto 0);
+    out_size : out std_ulogic_vector(7 downto 0)) is
+  begin
+    assert false
+      report "vhpi" severity failure;
+  end sim_jtag_read_msg;
+   
+  procedure sim_jtag_write_msg(
+    in_msg : in std_ulogic_vector(247 downto 0);
+    in_size : in std_ulogic_vector(7 downto 0)) is
+  begin
+    assert false
+      report "vhpi" severity failure;
+  end sim_jtag_write_msg;
+end sim_jtag_socket;

data/tests/parser_tests/test_microwatt_sim_uart.vhd

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+../microwatt/sim_uart.vhdl

data/tests/parser_tests/test_microwatt_sim_uart_pp.vhd

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+-- generated by Vertigo VHDL tool
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.wishbone_types.all;
+use work.sim_console.all;
+ 
+entity pp_soc_uart is
+  generic(
+    fifo_depth : natural64 := 64);
+  port(
+    clk : in std_logic;
+    reset : in std_logic;
+    txd : out std_logic;
+    rxd : in std_logic;
+    wb_adr_in : in std_logic_vector(11 downto 0);
+    wb_dat_in : in std_logic_vector(7 downto 0);
+    wb_dat_out : out std_logic_vector(7 downto 0);
+    wb_we_in : in std_logic;
+    wb_cyc_in : in std_logic;
+    wb_stb_in : in std_logic;
+    wb_ack_out : out std_logic);
+end entity pp_soc_uart;
+ 
+architecture behaviour of pp_soc_uart is
+  signal sample_clk_divisor : std_logic_vector(7 downto 0);
+  signal irq_recv_enable : std_logic;
+  signal irq_tx_ready_enable : std_logic := '0';
+   
+  type wb_state_type is (idle,write_ack,read_ack);
+  signal wb_state : wb_state_type;
+  signal wb_ack : std_logic;
+begin
+ 
+  wb_ack_out <= wb_ack and wb_cyc_in and wb_stb_in;
+   
+  wishbone : process(clk)
+    variable sim_tmp : std_logic_vector(63 downto 0);
+  begin
+    if rising_edge(clk) then
+      if reset = '1' then
+        wb_ack <= '0';
+        wb_state <= idle;
+        sample_clk_divisor <= (others => '0');
+        irq_recv_enable <= '0';
+        irq_tx_ready_enable <= '0';
+      else
+        case wb_state is
+          when idle =>
+            if wb_cyc_in = '1' and wb_stb_in = '1' then
+              if wb_we_in = '1' then
+                if wb_adr_in(11 downto 0) = x"000" then
+                  ()
+                elsif wb_adr_in(11 downto 0) = x"018" then
+                  sample_clk_divisor <= wb_dat_in;
+                elsif wb_adr_in(11 downto 0) = x"020" then
+                  irq_recv_enable <= wb_dat_in(0);
+                  irq_tx_ready_enable <= wb_dat_in(1);
+                end if;
+                wb_ack <= '1';
+                wb_state <= write_ack;
+              else
+                if wb_adr_in(11 downto 0) = x"008" then
+                  ()
+                  wb_dat_out <= sim_tmp(7 downto 0);
+                elsif wb_adr_in(11 downto 0) = x"010" then
+                  ()
+                  wb_dat_out <= "00000" & sim_tmp(0) & '1' & sim_tmp(0);
+                elsif wb_adr_in(11 downto 0) = x"018" then
+                  wb_dat_out <= sample_clk_divisor;
+                elsif wb_adr_in(11 downto 0) = x"020" then
+                  wb_dat_out <= (0 => irq_recv_enable,1 => irq_tx_ready_enable,others => '0');
+                else
+                  wb_dat_out <= (others => '0');
+                end if;
+                wb_ack <= '1';
+                wb_state <= read_ack;
+              end if;
+            end if;
+          when write_ack | read_ack =>
+            if wb_stb_in = '0' then
+              wb_ack <= '0';
+              wb_state <= idle;
+            end if;
+        end case;
+      end if;
+    end if;
+  end process;
+end behaviour;

data/tests/parser_tests/test_microwatt_soc.vhd

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+../microwatt/soc.vhdl

data/tests/parser_tests/test_microwatt_soc_pp.vhd

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+-- generated by Vertigo VHDL tool
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+use std.textio.all;
+use std.env.stop;
+library work;
+use work.common.all;
+use work.wishbone_types.all;
+ 
+entity soc is
+  generic(
+    memory_size : positive;
+    ram_init_file : string;
+    reset_low : boolean;
+    sim : boolean;
+    disable_flatten_core : booleanfalse := false);
+  port(
+    rst : in std_ulogic;
+    system_clk : in std_ulogic;
+    uart0_txd : out std_ulogic;
+    uart0_rxd : in std_ulogic);
+end entity soc;
+ 
+architecture behaviour of soc is
+  signal wishbone_dcore_in : wishbone_slave_out;
+  signal wishbone_dcore_out : wishbone_master_out;
+  signal wishbone_icore_in : wishbone_slave_out;
+  signal wishbone_icore_out : wishbone_master_out;
+  signal wishbone_debug_in : wishbone_slave_out;
+  signal wishbone_debug_out : wishbone_master_out;
+  constant num_wb_masters : positive := 3;
+  signal wb_masters_out : wishbone_master_out_vector(0 to num_wb_masters - 1);
+  signal wb_masters_in : wishbone_slave_out_vector(0 to num_wb_masters - 1);
+  signal wb_master_in : wishbone_slave_out;
+  signal wb_master_out : wishbone_master_out;
+  signal wb_uart0_in : wishbone_master_out;
+  signal wb_uart0_out : wishbone_slave_out;
+  signal uart_dat8 : std_ulogic_vector(7 downto 0);
+  signal wb_bram_in : wishbone_master_out;
+  signal wb_bram_out : wishbone_slave_out;
+  constant mem_adr_bits : positive := positive(ceil(log2(real(memory_size))));
+  signal dmi_addr : std_ulogic_vector(7 downto 0);
+  signal dmi_din : std_ulogic_vector(63 downto 0);
+  signal dmi_dout : std_ulogic_vector(63 downto 0);
+  signal dmi_req : std_ulogic;
+  signal dmi_wr : std_ulogic;
+  signal dmi_ack : std_ulogic;
+  signal dmi_wb_dout : std_ulogic_vector(63 downto 0);
+  signal dmi_wb_req : std_ulogic;
+  signal dmi_wb_ack : std_ulogic;
+  signal dmi_core_dout : std_ulogic_vector(63 downto 0);
+  signal dmi_core_req : std_ulogic;
+  signal dmi_core_ack : std_ulogic;
+begin
+ 
+  processor : entity work.core
+    port map(
+      clk => system_clk,
+      rst => rst,
+      wishbone_insn_in => wishbone_icore_in,
+      wishbone_insn_out => wishbone_icore_out,
+      wishbone_data_in => wishbone_dcore_in,
+      wishbone_data_out => wishbone_dcore_out,
+      dmi_addr => dmi_addr(3 downto 0),
+      dmi_dout => dmi_core_dout,
+      dmi_din => dmi_dout,
+      dmi_wr => dmi_wr,
+      dmi_ack => dmi_core_ack,
+      dmi_req => dmi_core_req);
+   
+  wb_masters_out <= (0 => wishbone_dcore_out,1 => wishbone_icore_out,2 => wishbone_debug_out);
+  wishbone_dcore_in <= wb_masters_in(0);
+  wishbone_icore_in <= wb_masters_in(1);
+  wishbone_debug_in <= wb_masters_in(2);
+  wishbone_arbiter_0 : entity work.wishbone_arbiter
+    port map(
+      clk => system_clk,
+      rst => rst,
+      wb_masters_in => wb_masters_out,
+      wb_masters_out => wb_masters_in,
+      wb_slave_out => wb_master_out,
+      wb_slave_in => wb_master_in);
+   
+   
+  slave_intercon : process(wb_master_out,wb_bram_out,wb_uart0_out)
+     
+    type slave_type is (slave_uart_0,slave_memory,slave_none);
+    variable slave : slave_type;
+  begin
+    slave := slave_none;
+    if wb_master_out.adr(31 downto 24) = x"00" then
+      slave := slave_memory;
+    elsif wb_master_out.adr(31 downto 24) = x"c0" then
+      if wb_master_out.adr(23 downto 12) = x"002" then
+        slave := slave_uart_0;
+      end if;
+    end if;
+    wb_bram_in <= wb_master_out;
+    wb_bram_in.cyc <= '0';
+    wb_uart0_in <= wb_master_out;
+    wb_uart0_in.cyc <= '0';
+    case slave is
+      when slave_memory =>
+        wb_bram_in.cyc <= wb_master_out.cyc;
+        wb_master_in <= wb_bram_out;
+      when slave_uart_0 =>
+        wb_uart0_in.cyc <= wb_master_out.cyc;
+        wb_master_in <= wb_uart0_out;
+      when others =>
+        wb_master_in.dat <= (others => '1');
+        wb_master_in.ack <= wb_master_out.stb and wb_master_out.cyc;
+        wb_master_in.stall <= '0';
+    end case;
+  end process;
+  uart0 : entity work.pp_soc_uart
+    port map(
+      clk => system_clk,
+      reset => rst,
+      txd => uart0_txd,
+      rxd => uart0_rxd,
+      wb_adr_in => wb_uart0_in.adr(11 downto 0),
+      wb_dat_in => wb_uart0_in.dat(7 downto 0),
+      wb_dat_out => uart_dat8,
+      wb_cyc_in => wb_uart0_in.cyc,
+      wb_stb_in => wb_uart0_in.stb,
+      wb_we_in => wb_uart0_in.we,
+      wb_ack_out => wb_uart0_out.ack);
+   
+  wb_uart0_out.dat <= x"00000000000000" & uart_dat8;
+  wb_uart0_out.stall <= '0' when wb_uart0_in.cyc = '0' else  wb_uart0_out.ack;
+  bram0 : entity work.wishbone_bram_wrapper
+    port map(
+      clk => system_clk,
+      rst => rst,
+      wishbone_in => wb_bram_in,
+      wishbone_out => wb_bram_out);
+   
+  dtm : entity work.dmi_dtm
+    port map(
+      sys_clk => system_clk,
+      sys_reset => rst,
+      dmi_addr => dmi_addr,
+      dmi_din => dmi_din,
+      dmi_dout => dmi_dout,
+      dmi_req => dmi_req,
+      dmi_wr => dmi_wr,
+      dmi_ack => dmi_ack);
+   
+   
+  dmi_intercon : process(dmi_addr,dmi_req,dmi_wb_ack,dmi_wb_dout,dmi_core_ack,dmi_core_dout)
+     
+    type slave_type is (slave_wb,slave_core,slave_none);
+    variable slave : slave_type;
+  begin
+    slave := slave_none;
+    if std_match(dmi_addr,"000000--") then
+      slave := slave_wb;
+    elsif std_match(dmi_addr,"0001----") then
+      slave := slave_core;
+    end if;
+    dmi_wb_req <= '0';
+    dmi_core_req <= '0';
+    case slave is
+      when slave_wb =>
+        dmi_wb_req <= dmi_req;
+        dmi_ack <= dmi_wb_ack;
+        dmi_din <= dmi_wb_dout;
+      when slave_core =>
+        dmi_core_req <= dmi_req;
+        dmi_ack <= dmi_core_ack;
+        dmi_din <= dmi_core_dout;
+      when others =>
+        dmi_ack <= dmi_req;
+        dmi_din <= (others => '1');
+    end case;
+    if sim and dmi_req = '1' and dmi_addr = "11111111" and dmi_wr = '1' then
+      ()
+    end if;
+  end process;
+  wishbone_debug : entity work.wishbone_debug_master
+    port map(
+      clk => system_clk,
+      rst => rst,
+      dmi_addr => dmi_addr(1 downto 0),
+      dmi_dout => dmi_wb_dout,
+      dmi_din => dmi_dout,
+      dmi_wr => dmi_wr,
+      dmi_ack => dmi_wb_ack,
+      dmi_req => dmi_wb_req,
+      wb_in => wishbone_debug_in,
+      wb_out => wishbone_debug_out);
+   
+end behaviour;