vertigo_vhdl 0.8.2

data/tests/parser_tests/test_microwatt_register_file.vhd

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+../microwatt/register_file.vhdl

data/tests/parser_tests/test_microwatt_register_file_pp.vhd

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+-- generated by Vertigo VHDL tool
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.common.all;
+ 
+entity register_file is
+  generic(
+    sim : booleanfalse := false);
+  port(
+    clk : in std_logic;
+    d_in : in decode2toregisterfiletype;
+    d_out : out registerfiletodecode2type;
+    w_in : in writebacktoregisterfiletype;
+    sim_dump : in std_ulogic;
+    sim_dump_done : out std_ulogic);
+end entity register_file;
+ 
+architecture behaviour of register_file is
+   
+  type regfile is array(range 0 to 63) of std_ulogic_vector(63 downto 0);
+  signal registers : regfile := (others => (others => '0'));
+begin
+ 
+   
+  register_write_0 : process(clk)
+  begin
+    if rising_edge(clk) then
+      if w_in.write_enable = '1' then
+        assert (is_x(w_in.write_data)) and (is_x(w_in.write_reg));
+        if w_in.write_reg(5) = '0' then
+          report "writing gpr " & to_hstring(w_in.write_reg) & " " & to_hstring(w_in.write_data);
+        else
+          report "writing gspr " & to_hstring(w_in.write_reg) & " " & to_hstring(w_in.write_data);
+        end if;
+        registers(to_integer(unsigned(w_in.write_reg))) <= w_in.write_data;
+      end if;
+    end if;
+  end process;
+   
+  register_read_0 : process(all)
+  begin
+    if d_in.read1_enable = '1' then
+      report "reading gpr " & to_hstring(d_in.read1_reg) & " " & to_hstring(registers(to_integer(unsigned(d_in.read1_reg))));
+    end if;
+    if d_in.read2_enable = '1' then
+      report "reading gpr " & to_hstring(d_in.read2_reg) & " " & to_hstring(registers(to_integer(unsigned(d_in.read2_reg))));
+    end if;
+    if d_in.read3_enable = '1' then
+      report "reading gpr " & to_hstring(d_in.read3_reg) & " " & to_hstring(registers(to_integer(unsigned(d_in.read3_reg))));
+    end if;
+    d_out.read1_data <= registers(to_integer(unsigned(d_in.read1_reg)));
+    d_out.read2_data <= registers(to_integer(unsigned(d_in.read2_reg)));
+    d_out.read3_data <= registers(to_integer(unsigned(gpr_to_gspr(d_in.read3_reg))));
+    if w_in.write_enable = '1' then
+      if d_in.read1_reg = w_in.write_reg then
+        d_out.read1_data <= w_in.write_data;
+      end if;
+      if d_in.read2_reg = w_in.write_reg then
+        d_out.read2_data <= w_in.write_data;
+      end if;
+      if gpr_to_gspr(d_in.read3_reg) = w_in.write_reg then
+        d_out.read3_data <= w_in.write_data;
+      end if;
+    end if;
+  end process;
+  if sim generate
+     
+    dump_registers : process(all)
+    begin
+      if sim_dump = '1' then
+        ;
+        report "lr " & to_hstring(registers(to_integer(unsigned(fast_spr_num(spr_lr)))));
+        report "ctr " & to_hstring(registers(to_integer(unsigned(fast_spr_num(spr_ctr)))));
+        report "xer " & to_hstring(registers(to_integer(unsigned(fast_spr_num(spr_xer)))));
+        sim_dump_done <= '1';
+      else
+        sim_dump_done <= '0';
+      end if;
+    end process;
+  end generate;
+  if sim generate
+    sim_dump_done <= '0';
+  end generate;
+end behaviour;

data/tests/parser_tests/test_microwatt_rotator.vhd

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+../microwatt/rotator.vhdl

data/tests/parser_tests/test_microwatt_rotator_pp.vhd

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+-- generated by Vertigo VHDL tool
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.common.all;
+ 
+entity rotator is
+  port(
+    rs : in std_ulogic_vector(63 downto 0);
+    ra : in std_ulogic_vector(63 downto 0);
+    shift : in std_ulogic_vector(6 downto 0);
+    insn : in std_ulogic_vector(31 downto 0);
+    is_32bit : in std_ulogic;
+    right_shift : in std_ulogic;
+    arith : in std_ulogic;
+    clear_left : in std_ulogic;
+    clear_right : in std_ulogic;
+    result : out std_ulogic_vector(63 downto 0);
+    carry_out : out std_ulogic);
+end entity rotator;
+ 
+architecture behaviour of rotator is
+  signal repl32 : std_ulogic_vector(63 downto 0);
+  signal rot_count : std_ulogic_vector(5 downto 0);
+  signal rot1 : std_ulogic_vector(63 downto 0);
+  signal rot2 : std_ulogic_vector(63 downto 0);
+  signal rot : std_ulogic_vector(63 downto 0);
+  signal sh : std_ulogic_vector(6 downto 0);
+  signal mb : std_ulogic_vector(6 downto 0);
+  signal me : std_ulogic_vector(6 downto 0);
+  signal mr : std_ulogic_vector(63 downto 0);
+  signal ml : std_ulogic_vector(63 downto 0);
+  signal output_mode : std_ulogic_vector(1 downto 0);
+   
+  function right_mask(mask_begin : std_ulogic_vector(6 downto 0)) return std_ulogic_vector is
+    variable ret : std_ulogic_vector(63 downto 0);
+  begin
+    ret := (others => '0');
+    return ret;
+  end function right_mask;
+   
+  function left_mask(mask_end : std_ulogic_vector(6 downto 0)) return std_ulogic_vector is
+    variable ret : std_ulogic_vector(63 downto 0);
+  begin
+    ret := (others => '0');
+    if mask_end(6) = '0' then
+      ;
+    end if;
+    return ret;
+  end function left_mask;
+begin
+ 
+   
+  rotator_0 : process(all)
+  begin
+    if is_32bit = '1' then
+      repl32 <= rs(31 downto 0) & rs(31 downto 0);
+    else
+      repl32 <= rs;
+    end if;
+    if right_shift = '1' then
+      rot_count <= std_ulogic_vector(signed(shift(5 downto 0)));
+    else
+      rot_count <= shift(5 downto 0);
+    end if;
+    case rot_count(1 downto 0) is
+      when "00" =>
+        rot1 <= repl32;
+      when "01" =>
+        rot1 <= repl32(62 downto 0) & repl32(63);
+      when "10" =>
+        rot1 <= repl32(61 downto 0) & repl32(63 downto 62);
+      when others =>
+        rot1 <= repl32(60 downto 0) & repl32(63 downto 61);
+    end case;
+    case rot_count(3 downto 2) is
+      when "00" =>
+        rot2 <= rot1;
+      when "01" =>
+        rot2 <= rot1(59 downto 0) & rot1(63 downto 60);
+      when "10" =>
+        rot2 <= rot1(55 downto 0) & rot1(63 downto 56);
+      when others =>
+        rot2 <= rot1(51 downto 0) & rot1(63 downto 52);
+    end case;
+    case rot_count(5 downto 4) is
+      when "00" =>
+        rot <= rot2;
+      when "01" =>
+        rot <= rot2(47 downto 0) & rot2(63 downto 48);
+      when "10" =>
+        rot <= rot2(31 downto 0) & rot2(63 downto 32);
+      when others =>
+        rot <= rot2(15 downto 0) & rot2(63 downto 16);
+    end case;
+    sh <= (shift(6) and is_32bit) & shift(5 downto 0);
+    if clear_left = '1' then
+      if is_32bit = '1' then
+        mb <= "01" & insn(10 downto 6);
+      else
+        mb <= "0" & insn(5) & insn(10 downto 6);
+      end if;
+    elsif right_shift = '1' then
+      if is_32bit = '1' then
+        mb <= sh(5) & sh(5) & sh(4 downto 0);
+      else
+        mb <= sh;
+      end if;
+    else
+      mb <= ('0' & is_32bit & "00000");
+    end if;
+    if clear_right = '1' and is_32bit = '1' then
+      me <= "01" & insn(5 downto 1);
+    elsif clear_right = '1' and clear_left = '0' then
+      me <= "0" & insn(5) & insn(10 downto 6);
+    else
+      me <= sh(6) & sh(5 downto 0);
+    end if;
+    mr <= right_mask(mb);
+    ml <= left_mask(me);
+    if (clear_left = '1' and clear_right = '0') or right_shift = '1' then
+      output_mode(1) <= '1';
+      output_mode(0) <= arith and repl32(63);
+    else
+      output_mode(1) <= '0';
+      if clear_right = '1' and unsigned(mb(5 downto 0)) > unsigned(me(5 downto 0)) then
+        output_mode(0) <= '1';
+      else
+        output_mode(0) <= '0';
+      end if;
+    end if;
+    case output_mode is
+      when "00" =>
+        result <= (rot and (mr and ml)) or (ra and (mr and ml));
+      when "01" =>
+        result <= (rot and (mr or ml)) or (ra and (mr or ml));
+      when "10" =>
+        result <= rot and mr;
+      when others =>
+        result <= rot or mr;
+    end case;
+    if output_mode = "11" then
+      carry_out <= or(rs and ml);
+    else
+      carry_out <= '0';
+    end if;
+  end process;
+end behaviour;

data/tests/parser_tests/test_microwatt_rotator_tb.vhd

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+../microwatt/rotator_tb.vhdl

data/tests/parser_tests/test_microwatt_rotator_tb_pp.vhd

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+-- generated by Vertigo VHDL tool
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.common.all;
+use work.glibc_random.all;
+use work.ppc_fx_insns.all;
+use work.insn_helpers.all;
+ 
+entity rotator_tb is
+end entity rotator_tb;
+ 
+architecture behave of rotator_tb is
+  constant clk_period : time := 10 ns;
+  signal ra : std_ulogic_vector(63 downto 0);
+  signal rs : std_ulogic_vector(63 downto 0);
+  signal shift : std_ulogic_vector(6 downto 0) := (others => '0');
+  signal insn : std_ulogic_vector(31 downto 0) := (others => '0');
+  signal is_32bit : std_ulogic;
+  signal right_shift : std_ulogic;
+  signal arith : std_ulogic;
+  signal clear_left : std_ulogic;
+  signal clear_right : std_ulogic := '0';
+  signal result : std_ulogic_vector(63 downto 0);
+  signal carry_out : std_ulogic;
+begin
+ 
+  rotator_0 : entity work.rotator
+    port map(
+      rs => rs,
+      ra => ra,
+      shift => shift,
+      insn => insn,
+      is_32bit => is_32bit,
+      right_shift => right_shift,
+      arith => arith,
+      clear_left => clear_left,
+      clear_right => clear_right,
+      result => result,
+      carry_out => carry_out);
+   
+   
+  stim_process : process
+    variable behave_ra : std_ulogic_vector(63 downto 0);
+    variable behave_ca_ra : std_ulogic_vector(64 downto 0);
+  begin
+    report "test rlw[i]nm";
+    ra <= (others => '0');
+    is_32bit <= '1';
+    right_shift <= '0';
+    arith <= '0';
+    clear_left <= '1';
+    clear_right <= '1';
+    report "test rlwimi";
+    is_32bit <= '1';
+    right_shift <= '0';
+    arith <= '0';
+    clear_left <= '1';
+    clear_right <= '1';
+    report "test rld[i]cl";
+    ra <= (others => '0');
+    is_32bit <= '0';
+    right_shift <= '0';
+    arith <= '0';
+    clear_left <= '1';
+    clear_right <= '0';
+    report "test rld[i]cr";
+    ra <= (others => '0');
+    is_32bit <= '0';
+    right_shift <= '0';
+    arith <= '0';
+    clear_left <= '0';
+    clear_right <= '1';
+    report "test rldic";
+    ra <= (others => '0');
+    is_32bit <= '0';
+    right_shift <= '0';
+    arith <= '0';
+    clear_left <= '1';
+    clear_right <= '1';
+    report "test rldimi";
+    is_32bit <= '0';
+    right_shift <= '0';
+    arith <= '0';
+    clear_left <= '1';
+    clear_right <= '1';
+    report "test slw";
+    ra <= (others => '0');
+    is_32bit <= '1';
+    right_shift <= '0';
+    arith <= '0';
+    clear_left <= '0';
+    clear_right <= '0';
+    report "test sld";
+    ra <= (others => '0');
+    is_32bit <= '0';
+    right_shift <= '0';
+    arith <= '0';
+    clear_left <= '0';
+    clear_right <= '0';
+    report "test srw";
+    ra <= (others => '0');
+    is_32bit <= '1';
+    right_shift <= '1';
+    arith <= '0';
+    clear_left <= '0';
+    clear_right <= '0';
+    report "test srd";
+    ra <= (others => '0');
+    is_32bit <= '0';
+    right_shift <= '1';
+    arith <= '0';
+    clear_left <= '0';
+    clear_right <= '0';
+    report "test sraw[i]";
+    ra <= (others => '0');
+    is_32bit <= '1';
+    right_shift <= '1';
+    arith <= '1';
+    clear_left <= '0';
+    clear_right <= '0';
+    report "test srad[i]";
+    ra <= (others => '0');
+    is_32bit <= '0';
+    right_shift <= '1';
+    arith <= '1';
+    clear_left <= '0';
+    clear_right <= '0';
+    assert false
+      report "end of test" severity failure;
+    wait ;
+  end process;
+end behave;

data/tests/parser_tests/test_microwatt_sim_bram.vhd

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+../microwatt/sim_bram.vhdl

data/tests/parser_tests/test_microwatt_sim_bram_helpers.vhd

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+../microwatt/sim_bram_helpers.vhdl

data/tests/parser_tests/test_microwatt_sim_bram_helpers_pp.vhd

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+-- generated by Vertigo VHDL tool
+library ieee;
+use ieee.std_logic_1164.all;
+ 
+package sim_bram_helpers is
+  function behavioural_initialize(filename : string;size : integer) return integer
+  attribute foreign of behavioural_initialize : function is "vhpidirect behavioural_initialize";
+   
+  procedure behavioural_read(
+    val : out std_ulogic_vector(63 downto 0);
+    addr : std_ulogic_vector(63 downto 0);
+    length : integer;
+    identifier : integer);
+  attribute foreign of behavioural_read : procedure is "vhpidirect behavioural_read";
+   
+  procedure behavioural_write(
+    val : std_ulogic_vector(63 downto 0);
+    addr : std_ulogic_vector(63 downto 0);
+    length : integer;
+    identifier : integer);
+  attribute foreign of behavioural_write : procedure is "vhpidirect behavioural_write";
+ 
+end sim_bram_helpers;
+ 
+package body sim_bram_helpers is
+   
+  function behavioural_initialize(filename : string;size : integer) return integer is
+  begin
+    assert false
+      report "vhpi" severity failure;
+  end function behavioural_initialize;
+   
+  procedure behavioural_read(
+    val : out std_ulogic_vector(63 downto 0);
+    addr : std_ulogic_vector(63 downto 0);
+    length : integer;
+    identifier : integer) is
+  begin
+    assert false
+      report "vhpi" severity failure;
+  end behavioural_read;
+   
+  procedure behavioural_write(
+    val : std_ulogic_vector(63 downto 0);
+    addr : std_ulogic_vector(63 downto 0);
+    length : integer;
+    identifier : integer) is
+  begin
+    assert false
+      report "vhpi" severity failure;
+  end behavioural_write;
+end sim_bram_helpers;

data/tests/parser_tests/test_microwatt_sim_bram_pp.vhd

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+-- generated by Vertigo VHDL tool
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+library work;
+use work.utils.all;
+use work.sim_bram_helpers.all;
+ 
+entity main_bram is
+  generic(
+    width : natural64 := 64;
+    height_bits : natural1024 := 1024;
+    memory_size : natural65536 := 65536;
+    ram_init_file : string);
+  port(
+    clk : in std_logic;
+    addr : in std_logic_vector(height_bits - 1 downto 0);
+    di : in std_logic_vector(width - 1 downto 0);
+    do : out std_logic_vector(width - 1 downto 0);
+    sel : in std_logic_vector((width / 8) - 1 downto 0);
+    re : in std_ulogic;
+    we : in std_ulogic);
+end entity main_bram;
+ 
+architecture sim of main_bram is
+  constant width_bytes : natural := width / 8;
+  constant pad_zeros : std_ulogic_vector(log2(width_bytes) - 1 downto 0) := (others => '0');
+  signal identifier : integer := behavioural_initialize(filename => ram_init_file,size => memory_size);
+  signal obuf : std_logic_vector(width - 1 downto 0);
+begin
+ 
+   
+  memory_0 : process(clk)
+    variable ret_dat_v : std_ulogic_vector(63 downto 0);
+    variable addr64 : std_ulogic_vector(63 downto 0);
+  begin
+    if rising_edge(clk) then
+      addr64 := (others => '0');
+      addr64(height_bits + 2 downto 3) := addr;
+      if we = '1' then
+        report "ram writing " & to_hstring(di) & " to " & to_hstring(addr & pad_zeros) & " sel:" & to_hstring(sel);
+        ()
+      end if;
+      if re = '1' then
+        ()
+        report "ram reading from " & to_hstring(addr & pad_zeros) & " returns " & to_hstring(ret_dat_v);
+        obuf <= ret_dat_v(obuf'left downto 0);
+      end if;
+      do <= obuf;
+    end if;
+  end process;
+end sim;