vertigo_vhdl 0.8.2

data/tests/parser_tests/test_microwatt_insn_helpers_pp.vhd

@@ -0,0 +1,208 @@
+-- generated by Vertigo VHDL tool
+library ieee;
+use ieee.std_logic_1164.all;
+ 
+package insn_helpers is
+  function insn_rs(insn_in : std_ulogic_vector) return std_ulogic_vector
+  function insn_rt(insn_in : std_ulogic_vector) return std_ulogic_vector
+  function insn_ra(insn_in : std_ulogic_vector) return std_ulogic_vector
+  function insn_rb(insn_in : std_ulogic_vector) return std_ulogic_vector
+  function insn_si(insn_in : std_ulogic_vector) return std_ulogic_vector
+  function insn_ui(insn_in : std_ulogic_vector) return std_ulogic_vector
+  function insn_l(insn_in : std_ulogic_vector) return std_ulogic
+  function insn_sh32(insn_in : std_ulogic_vector) return std_ulogic_vector
+  function insn_mb32(insn_in : std_ulogic_vector) return std_ulogic_vector
+  function insn_me32(insn_in : std_ulogic_vector) return std_ulogic_vector
+  function insn_li(insn_in : std_ulogic_vector) return std_ulogic_vector
+  function insn_lk(insn_in : std_ulogic_vector) return std_ulogic
+  function insn_aa(insn_in : std_ulogic_vector) return std_ulogic
+  function insn_rc(insn_in : std_ulogic_vector) return std_ulogic
+  function insn_oe(insn_in : std_ulogic_vector) return std_ulogic
+  function insn_bd(insn_in : std_ulogic_vector) return std_ulogic_vector
+  function insn_bf(insn_in : std_ulogic_vector) return std_ulogic_vector
+  function insn_bfa(insn_in : std_ulogic_vector) return std_ulogic_vector
+  function insn_cr(insn_in : std_ulogic_vector) return std_ulogic_vector
+  function insn_bt(insn_in : std_ulogic_vector) return std_ulogic_vector
+  function insn_ba(insn_in : std_ulogic_vector) return std_ulogic_vector
+  function insn_bb(insn_in : std_ulogic_vector) return std_ulogic_vector
+  function insn_fxm(insn_in : std_ulogic_vector) return std_ulogic_vector
+  function insn_bo(insn_in : std_ulogic_vector) return std_ulogic_vector
+  function insn_bi(insn_in : std_ulogic_vector) return std_ulogic_vector
+  function insn_bh(insn_in : std_ulogic_vector) return std_ulogic_vector
+  function insn_d(insn_in : std_ulogic_vector) return std_ulogic_vector
+  function insn_ds(insn_in : std_ulogic_vector) return std_ulogic_vector
+  function insn_to(insn_in : std_ulogic_vector) return std_ulogic_vector
+  function insn_bc(insn_in : std_ulogic_vector) return std_ulogic_vector
+  function insn_sh(insn_in : std_ulogic_vector) return std_ulogic_vector
+  function insn_me(insn_in : std_ulogic_vector) return std_ulogic_vector
+  function insn_mb(insn_in : std_ulogic_vector) return std_ulogic_vector
+ 
+end insn_helpers;
+ 
+package body insn_helpers is
+   
+  function insn_rs(insn_in : std_ulogic_vector) return std_ulogic_vector is
+  begin
+    return insn_in(25 downto 21);
+  end function insn_rs;
+   
+  function insn_rt(insn_in : std_ulogic_vector) return std_ulogic_vector is
+  begin
+    return insn_in(25 downto 21);
+  end function insn_rt;
+   
+  function insn_ra(insn_in : std_ulogic_vector) return std_ulogic_vector is
+  begin
+    return insn_in(20 downto 16);
+  end function insn_ra;
+   
+  function insn_rb(insn_in : std_ulogic_vector) return std_ulogic_vector is
+  begin
+    return insn_in(15 downto 11);
+  end function insn_rb;
+   
+  function insn_si(insn_in : std_ulogic_vector) return std_ulogic_vector is
+  begin
+    return insn_in(15 downto 0);
+  end function insn_si;
+   
+  function insn_ui(insn_in : std_ulogic_vector) return std_ulogic_vector is
+  begin
+    return insn_in(15 downto 0);
+  end function insn_ui;
+   
+  function insn_l(insn_in : std_ulogic_vector) return std_ulogic is
+  begin
+    return insn_in(21);
+  end function insn_l;
+   
+  function insn_sh32(insn_in : std_ulogic_vector) return std_ulogic_vector is
+  begin
+    return insn_in(15 downto 11);
+  end function insn_sh32;
+   
+  function insn_mb32(insn_in : std_ulogic_vector) return std_ulogic_vector is
+  begin
+    return insn_in(10 downto 6);
+  end function insn_mb32;
+   
+  function insn_me32(insn_in : std_ulogic_vector) return std_ulogic_vector is
+  begin
+    return insn_in(5 downto 1);
+  end function insn_me32;
+   
+  function insn_li(insn_in : std_ulogic_vector) return std_ulogic_vector is
+  begin
+    return insn_in(25 downto 2);
+  end function insn_li;
+   
+  function insn_lk(insn_in : std_ulogic_vector) return std_ulogic is
+  begin
+    return insn_in(0);
+  end function insn_lk;
+   
+  function insn_aa(insn_in : std_ulogic_vector) return std_ulogic is
+  begin
+    return insn_in(1);
+  end function insn_aa;
+   
+  function insn_rc(insn_in : std_ulogic_vector) return std_ulogic is
+  begin
+    return insn_in(0);
+  end function insn_rc;
+   
+  function insn_oe(insn_in : std_ulogic_vector) return std_ulogic is
+  begin
+    return insn_in(10);
+  end function insn_oe;
+   
+  function insn_bd(insn_in : std_ulogic_vector) return std_ulogic_vector is
+  begin
+    return insn_in(15 downto 2);
+  end function insn_bd;
+   
+  function insn_bf(insn_in : std_ulogic_vector) return std_ulogic_vector is
+  begin
+    return insn_in(25 downto 23);
+  end function insn_bf;
+   
+  function insn_bfa(insn_in : std_ulogic_vector) return std_ulogic_vector is
+  begin
+    return insn_in(20 downto 18);
+  end function insn_bfa;
+   
+  function insn_cr(insn_in : std_ulogic_vector) return std_ulogic_vector is
+  begin
+    return insn_in(10 downto 1);
+  end function insn_cr;
+   
+  function insn_bb(insn_in : std_ulogic_vector) return std_ulogic_vector is
+  begin
+    return insn_in(15 downto 11);
+  end function insn_bb;
+   
+  function insn_ba(insn_in : std_ulogic_vector) return std_ulogic_vector is
+  begin
+    return insn_in(20 downto 16);
+  end function insn_ba;
+   
+  function insn_bt(insn_in : std_ulogic_vector) return std_ulogic_vector is
+  begin
+    return insn_in(25 downto 21);
+  end function insn_bt;
+   
+  function insn_fxm(insn_in : std_ulogic_vector) return std_ulogic_vector is
+  begin
+    return insn_in(19 downto 12);
+  end function insn_fxm;
+   
+  function insn_bo(insn_in : std_ulogic_vector) return std_ulogic_vector is
+  begin
+    return insn_in(25 downto 21);
+  end function insn_bo;
+   
+  function insn_bi(insn_in : std_ulogic_vector) return std_ulogic_vector is
+  begin
+    return insn_in(20 downto 16);
+  end function insn_bi;
+   
+  function insn_bh(insn_in : std_ulogic_vector) return std_ulogic_vector is
+  begin
+    return insn_in(12 downto 11);
+  end function insn_bh;
+   
+  function insn_d(insn_in : std_ulogic_vector) return std_ulogic_vector is
+  begin
+    return insn_in(15 downto 0);
+  end function insn_d;
+   
+  function insn_ds(insn_in : std_ulogic_vector) return std_ulogic_vector is
+  begin
+    return insn_in(15 downto 2);
+  end function insn_ds;
+   
+  function insn_to(insn_in : std_ulogic_vector) return std_ulogic_vector is
+  begin
+    return insn_in(25 downto 21);
+  end function insn_to;
+   
+  function insn_bc(insn_in : std_ulogic_vector) return std_ulogic_vector is
+  begin
+    return insn_in(10 downto 6);
+  end function insn_bc;
+   
+  function insn_sh(insn_in : std_ulogic_vector) return std_ulogic_vector is
+  begin
+    return insn_in(1) & insn_in(15 downto 11);
+  end function insn_sh;
+   
+  function insn_me(insn_in : std_ulogic_vector) return std_ulogic_vector is
+  begin
+    return insn_in(5) & insn_in(10 downto 6);
+  end function insn_me;
+   
+  function insn_mb(insn_in : std_ulogic_vector) return std_ulogic_vector is
+  begin
+    return insn_in(5) & insn_in(10 downto 6);
+  end function insn_mb;
+end insn_helpers;

data/tests/parser_tests/test_microwatt_loadstore1.vhd

@@ -0,0 +1 @@
+../microwatt/loadstore1.vhdl

data/tests/parser_tests/test_microwatt_loadstore1_pp.vhd

@@ -0,0 +1,222 @@
+-- generated by Vertigo VHDL tool
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.common.all;
+use work.helpers.all;
+ 
+entity loadstore1 is
+  port(
+    clk : in std_ulogic;
+    rst : in std_ulogic;
+    l_in : in execute1toloadstore1type;
+    l_out : out loadstore1towritebacktype;
+    d_out : out loadstore1todcachetype;
+    d_in : in dcachetoloadstore1type;
+    dc_stall : in std_ulogic;
+    stall_out : out std_ulogic);
+end entity loadstore1;
+ 
+architecture behave of loadstore1 is
+   
+  type state_t is (idle,second_req,first_ack_wait,last_ack_wait,ld_update);
+   
+  type reg_stage_t is record
+    load : std_ulogic;
+    addr : std_ulogic_vector(63 downto 0);
+    store_data : std_ulogic_vector(63 downto 0);
+    load_data : std_ulogic_vector(63 downto 0);
+    write_reg : gpr_index_t;
+    length : std_ulogic_vector(3 downto 0);
+    byte_reverse : std_ulogic;
+    sign_extend : std_ulogic;
+    update : std_ulogic;
+    update_reg : gpr_index_t;
+    xerc : xer_common_t;
+    reserve : std_ulogic;
+    rc : std_ulogic;
+    nc : std_ulogic;
+    state : state_t;
+    second_bytes : std_ulogic_vector(7 downto 0);
+  end record;
+   
+  type byte_sel_t is array(range 0 to 7) of std_ulogic;
+   
+  subtype byte_trim_t is std_ulogic_vector(1 downto 0);
+   
+  type trim_ctl_t is array(range 0 to 7) of byte_trim_t;
+  signal r : reg_stage_t;
+  signal rin : reg_stage_t;
+  signal lsu_sum : std_ulogic_vector(63 downto 0);
+   
+  function length_to_sel(length : in std_logic_vector(3 downto 0)) return std_ulogic_vector is
+  begin
+    case length is
+      when "0001" =>
+        return "00000001";
+      when "0010" =>
+        return "00000011";
+      when "0100" =>
+        return "00001111";
+      when "1000" =>
+        return "11111111";
+      when others =>
+        return "00000000";
+    end case;
+  end function length_to_sel;
+   
+  function xfer_data_sel(size : in std_logic_vector(3 downto 0);address : in std_logic_vector(2 downto 0)) return std_ulogic_vector is
+    variable longsel : std_ulogic_vector(15 downto 0);
+  begin
+    longsel := "00000000" & length_to_sel(size);
+    return std_ulogic_vector(shift_left(unsigned(longsel),to_integer(unsigned(address))));
+  end function xfer_data_sel;
+begin
+ 
+  lsu_sum <= std_ulogic_vector(unsigned(l_in.addr1) + unsigned(l_in.addr2)) when l_in.valid = '1' else  (others => '0');
+   
+  loadstore1_0 : process(clk)
+  begin
+    if rising_edge(clk) then
+      if rst = '1' then
+        r.state <= idle;
+      else
+        r <= rin;
+      end if;
+    end if;
+  end process;
+   
+  loadstore1_1 : process(all)
+    variable v : reg_stage_t;
+    variable brev_lenm1 : unsigned(2 downto 0);
+    variable byte_offset : unsigned(2 downto 0);
+    variable j : integer;
+    variable k : unsigned(2 downto 0);
+    variable kk : unsigned(3 downto 0);
+    variable long_sel : std_ulogic_vector(15 downto 0);
+    variable byte_sel : std_ulogic_vector(7 downto 0);
+    variable req : std_ulogic;
+    variable stall : std_ulogic;
+    variable addr : std_ulogic_vector(63 downto 0);
+    variable wdata : std_ulogic_vector(63 downto 0);
+    variable write_enable : std_ulogic;
+    variable do_update : std_ulogic;
+    variable two_dwords : std_ulogic;
+    variable done : std_ulogic;
+    variable data_permuted : std_ulogic_vector(63 downto 0);
+    variable data_trimmed : std_ulogic_vector(63 downto 0);
+    variable use_second : byte_sel_t;
+    variable trim_ctl : trim_ctl_t;
+    variable negative : std_ulogic;
+  begin
+    v := r;
+    req := '0';
+    stall := '0';
+    done := '0';
+    byte_sel := (others => '0');
+    addr := lsu_sum;
+    write_enable := '0';
+    do_update := '0';
+    two_dwords := or(r.second_bytes);
+    if r.load = '1' then
+      byte_offset := unsigned(r.addr(2 downto 0));
+      brev_lenm1 := "000";
+      if r.byte_reverse = '1' then
+        brev_lenm1 := unsigned(r.length(2 downto 0)) - 1;
+      end if;
+      negative := (r.length(3) and data_permuted(63)) or (r.length(2) and data_permuted(31)) or (r.length(1) and data_permuted(15)) or (r.length(0) and data_permuted(7));
+    end if;
+    case r.state is
+      when idle =>
+        if l_in.valid = '1' then
+          v.load := l_in.load;
+          v.addr := lsu_sum;
+          v.write_reg := l_in.write_reg;
+          v.length := l_in.length;
+          v.byte_reverse := l_in.byte_reverse;
+          v.sign_extend := l_in.sign_extend;
+          v.update := l_in.update;
+          v.update_reg := l_in.update_reg;
+          v.xerc := l_in.xerc;
+          v.reserve := l_in.reserve;
+          v.rc := l_in.rc;
+          v.nc := l_in.ci;
+          if lsu_sum(31 downto 28) = "1100" then
+            v.nc := '1';
+          end if;
+          long_sel := xfer_data_sel(l_in.length,v.addr(2 downto 0));
+          byte_sel := long_sel(7 downto 0);
+          v.second_bytes := long_sel(15 downto 8);
+          v.addr := lsu_sum;
+          if v.load = '0' then
+            byte_offset := unsigned(lsu_sum(2 downto 0));
+            brev_lenm1 := "000";
+            if l_in.byte_reverse = '1' then
+              brev_lenm1 := unsigned(l_in.length(2 downto 0)) - 1;
+            end if;
+          end if;
+          req := '1';
+          stall := '1';
+          if long_sel(15 downto 8) = "00000000" then
+            v.state := last_ack_wait;
+          else
+            v.state := second_req;
+          end if;
+        end if;
+      when second_req =>
+        addr := std_ulogic_vector(unsigned(r.addr(63 downto 3)) + 1) & "000";
+        byte_sel := r.second_bytes;
+        req := '1';
+        stall := '1';
+        v.state := first_ack_wait;
+      when first_ack_wait =>
+        stall := '1';
+        if d_in.valid = '1' then
+          v.state := last_ack_wait;
+          if r.load = '1' then
+            v.load_data := data_permuted;
+          end if;
+        end if;
+      when last_ack_wait =>
+        stall := '1';
+        if d_in.valid = '1' then
+          write_enable := r.load;
+          if r.load = '1' and r.update = '1' then
+            v.state := ld_update;
+          else
+            do_update := r.update;
+            stall := '0';
+            done := '1';
+            v.state := idle;
+          end if;
+        end if;
+      when ld_update =>
+        do_update := '1';
+        v.state := idle;
+        done := '1';
+    end case;
+    d_out.valid <= req;
+    d_out.load <= v.load;
+    d_out.nc <= v.nc;
+    d_out.reserve <= v.reserve;
+    d_out.addr <= addr;
+    d_out.data <= v.store_data;
+    d_out.byte_sel <= byte_sel;
+    l_out.valid <= done;
+    if do_update = '1' then
+      l_out.write_enable <= '1';
+      l_out.write_reg <= r.update_reg;
+      l_out.write_data <= r.addr;
+    else
+      l_out.write_enable <= write_enable;
+      l_out.write_reg <= r.write_reg;
+      l_out.write_data <= data_trimmed;
+    end if;
+    l_out.xerc <= r.xerc;
+    l_out.rc <= r.rc and done;
+    l_out.store_done <= d_in.store_done;
+    stall_out <= stall;
+    rin <= v;
+  end process;
+end behave;

data/tests/parser_tests/test_microwatt_logical.vhd

@@ -0,0 +1 @@
+../microwatt/logical.vhdl

data/tests/parser_tests/test_microwatt_logical_pp.vhd

@@ -0,0 +1,87 @@
+-- generated by Vertigo VHDL tool
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.decode_types.all;
+ 
+entity logical is
+  port(
+    rs : in std_ulogic_vector(63 downto 0);
+    rb : in std_ulogic_vector(63 downto 0);
+    op : in insn_type_t;
+    invert_in : in std_ulogic;
+    invert_out : in std_ulogic;
+    result : out std_ulogic_vector(63 downto 0);
+    datalen : in std_logic_vector(3 downto 0);
+    popcnt : out std_ulogic_vector(63 downto 0);
+    parity : out std_ulogic_vector(63 downto 0));
+end entity logical;
+ 
+architecture behaviour of logical is
+   
+  subtype twobit is unsigned(1 downto 0);
+   
+  type twobit32 is array(range 0 to 31) of twobit;
+  signal pc2 : twobit32;
+   
+  subtype threebit is unsigned(2 downto 0);
+   
+  type threebit16 is array(range 0 to 15) of threebit;
+  signal pc4 : threebit16;
+   
+  subtype fourbit is unsigned(3 downto 0);
+   
+  type fourbit8 is array(range 0 to 7) of fourbit;
+  signal pc8 : fourbit8;
+   
+  subtype sixbit is unsigned(5 downto 0);
+   
+  type sixbit2 is array(range 0 to 1) of sixbit;
+  signal pc32 : sixbit2;
+  signal par0 : std_ulogic;
+  signal par1 : std_ulogic;
+begin
+ 
+   
+  logical_0 : process(all)
+    variable rb_adj : std_ulogic_vector(63 downto 0);
+    variable tmp : std_ulogic_vector(63 downto 0);
+  begin
+    rb_adj := rb;
+    if invert_in = '1' then
+      rb_adj := rb;
+    end if;
+    case op is
+      when op_and =>
+        tmp := rs and rb_adj;
+      when op_or =>
+        tmp := rs or rb_adj;
+      when others =>
+        tmp := rs xor rb_adj;
+    end case;
+    result <= tmp;
+    if invert_out = '1' then
+      result <= tmp;
+    end if;
+    ;
+    ;
+    popcnt <= (others => '0');
+    if datalen(3 downto 2) = "00" then
+      ;
+    elsif datalen(3) = '0' then
+      ;
+    else
+      popcnt(6 downto 0) <= std_ulogic_vector(('0' & pc32(0)) + ('0' & pc32(1)));
+    end if;
+    par0 <= rs(0) xor rs(8) xor rs(16) xor rs(24);
+    par1 <= rs(32) xor rs(40) xor rs(48) xor rs(56);
+    parity <= (others => '0');
+    if datalen(3) = '1' then
+      parity(0) <= par0 xor par1;
+    else
+      parity(0) <= par0;
+      parity(32) <= par1;
+    end if;
+  end process;
+end behaviour;