vertigo_vhdl 0.8.2

data/tests/parser_tests/test_microwatt_decode_types.vhd

@@ -0,0 +1 @@
+../microwatt/decode_types.vhdl

data/tests/parser_tests/test_microwatt_decode_types_pp.vhd

@@ -0,0 +1,67 @@
+-- generated by Vertigo VHDL tool
+library ieee;
+use ieee.std_logic_1164.all;
+ 
+package decode_types is
+   
+  type insn_type_t is (op_illegal,op_nop,op_add,op_addpcis,op_and,op_attn,op_b,op_bc,op_bcreg,op_bperm,op_cmp,op_cmpb,op_cmpeqb,op_cmprb,op_cntz,op_crand,op_crandc,op_creqv,op_crnand,op_crnor,op_cror,op_crorc,op_crxor,op_darn,op_dcbf,op_dcbst,op_dcbt,op_dcbtst,op_dcbz,op_div,op_dive,op_exts,op_extswsli,op_icbi,op_icbt,op_isel,op_isync,op_load,op_store,op_maddhd,op_maddhdu,op_maddld,op_mcrf,op_mcrxr,op_mcrxrx,op_mfcr,op_mfmsr,op_mfspr,op_mod,op_mtcrf,op_mtmsrd,op_mtspr,op_mul_l64,op_mul_h64,op_mul_h32,op_or,op_popcnt,op_prty,op_rfid,op_rlc,op_rlcl,op_rlcr,op_sc,op_setb,op_shl,op_shr,op_sync,op_td,op_tdi,op_tw,op_twi,op_xor,op_sim_config);
+   
+  type input_reg_a_t is (none,ra,ra_or_zero,spr);
+   
+  type input_reg_b_t is (none,rb,const_ui,const_si,const_si_hi,const_ui_hi,const_li,const_bd,const_ds,const_m1,const_sh,const_sh32,spr);
+   
+  type input_reg_c_t is (none,rs);
+   
+  type output_reg_a_t is (none,rt,ra,spr);
+   
+  type rc_t is (none,one,rc);
+   
+  type carry_in_t is (zero,ca,one);
+  constant sh_offset : integer := 0;
+  constant mb_offset : integer := 1;
+  constant me_offset : integer := 1;
+  constant sh32_offset : integer := 0;
+  constant mb32_offset : integer := 1;
+  constant me32_offset : integer := 2;
+  constant fxm_offset : integer := 0;
+  constant bo_offset : integer := 0;
+  constant bi_offset : integer := 1;
+  constant bh_offset : integer := 2;
+  constant bf_offset : integer := 0;
+  constant l_offset : integer := 1;
+  constant too_offset : integer := 0;
+   
+  type unit_t is (none,alu,ldst);
+   
+  type length_t is (none,is1b,is2b,is4b,is8b);
+   
+  type decode_rom_t is record
+    unit : unit_t;
+    insn_type : insn_type_t;
+    input_reg_a : input_reg_a_t;
+    input_reg_b : input_reg_b_t;
+    input_reg_c : input_reg_c_t;
+    output_reg_a : output_reg_a_t;
+    input_cr : std_ulogic;
+    output_cr : std_ulogic;
+    invert_a : std_ulogic;
+    invert_out : std_ulogic;
+    input_carry : carry_in_t;
+    output_carry : std_ulogic;
+    length : length_t;
+    byte_reverse : std_ulogic;
+    sign_extend : std_ulogic;
+    update : std_ulogic;
+    reserve : std_ulogic;
+    is_32bit : std_ulogic;
+    is_signed : std_ulogic;
+    rc : rc_t;
+    lr : std_ulogic;
+    sgl_pipe : std_ulogic;
+  end record;
+  constant decode_rom_init : decode_rom_t := (unit => none,insn_type => op_illegal,input_reg_a => none,input_reg_b => none,input_reg_c => none,output_reg_a => none,input_cr => '0',output_cr => '0',invert_a => '0',invert_out => '0',input_carry => zero,output_carry => '0',length => none,byte_reverse => '0',sign_extend => '0',update => '0',reserve => '0',is_32bit => '0',is_signed => '0',rc => none,lr => '0',sgl_pipe => '0');
+ 
+end decode_types;
+ 
+package body decode_types is
+end decode_types;

data/tests/parser_tests/test_microwatt_divider.vhd

@@ -0,0 +1 @@
+../microwatt/divider.vhdl

data/tests/parser_tests/test_microwatt_divider_pp.vhd

@@ -0,0 +1,132 @@
+-- generated by Vertigo VHDL tool
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.common.all;
+use work.decode_types.all;
+ 
+entity divider is
+  port(
+    clk : in std_logic;
+    rst : in std_logic;
+    d_in : in execute1todividertype;
+    d_out : out dividertoexecute1type);
+end entity divider;
+ 
+architecture behaviour of divider is
+  signal dend : std_ulogic_vector(128 downto 0);
+  signal div : unsigned(63 downto 0);
+  signal quot : std_ulogic_vector(63 downto 0);
+  signal result : std_ulogic_vector(63 downto 0);
+  signal sresult : std_ulogic_vector(64 downto 0);
+  signal oresult : std_ulogic_vector(63 downto 0);
+  signal running : std_ulogic;
+  signal count : unsigned(6 downto 0);
+  signal neg_result : std_ulogic;
+  signal is_modulus : std_ulogic;
+  signal is_32bit : std_ulogic;
+  signal extended : std_ulogic;
+  signal is_signed : std_ulogic;
+  signal overflow : std_ulogic;
+  signal ovf32 : std_ulogic;
+  signal did_ovf : std_ulogic;
+begin
+ 
+   
+  divider_0 : process(clk)
+  begin
+    if rising_edge(clk) then
+      if rst = '1' then
+        dend <= (others => '0');
+        div <= (others => '0');
+        quot <= (others => '0');
+        running <= '0';
+        count <= "0000000";
+      elsif d_in.valid = '1' then
+        if d_in.is_extended = '1' then
+          dend <= '0' & d_in.dividend & x"0000000000000000";
+        else
+          dend <= '0' & x"0000000000000000" & d_in.dividend;
+        end if;
+        div <= unsigned(d_in.divisor);
+        quot <= (others => '0');
+        neg_result <= d_in.neg_result;
+        is_modulus <= d_in.is_modulus;
+        extended <= d_in.is_extended;
+        is_32bit <= d_in.is_32bit;
+        is_signed <= d_in.is_signed;
+        count <= "1111111";
+        running <= '1';
+        overflow <= '0';
+        ovf32 <= '0';
+      elsif running = '1' then
+        if count = "0111111" then
+          running <= '0';
+        end if;
+        overflow <= quot(63);
+        if dend(128) = '1' or unsigned(dend(127 downto 64)) >= div then
+          ovf32 <= ovf32 or quot(31);
+          dend <= std_ulogic_vector(unsigned(dend(127 downto 64)) - div) & dend(63 downto 0) & '0';
+          quot <= quot(62 downto 0) & '1';
+          count <= count + 1;
+        elsif dend(128 downto 57) = x"000000000000000000" and count(6 downto 3) /= "0111" then
+          ovf32 <= or(ovf32 & quot(31 downto 24));
+          dend <= dend(120 downto 0) & x"00";
+          quot <= quot(55 downto 0) & x"00";
+          count <= count + 8;
+        else
+          ovf32 <= ovf32 or quot(31);
+          dend <= dend(127 downto 0) & '0';
+          quot <= quot(62 downto 0) & '0';
+          count <= count + 1;
+        end if;
+      else
+        count <= "0000000";
+      end if;
+    end if;
+  end process;
+   
+  divider_1 : process(all)
+  begin
+    if is_modulus = '1' then
+      result <= dend(128 downto 65);
+    else
+      result <= quot;
+    end if;
+    if neg_result = '1' then
+      sresult <= std_ulogic_vector(signed('0' & result));
+    else
+      sresult <= '0' & result;
+    end if;
+    did_ovf <= '0';
+    if is_32bit = '0' then
+      did_ovf <= overflow or (is_signed and (sresult(64) xor sresult(63)));
+    elsif is_signed = '1' then
+      if ovf32 = '1' or sresult(32) /= sresult(31) then
+        did_ovf <= '1';
+      end if;
+    else
+      did_ovf <= ovf32;
+    end if;
+    if did_ovf = '1' then
+      oresult <= (others => '0');
+    elsif (is_32bit = '1') and (is_modulus = '0') then
+      oresult <= x"00000000" & sresult(31 downto 0);
+    else
+      oresult <= sresult(63 downto 0);
+    end if;
+  end process;
+   
+  divider_out : process(clk)
+  begin
+    if rising_edge(clk) then
+      d_out.valid <= '0';
+      d_out.write_reg_data <= oresult;
+      d_out.overflow <= did_ovf;
+      if count = "1000000" then
+        d_out.valid <= '1';
+      end if;
+    end if;
+  end process;
+end behaviour;

data/tests/parser_tests/test_microwatt_divider_tb.vhd

@@ -0,0 +1 @@
+../microwatt/divider_tb.vhdl

data/tests/parser_tests/test_microwatt_divider_tb_pp.vhd

@@ -0,0 +1,95 @@
+-- generated by Vertigo VHDL tool
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.decode_types.all;
+use work.common.all;
+use work.glibc_random.all;
+use work.ppc_fx_insns.all;
+ 
+entity divider_tb is
+end entity divider_tb;
+ 
+architecture behave of divider_tb is
+  signal clk : std_ulogic;
+  signal rst : std_ulogic;
+  constant clk_period : time := 10 ns;
+  signal d1 : execute1todividertype;
+  signal d2 : dividertoexecute1type;
+begin
+ 
+  divider_0 : entity work.divider
+    port map(
+      clk => clk,
+      rst => rst,
+      d_in => d1,
+      d_out => d2);
+   
+   
+  clk_process : process
+  begin
+    clk <= '0';
+    wait clk_period / 2;
+    clk <= '1';
+    wait clk_period / 2;
+  end process;
+   
+  stim_process : process
+    variable ra : std_ulogic_vector(63 downto 0);
+    variable rb : std_ulogic_vector(63 downto 0);
+    variable rt : std_ulogic_vector(63 downto 0);
+    variable behave_rt : std_ulogic_vector(63 downto 0);
+    variable si : std_ulogic_vector(15 downto 0);
+    variable d128 : std_ulogic_vector(127 downto 0);
+    variable q128 : std_ulogic_vector(127 downto 0);
+    variable q64 : std_ulogic_vector(63 downto 0);
+    variable rem32 : std_ulogic_vector(31 downto 0);
+  begin
+    rst <= '1';
+    wait clk_period;
+    rst <= '0';
+    d1.valid <= '1';
+    d1.dividend <= x"0000000010001000";
+    d1.divisor <= x"0000000000001111";
+    d1.is_signed <= '0';
+    d1.is_32bit <= '0';
+    d1.is_extended <= '0';
+    d1.is_modulus <= '0';
+    d1.neg_result <= '0';
+    wait clk_period;
+    assert d2.valid = '0';
+    d1.valid <= '0';
+    assert d2.valid = '1';
+    assert d2.write_reg_data = x"000000000000f001"
+      report "result " & to_hstring(d2.write_reg_data);
+    wait clk_period;
+    assert d2.valid = '0'
+      report "valid";
+    d1.valid <= '1';
+    wait clk_period;
+    assert d2.valid = '0'
+      report "valid";
+    d1.valid <= '0';
+    assert d2.valid = '1';
+    assert d2.write_reg_data = x"000000000000f001"
+      report "result " & to_hstring(d2.write_reg_data);
+    wait clk_period;
+    assert d2.valid = '0';
+    report "test divd";
+    report "test divdu";
+    report "test divde";
+    report "test divdeu";
+    report "test divw";
+    report "test divwu";
+    report "test divwe";
+    report "test divweu";
+    report "test modsd";
+    report "test modud";
+    report "test modsw";
+    report "test moduw";
+    assert false
+      report "end of test" severity failure;
+    wait ;
+  end process;
+end behave;

data/tests/parser_tests/test_microwatt_dmi_dtm_dummy.vhd

@@ -0,0 +1 @@
+../microwatt/dmi_dtm_dummy.vhdl

data/tests/parser_tests/test_microwatt_dmi_dtm_dummy_pp.vhd

@@ -0,0 +1,29 @@
+-- generated by Vertigo VHDL tool
+library ieee;
+use ieee.std_logic_1164.all;
+library work;
+use work.wishbone_types.all;
+ 
+entity dmi_dtm is
+  generic(
+    abits : integer8 := 8;
+    dbits : integer32 := 32);
+  port(
+    sys_clk : in std_ulogic;
+    sys_reset : in std_ulogic;
+    dmi_addr : out std_ulogic_vector(abits - 1 downto 0);
+    dmi_din : in std_ulogic_vector(dbits - 1 downto 0);
+    dmi_dout : out std_ulogic_vector(dbits - 1 downto 0);
+    dmi_req : out std_ulogic;
+    dmi_wr : out std_ulogic;
+    dmi_ack : in std_ulogic);
+end entity dmi_dtm;
+ 
+architecture behaviour of dmi_dtm is
+begin
+ 
+  dmi_addr <= (others => '0');
+  dmi_dout <= (others => '0');
+  dmi_req <= '0';
+  dmi_wr <= '0';
+end behaviour;

data/tests/parser_tests/test_microwatt_dmi_dtm_tb.vhd

@@ -0,0 +1 @@
+../microwatt/dmi_dtm_tb.vhdl

data/tests/parser_tests/test_microwatt_dmi_dtm_tb_pp.vhd

@@ -0,0 +1,197 @@
+-- generated by Vertigo VHDL tool
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.common.all;
+use work.wishbone_types.all;
+library unisim;
+use unisim.vcomponents.all;
+ 
+entity dmi_dtm_tb is
+end entity dmi_dtm_tb;
+ 
+architecture behave of dmi_dtm_tb is
+  signal clk : std_ulogic;
+  signal rst : std_ulogic;
+  constant clk_period : time := 10 ns;
+  constant jclk_period : time := 30 ns;
+  signal dmi_addr : std_ulogic_vector(7 downto 0);
+  signal dmi_din : std_ulogic_vector(63 downto 0);
+  signal dmi_dout : std_ulogic_vector(63 downto 0);
+  signal dmi_req : std_ulogic;
+  signal dmi_wr : std_ulogic;
+  signal dmi_ack : std_ulogic;
+  alias j : glob_jtag_t is glob_jtag ;
+  signal wishbone_ram_in : wishbone_slave_out;
+  signal wishbone_ram_out : wishbone_master_out;
+begin
+ 
+  dtm : entity work.dmi_dtm
+    port map(
+      sys_clk => clk,
+      sys_reset => rst,
+      dmi_addr => dmi_addr,
+      dmi_din => dmi_din,
+      dmi_dout => dmi_dout,
+      dmi_req => dmi_req,
+      dmi_wr => dmi_wr,
+      dmi_ack => dmi_ack);
+   
+  simple_ram_0 : entity work.wishbone_bram_wrapper
+    port map(
+      clk => clk,
+      rst => rst,
+      wishbone_in => wishbone_ram_out,
+      wishbone_out => wishbone_ram_in);
+   
+  wishbone_debug_0 : entity work.wishbone_debug_master
+    port map(
+      clk => clk,
+      rst => rst,
+      dmi_addr => dmi_addr(1 downto 0),
+      dmi_dout => dmi_din,
+      dmi_din => dmi_dout,
+      dmi_wr => dmi_wr,
+      dmi_ack => dmi_ack,
+      dmi_req => dmi_req,
+      wb_in => wishbone_ram_in,
+      wb_out => wishbone_ram_out);
+   
+   
+  sys_clk : process
+  begin
+    clk <= '1';
+    wait clk_period / 2;
+    clk <= '0';
+    wait clk_period / 2;
+  end process;
+   
+  sys_sim : process
+  begin
+    rst <= '1';
+    wait clk_period;
+    rst <= '0';
+    wait ;
+  end process;
+   
+  sim_jtag : process
+     
+    procedure clock(
+      count : in integer) is
+    begin
+      ;
+    end clock;
+     
+    procedure shift_out(
+      val : in std_ulogic_vector) is
+    begin
+      ;
+    end shift_out;
+     
+    procedure shift_in(
+      val : out std_ulogic_vector) is
+    begin
+      ;
+    end shift_in;
+     
+    procedure send_command(
+      addr : in std_ulogic_vector(7 downto 0);
+      data : in std_ulogic_vector(63 downto 0);
+      op : in std_ulogic_vector(1 downto 0)) is
+    begin
+      j.capture <= '1';
+      ()
+      j.capture <= '0';
+      ()
+      j.shift <= '1';
+      ()
+      ()
+      ()
+      j.shift <= '0';
+      j.update <= '1';
+      ()
+      j.update <= '0';
+      ()
+    end send_command;
+     
+    procedure read_resp(
+      op : out std_ulogic_vector(1 downto 0);
+      data : out std_ulogic_vector(63 downto 0)) is
+    #<Vertigo::Variable:0x000055d91bc0f3b0>
+    begin
+      j.capture <= '1';
+      ()
+      j.capture <= '0';
+      ()
+      j.shift <= '1';
+      ()
+      ()
+      ()
+      j.shift <= '0';
+      j.update <= '1';
+      ()
+      j.update <= '0';
+      ()
+    end read_resp;
+     
+    procedure dmi_write(
+      addr : in std_ulogic_vector(7 downto 0);
+      data : in std_ulogic_vector(63 downto 0)) is
+    #<Vertigo::Variable:0x000055d91bc0bc38>
+    #<Vertigo::Variable:0x000055d91bc0b8f0>
+    #<Vertigo::Variable:0x000055d91bc0b5a8>
+    begin
+      ()
+      ;
+    end dmi_write;
+     
+    procedure dmi_read(
+      addr : in std_ulogic_vector(7 downto 0);
+      data : out std_ulogic_vector(63 downto 0)) is
+    #<Vertigo::Variable:0x000055d91bc09190>
+    #<Vertigo::Variable:0x000055d91bc08e48>
+    begin
+      ()
+      ;
+    end dmi_read;
+    variable data : std_ulogic_vector(63 downto 0);
+  begin
+    j.reset <= '1';
+    j.sel <= "0000";
+    j.capture <= '0';
+    j.update <= '0';
+    j.shift <= '0';
+    j.tdi <= '0';
+    j.tms <= '0';
+    j.runtest <= '0';
+    ()
+    j.reset <= '0';
+    ()
+    j.sel <= "0010";
+    ()
+    ()
+    report "read addr reg:" & to_hstring(data);
+    report "writing addr reg to all 1's";
+    ()
+    ()
+    report "read addr reg:" & to_hstring(data);
+    report "writing ctrl reg to all 1's";
+    ()
+    ()
+    report "read ctrl reg:" & to_hstring(data);
+    report "read memory at 0...\n";
+    ()
+    ()
+    ()
+    report "00:" & to_hstring(data);
+    ()
+    report "08:" & to_hstring(data);
+    ()
+    report "10:" & to_hstring(data);
+    ()
+    report "18:" & to_hstring(data);
+    ()
+    ()
+  end process;
+end behave;