vertigo_vhdl 0.8.2

data/tests/parser_tests/test_tb-00_pp.vhd

@@ -0,0 +1,71 @@
+-- generated by Vertigo VHDL tool
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+ 
+entity decoder_tb is
+end entity decoder_tb;
+ 
+architecture tb of decoder_tb is
+  signal t_i : std_logic_vector(1 downto 0) := "00";
+  signal t_o : std_logic_vector(3 downto 0);
+  component decoder is
+    port(
+        i : in std_logic_vector(1 downto 0);
+        o : out std_logic_vector(3 downto 0));
+  end component;
+begin
+ 
+  u_decoder : component decoder
+    port map(
+      t_i,
+      t_o);
+   
+   
+  process
+    variable err_cnt : integer := 0;
+  begin
+    wait 10 ns;
+    t_i <= "00";
+    wait 1 ns;
+    assert (t_o = "0001")
+      report "error case 0" severity error;
+    if (t_o /= "0001") then
+      err_cnt := err_cnt + 1;
+    end if;
+    wait 10 ns;
+    t_i <= "01";
+    wait 1 ns;
+    assert (t_o = "0010")
+      report "error case 1" severity error;
+    if (t_o /= "0010") then
+      err_cnt := err_cnt + 1;
+    end if;
+    wait 10 ns;
+    t_i <= "10";
+    wait 1 ns;
+    assert (t_o = "0100")
+      report "error case 2" severity error;
+    if (t_o /= "0100") then
+      err_cnt := err_cnt + 1;
+    end if;
+    wait 10 ns;
+    t_i <= "11";
+    wait 1 ns;
+    assert (t_o = "1000")
+      report "error case 3" severity error;
+    if (t_o /= "1000") then
+      err_cnt := err_cnt + 1;
+    end if;
+    wait 10 ns;
+    t_i <= "uu";
+    if (err_cnt = 0) then
+      assert false
+        report "testbench of adder completed successfully!" severity note;
+    else
+      assert true
+        report "something wrong, try again" severity error;
+    end if;
+    wait ;
+  end process;
+end tb;

data/tests/parser_tests/test_type_decl_02.vhd

@@ -0,0 +1,9 @@
+entity test is
+end;
+
+architecture test_var of test is
+
+  type TestIt is array(natural range <>) of boolean;
+
+begin
+end test_var;

data/tests/parser_tests/test_type_decl_02_pp.vhd

@@ -0,0 +1,11 @@
+-- generated by Vertigo VHDL tool
+ 
+entity test is
+end entity test;
+ 
+architecture test_var of test is
+   
+  type testit is array(natural range <>) of boolean;
+begin
+ 
+end test_var;

data/tests/parser_tests/test_use.vhd

@@ -0,0 +1,7 @@
+library ieee,std;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.accelerator_pkg.all;
+
+entity test is
+end entity;

data/tests/parser_tests/test_use_pp.vhd

@@ -0,0 +1,10 @@
+-- generated by Vertigo VHDL tool
+library ieee;
+library std;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.accelerator_pkg.all;
+ 
+entity test is
+end entity test;
+ 

data/tests/parser_tests/test_while_1.vhd

@@ -0,0 +1,38 @@
+
+
+architecture test_while of while_tester is
+
+begin  -- test_while
+
+  Clk_1 : process (Clock)
+  begin
+    L1 : loop
+      Clock <= not Clock after 5 ns;
+    end loop L1;
+  end process Clk_1;
+
+  process
+    begin
+    L2 : loop
+      A := A+1;
+      exit L2 when A > 10;
+    end loop L2;
+  end process;
+
+  Shift_3 : process (Input_X)
+    variable i : positive := 1;
+  begin
+    L3 : while i <= 8 loop
+      Output_X(i) <= Input_X(i+8) after 5 ns;
+      i           := i + 1;
+    end loop L3;
+  end process Shift_3;
+
+  Shift_4 : process (Input_X)
+  begin
+    L4 : for count_value in 1 to 8 loop
+      Output_X(count_value) <= Input_X(count_value + 8) after 5 ns;
+    end loop L4;
+  end process Shift_4;
+
+end test_while;

data/tests/parser_tests/test_while_1_pp.vhd

@@ -0,0 +1,26 @@
+-- generated by Vertigo VHDL tool
+architecture test_while of while_tester is
+begin
+ 
+   
+  clk_1 : process(clock)
+  begin
+    ;
+  end process;
+   
+  process
+  begin
+    ;
+  end process;
+   
+  shift_3 : process(input_x)
+    variable i : positive := 1;
+  begin
+    ;
+  end process;
+   
+  shift_4 : process(input_x)
+  begin
+    ;
+  end process;
+end test_while;

data/tests/parser_tests/test_with-00.vhd

@@ -0,0 +1,21 @@
+
+
+architecture flow of ttimer is
+
+begin
+
+ with s_sum select
+ dig_sig1 <= "10000001" when 0,
+    "11001111"  when 1,
+    "10010010"  when 2,
+    "10000110" when 3,
+    "10000100" when 59;
+
+ dig_sig0 <= "10000001" when s_sum >= 0  and s_sum <= 9  else
+    "11001111"  when s_sum >=10  and s_sum <= 19 else
+    "10010010"  when s_sum >=20  and s_sum <= 29 else
+    "10000110" when s_sum >=30  and s_sum <= 39 else
+    "11001100" when s_sum >=40  and s_sum <= 49 else
+    "10100100" ;
+
+end flow;

data/tests/parser_tests/test_with-00_pp.vhd

@@ -0,0 +1,12 @@
+-- generated by Vertigo VHDL tool
+architecture flow of ttimer is
+begin
+ 
+  with s_sum select dig_sig1 <=
+    "10000001" when 0,
+    "11001111" when 1,
+    "10010010" when 2,
+    "10000110" when 3,
+    "10000100" when 59,;
+  dig_sig0 <= "10000001" when s_sum >= 0 and s_sum <= 9 else "11001111" when s_sum >= 10 and s_sum <= 19 else "10010010" when s_sum >= 20 and s_sum <= 29 else "10000110" when s_sum >= 30 and s_sum <= 39 else "11001100" when s_sum >= 40 and s_sum <= 49 else  "10100100";
+end flow;

data/tests/tb_gen_tests/test_accelerator.vhd

@@ -0,0 +1,160 @@
+library ieee,std;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.accelerator_pkg.all;
+
+entity accelerator is
+  port(
+    clock          : in  std_logic;
+    reset_n      : in  std_logic;
+    bus_addr     : in  std_logic_vector(31 downto 0);
+    bus_data_p2a : in  std_logic_vector(31 downto 0);
+    bus_data_a2p : out std_logic_vector(31 downto 0);
+    bus_rd       : in  std_logic;
+    bus_wr       : in  std_logic
+    );
+end accelerator;
+
+architecture rtl of accelerator is
+
+  type regs_t is record
+    a, b, res : std_logic_vector(31 downto 0);
+    ctrl      : std_logic;
+    status    : std_logic_vector(1 downto 0);  --busy,done
+  end record;
+
+  constant INIT_REGS : regs_t := (
+    (others => '0'),
+    (others => '0'),
+    (others => '0'),
+    '0',
+    "00"
+    );
+
+  signal ifregs : regs_t;
+
+  type   state_t is (idle, running);
+  signal state, state_c : state_t;
+
+  type vars_t is record
+    go   : std_logic;
+    a, b : unsigned(31 downto 0);
+    done : std_logic;
+  end record;
+
+  -- constant VARS_INIT : vars_t := (
+  --   '0',
+  --   to_unsigned(0, 32),
+  --   to_unsigned(0, 32),
+  --   '0');
+
+  signal vars, vars_c : vars_t;
+
+begin
+  --========================================
+  -- Bus interface
+  --========================================
+  bus_wr_proc : process(clk, reset_n)
+  begin
+    if reset_n = '0' then
+      ifregs <= INIT_REGS;
+    elsif rising_edge(clk) then
+      ifregs.ctrl <= '0';                               --autoreset
+      if bus_wr = '1' then
+        case bus_addr is
+          when ADDR_A =>
+            ifregs.a <= bus_data_p2a;
+          when ADDR_B =>
+            ifregs.b <= bus_data_p2a;
+          when ADDR_CTRL =>
+            ifregs.ctrl <= bus_data_p2a(0);             --write/clear a go
+          when ADDR_STATUS =>
+            ifregs.status <= bus_data_p2a(1 downto 0);  --clear rdy
+          when others => null;
+        end case;
+      elsif vars.done = '1' then
+        ifregs.res       <= std_logic_vector(vars.a);  --BUG : vars.a ne passait pas
+                                                       --=> FIX lexer : selected_name
+        --ifregs.status(0) <= vars.done;  --BUG : (0) ne passe pas
+        ifregs.status <= vars.done;  --BUG : (0) ne passe pas
+      end if;
+    end if;
+  end process;
+
+  bus_rd_proc : process(reset_n, clk)
+  begin
+    if reset_n = '0' then
+      bus_data_a2p <= (others => '0');
+    elsif rising_edge(clk) then
+      if bus_rd = '1' then
+        case bus_addr is
+          when ADDR_A =>
+            bus_data_a2p <= ifregs.a;
+          when ADDR_B =>
+            bus_data_a2p <= ifregs.b;
+          when ADDR_CTRL =>
+            null;
+            --bus_data_a2p <= X"0000000" & "000" & ifregs.ctrl;  --write/clear a go
+          when ADDR_STATUS =>
+            null;
+            bus_data_a2p <= X"0000000" & "00" & ifregs.status;
+          when ADDR_RES =>
+            bus_data_a2p <= ifregs.res;
+          when others => null;
+        end case;
+      end if;
+    end if;
+  end process;
+
+--=============================================
+-- BUG
+--=============================================
+
+  reg : process(clk, reset_n)
+  begin
+    if reset_n = '0' then
+      state <= idle;
+      vars  <= VARS_INIT;
+    elsif rising_edge(clk) then
+      state <= state_c;
+      vars  <= vars_c;
+      if ifregs.ctrl = '1' then
+        vars.a  <= unsigned(ifregs.a);
+        vars.b  <= unsigned(ifregs.b);
+        vars.go <= '1';
+      end if;
+    end if;
+  end process;
+
+  comb : process (state, vars)
+    variable state_v : state_t;
+    variable vars_v  : vars_t;
+  begin
+    state_v := state;
+    vars_v  := vars;
+    case state_v is
+      when idle =>
+        if vars_v.go = '1' then
+          state_v   := running;
+          vars_v.go := '0';
+        else
+          vars_v := VARS_INIT;
+        end if;
+      when running =>
+        if vars_v.a /= vars_v.b then
+          if vars_v.a > vars_v.b then
+            vars_v.a := vars_v.a-vars_v.b;
+          else
+            vars_v.b := vars_v.b-vars_v.a;
+          end if;
+        else
+          vars_v.done := '1';
+          state_v     := idle;
+        end if;
+      when others => null;
+    end case;
+    state_c <= state_v;
+    vars_c  <= vars_v;
+  end process;
+
+end rtl;

metadata

@@ -0,0 +1,224 @@
+--- !ruby/object:Gem::Specification
+name: vertigo_vhdl
+version: !ruby/object:Gem::Version
+  version: 0.8.2
+platform: ruby
+authors:
+- Jean-Christophe Le Lann
+autorequire: 
+bindir: bin
+cert_chain: []
+date: 2020-05-04 00:00:00.000000000 Z
+dependencies: []
+description: A Ruby handwritten VHDL parser and utilities
+email: jean-christophe.le_lann@ensta-bretagne.fr
+executables:
+- vertigo
+extensions: []
+extra_rdoc_files: []
+files:
+- bin/vertigo
+- lib/vertigo.rb
+- lib/vertigo/ast.rb
+- lib/vertigo/ast_vertigo_rkgen.rb
+- lib/vertigo/code.rb
+- lib/vertigo/compiler.rb
+- lib/vertigo/generic_lexer.rb
+- lib/vertigo/generic_parser.rb
+- lib/vertigo/indent.rb
+- lib/vertigo/lexer.rb
+- lib/vertigo/parser.rb
+- lib/vertigo/pretty_printer.rb
+- lib/vertigo/runner.rb
+- lib/vertigo/tb_generator.rb
+- lib/vertigo/template.tb.vhd
+- lib/vertigo/token.rb
+- lib/vertigo/version.rb
+- lib/vertigo/vertigo.rkg
+- lib/vertigo/visitor_vertigo_rkgen.rb
+- tests/ghdl_tests/fsm.vhd
+- tests/ghdl_tests/fsm_synth.vhd
+- tests/ghdl_tests/test_fsm.vhd
+- tests/parser_tests/else.vhd
+- tests/parser_tests/test_MUST_fail.vhd
+- tests/parser_tests/test_accelerator.vhd
+- tests/parser_tests/test_accelerator_pp.vhd
+- tests/parser_tests/test_aggregate.vhd
+- tests/parser_tests/test_aggregate_pp.vhd
+- tests/parser_tests/test_archi_1.vhd
+- tests/parser_tests/test_archi_1_pp.vhd
+- tests/parser_tests/test_array_array_00.vhd
+- tests/parser_tests/test_array_array_00_pp.vhd
+- tests/parser_tests/test_array_urange.vhd
+- tests/parser_tests/test_array_urange_pp.vhd
+- tests/parser_tests/test_chu-1.vhd
+- tests/parser_tests/test_chu-1_pp.vhd
+- tests/parser_tests/test_concat.vhd
+- tests/parser_tests/test_concat_pp.vhd
+- tests/parser_tests/test_counter.vhd
+- tests/parser_tests/test_counter_pp.vhd
+- tests/parser_tests/test_de2.vhd
+- tests/parser_tests/test_de2_pp.vhd
+- tests/parser_tests/test_encode.vhd
+- tests/parser_tests/test_encode_pp.vhd
+- tests/parser_tests/test_fsm.vhd
+- tests/parser_tests/test_fsm_pp.vhd
+- tests/parser_tests/test_fsm_synth.vhd
+- tests/parser_tests/test_fsm_synth_pp.vhd
+- tests/parser_tests/test_function-01.vhd
+- tests/parser_tests/test_function-01_pp.vhd
+- tests/parser_tests/test_lfsr.vhd
+- tests/parser_tests/test_lfsr_pp.vhd
+- tests/parser_tests/test_microwatt_cache_ram.vhd
+- tests/parser_tests/test_microwatt_cache_ram_pp.vhd
+- tests/parser_tests/test_microwatt_common.vhd
+- tests/parser_tests/test_microwatt_common_pp.vhd
+- tests/parser_tests/test_microwatt_control.vhd
+- tests/parser_tests/test_microwatt_control_pp.vhd
+- tests/parser_tests/test_microwatt_core.vhd
+- tests/parser_tests/test_microwatt_core_debug.vhd
+- tests/parser_tests/test_microwatt_core_debug_pp.vhd
+- tests/parser_tests/test_microwatt_core_pp.vhd
+- tests/parser_tests/test_microwatt_core_tb.vhd
+- tests/parser_tests/test_microwatt_core_tb_pp.vhd
+- tests/parser_tests/test_microwatt_countzero.vhd
+- tests/parser_tests/test_microwatt_countzero_pp.vhd
+- tests/parser_tests/test_microwatt_countzero_tb.vhd
+- tests/parser_tests/test_microwatt_countzero_tb_pp.vhd
+- tests/parser_tests/test_microwatt_cr_file.vhd
+- tests/parser_tests/test_microwatt_cr_file_pp.vhd
+- tests/parser_tests/test_microwatt_cr_hazard.vhd
+- tests/parser_tests/test_microwatt_cr_hazard_pp.vhd
+- tests/parser_tests/test_microwatt_crhelpers.vhd
+- tests/parser_tests/test_microwatt_crhelpers_pp.vhd
+- tests/parser_tests/test_microwatt_dcache.vhd
+- tests/parser_tests/test_microwatt_dcache_pp.vhd
+- tests/parser_tests/test_microwatt_dcache_tb.vhd
+- tests/parser_tests/test_microwatt_dcache_tb_pp.vhd
+- tests/parser_tests/test_microwatt_decode1.vhd
+- tests/parser_tests/test_microwatt_decode1_pp.vhd
+- tests/parser_tests/test_microwatt_decode2.vhd
+- tests/parser_tests/test_microwatt_decode2_pp.vhd
+- tests/parser_tests/test_microwatt_decode_types.vhd
+- tests/parser_tests/test_microwatt_decode_types_pp.vhd
+- tests/parser_tests/test_microwatt_divider.vhd
+- tests/parser_tests/test_microwatt_divider_pp.vhd
+- tests/parser_tests/test_microwatt_divider_tb.vhd
+- tests/parser_tests/test_microwatt_divider_tb_pp.vhd
+- tests/parser_tests/test_microwatt_dmi_dtm_dummy.vhd
+- tests/parser_tests/test_microwatt_dmi_dtm_dummy_pp.vhd
+- tests/parser_tests/test_microwatt_dmi_dtm_tb.vhd
+- tests/parser_tests/test_microwatt_dmi_dtm_tb_pp.vhd
+- tests/parser_tests/test_microwatt_dmi_dtm_xilinx.vhd
+- tests/parser_tests/test_microwatt_dmi_dtm_xilinx_pp.vhd
+- tests/parser_tests/test_microwatt_execute1.vhd
+- tests/parser_tests/test_microwatt_execute1_pp.vhd
+- tests/parser_tests/test_microwatt_fetch1.vhd
+- tests/parser_tests/test_microwatt_fetch1_pp.vhd
+- tests/parser_tests/test_microwatt_fetch2.vhd
+- tests/parser_tests/test_microwatt_fetch2_pp.vhd
+- tests/parser_tests/test_microwatt_glibc_random.vhd
+- tests/parser_tests/test_microwatt_glibc_random_helpers.vhd
+- tests/parser_tests/test_microwatt_glibc_random_helpers_pp.vhd
+- tests/parser_tests/test_microwatt_glibc_random_pp.vhd
+- tests/parser_tests/test_microwatt_gpr_hazard.vhd
+- tests/parser_tests/test_microwatt_gpr_hazard_pp.vhd
+- tests/parser_tests/test_microwatt_helpers.vhd
+- tests/parser_tests/test_microwatt_helpers_pp.vhd
+- tests/parser_tests/test_microwatt_icache.vhd
+- tests/parser_tests/test_microwatt_icache_pp.vhd
+- tests/parser_tests/test_microwatt_icache_tb.vhd
+- tests/parser_tests/test_microwatt_icache_tb_pp.vhd
+- tests/parser_tests/test_microwatt_insn_helpers.vhd
+- tests/parser_tests/test_microwatt_insn_helpers_pp.vhd
+- tests/parser_tests/test_microwatt_loadstore1.vhd
+- tests/parser_tests/test_microwatt_loadstore1_pp.vhd
+- tests/parser_tests/test_microwatt_logical.vhd
+- tests/parser_tests/test_microwatt_logical_pp.vhd
+- tests/parser_tests/test_microwatt_multiply.vhd
+- tests/parser_tests/test_microwatt_multiply_pp.vhd
+- tests/parser_tests/test_microwatt_multiply_tb.vhd
+- tests/parser_tests/test_microwatt_multiply_tb_pp.vhd
+- tests/parser_tests/test_microwatt_plru.vhd
+- tests/parser_tests/test_microwatt_plru_pp.vhd
+- tests/parser_tests/test_microwatt_plru_tb.vhd
+- tests/parser_tests/test_microwatt_plru_tb_pp.vhd
+- tests/parser_tests/test_microwatt_ppc_fx_insns.vhd
+- tests/parser_tests/test_microwatt_ppc_fx_insns_pp.vhd
+- tests/parser_tests/test_microwatt_register_file.vhd
+- tests/parser_tests/test_microwatt_register_file_pp.vhd
+- tests/parser_tests/test_microwatt_rotator.vhd
+- tests/parser_tests/test_microwatt_rotator_pp.vhd
+- tests/parser_tests/test_microwatt_rotator_tb.vhd
+- tests/parser_tests/test_microwatt_rotator_tb_pp.vhd
+- tests/parser_tests/test_microwatt_sim_bram.vhd
+- tests/parser_tests/test_microwatt_sim_bram_helpers.vhd
+- tests/parser_tests/test_microwatt_sim_bram_helpers_pp.vhd
+- tests/parser_tests/test_microwatt_sim_bram_pp.vhd
+- tests/parser_tests/test_microwatt_sim_console.vhd
+- tests/parser_tests/test_microwatt_sim_console_pp.vhd
+- tests/parser_tests/test_microwatt_sim_jtag.vhd
+- tests/parser_tests/test_microwatt_sim_jtag_pp.vhd
+- tests/parser_tests/test_microwatt_sim_jtag_socket.vhd
+- tests/parser_tests/test_microwatt_sim_jtag_socket_pp.vhd
+- tests/parser_tests/test_microwatt_sim_uart.vhd
+- tests/parser_tests/test_microwatt_sim_uart_pp.vhd
+- tests/parser_tests/test_microwatt_soc.vhd
+- tests/parser_tests/test_microwatt_soc_pp.vhd
+- tests/parser_tests/test_microwatt_utils.vhd
+- tests/parser_tests/test_microwatt_utils_pp.vhd
+- tests/parser_tests/test_microwatt_wishbone_arbiter.vhd
+- tests/parser_tests/test_microwatt_wishbone_arbiter_pp.vhd
+- tests/parser_tests/test_microwatt_wishbone_bram_tb.vhd
+- tests/parser_tests/test_microwatt_wishbone_bram_tb_pp.vhd
+- tests/parser_tests/test_microwatt_wishbone_bram_wrapper.vhd
+- tests/parser_tests/test_microwatt_wishbone_bram_wrapper_pp.vhd
+- tests/parser_tests/test_microwatt_wishbone_debug_master.vhd
+- tests/parser_tests/test_microwatt_wishbone_debug_master_pp.vhd
+- tests/parser_tests/test_microwatt_wishbone_types.vhd
+- tests/parser_tests/test_microwatt_wishbone_types_pp.vhd
+- tests/parser_tests/test_microwatt_writeback.vhd
+- tests/parser_tests/test_microwatt_writeback_pp.vhd
+- tests/parser_tests/test_package-1.vhd
+- tests/parser_tests/test_package-1_pp.vhd
+- tests/parser_tests/test_precedence.vhd
+- tests/parser_tests/test_precedence_pp.vhd
+- tests/parser_tests/test_selected_sig.vhd
+- tests/parser_tests/test_selected_sig_pp.vhd
+- tests/parser_tests/test_slice.vhd
+- tests/parser_tests/test_slice_pp.vhd
+- tests/parser_tests/test_tb-00.vhd
+- tests/parser_tests/test_tb-00_pp.vhd
+- tests/parser_tests/test_type_decl_02.vhd
+- tests/parser_tests/test_type_decl_02_pp.vhd
+- tests/parser_tests/test_use.vhd
+- tests/parser_tests/test_use_pp.vhd
+- tests/parser_tests/test_while_1.vhd
+- tests/parser_tests/test_while_1_pp.vhd
+- tests/parser_tests/test_with-00.vhd
+- tests/parser_tests/test_with-00_pp.vhd
+- tests/tb_gen_tests/test_accelerator.vhd
+homepage: http://www.github.com/JC-LL/vertigo
+licenses:
+- GPL-2.0-only
+metadata: {}
+post_install_message: 
+rdoc_options: []
+require_paths:
+- lib
+required_ruby_version: !ruby/object:Gem::Requirement
+  requirements:
+  - - ">="
+    - !ruby/object:Gem::Version
+      version: '0'
+required_rubygems_version: !ruby/object:Gem::Requirement
+  requirements:
+  - - ">="
+    - !ruby/object:Gem::Version
+      version: '0'
+requirements: []
+rubygems_version: 3.0.6
+signing_key: 
+specification_version: 4
+summary: VHDL parser and utilities
+test_files: []