vertigo_vhdl 0.8.2

data/tests/parser_tests/test_microwatt_core.vhd

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+../microwatt/core.vhdl

data/tests/parser_tests/test_microwatt_core_debug.vhd

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+../microwatt/core_debug.vhdl

data/tests/parser_tests/test_microwatt_core_debug_pp.vhd

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+-- generated by Vertigo VHDL tool
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.common.all;
+ 
+entity core_debug is
+  port(
+    clk : in std_logic;
+    rst : in std_logic;
+    dmi_addr : in std_ulogic_vector(3 downto 0);
+    dmi_din : in std_ulogic_vector(63 downto 0);
+    dmi_dout : out std_ulogic_vector(63 downto 0);
+    dmi_req : in std_ulogic;
+    dmi_wr : in std_ulogic;
+    dmi_ack : out std_ulogic;
+    core_stop : out std_ulogic;
+    core_rst : out std_ulogic;
+    icache_rst : out std_ulogic;
+    terminate : in std_ulogic;
+    core_stopped : in std_ulogic;
+    nia : in std_ulogic_vector(63 downto 0);
+    terminated_out : out std_ulogic);
+end entity core_debug;
+ 
+architecture behave of core_debug is
+  signal dmi_req_1 : std_ulogic;
+  constant dbg_core_ctrl : std_ulogic_vector(3 downto 0) := "0000";
+  constant dbg_core_ctrl_stop : integer := 0;
+  constant dbg_core_ctrl_reset : integer := 1;
+  constant dbg_core_ctrl_icreset : integer := 2;
+  constant dbg_core_ctrl_step : integer := 3;
+  constant dbg_core_ctrl_start : integer := 4;
+  constant dbg_core_stat : std_ulogic_vector(3 downto 0) := "0001";
+  constant dbg_core_stat_stopping : integer := 0;
+  constant dbg_core_stat_stopped : integer := 1;
+  constant dbg_core_stat_term : integer := 2;
+  constant dbg_core_nia : std_ulogic_vector(3 downto 0) := "0010";
+  signal stat_reg : std_ulogic_vector(63 downto 0);
+  signal stopping : std_ulogic;
+  signal do_step : std_ulogic;
+  signal do_reset : std_ulogic;
+  signal do_icreset : std_ulogic;
+  signal terminated : std_ulogic;
+begin
+ 
+  dmi_ack <= dmi_req;
+  stat_reg <= (2 => terminated,1 => core_stopped,0 => stopping,others => '0');
+  with dmi_addr select dmi_dout <=
+    stat_reg when dbg_core_stat,
+    nia when dbg_core_nia,
+    (others => '0') when others,;
+   
+  reg_write : process(clk)
+  begin
+    if rising_edge(clk) then
+      do_step <= '0';
+      do_reset <= '0';
+      do_icreset <= '0';
+      if (rst) then
+        stopping <= '0';
+        terminated <= '0';
+      else
+        dmi_req_1 <= dmi_req;
+        if dmi_req = '1' and dmi_req_1 = '0' then
+          if dmi_wr = '1' then
+            report ("dmi write to " & to_hstring(dmi_addr));
+            if dmi_addr = dbg_core_ctrl then
+              if dmi_din(dbg_core_ctrl_reset) = '1' then
+                do_reset <= '1';
+                terminated <= '0';
+              end if;
+              if dmi_din(dbg_core_ctrl_stop) = '1' then
+                stopping <= '1';
+              end if;
+              if dmi_din(dbg_core_ctrl_step) = '1' then
+                do_step <= '1';
+                terminated <= '0';
+              end if;
+              if dmi_din(dbg_core_ctrl_icreset) = '1' then
+                do_icreset <= '1';
+              end if;
+              if dmi_din(dbg_core_ctrl_start) = '1' then
+                stopping <= '0';
+                terminated <= '0';
+              end if;
+            end if;
+          else
+            report ("dmi read from " & to_string(dmi_addr));
+          end if;
+        end if;
+        if terminate = '1' then
+          stopping <= '1';
+          terminated <= '1';
+        end if;
+      end if;
+    end if;
+  end process;
+  core_stop <= stopping and do_step;
+  core_rst <= do_reset;
+  icache_rst <= do_icreset;
+  terminated_out <= terminated;
+end behave;

data/tests/parser_tests/test_microwatt_core_pp.vhd

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+-- generated by Vertigo VHDL tool
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.common.all;
+use work.wishbone_types.all;
+ 
+entity core is
+  generic(
+    sim : booleanfalse := false;
+    disable_flatten : booleanfalse := false;
+    ex1_bypass : booleantrue := true);
+  port(
+    clk : in std_logic;
+    rst : in std_logic;
+    wishbone_insn_in : in wishbone_slave_out;
+    wishbone_insn_out : out wishbone_master_out;
+    wishbone_data_in : in wishbone_slave_out;
+    wishbone_data_out : out wishbone_master_out;
+    dmi_addr : in std_ulogic_vector(3 downto 0);
+    dmi_din : in std_ulogic_vector(63 downto 0);
+    dmi_dout : out std_ulogic_vector(63 downto 0);
+    dmi_req : in std_ulogic;
+    dmi_wr : in std_ulogic;
+    dmi_ack : out std_ulogic;
+    terminated_out : out std_logic);
+end entity core;
+ 
+architecture behave of core is
+  signal fetch2_to_decode1 : fetch2todecode1type;
+  signal fetch1_to_icache : fetch1toicachetype;
+  signal icache_to_fetch2 : icachetofetch2type;
+  signal decode1_to_decode2 : decode1todecode2type;
+  signal decode2_to_execute1 : decode2toexecute1type;
+  signal register_file_to_decode2 : registerfiletodecode2type;
+  signal decode2_to_register_file : decode2toregisterfiletype;
+  signal writeback_to_register_file : writebacktoregisterfiletype;
+  signal decode2_to_cr_file : decode2tocrfiletype;
+  signal cr_file_to_decode2 : crfiletodecode2type;
+  signal writeback_to_cr_file : writebacktocrfiletype;
+  signal execute1_to_writeback : execute1towritebacktype;
+  signal execute1_to_fetch1 : execute1tofetch1type;
+  signal execute1_to_loadstore1 : execute1toloadstore1type;
+  signal loadstore1_to_writeback : loadstore1towritebacktype;
+  signal loadstore1_to_dcache : loadstore1todcachetype;
+  signal dcache_to_loadstore1 : dcachetoloadstore1type;
+  signal fetch1_stall_in : std_ulogic;
+  signal icache_stall_out : std_ulogic;
+  signal fetch2_stall_in : std_ulogic;
+  signal decode1_stall_in : std_ulogic;
+  signal decode2_stall_in : std_ulogic;
+  signal decode2_stall_out : std_ulogic;
+  signal ex1_icache_inval : std_ulogic;
+  signal ex1_stall_out : std_ulogic;
+  signal ls1_stall_out : std_ulogic;
+  signal dcache_stall_out : std_ulogic;
+  signal flush : std_ulogic;
+  signal complete : std_ulogic;
+  signal terminate : std_ulogic;
+  signal core_rst : std_ulogic;
+  signal icache_rst : std_ulogic;
+  signal sim_cr_dump : std_ulogic;
+  signal dbg_core_stop : std_ulogic;
+  signal dbg_core_rst : std_ulogic;
+  signal dbg_icache_rst : std_ulogic;
+  signal dbg_core_is_stopped : std_ulogic;
+   
+  function keep_h(disable : boolean) return string is
+  begin
+    if disable then
+      return "yes";
+    else
+      return "no";
+    end if;
+  end function keep_h;
+  attribute keep_hierarchy : string;
+  attribute keep_hierarchy of fetch1_0 : label is keep_h(disable_flatten);
+  attribute keep_hierarchy of icache_0 : label is keep_h(disable_flatten);
+  attribute keep_hierarchy of fetch2_0 : label is keep_h(disable_flatten);
+  attribute keep_hierarchy of decode1_0 : label is keep_h(disable_flatten);
+  attribute keep_hierarchy of decode2_0 : label is keep_h(disable_flatten);
+  attribute keep_hierarchy of register_file_0 : label is keep_h(disable_flatten);
+  attribute keep_hierarchy of cr_file_0 : label is keep_h(disable_flatten);
+  attribute keep_hierarchy of execute1_0 : label is keep_h(disable_flatten);
+  attribute keep_hierarchy of loadstore1_0 : label is keep_h(disable_flatten);
+  attribute keep_hierarchy of dcache_0 : label is keep_h(disable_flatten);
+  attribute keep_hierarchy of writeback_0 : label is keep_h(disable_flatten);
+  attribute keep_hierarchy of debug_0 : label is keep_h(disable_flatten);
+begin
+ 
+  core_rst <= dbg_core_rst or rst;
+  fetch1_0 : entity work.fetch1
+    port map(
+      clk => clk,
+      rst => core_rst,
+      stall_in => fetch1_stall_in,
+      flush_in => flush,
+      stop_in => dbg_core_stop,
+      e_in => execute1_to_fetch1,
+      i_out => fetch1_to_icache);
+   
+  fetch1_stall_in <= icache_stall_out or decode2_stall_out;
+  icache_0 : entity work.icache
+    port map(
+      clk => clk,
+      rst => icache_rst,
+      i_in => fetch1_to_icache,
+      i_out => icache_to_fetch2,
+      flush_in => flush,
+      stall_out => icache_stall_out,
+      wishbone_out => wishbone_insn_out,
+      wishbone_in => wishbone_insn_in);
+   
+  icache_rst <= rst or dbg_icache_rst or ex1_icache_inval;
+  fetch2_0 : entity work.fetch2
+    port map(
+      clk => clk,
+      rst => core_rst,
+      stall_in => fetch2_stall_in,
+      flush_in => flush,
+      i_in => icache_to_fetch2,
+      f_out => fetch2_to_decode1);
+   
+  fetch2_stall_in <= decode2_stall_out;
+  decode1_0 : entity work.decode1
+    port map(
+      clk => clk,
+      rst => core_rst,
+      stall_in => decode1_stall_in,
+      flush_in => flush,
+      f_in => fetch2_to_decode1,
+      d_out => decode1_to_decode2);
+   
+  decode1_stall_in <= decode2_stall_out;
+  decode2_0 : entity work.decode2
+    port map(
+      clk => clk,
+      rst => core_rst,
+      stall_in => decode2_stall_in,
+      stall_out => decode2_stall_out,
+      flush_in => flush,
+      complete_in => complete,
+      stopped_out => dbg_core_is_stopped,
+      d_in => decode1_to_decode2,
+      e_out => decode2_to_execute1,
+      r_in => register_file_to_decode2,
+      r_out => decode2_to_register_file,
+      c_in => cr_file_to_decode2,
+      c_out => decode2_to_cr_file);
+   
+  decode2_stall_in <= ex1_stall_out or ls1_stall_out;
+  register_file_0 : entity work.register_file
+    port map(
+      clk => clk,
+      d_in => decode2_to_register_file,
+      d_out => register_file_to_decode2,
+      w_in => writeback_to_register_file,
+      sim_dump => terminate,
+      sim_dump_done => sim_cr_dump);
+   
+  cr_file_0 : entity work.cr_file
+    port map(
+      clk => clk,
+      d_in => decode2_to_cr_file,
+      d_out => cr_file_to_decode2,
+      w_in => writeback_to_cr_file,
+      sim_dump => sim_cr_dump);
+   
+  execute1_0 : entity work.execute1
+    port map(
+      clk => clk,
+      rst => core_rst,
+      flush_out => flush,
+      stall_out => ex1_stall_out,
+      e_in => decode2_to_execute1,
+      l_out => execute1_to_loadstore1,
+      f_out => execute1_to_fetch1,
+      e_out => execute1_to_writeback,
+      icache_inval => ex1_icache_inval,
+      terminate_out => terminate);
+   
+  loadstore1_0 : entity work.loadstore1
+    port map(
+      clk => clk,
+      rst => core_rst,
+      l_in => execute1_to_loadstore1,
+      l_out => loadstore1_to_writeback,
+      d_out => loadstore1_to_dcache,
+      d_in => dcache_to_loadstore1,
+      dc_stall => dcache_stall_out,
+      stall_out => ls1_stall_out);
+   
+  dcache_0 : entity work.dcache
+    port map(
+      clk => clk,
+      rst => core_rst,
+      d_in => loadstore1_to_dcache,
+      d_out => dcache_to_loadstore1,
+      stall_out => dcache_stall_out,
+      wishbone_in => wishbone_data_in,
+      wishbone_out => wishbone_data_out);
+   
+  writeback_0 : entity work.writeback
+    port map(
+      clk => clk,
+      e_in => execute1_to_writeback,
+      l_in => loadstore1_to_writeback,
+      w_out => writeback_to_register_file,
+      c_out => writeback_to_cr_file,
+      complete_out => complete);
+   
+  debug_0 : entity work.core_debug
+    port map(
+      clk => clk,
+      rst => rst,
+      dmi_addr => dmi_addr,
+      dmi_din => dmi_din,
+      dmi_dout => dmi_dout,
+      dmi_req => dmi_req,
+      dmi_wr => dmi_wr,
+      dmi_ack => dmi_ack,
+      core_stop => dbg_core_stop,
+      core_rst => dbg_core_rst,
+      icache_rst => dbg_icache_rst,
+      terminate => terminate,
+      core_stopped => dbg_core_is_stopped,
+      nia => fetch1_to_icache.nia,
+      terminated_out => terminated_out);
+   
+end behave;

data/tests/parser_tests/test_microwatt_core_tb.vhd

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+../microwatt/core_tb.vhdl

data/tests/parser_tests/test_microwatt_core_tb_pp.vhd

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+-- generated by Vertigo VHDL tool
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.common.all;
+use work.wishbone_types.all;
+ 
+entity core_tb is
+end entity core_tb;
+ 
+architecture behave of core_tb is
+  signal clk : std_logic;
+  signal rst : std_logic;
+  constant clk_period : time := 10 ns;
+begin
+ 
+  soc0 : entity work.soc
+    port map(
+      rst => rst,
+      system_clk => clk,
+      uart0_rxd => '0',
+      uart0_txd => open);
+   
+   
+  clk_process : process
+  begin
+    clk <= '0';
+    wait clk_period / 2;
+    clk <= '1';
+    wait clk_period / 2;
+  end process;
+   
+  rst_process : process
+  begin
+    rst <= '1';
+    wait 10 * clk_period;
+    rst <= '0';
+    wait ;
+  end process;
+  jtag : entity work.sim_jtag
+   
+end behave;

data/tests/parser_tests/test_microwatt_countzero.vhd

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+../microwatt/countzero.vhdl

data/tests/parser_tests/test_microwatt_countzero_pp.vhd

@@ -0,0 +1,120 @@
+-- generated by Vertigo VHDL tool
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+ 
+entity zero_counter is
+  port(
+    clk : in std_logic;
+    rs : in std_ulogic_vector(63 downto 0);
+    count_right : in std_ulogic;
+    is_32bit : in std_ulogic;
+    result : out std_ulogic_vector(63 downto 0));
+end entity zero_counter;
+ 
+architecture behaviour of zero_counter is
+   
+  type intermediate_result is record
+    v16 : std_ulogic_vector(15 downto 0);
+    sel_hi : std_ulogic_vector(1 downto 0);
+    is_32bit : std_ulogic;
+    count_right : std_ulogic;
+  end record;
+  signal r : intermediate_result;
+  signal r_in : intermediate_result;
+   
+  function encoder(v : std_ulogic_vector(3 downto 0);right : std_ulogic) return std_ulogic_vector is
+  begin
+    if right = '0' then
+      if v(3) = '1' then
+        return "11";
+      elsif v(2) = '1' then
+        return "10";
+      elsif v(1) = '1' then
+        return "01";
+      else
+        return "00";
+      end if;
+    else
+      if v(0) = '1' then
+        return "00";
+      elsif v(1) = '1' then
+        return "01";
+      elsif v(2) = '1' then
+        return "10";
+      else
+        return "11";
+      end if;
+    end if;
+  end function encoder;
+begin
+ 
+   
+  zerocounter_0 : process(clk)
+  begin
+    if rising_edge(clk) then
+      r <= r_in;
+    end if;
+  end process;
+   
+  zerocounter_1 : process(all)
+    variable v : intermediate_result;
+    variable y : std_ulogic_vector(3 downto 0);
+    variable z : std_ulogic_vector(3 downto 0);
+    variable sel : std_ulogic_vector(5 downto 0);
+    variable v4 : std_ulogic_vector(3 downto 0);
+  begin
+    z(0) := or(rs(15 downto 0));
+    z(1) := or(rs(31 downto 16));
+    z(2) := or(rs(47 downto 32));
+    z(3) := or(rs(63 downto 48));
+    if is_32bit = '0' then
+      v.sel_hi := encoder(z,count_right);
+    else
+      v.sel_hi(1) := '0';
+      if count_right = '0' then
+        v.sel_hi(0) := z(1);
+      else
+        v.sel_hi(0) := z(0);
+      end if;
+    end if;
+    case v.sel_hi is
+      when "00" =>
+        v.v16 := rs(15 downto 0);
+      when "01" =>
+        v.v16 := rs(31 downto 16);
+      when "10" =>
+        v.v16 := rs(47 downto 32);
+      when others =>
+        v.v16 := rs(63 downto 48);
+    end case;
+    v.is_32bit := is_32bit;
+    v.count_right := count_right;
+    r_in <= v;
+    sel(5 downto 4) := r.sel_hi;
+    y(0) := or(r.v16(3 downto 0));
+    y(1) := or(r.v16(7 downto 4));
+    y(2) := or(r.v16(11 downto 8));
+    y(3) := or(r.v16(15 downto 12));
+    sel(3 downto 2) := encoder(y,r.count_right);
+    case sel(3 downto 2) is
+      when "00" =>
+        v4 := r.v16(3 downto 0);
+      when "01" =>
+        v4 := r.v16(7 downto 4);
+      when "10" =>
+        v4 := r.v16(11 downto 8);
+      when others =>
+        v4 := r.v16(15 downto 12);
+    end case;
+    sel(1 downto 0) := encoder(v4,r.count_right);
+    if v4 = "0000" then
+      result <= x"00000000000000" & '0' & r.is_32bit & r.is_32bit & "00000";
+    elsif r.count_right = '0' then
+      result <= x"00000000000000" & "00" & (sel(5) and r.is_32bit) & sel(4 downto 0);
+    else
+      result <= x"00000000000000" & "00" & sel;
+    end if;
+  end process;
+end behaviour;