vertigo_vhdl 0.8.2

data/tests/parser_tests/test_microwatt_wishbone_types.vhd

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+../microwatt/wishbone_types.vhdl

data/tests/parser_tests/test_microwatt_wishbone_types_pp.vhd

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+-- generated by Vertigo VHDL tool
+library ieee;
+use ieee.std_logic_1164.all;
+ 
+package wishbone_types is
+  constant wishbone_addr_bits : integer := 32;
+  constant wishbone_data_bits : integer := 64;
+  constant wishbone_sel_bits : integer := wishbone_data_bits / 8;
+   
+  subtype wishbone_addr_type is std_ulogic_vector(wishbone_addr_bits - 1 downto 0);
+   
+  subtype wishbone_data_type is std_ulogic_vector(wishbone_data_bits - 1 downto 0);
+   
+  subtype wishbone_sel_type is std_ulogic_vector(wishbone_sel_bits - 1 downto 0);
+   
+  type wishbone_master_out is record
+    adr : wishbone_addr_type;
+    dat : wishbone_data_type;
+    cyc : std_ulogic;
+    stb : std_ulogic;
+    sel : wishbone_sel_type;
+    we : std_ulogic;
+  end record;
+  constant wishbone_master_out_init : wishbone_master_out := (cyc => '0',stb => '0',we => '0',others => (others => '0'));
+   
+  type wishbone_slave_out is record
+    dat : wishbone_data_type;
+    ack : std_ulogic;
+    stall : std_ulogic;
+  end record;
+  constant wishbone_slave_out_init : wishbone_slave_out := (ack => '0',stall => '0',others => (others => '0'));
+   
+  type wishbone_master_out_vector is array(natural range <>) of wishbone_master_out;
+   
+  type wishbone_slave_out_vector is array(natural range <>) of wishbone_slave_out;
+ 
+end wishbone_types;
+ 

data/tests/parser_tests/test_microwatt_writeback.vhd

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+../microwatt/writeback.vhdl

data/tests/parser_tests/test_microwatt_writeback_pp.vhd

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+-- generated by Vertigo VHDL tool
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.common.all;
+use work.crhelpers.all;
+ 
+entity writeback is
+  port(
+    clk : in std_ulogic;
+    e_in : in execute1towritebacktype;
+    l_in : in loadstore1towritebacktype;
+    w_out : out writebacktoregisterfiletype;
+    c_out : out writebacktocrfiletype;
+    complete_out : out std_ulogic);
+end entity writeback;
+ 
+architecture behaviour of writeback is
+begin
+ 
+   
+  writeback_1 : process(all)
+    variable x : std_ulogic_vector(0 downto 0);
+    variable y : std_ulogic_vector(0 downto 0);
+    variable w : std_ulogic_vector(0 downto 0);
+    variable cf : std_ulogic_vector(3 downto 0);
+    variable zero : std_ulogic;
+    variable sign : std_ulogic;
+    variable scf : std_ulogic_vector(3 downto 0);
+  begin
+    x(0) := e_in.valid;
+    y(0) := l_in.valid;
+    assert (to_integer(unsigned(x)) + to_integer(unsigned(y))) <= 1;
+    x(0) := e_in.write_enable;
+    y(0) := l_in.write_enable;
+    assert (to_integer(unsigned(x)) + to_integer(unsigned(y))) <= 1;
+    w(0) := e_in.write_cr_enable;
+    x(0) := (e_in.write_enable and e_in.rc);
+    assert (to_integer(unsigned(w)) + to_integer(unsigned(x))) <= 1;
+    w_out <= writebacktoregisterfileinit;
+    c_out <= writebacktocrfileinit;
+    complete_out <= '0';
+    if e_in.valid = '1' or l_in.valid = '1' then
+      complete_out <= '1';
+    end if;
+    if e_in.write_enable = '1' then
+      w_out.write_reg <= e_in.write_reg;
+      w_out.write_data <= e_in.write_data;
+      w_out.write_enable <= '1';
+    end if;
+    if e_in.write_cr_enable = '1' then
+      c_out.write_cr_enable <= '1';
+      c_out.write_cr_mask <= e_in.write_cr_mask;
+      c_out.write_cr_data <= e_in.write_cr_data;
+    end if;
+    if e_in.write_xerc_enable = '1' then
+      c_out.write_xerc_enable <= '1';
+      c_out.write_xerc_data <= e_in.xerc;
+    end if;
+    if l_in.write_enable = '1' then
+      w_out.write_reg <= gpr_to_gspr(l_in.write_reg);
+      w_out.write_data <= l_in.write_data;
+      w_out.write_enable <= '1';
+    end if;
+    if l_in.rc = '1' then
+      scf(3) := '0';
+      scf(2) := '0';
+      scf(1) := l_in.store_done;
+      scf(0) := l_in.xerc.so;
+      c_out.write_cr_enable <= '1';
+      c_out.write_cr_mask <= num_to_fxm(0);
+      c_out.write_cr_data(31 downto 28) <= scf;
+    end if;
+    if e_in.rc = '1' and e_in.write_enable = '1' then
+      sign := e_in.write_data(63);
+      zero := (or(e_in.write_data));
+      c_out.write_cr_enable <= '1';
+      c_out.write_cr_mask <= num_to_fxm(0);
+      cf(3) := sign;
+      cf(2) := sign and zero;
+      cf(1) := zero;
+      cf(0) := e_in.xerc.so;
+      c_out.write_cr_data(31 downto 28) <= cf;
+    end if;
+  end process;
+end behaviour;

data/tests/parser_tests/test_package-1.vhd

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+------------------------------------------------------------------------------
+-- Test Bench for ALU design (ESD figure 2.5)
+-- by Weijun Zhang, 04/2001
+--
+-- we illustrate how to use package and procedure in this example
+-- it seems a kind of complex testbench for this simple module,
+-- the method, however, makes huge circuit testing more complete,
+-- covenient and managable
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+-- define constant, signal and procedure within package for ALU
+
+package ALU_package is
+
+    constant INTERVAL: TIME := 8 ns;
+
+    signal sig_A, sig_B: std_logic_vector(1 downto 0);
+    signal sig_Sel: std_logic_vector(1 downto 0);
+    signal sig_Res: std_logic_vector(1 downto 0);
+
+    procedure load_data(
+		  signal A, B: out std_logic_vector(1 downto 0);
+      signal Sel: out std_logic_vector(1 downto 0)
+			);
+
+    procedure check_data(signal Sel: out std_logic_vector( 1 downto 0));
+
+end ALU_package;
+
+-- put all the procedure descriptions within package body
+
+package body ALU_package is
+
+    procedure load_data (signal A, B: out std_logic_vector(1 downto 0);
+			 signal Sel: out std_logic_vector(1 downto 0) ) is
+    begin
+	    A <= sig_A;
+	    B <= sig_B;
+	    Sel <= sig_Sel;
+    end load_data;
+
+    procedure check_data (signal Sel: out std_logic_vector( 1 downto 0)) is
+    begin
+    	Sel <= sig_Sel;
+    	if (sig_Sel="00") then
+    	    assert(sig_Res = (sig_A + sig_B))
+    	    report "Error detected in Addition!"
+    	    severity warning;
+    	elsif (sig_Sel="01") then
+    	    assert(sig_Res = (sig_A - sig_B))
+    	    report "Error detected in Subtraction!"
+    	    severity warning;
+    	elsif (sig_Sel="10") then
+    	    assert(sig_Res = (sig_A and sig_B))
+    	    report "AND Operation Error!"
+    	    severity warning;
+    	elsif (sig_Sel="11") then
+    	    assert(sig_Res = (sig_A or sig_B))
+    	    report "OR operation Error!"
+    	    severity warning;
+    	end if;
+    end check_data;
+
+end ALU_package;

data/tests/parser_tests/test_package-1_pp.vhd

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+-- generated by Vertigo VHDL tool
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+ 
+package alu_package is
+  constant interval : time := 8 ns;
+  signal sig_a : std_logic_vector(1 downto 0);
+  signal sig_b : std_logic_vector(1 downto 0);
+  signal sig_sel : std_logic_vector(1 downto 0);
+  signal sig_res : std_logic_vector(1 downto 0);
+   
+  procedure load_data(
+    a : out std_logic_vector(1 downto 0);
+    b : out std_logic_vector(1 downto 0);
+    sel : out std_logic_vector(1 downto 0));
+   
+  procedure check_data(
+    sel : out std_logic_vector(1 downto 0));
+ 
+end alu_package;
+ 
+package body alu_package is
+   
+  procedure load_data(
+    a : out std_logic_vector(1 downto 0);
+    b : out std_logic_vector(1 downto 0);
+    sel : out std_logic_vector(1 downto 0)) is
+  begin
+    a <= sig_a;
+    b <= sig_b;
+    sel <= sig_sel;
+  end load_data;
+   
+  procedure check_data(
+    sel : out std_logic_vector(1 downto 0)) is
+  begin
+    sel <= sig_sel;
+    if (sig_sel = "00") then
+      assert (sig_res = (sig_a + sig_b))
+        report "error detected in addition!" severity warning;
+    elsif (sig_sel = "01") then
+      assert (sig_res = (sig_a - sig_b))
+        report "error detected in subtraction!" severity warning;
+    elsif (sig_sel = "10") then
+      assert (sig_res = (sig_a and sig_b))
+        report "and operation error!" severity warning;
+    elsif (sig_sel = "11") then
+      assert (sig_res = (sig_a or sig_b))
+        report "or operation error!" severity warning;
+    end if;
+  end check_data;
+end alu_package;

data/tests/parser_tests/test_precedence.vhd

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+
+entity test is
+end test;
+
+architecture bhv of test is
+begin
+  process
+  begin
+    if clk'event and clk='1' then
+      report "hourra!";
+    end if;
+  end process;
+end bhv;

data/tests/parser_tests/test_precedence_pp.vhd

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+-- generated by Vertigo VHDL tool
+ 
+entity test is
+end entity test;
+ 
+architecture bhv of test is
+begin
+ 
+   
+  process
+  begin
+    if clk'event and clk = '1' then
+      report "hourra!";
+    end if;
+  end process;
+end bhv;

data/tests/parser_tests/test_selected_sig.vhd

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+
+-- Deuxieme architecture concurrente decrivant un mux :
+
+ARCHITECTURE mux_4_vers_1 OF porte_4_vers_1 IS
+
+BEGIN
+
+  WITH adr SELECT
+    s <=  a  WHEN "00",
+          b  WHEN "01",
+          c  WHEN "10",
+          d  WHEN others;
+
+END mux_4_vers_1;

data/tests/parser_tests/test_selected_sig_pp.vhd

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+-- generated by Vertigo VHDL tool
+architecture mux_4_vers_1 of porte_4_vers_1 is
+begin
+ 
+  with adr select s <=
+    a when "00",
+    b when "01",
+    c when "10",
+    d when others,;
+end mux_4_vers_1;

data/tests/parser_tests/test_slice.vhd

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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity test is
+end entity;
+
+architecture arch of test is
+  constant CST : std_logic_vector(15 downto 0) := x"1234";
+  signal s1,s2 : std_logic_vector(31 downto 0);
+begin
+
+  s2 <= s1(15 downto 0) & CST;
+
+end architecture;

data/tests/parser_tests/test_slice_pp.vhd

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+-- generated by Vertigo VHDL tool
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+ 
+entity test is
+end entity test;
+ 
+architecture arch of test is
+  constant cst : std_logic_vector(15 downto 0) := x"1234";
+  signal s1 : std_logic_vector(31 downto 0);
+  signal s2 : std_logic_vector(31 downto 0);
+begin
+ 
+  s2 <= s1(15 downto 0) & cst;
+end arch;

data/tests/parser_tests/test_tb-00.vhd

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+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+entity DECODER_TB is
+end DECODER_TB;
+
+architecture TB of DECODER_TB is
+
+  signal T_I : std_logic_vector(1 downto 0) := "00";
+  signal T_O : std_logic_vector(3 downto 0);
+  
+  
+  component decoder port(
+    I : in  std_logic_vector(1 downto 0);
+    O : out std_logic_vector(3 downto 0)
+    );
+  end component;
+
+begin
+
+  U_DECODER : DECODER port map (T_I, T_O);
+
+  process
+    variable err_cnt : integer := 0;
+  begin
+
+    wait for 10 ns;   
+    T_I <= "00";
+    wait for 1 ns;
+    assert (T_O="0001") report "Error Case 0"  severity error;
+    if (T_O/="0001") then 
+        err_cnt := err_cnt + 1;
+    end if;
+
+
+    wait for 10 ns;
+    T_I <= "01";                                                                                
+    wait for 1 ns;
+    assert (T_O="0010") report "Error Case 1" 
+    severity error;
+    if (T_O/="0010") then
+        err_cnt := err_cnt + 1;
+    end if;
+
+
+    wait for 10 ns;
+    T_I <= "10";                                                                                 
+    wait for 1 ns;
+    assert (T_O="0100") report "Error Case 2" 
+    severity error;
+    if (T_O/="0100") then
+        err_cnt := err_cnt + 1;
+    end if;
+
+
+    wait for 10 ns;
+    T_I <= "11";                                                                                
+    wait for 1 ns;
+    assert (T_O="1000") report "Error Case 3" 
+    severity error;
+    if (T_O/="1000") then
+        err_cnt := err_cnt + 1;
+    end if;
+
+
+    wait for 10 ns;
+    T_I <= "UU";              
+
+
+    if (err_cnt=0) then                       
+        assert false 
+        report "Testbench of Adder completed successfully!" 
+        severity note; 
+    else 
+        assert true 
+        report "Something wrong, try again" 
+        severity error; 
+    end if; 
+
+    wait;
+
+  end process;
+
+end TB;
+
+---------------------------------------------------------------
+configuration CFG_TB of DECODER_TB is
+  for TB
+  end for;
+end CFG_TB;
+----------------------------------------------------------------