RubyGems - vertigo_vhdl - Versions diffs - 0.8.2 - Mend

vertigo_vhdl 0.8.2

Files changed (183) hide show

checksums.yaml +7 -0
data/bin/vertigo +7 -0
data/lib/vertigo.rb +4 -0
data/lib/vertigo/ast.rb +87 -0
data/lib/vertigo/ast_vertigo_rkgen.rb +607 -0
data/lib/vertigo/code.rb +57 -0
data/lib/vertigo/compiler.rb +61 -0
data/lib/vertigo/generic_lexer.rb +61 -0
data/lib/vertigo/generic_parser.rb +44 -0
data/lib/vertigo/indent.rb +20 -0
data/lib/vertigo/lexer.rb +172 -0
data/lib/vertigo/parser.rb +1458 -0
data/lib/vertigo/pretty_printer.rb +749 -0
data/lib/vertigo/runner.rb +115 -0
data/lib/vertigo/tb_generator.rb +81 -0
data/lib/vertigo/template.tb.vhd +72 -0
data/lib/vertigo/token.rb +67 -0
data/lib/vertigo/version.rb +3 -0
data/lib/vertigo/vertigo.rkg +354 -0
data/lib/vertigo/visitor_vertigo_rkgen.rb +447 -0
data/tests/ghdl_tests/fsm.vhd +98 -0
data/tests/ghdl_tests/fsm_synth.vhd +248 -0
data/tests/ghdl_tests/test_fsm.vhd +162 -0
data/tests/parser_tests/else.vhd +64 -0
data/tests/parser_tests/test_MUST_fail.vhd +1 -0
data/tests/parser_tests/test_accelerator.vhd +160 -0
data/tests/parser_tests/test_accelerator_pp.vhd +144 -0
data/tests/parser_tests/test_aggregate.vhd +17 -0
data/tests/parser_tests/test_aggregate_pp.vhd +15 -0
data/tests/parser_tests/test_archi_1.vhd +45 -0
data/tests/parser_tests/test_archi_1_pp.vhd +41 -0
data/tests/parser_tests/test_array_array_00.vhd +25 -0
data/tests/parser_tests/test_array_array_00_pp.vhd +25 -0
data/tests/parser_tests/test_array_urange.vhd +25 -0
data/tests/parser_tests/test_array_urange_pp.vhd +25 -0
data/tests/parser_tests/test_chu-1.vhd +80 -0
data/tests/parser_tests/test_chu-1_pp.vhd +104 -0
data/tests/parser_tests/test_concat.vhd +11 -0
data/tests/parser_tests/test_concat_pp.vhd +14 -0
data/tests/parser_tests/test_counter.vhd +35 -0
data/tests/parser_tests/test_counter_pp.vhd +35 -0
data/tests/parser_tests/test_de2.vhd +358 -0
data/tests/parser_tests/test_de2_pp.vhd +274 -0
data/tests/parser_tests/test_encode.vhd +2679 -0
data/tests/parser_tests/test_encode_pp.vhd +2549 -0
data/tests/parser_tests/test_fsm.vhd +162 -0
data/tests/parser_tests/test_fsm_pp.vhd +125 -0
data/tests/parser_tests/test_fsm_synth.vhd +248 -0
data/tests/parser_tests/test_fsm_synth_pp.vhd +197 -0
data/tests/parser_tests/test_function-01.vhd +33 -0
data/tests/parser_tests/test_function-01_pp.vhd +18 -0
data/tests/parser_tests/test_lfsr.vhd +75 -0
data/tests/parser_tests/test_lfsr_pp.vhd +44 -0
data/tests/parser_tests/test_microwatt_cache_ram.vhd +1 -0
data/tests/parser_tests/test_microwatt_cache_ram_pp.vhd +68 -0
data/tests/parser_tests/test_microwatt_common.vhd +1 -0
data/tests/parser_tests/test_microwatt_common_pp.vhd +336 -0
data/tests/parser_tests/test_microwatt_control.vhd +1 -0
data/tests/parser_tests/test_microwatt_control_pp.vhd +187 -0
data/tests/parser_tests/test_microwatt_core.vhd +1 -0
data/tests/parser_tests/test_microwatt_core_debug.vhd +1 -0
data/tests/parser_tests/test_microwatt_core_debug_pp.vhd +104 -0
data/tests/parser_tests/test_microwatt_core_pp.vhd +231 -0
data/tests/parser_tests/test_microwatt_core_tb.vhd +1 -0
data/tests/parser_tests/test_microwatt_core_tb_pp.vhd +43 -0
data/tests/parser_tests/test_microwatt_countzero.vhd +1 -0
data/tests/parser_tests/test_microwatt_countzero_pp.vhd +120 -0
data/tests/parser_tests/test_microwatt_countzero_tb.vhd +1 -0
data/tests/parser_tests/test_microwatt_countzero_tb_pp.vhd +70 -0
data/tests/parser_tests/test_microwatt_cr_file.vhd +1 -0
data/tests/parser_tests/test_microwatt_cr_file_pp.vhd +74 -0
data/tests/parser_tests/test_microwatt_cr_hazard.vhd +1 -0
data/tests/parser_tests/test_microwatt_cr_hazard_pp.vhd +51 -0
data/tests/parser_tests/test_microwatt_crhelpers.vhd +1 -0
data/tests/parser_tests/test_microwatt_crhelpers_pp.vhd +48 -0
data/tests/parser_tests/test_microwatt_dcache.vhd +1 -0
data/tests/parser_tests/test_microwatt_dcache_pp.vhd +481 -0
data/tests/parser_tests/test_microwatt_dcache_tb.vhd +1 -0
data/tests/parser_tests/test_microwatt_dcache_tb_pp.vhd +98 -0
data/tests/parser_tests/test_microwatt_decode1.vhd +1 -0
data/tests/parser_tests/test_microwatt_decode1_pp.vhd +138 -0
data/tests/parser_tests/test_microwatt_decode2.vhd +1 -0
data/tests/parser_tests/test_microwatt_decode2_pp.vhd +300 -0
data/tests/parser_tests/test_microwatt_decode_types.vhd +1 -0
data/tests/parser_tests/test_microwatt_decode_types_pp.vhd +67 -0
data/tests/parser_tests/test_microwatt_divider.vhd +1 -0
data/tests/parser_tests/test_microwatt_divider_pp.vhd +132 -0
data/tests/parser_tests/test_microwatt_divider_tb.vhd +1 -0
data/tests/parser_tests/test_microwatt_divider_tb_pp.vhd +95 -0
data/tests/parser_tests/test_microwatt_dmi_dtm_dummy.vhd +1 -0
data/tests/parser_tests/test_microwatt_dmi_dtm_dummy_pp.vhd +29 -0
data/tests/parser_tests/test_microwatt_dmi_dtm_tb.vhd +1 -0
data/tests/parser_tests/test_microwatt_dmi_dtm_tb_pp.vhd +197 -0
data/tests/parser_tests/test_microwatt_dmi_dtm_xilinx.vhd +1 -0
data/tests/parser_tests/test_microwatt_dmi_dtm_xilinx_pp.vhd +139 -0
data/tests/parser_tests/test_microwatt_execute1.vhd +1 -0
data/tests/parser_tests/test_microwatt_execute1_pp.vhd +689 -0
data/tests/parser_tests/test_microwatt_fetch1.vhd +1 -0
data/tests/parser_tests/test_microwatt_fetch1_pp.vhd +88 -0
data/tests/parser_tests/test_microwatt_fetch2.vhd +1 -0
data/tests/parser_tests/test_microwatt_fetch2_pp.vhd +79 -0
data/tests/parser_tests/test_microwatt_glibc_random.vhd +1 -0
data/tests/parser_tests/test_microwatt_glibc_random_helpers.vhd +1 -0
data/tests/parser_tests/test_microwatt_glibc_random_helpers_pp.vhd +25 -0
data/tests/parser_tests/test_microwatt_glibc_random_pp.vhd +41 -0
data/tests/parser_tests/test_microwatt_gpr_hazard.vhd +1 -0
data/tests/parser_tests/test_microwatt_gpr_hazard_pp.vhd +68 -0
data/tests/parser_tests/test_microwatt_helpers.vhd +1 -0
data/tests/parser_tests/test_microwatt_helpers_pp.vhd +153 -0
data/tests/parser_tests/test_microwatt_icache.vhd +1 -0
data/tests/parser_tests/test_microwatt_icache_pp.vhd +337 -0
data/tests/parser_tests/test_microwatt_icache_tb.vhd +1 -0
data/tests/parser_tests/test_microwatt_icache_tb_pp.vhd +104 -0
data/tests/parser_tests/test_microwatt_insn_helpers.vhd +1 -0
data/tests/parser_tests/test_microwatt_insn_helpers_pp.vhd +208 -0
data/tests/parser_tests/test_microwatt_loadstore1.vhd +1 -0
data/tests/parser_tests/test_microwatt_loadstore1_pp.vhd +222 -0
data/tests/parser_tests/test_microwatt_logical.vhd +1 -0
data/tests/parser_tests/test_microwatt_logical_pp.vhd +87 -0
data/tests/parser_tests/test_microwatt_multiply.vhd +1 -0
data/tests/parser_tests/test_microwatt_multiply_pp.vhd +84 -0
data/tests/parser_tests/test_microwatt_multiply_tb.vhd +1 -0
data/tests/parser_tests/test_microwatt_multiply_tb_pp.vhd +75 -0
data/tests/parser_tests/test_microwatt_plru.vhd +1 -0
data/tests/parser_tests/test_microwatt_plru_pp.vhd +46 -0
data/tests/parser_tests/test_microwatt_plru_tb.vhd +1 -0
data/tests/parser_tests/test_microwatt_plru_tb_pp.vhd +93 -0
data/tests/parser_tests/test_microwatt_ppc_fx_insns.vhd +1 -0
data/tests/parser_tests/test_microwatt_ppc_fx_insns_pp.vhd +665 -0
data/tests/parser_tests/test_microwatt_register_file.vhd +1 -0
data/tests/parser_tests/test_microwatt_register_file_pp.vhd +86 -0
data/tests/parser_tests/test_microwatt_rotator.vhd +1 -0
data/tests/parser_tests/test_microwatt_rotator_pp.vhd +149 -0
data/tests/parser_tests/test_microwatt_rotator_tb.vhd +1 -0
data/tests/parser_tests/test_microwatt_rotator_tb_pp.vhd +134 -0
data/tests/parser_tests/test_microwatt_sim_bram.vhd +1 -0
data/tests/parser_tests/test_microwatt_sim_bram_helpers.vhd +1 -0
data/tests/parser_tests/test_microwatt_sim_bram_helpers_pp.vhd +52 -0
data/tests/parser_tests/test_microwatt_sim_bram_pp.vhd +53 -0
data/tests/parser_tests/test_microwatt_sim_console.vhd +1 -0
data/tests/parser_tests/test_microwatt_sim_console_pp.vhd +43 -0
data/tests/parser_tests/test_microwatt_sim_jtag.vhd +1 -0
data/tests/parser_tests/test_microwatt_sim_jtag_pp.vhd +64 -0
data/tests/parser_tests/test_microwatt_sim_jtag_socket.vhd +1 -0
data/tests/parser_tests/test_microwatt_sim_jtag_socket_pp.vhd +36 -0
data/tests/parser_tests/test_microwatt_sim_uart.vhd +1 -0
data/tests/parser_tests/test_microwatt_sim_uart_pp.vhd +90 -0
data/tests/parser_tests/test_microwatt_soc.vhd +1 -0
data/tests/parser_tests/test_microwatt_soc_pp.vhd +195 -0
data/tests/parser_tests/test_microwatt_utils.vhd +1 -0
data/tests/parser_tests/test_microwatt_utils_pp.vhd +39 -0
data/tests/parser_tests/test_microwatt_wishbone_arbiter.vhd +1 -0
data/tests/parser_tests/test_microwatt_wishbone_arbiter_pp.vhd +54 -0
data/tests/parser_tests/test_microwatt_wishbone_bram_tb.vhd +1 -0
data/tests/parser_tests/test_microwatt_wishbone_bram_tb_pp.vhd +157 -0
data/tests/parser_tests/test_microwatt_wishbone_bram_wrapper.vhd +1 -0
data/tests/parser_tests/test_microwatt_wishbone_bram_wrapper_pp.vhd +62 -0
data/tests/parser_tests/test_microwatt_wishbone_debug_master.vhd +1 -0
data/tests/parser_tests/test_microwatt_wishbone_debug_master_pp.vhd +124 -0
data/tests/parser_tests/test_microwatt_wishbone_types.vhd +1 -0
data/tests/parser_tests/test_microwatt_wishbone_types_pp.vhd +38 -0
data/tests/parser_tests/test_microwatt_writeback.vhd +1 -0
data/tests/parser_tests/test_microwatt_writeback_pp.vhd +87 -0
data/tests/parser_tests/test_package-1.vhd +68 -0
data/tests/parser_tests/test_package-1_pp.vhd +53 -0
data/tests/parser_tests/test_precedence.vhd +13 -0
data/tests/parser_tests/test_precedence_pp.vhd +16 -0
data/tests/parser_tests/test_selected_sig.vhd +14 -0
data/tests/parser_tests/test_selected_sig_pp.vhd +10 -0
data/tests/parser_tests/test_slice.vhd +15 -0
data/tests/parser_tests/test_slice_pp.vhd +16 -0
data/tests/parser_tests/test_tb-00.vhd +94 -0
data/tests/parser_tests/test_tb-00_pp.vhd +71 -0
data/tests/parser_tests/test_type_decl_02.vhd +9 -0
data/tests/parser_tests/test_type_decl_02_pp.vhd +11 -0
data/tests/parser_tests/test_use.vhd +7 -0
data/tests/parser_tests/test_use_pp.vhd +10 -0
data/tests/parser_tests/test_while_1.vhd +38 -0
data/tests/parser_tests/test_while_1_pp.vhd +26 -0
data/tests/parser_tests/test_with-00.vhd +21 -0
data/tests/parser_tests/test_with-00_pp.vhd +12 -0
data/tests/tb_gen_tests/test_accelerator.vhd +160 -0
metadata +224 -0

data/lib/vertigo/visitor_vertigo_rkgen.rb ADDED Viewed

@@ -0,0 +1,447 @@
+# ============================================================
+# This code was generated by rkgen utility.
+# DO NOT MODIFY !
+# ============================================================
+module Vertigo
+  class Visitor
+    def visit ast
+      puts "visiting ast #{ast}"
+      ast.accept(self)
+    end
+    def visitRoot(root_,args=nil)
+      root_.design_units.each{|design_unit_| design_unit_.accept(self,args)}
+    end
+    def visitComment(comment_,args=nil)
+      comment_.str.accept(self,args)
+    end
+    def visitLibrary(library_,args=nil)
+      library_.name.accept(self,args)
+    end
+    def visitUse(use_,args=nil)
+      use_.library.accept(self,args)
+      use_.package.accept(self,args)
+      use_.element.accept(self,args)
+    end
+    def visitEntity(entity_,args=nil)
+      entity_.name.accept(self,args)
+      entity_.generics.each{|generic_| generic_.accept(self,args)}
+      entity_.ports.each{|port_| port_.accept(self,args)}
+    end
+    def visitGeneric(generic_,args=nil)
+      generic_.name.accept(self,args)
+      generic_.type.accept(self,args)
+      generic_.init.accept(self,args)
+    end
+    def visitInput(input_,args=nil)
+      input_.name.accept(self,args)
+      input_.type.accept(self,args)
+      input_.init.accept(self,args)
+    end
+    def visitOutput(output_,args=nil)
+      output_.name.accept(self,args)
+      output_.type.accept(self,args)
+      output_.init.accept(self,args)
+    end
+    def visitInOut(inout_,args=nil)
+      inout_.name.accept(self,args)
+      inout_.type.accept(self,args)
+      inout_.init.accept(self,args)
+    end
+    def visitPackage(package_,args=nil)
+      package_.name.accept(self,args)
+      package_.decls.each{|decl_| decl_.accept(self,args)}
+    end
+    def visitPackageBody(packagebody_,args=nil)
+      packagebody_.name.accept(self,args)
+      packagebody_.decls.each{|decl_| decl_.accept(self,args)}
+    end
+    def visitProcedureDecl(proceduredecl_,args=nil)
+      proceduredecl_.name.accept(self,args)
+      proceduredecl_.formal_args.each{|formal_arg_| formal_arg_.accept(self,args)}
+      proceduredecl_.decls.each{|decl_| decl_.accept(self,args)}
+      proceduredecl_.body.accept(self,args)
+    end
+    def visitFormalArg(formalarg_,args=nil)
+      formalarg_.signal.accept(self,args)
+      formalarg_.direction.accept(self,args)
+      formalarg_.name.accept(self,args)
+      formalarg_.type.accept(self,args)
+    end
+    def visitProcedureCall(procedurecall_,args=nil)
+      procedurecall_.name.accept(self,args)
+      procedurecall_.actual_args.each{|actual_arg_| actual_arg_.accept(self,args)}
+    end
+    def visitArchitecture(architecture_,args=nil)
+      architecture_.name.accept(self,args)
+      architecture_.entity_name.accept(self,args)
+      architecture_.decls.each{|decl_| decl_.accept(self,args)}
+      architecture_.body.accept(self,args)
+    end
+    def visitBody(body_,args=nil)
+      body_.elements.each{|element_| element_.accept(self,args)}
+    end
+    def visitProcess(process_,args=nil)
+      process_.sensitivity.accept(self,args)
+      process_.decls.each{|decl_| decl_.accept(self,args)}
+      process_.body.accept(self,args)
+    end
+    def visitSensitivity(sensitivity_,args=nil)
+      sensitivity_.elements.each{|element_| element_.accept(self,args)}
+    end
+    def visitEntityInstance(entityinstance_,args=nil)
+      entityinstance_.full_name.accept(self,args)
+      entityinstance_.arch_name.accept(self,args)
+      entityinstance_.generic_map.accept(self,args)
+      entityinstance_.port_map.accept(self,args)
+    end
+    def visitComponentDecl(componentdecl_,args=nil)
+      componentdecl_.name.accept(self,args)
+      componentdecl_.generics.each{|generic_| generic_.accept(self,args)}
+      componentdecl_.ports.each{|port_| port_.accept(self,args)}
+    end
+    def visitComponentInstance(componentinstance_,args=nil)
+      componentinstance_.name.accept(self,args)
+      componentinstance_.generic_map.accept(self,args)
+      componentinstance_.port_map.accept(self,args)
+    end
+    def visitPortMap(portmap_,args=nil)
+      portmap_.elements.each{|element_| element_.accept(self,args)}
+    end
+    def visitGenericMap(genericmap_,args=nil)
+      genericmap_.elements.each{|element_| element_.accept(self,args)}
+    end
+    def visitMap(map_,args=nil)
+      map_.lhs.accept(self,args)
+      map_.rhs.accept(self,args)
+    end
+    def visitAttributeDecl(attributedecl_,args=nil)
+      attributedecl_.name.accept(self,args)
+      attributedecl_.type.accept(self,args)
+    end
+    def visitAttributeSpec(attributespec_,args=nil)
+      attributespec_.name.accept(self,args)
+      attributespec_.entity_spec.accept(self,args)
+      attributespec_.expr.accept(self,args)
+    end
+    def visitEntitySpec(entityspec_,args=nil)
+      entityspec_.elements.each{|element_| element_.accept(self,args)}
+      entityspec_.entity_class.accept(self,args)
+    end
+    def visitSigAssign(sigassign_,args=nil)
+      sigassign_.lhs.accept(self,args)
+      sigassign_.rhs.accept(self,args)
+    end
+    def visitVarAssign(varassign_,args=nil)
+      varassign_.lhs.accept(self,args)
+      varassign_.rhs.accept(self,args)
+    end
+    def visitWait(wait_,args=nil)
+      wait_.until_.accept(self,args)
+      wait_.for_.accept(self,args)
+    end
+    def visitIf(if_,args=nil)
+      if_.cond.accept(self,args)
+      if_.body.accept(self,args)
+      if_.elsifs.each{|elsif_| elsif_.accept(self,args)}
+      if_.else_.accept(self,args)
+    end
+    def visitElsif(elsif_,args=nil)
+      elsif_.cond.accept(self,args)
+      elsif_.body.accept(self,args)
+    end
+    def visitElse(else_,args=nil)
+      else_.body.accept(self,args)
+    end
+    def visitCase(case_,args=nil)
+      case_.expr.accept(self,args)
+      case_.whens.each{|when_| when_.accept(self,args)}
+    end
+    def visitCaseWhen(casewhen_,args=nil)
+      casewhen_.expr.accept(self,args)
+      casewhen_.body.accept(self,args)
+    end
+    def visitAlternative(alternative_,args=nil)
+      alternative_.elements.each{|element_| element_.accept(self,args)}
+    end
+    def visitNullStmt(nullstmt_,args=nil)
+      nullstmt_.dummy.accept(self,args)
+    end
+    def visitAssert(assert_,args=nil)
+      assert_.cond.accept(self,args)
+      assert_.report.accept(self,args)
+      assert_.severity.accept(self,args)
+    end
+    def visitReport(report_,args=nil)
+      report_.expr.accept(self,args)
+      report_.severity.accept(self,args)
+    end
+    def visitSeverity(severity_,args=nil)
+      severity_.type.accept(self,args)
+    end
+    def visitReturn(return_,args=nil)
+      return_.expr.accept(self,args)
+    end
+    def visitWithSelect(withselect_,args=nil)
+      withselect_.with_expr.accept(self,args)
+      withselect_.assigned.accept(self,args)
+      withselect_.selected_whens.each{|selected_when_| selected_when_.accept(self,args)}
+    end
+    def visitSelectedWhen(selectedwhen_,args=nil)
+      selectedwhen_.lhs.accept(self,args)
+      selectedwhen_.rhs.accept(self,args)
+    end
+    def visitIfGenerate(ifgenerate_,args=nil)
+      ifgenerate_.cond.accept(self,args)
+      ifgenerate_.body.accept(self,args)
+    end
+    def visitForGenerate(forgenerate_,args=nil)
+      forgenerate_.index.accept(self,args)
+      forgenerate_.range.accept(self,args)
+      forgenerate_.decls.each{|decl_| decl_.accept(self,args)}
+      forgenerate_.body.accept(self,args)
+    end
+    def visitIsolatedRange(isolatedrange_,args=nil)
+      isolatedrange_.lhs.accept(self,args)
+      isolatedrange_.rhs.accept(self,args)
+    end
+    def visitTypeDecl(typedecl_,args=nil)
+      typedecl_.name.accept(self,args)
+      typedecl_.spec.accept(self,args)
+    end
+    def visitSubTypeDecl(subtypedecl_,args=nil)
+      subtypedecl_.name.accept(self,args)
+      subtypedecl_.spec.accept(self,args)
+    end
+    def visitEnumDecl(enumdecl_,args=nil)
+      enumdecl_.elements.each{|element_| element_.accept(self,args)}
+    end
+    def visitRecordDecl(recorddecl_,args=nil)
+      recorddecl_.elements.each{|element_| element_.accept(self,args)}
+    end
+    def visitRecordItem(recorditem_,args=nil)
+      recorditem_.name.accept(self,args)
+      recorditem_.type.accept(self,args)
+    end
+    def visitArrayDecl(arraydecl_,args=nil)
+      arraydecl_.dim_decls.each{|dim_decl_| dim_decl_.accept(self,args)}
+      arraydecl_.type.accept(self,args)
+    end
+    def visitArrayDimDecl(arraydimdecl_,args=nil)
+      arraydimdecl_.type_mark.accept(self,args)
+      arraydimdecl_.range.accept(self,args)
+    end
+    def visitConstant(constant_,args=nil)
+      constant_.name.accept(self,args)
+      constant_.type.accept(self,args)
+      constant_.expr.accept(self,args)
+    end
+    def visitSignal(signal_,args=nil)
+      signal_.name.accept(self,args)
+      signal_.type.accept(self,args)
+      signal_.init.accept(self,args)
+    end
+    def visitVariable(variable_,args=nil)
+      variable_.name.accept(self,args)
+      variable_.type.accept(self,args)
+      variable_.init.accept(self,args)
+    end
+    def visitAlias(alias_,args=nil)
+      alias_.designator.accept(self,args)
+      alias_.type.accept(self,args)
+      alias_.name.accept(self,args)
+      alias_.signature.accept(self,args)
+    end
+    def visitStdType(stdtype_,args=nil)
+      stdtype_.ident.accept(self,args)
+    end
+    def visitRangedType(rangedtype_,args=nil)
+      rangedtype_.type.accept(self,args)
+      rangedtype_.range.accept(self,args)
+    end
+    def visitNamedType(namedtype_,args=nil)
+      namedtype_.ident.accept(self,args)
+    end
+    def visitArrayType(arraytype_,args=nil)
+      arraytype_.name.accept(self,args)
+      arraytype_.discrete_ranges.each{|discrete_range_| discrete_range_.accept(self,args)}
+    end
+    def visitDiscreteRange(discreterange_,args=nil)
+      discreterange_.lhs.accept(self,args)
+      discreterange_.dir.accept(self,args)
+      discreterange_.rhs.accept(self,args)
+    end
+    def visitParenth(parenth_,args=nil)
+      parenth_.expr.accept(self,args)
+    end
+    def visitWaveform(waveform_,args=nil)
+      waveform_.elements.each{|element_| element_.accept(self,args)}
+    end
+    def visitCondExpr(condexpr_,args=nil)
+      condexpr_.whens.each{|when_| when_.accept(self,args)}
+      condexpr_.else_.accept(self,args)
+    end
+    def visitWhen(when_,args=nil)
+      when_.expr.accept(self,args)
+      when_.cond.accept(self,args)
+    end
+    def visitBinary(binary_,args=nil)
+      binary_.lhs.accept(self,args)
+      binary_.op.accept(self,args)
+      binary_.rhs.accept(self,args)
+    end
+    def visitAfter(after_,args=nil)
+      after_.lhs.accept(self,args)
+      after_.rhs.accept(self,args)
+    end
+    def visitTimed(timed_,args=nil)
+      timed_.lhs.accept(self,args)
+      timed_.rhs.accept(self,args)
+    end
+    def visitAttributed(attributed_,args=nil)
+      attributed_.lhs.accept(self,args)
+      attributed_.rhs.accept(self,args)
+    end
+    def visitConcat(concat_,args=nil)
+      concat_.lhs.accept(self,args)
+      concat_.rhs.accept(self,args)
+    end
+    def visitQualified(qualified_,args=nil)
+      qualified_.lhs.accept(self,args)
+      qualified_.rhs.accept(self,args)
+    end
+    def visitSliced(sliced_,args=nil)
+      sliced_.expr.accept(self,args)
+      sliced_.lhs.accept(self,args)
+      sliced_.dir.accept(self,args)
+      sliced_.rhs.accept(self,args)
+    end
+    def visitIdent(ident_,args=nil)
+      ident_.tok.accept(self,args)
+    end
+    def visitIntLit(intlit_,args=nil)
+      intlit_.tok.accept(self,args)
+    end
+    def visitCharLit(charlit_,args=nil)
+      charlit_.tok.accept(self,args)
+    end
+    def visitBoolLit(boollit_,args=nil)
+      boollit_.tok.accept(self,args)
+    end
+    def visitSelectedName(selectedname_,args=nil)
+      selectedname_.lhs.accept(self,args)
+      selectedname_.rhs.accept(self,args)
+    end
+    def visitFuncProtoDecl(funcprotodecl_,args=nil)
+      funcprotodecl_.name.accept(self,args)
+      funcprotodecl_.formal_args.each{|formal_arg_| formal_arg_.accept(self,args)}
+      funcprotodecl_.return_type.accept(self,args)
+    end
+    def visitFuncDecl(funcdecl_,args=nil)
+      funcdecl_.name.accept(self,args)
+      funcdecl_.formal_args.each{|formal_arg_| formal_arg_.accept(self,args)}
+      funcdecl_.return_type.accept(self,args)
+      funcdecl_.decls.accept(self,args)
+      funcdecl_.body.accept(self,args)
+    end
+    def visitFuncCall(funccall_,args=nil)
+      funccall_.name.accept(self,args)
+      funccall_.actual_args.each{|actual_arg_| actual_arg_.accept(self,args)}
+    end
+    def visitAggregate(aggregate_,args=nil)
+      aggregate_.elements.each{|element_| element_.accept(self,args)}
+    end
+    def visitLabel(label_,args=nil)
+      label_.ident.accept(self,args)
+    end
+    def visitAssoc(assoc_,args=nil)
+      assoc_.lhs.accept(self,args)
+      assoc_.rhs.accept(self,args)
+    end
+  end # visitor
+end # Vertigo

data/tests/ghdl_tests/fsm.vhd ADDED Viewed

@@ -0,0 +1,98 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.numeric_std.all;
+entity fsm is
+  port (
+    reset_n  : in std_logic;
+    clk      : in std_logic;
+    switches : in std_logic_vector(7 downto 0);
+    leds     : out std_logic_vector(7 downto 0);
+    o1,o2    : out std_logic;
+    o3       : out unsigned(3 downto 0)
+  );
+end entity;
+architecture arch of fsm is
+  type state_t is (S0,S1,S2,S3,S4,S5,S6,S7);
+  signal state,state_c : state_t;
+  signal c3 : unsigned(3 downto 0);
+begin
+  tick :process(reset_n,clk)
+  begin
+    if reset_n='0' then
+      state <= S0;
+    elsif rising_edge(clk) then
+      state <= state_c;
+    end if;
+  end process;
+  next_state_logic:process(switches)
+  variable state_v : state_t;
+  begin
+    state_v:= state;
+    o1 <= '0';
+    o2 <= '1';
+    case state_v is
+      when S0 =>
+        if switches(0)='1' then
+          state_v := S1;
+        end if;
+      when S1 =>
+        if switches(1)='1' then
+          state_v := S2;
+        end if;
+      when S2 =>
+        if switches(2)='1' then
+          state_v := S3;
+        end if;
+      when S3 =>
+        if switches(3)='1' then
+          state_v := S4;
+        end if;
+      when S4 =>
+        if switches(4)='1' then
+          state_v := S5;
+        end if;
+      when S5 =>
+        if switches(5)='1' then
+          state_v := S6;
+          o1 <= '1';
+        end if;
+      when S6 =>
+        if switches(6)='1' then
+          state_v := S7;
+          o2 <= '1';
+        end if;
+      when S7 =>
+        if switches(7)='1' then
+          state_v := S0;
+        end if;
+      when others =>
+        null;
+    end case;
+    state_c <= state_v;
+  end process;
+  -- single output
+  leds <= std_logic_vector(to_unsigned(0,8)) when state=S0 else
+          std_logic_vector(to_unsigned(1,8)) when state=S1 else
+          std_logic_vector(to_unsigned(2,8)) when state=S2 else
+          std_logic_vector(to_unsigned(3,8)) when state=S3 else
+          std_logic_vector(to_unsigned(4,8)) when state=S4 else
+          std_logic_vector(to_unsigned(5,8)) when state=S5 else
+          std_logic_vector(to_unsigned(6,8)) when state=S6 else
+          std_logic_vector(to_unsigned(7,8));
+  process(reset_n,clk)
+  begin
+    if reset_n='0' then
+      c3 <= to_unsigned(0,4);
+    elsif rising_edge(clk) then
+      c3 <= c3 + 1;
+    end if;
+  end process;
+  o3 <= c3;
+end architecture;