badline 0.12.0 → 0.13.0

data/lib/badline/z80/main_page.rb

@@ -1,134 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  class Z80
-    # The unprefixed opcodes, which DD and FD reuse with IX or IY for HL.
-    # An opcode splits into its quarter (bits 7-6), its row (5-3) and its
-    # column (2-0), and each quarter of the page is regular in rows and
-    # columns.
-    module MainPage
-      private
-
-      def execute(opcode)
-        case opcode >> 6
-        when 0 then execute_low(opcode)
-        when 1 then opcode == 0x76 ? @halted = true : load_register((opcode >> 3) & 7, opcode & 7)
-        when 2 then alu((opcode >> 3) & 7, operand(opcode & 7))
-        else execute_high(opcode)
-        end
-      end
-
-      def execute_low(opcode)
-        row = (opcode >> 3) & 7
-        case opcode & 7
-        when 0 then relative_jump(row)
-        when 1 then opcode.nobits?(8) ? set_pair(row >> 1, fetch_word) : add_pair(row >> 1)
-        when 2 then indirect_load(row)
-        when 3 then step_pair(row)
-        when 4 then modify(row, true)
-        when 5 then modify(row, false)
-        when 6 then load_immediate(row)
-        else accumulator_operation(row)
-        end
-      end
-
-      def execute_high(opcode)
-        row = (opcode >> 3) & 7
-        case opcode & 7
-        when 0 then conditional_return(row)
-        when 1 then opcode.nobits?(8) ? set_stack_pair(row >> 1, pop) : stack_and_exchange(row >> 1)
-        when 2 then jump(condition?(row))
-        when 3 then miscellaneous(row)
-        when 4 then call(condition?(row))
-        when 5 then opcode.nobits?(8) ? push_pair(row >> 1) : call_or_prefix(row >> 1)
-        when 6 then alu(row, fetch_byte)
-        else restart(row << 3)
-        end
-      end
-
-      # The operand of the 8-bit ALU opcodes: a register or (HL).
-      def operand(index)
-        index == 6 ? read_byte(operand_address) : register(index)
-      end
-
-      # INC and DEC on a register or (HL).
-      def modify(index, increase)
-        if index == 6
-          address = operand_address
-          value = read_byte(address)
-          @cycles += 1
-          write_byte(address, increase ? increment(value) : decrement(value))
-        else
-          set_register(index, increase ? increment(register(index)) : decrement(register(index)))
-        end
-      end
-
-      # INC and DEC on a pair, which touch no flags.
-      def step_pair(row)
-        @cycles += 2
-        index = row >> 1
-        set_pair(index, (pair(index) + (row.nobits?(1) ? 1 : -1)) & 0xffff)
-      end
-
-      def add_pair(index)
-        self.hl_or_index = add16(hl_or_index, pair(index))
-        @cycles += 7
-      end
-
-      def accumulator_operation(row)
-        case row
-        when 0, 1, 2, 3 then rotate_a(row)
-        when 4 then daa
-        when 5 then complement
-        when 6 then assign_flags((@f & (SF | ZF | PF)) | CF | (((@last_q ^ @f) | @a) & XYF))
-        else assign_flags((@f & (SF | ZF | PF)) | ((@f & CF) << 4) | ((@f & CF) ^ CF) | (((@last_q ^ @f) | @a) & XYF))
-        end
-      end
-
-      def complement
-        @a ^= 0xff
-        assign_flags((@f & (SF | ZF | PF | CF)) | HF | NF | (@a & XYF))
-      end
-
-      def miscellaneous(row)
-        case row
-        when 0 then jump(true)
-        when 1 then @prefix.zero? ? execute_bits(fetch_opcode) : execute_index_bits
-        when 2 then output_immediate
-        when 3 then input_immediate
-        when 4 then exchange_stack_top
-        when 5 then exchange_de_hl
-        when 6 then @iff1 = @iff2 = false
-        else enable_interrupts
-        end
-      end
-
-      def call_or_prefix(index)
-        case index
-        when 0 then call(true)
-        when 1 then index_prefix(1)
-        when 2 then extended_prefix
-        else index_prefix(2)
-        end
-      end
-
-      # DD and FD: the next opcode runs with IX or IY for HL. A prefix
-      # after a prefix replaces it.
-      def index_prefix(prefix)
-        @prefix = prefix
-        @last_q = 0
-        execute(fetch_opcode)
-      end
-
-      def extended_prefix
-        @prefix = 0
-        execute_extended(fetch_opcode)
-      end
-
-      def enable_interrupts
-        @iff1 = @iff2 = true
-        @after_ei = true
-      end
-    end
-  end
-end

data/lib/badline/z80/registers.rb

@@ -1,120 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  class Z80
-    # The register file. Opcodes name 8-bit registers by a 3-bit index,
-    # B C D E H L (HL) A, and pairs by a 2-bit one, BC DE HL SP, or BC DE
-    # HL AF for PUSH and POP. After a DD or FD prefix, HL means IX or IY
-    # and H and L their halves, except beside an (IX+d) operand.
-    module Registers
-      attr_accessor :a, :f, :b, :c, :d, :e, :h, :l, :i, :r, :pc, :sp, :ix, :iy, :wz, :im, :q,
-                    :af_alt, :bc_alt, :de_alt, :hl_alt, :iff1, :iff2, :halted, :after_ei, :after_ld_a_ir
-
-      def af = (@a << 8) | @f
-      def bc = (@b << 8) | @c
-      def de = (@d << 8) | @e
-      def hl = (@h << 8) | @l
-
-      def af=(value)
-        @a = value >> 8
-        @f = value & 0xff
-      end
-
-      def bc=(value)
-        @b = value >> 8
-        @c = value & 0xff
-      end
-
-      def de=(value)
-        @d = value >> 8
-        @e = value & 0xff
-      end
-
-      def hl=(value)
-        @h = value >> 8
-        @l = value & 0xff
-      end
-
-      private
-
-      def register(index)
-        case index
-        when 0 then @b
-        when 1 then @c
-        when 2 then @d
-        when 3 then @e
-        when 4 then @prefix.zero? ? @h : index_register >> 8
-        when 5 then @prefix.zero? ? @l : index_register & 0xff
-        else @a
-        end
-      end
-
-      def set_register(index, value)
-        case index
-        when 0 then @b = value
-        when 1 then @c = value
-        when 2 then @d = value
-        when 3 then @e = value
-        when 4 then @prefix.zero? ? @h = value : self.index_register = (index_register & 0xff) | (value << 8)
-        when 5 then @prefix.zero? ? @l = value : self.index_register = (index_register & 0xff00) | value
-        else @a = value
-        end
-      end
-
-      # The register an (HL) or (IX+d) operand sits beside: H and L are
-      # always themselves.
-      def plain_register(index)
-        case index
-        when 4 then @h
-        when 5 then @l
-        else register(index)
-        end
-      end
-
-      def set_plain_register(index, value)
-        case index
-        when 4 then @h = value
-        when 5 then @l = value
-        else set_register(index, value)
-        end
-      end
-
-      def pair(index)
-        case index
-        when 0 then bc
-        when 1 then de
-        when 2 then hl_or_index
-        else @sp
-        end
-      end
-
-      def set_pair(index, value)
-        case index
-        when 0 then self.bc = value
-        when 1 then self.de = value
-        when 2 then self.hl_or_index = value
-        else @sp = value
-        end
-      end
-
-      # The pairs PUSH and POP name, with AF in place of SP.
-      def stack_pair(index) = index == 3 ? af : pair(index)
-
-      def set_stack_pair(index, value)
-        index == 3 ? self.af = value : set_pair(index, value)
-      end
-
-      def hl_or_index = @prefix.zero? ? hl : index_register
-
-      def hl_or_index=(value)
-        @prefix.zero? ? self.hl = value : self.index_register = value
-      end
-
-      def index_register = @prefix == 1 ? @ix : @iy
-
-      def index_register=(value)
-        @prefix == 1 ? @ix = value : @iy = value
-      end
-    end
-  end
-end

data/lib/badline/z80/saved_state.rb

@@ -1,69 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  class Z80
-    # The registers, the T-state count and the interrupt latches for a
-    # snapshot, taken between instructions.
-    module SavedState
-      def save_state(out)
-        out.marker("Z80")
-        out.int(@a).int(@f).int(@b).int(@c).int(@d).int(@e).int(@h).int(@l)
-        out.int(@af_alt).int(@bc_alt).int(@de_alt).int(@hl_alt)
-        out.int(@i).int(@r).int(@pc).int(@sp).int(@ix).int(@iy).int(@wz).int(@q).int(@last_q).int(@im)
-        out.int(@cycles)
-        out.boolean(@iff1).boolean(@iff2).boolean(@halted).boolean(@after_ei).boolean(@after_ld_a_ir)
-        out.boolean(@int).boolean(@nmi).boolean(@nmi_pending)
-      end
-
-      def load_state(input)
-        input.marker("Z80")
-        load_main_registers(input)
-        @af_alt = input.int
-        @bc_alt = input.int
-        @de_alt = input.int
-        @hl_alt = input.int
-        load_special_registers(input)
-        @cycles = input.int
-        load_latches(input)
-        @prefix = 0
-      end
-
-      private
-
-      def load_main_registers(input)
-        @a = input.int
-        @f = input.int
-        @b = input.int
-        @c = input.int
-        @d = input.int
-        @e = input.int
-        @h = input.int
-        @l = input.int
-      end
-
-      def load_special_registers(input)
-        @i = input.int
-        @r = input.int
-        @pc = input.int
-        @sp = input.int
-        @ix = input.int
-        @iy = input.int
-        @wz = input.int
-        @q = input.int
-        @last_q = input.int
-        @im = input.int
-      end
-
-      def load_latches(input)
-        @iff1 = input.boolean?
-        @iff2 = input.boolean?
-        @halted = input.boolean?
-        @after_ei = input.boolean?
-        @after_ld_a_ir = input.boolean?
-        @int = input.boolean?
-        @nmi = input.boolean?
-        @nmi_pending = input.boolean?
-      end
-    end
-  end
-end

data/lib/badline/z80/shifts.rb

@@ -1,64 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  class Z80
-    # Rotates, shifts and the bit operations.
-    module Shifts
-      private
-
-      # RLCA RRCA RLA RRA, which leave S, Z and P/V alone.
-      def rotate_a(operation)
-        carry = operation.even? ? @a >> 7 : @a & 1
-        @a = shifted(operation, @a, carry)
-        assign_flags((@f & (SF | ZF | PF)) | (@a & XYF) | carry)
-      end
-
-      # The CB page's rotates and shifts by bits 5-3: RLC RRC RL RR SLA SRA
-      # SLL SRL. SLL shifts a 1 in.
-      def shift(operation, value)
-        carry = operation.even? ? value >> 7 : value & 1
-        result = shifted(operation, value, carry)
-        assign_flags(SZ53P[result] | carry)
-        result
-      end
-
-      def shifted(operation, value, carry)
-        case operation
-        when 0 then ((value << 1) | carry) & 0xff
-        when 1 then (value >> 1) | (carry << 7)
-        when 2 then ((value << 1) | (@f & CF)) & 0xff
-        when 3 then (value >> 1) | ((@f & CF) << 7)
-        when 4 then (value << 1) & 0xff
-        when 5 then (value >> 1) | (value & 0x80)
-        when 6 then ((value << 1) | 1) & 0xff
-        else value >> 1
-        end
-      end
-
-      # BIT n tests a bit of +value+ and copies bits 5 and 3 from +source+:
-      # the operand for a register, WZ's high byte for a memory operand.
-      def bit(number, value, source)
-        tested = value & (1 << number)
-        flags = (@f & CF) | HF | (source & XYF) | (tested & SF)
-        flags |= ZF | PF if tested.zero?
-        assign_flags(flags)
-      end
-
-      # RRD and RLD rotate a digit through A and (HL).
-      def rotate_digits(left)
-        address = hl
-        value = read_byte(address)
-        @cycles += 4
-        if left
-          write_byte(address, ((value << 4) | (@a & 0x0f)) & 0xff)
-          @a = (@a & 0xf0) | (value >> 4)
-        else
-          write_byte(address, ((@a << 4) | (value >> 4)) & 0xff)
-          @a = (@a & 0xf0) | (value & 0x0f)
-        end
-        @wz = (address + 1) & 0xffff
-        assign_flags((@f & CF) | SZ53P[@a])
-      end
-    end
-  end
-end

data/lib/badline/z80.rb

@@ -1,11 +0,0 @@
-# frozen_string_literal: true
-
-require "badline/z80/core"
-
-module Badline
-  # The Zilog Z80 (NMOS), which the C128 has beside its 8502. It is not
-  # part of badline/core, so a machine that has one requires it.
-  class Z80
-    include Core
-  end
-end