badline 0.12.0 → 0.13.0

data/lib/badline/c64/cartridge/bank.rb

@@ -0,0 +1,83 @@
+# frozen_string_literal: true
+
+module Badline
+  class C64
+    class Cartridge
+      # One 8K bank of cartridge ROM. The chip decodes only the low address
+      # lines, so the same bank answers at $8000, $A000 or $E000, and a smaller
+      # chip mirrors across the window.
+      class Bank
+        def initialize(data)
+          size = [1 << (data.length - 1).bit_length, 1].max
+          @mask = size - 1
+          @data = (data + ([0xff] * (size - data.length))).freeze
+        end
+
+        def peek(addr)
+          @data[addr & @mask]
+        end
+        alias [] peek
+      end
+
+      # Cartridge RAM mapped into the ROML or ROMH window. Writes land in the
+      # C64's RAM underneath as well, when there is a backing. Banks built on
+      # the same data are views of the same RAM.
+      class RAMBank
+        attr_reader :data
+        attr_writer :backing
+
+        def initialize(data = Array.new(BANK_SIZE, 0))
+          @data = data
+          @backing = nil
+        end
+
+        def peek(addr)
+          @data[addr & 0x1fff]
+        end
+        alias [] peek
+
+        def poke(addr, value)
+          @data[addr & 0x1fff] = value
+          @backing&.poke(addr, value)
+        end
+        alias []= poke
+      end
+
+      # Cartridge RAM the window reads, where the cartridge ignores writes.
+      class RAMReader
+        def initialize(data)
+          @data = data
+        end
+
+        def peek(addr)
+          @data[addr & 0x1fff]
+        end
+        alias [] peek
+      end
+
+      # Cartridge RAM that takes writes while the window reads something else.
+      class WriteOnlyRAM < RAMBank
+        def initialize(data, reader)
+          super(data)
+          @reader = reader
+        end
+
+        def peek(addr)
+          @reader.peek(addr)
+        end
+        alias [] peek
+      end
+
+      # Cartridge RAM selected together with the C64's RAM, both driving the
+      # bus on a read. The result is ORed, as VICE has it.
+      class ContendedRAM < RAMBank
+        def peek(addr)
+          @data[addr & 0x1fff] | @backing.peek(addr)
+        end
+        alias [] peek
+      end
+
+      EMPTY_BANK = Bank.new([0xff])
+    end
+  end
+end

data/lib/badline/c64/cartridge/comal80.rb

@@ -0,0 +1,52 @@
+# frozen_string_literal: true
+
+module Badline
+  class C64
+    class Cartridge
+      # Comal-80: four 16K banks, or eight with the extra ROMs. A write to
+      # I/O 1 selects the bank and the memory configuration. The black board
+      # (subtype 0) takes the bank from bits 0-2 and switches the ROM out with
+      # bit 6; the grey one (subtype 1) takes the bank from bits 0-1 and the
+      # configuration from bits 5-6.
+      class Comal80 < Cartridge
+        GREY_MODES = %i[rom16k ultimax rom8k off].freeze
+
+        def initialize(crt)
+          @grey = crt.subtype == 1
+          super
+        end
+
+        def poke(addr, value)
+          return if addr > 0xdeff
+
+          if @grey
+            select(value & 0x03, GREY_MODES[(value >> 5) & 0x03])
+          else
+            select(value & 0x07, value.anybits?(0x40) ? :off : :rom16k)
+          end
+          changed!
+        end
+
+        def reset
+          select(0, :rom16k)
+          changed!
+        end
+
+        private
+
+        def windows = [*@roml_banks, *@romh_banks, EMPTY_BANK]
+
+        def select(number, mode)
+          @roml = bank(@roml_banks, number)
+          @romh = bank(@romh_banks, number)
+          self.mode = mode
+        end
+
+        def install_chips(chips)
+          @roml_banks, @romh_banks = banks_from(chips)
+          reset
+        end
+      end
+    end
+  end
+end

data/lib/badline/c64/cartridge/dinamic.rb

@@ -0,0 +1,36 @@
+# frozen_string_literal: true
+
+module Badline
+  class C64
+    class Cartridge
+      # Dinamic: up to 16 8K banks. Reading $DE00-$DE0F selects the bank from
+      # the low address bits.
+      class Dinamic < Cartridge
+        def readable_io_pages
+          [0xde]
+        end
+
+        def peek(addr)
+          if addr < 0xde10
+            @roml = bank(@banks, addr & 0x0f)
+            changed!
+          end
+          open_bus(addr)
+        end
+
+        def reset
+          @roml = bank(@banks, 0)
+          changed!
+        end
+
+        private
+
+        def install_chips(chips)
+          @banks = banks_from(chips).first
+          self.mode = :rom8k
+          reset
+        end
+      end
+    end
+  end
+end

data/lib/badline/c64/cartridge/easy_flash.rb

@@ -0,0 +1,147 @@
+# frozen_string_literal: true
+
+module Badline
+  class C64
+    class Cartridge
+      # EasyFlash: two Am29F040B flash chips, one for ROML and one for ROMH,
+      # each 64 banks of 8K, and 256 bytes of RAM at $DF00. $DE00 selects the
+      # bank. $DE02 sets the memory configuration: bit 2 hands the GAME line
+      # to bit 0 (otherwise the boot jumper holds it low), bit 1 pulls EXROM
+      # low and bit 7 drives the LED.
+      #
+      # The flash takes writes in Ultimax mode, at $8000 for ROML and $E000
+      # for ROMH, which is how EAPI programs and erases it. The writes stay in
+      # memory; #save_crt writes the flash out as a new image.
+      #
+      # An image built for EasyFlash carries an EAPI, the flash driver, at $B800
+      # in bank 0 of ROMH. On attach, as in VICE, the bundled Am29F040 EAPI
+      # (roms/eapi) takes its place, so the image drives the flash emulated here.
+      class EasyFlash < Cartridge
+        BANKS = 64
+        EAPI_OFFSET = 0x1800
+
+        def self.eapi
+          @eapi ||= ROM.read("eapi/eapi-am29f040-14").drop(2).freeze
+        end
+
+        attr_reader :low_flash, :high_flash
+
+        def clock=(clock)
+          super
+          [@low_flash, @high_flash].each { |flash| flash.clock = clock }
+        end
+
+        def readable_io_pages
+          [0xdf]
+        end
+
+        def peek(addr)
+          @io_ram[addr & 0xff]
+        end
+
+        def poke(addr, value)
+          if addr >= 0xdf00
+            @io_ram[addr & 0xff] = value
+          elsif addr.nobits?(0x02)
+            @bank = value & 0x3f
+            select_bank
+          else
+            @control = value & 0x87
+            apply_control
+            changed!
+          end
+        end
+
+        def led?
+          @control.anybits?(0x80)
+        end
+
+        # Reset clears both registers, and leaves the flash and the RAM.
+        def reset
+          @bank = 0
+          @control = 0
+          apply_control
+          select_bank
+        end
+
+        # Writes every bank that isn't blank to a CRT image at path.
+        def save_crt(path)
+          chips = (0...BANKS).flat_map do |number|
+            [[@low_flash, 0x8000], [@high_flash, 0xa000]].filter_map do |flash, address|
+              data = flash.data[number * BANK_SIZE, BANK_SIZE]
+              Storage::CRTFile::Chip.new(chip_type: 2, bank: number, address:, data:) if data.any?(0..0xfe)
+            end
+          end
+          image = Storage::CRTFile::Image.new(hardware_type: 32, subtype: 0, exrom: 1, game: 0, name:, chips:)
+          Storage::CRTFile.write(path, image)
+        end
+
+        private
+
+        def select_bank
+          map_bank
+          changed!
+        end
+
+        def map_bank
+          @roml = @low_flash.window(@bank * BANK_SIZE)
+          @romh = @high_flash.window(@bank * BANK_SIZE)
+        end
+
+        def save_mapper(out)
+          out.int(@bank).int(@control).blob(@io_ram)
+          @low_flash.save_state(out)
+          @high_flash.save_state(out)
+        end
+
+        def load_mapper(input)
+          @bank = input.int
+          @control = input.int
+          input.blob_into(@io_ram)
+          @low_flash.load_state(input)
+          @high_flash.load_state(input)
+          map_bank
+        end
+
+        def apply_control
+          game = @control.nobits?(0x04) || @control.anybits?(0x01)
+          exrom = @control.anybits?(0x02)
+          @game = game ? 0 : 1
+          @exrom = exrom ? 0 : 1
+        end
+
+        def install_chips(chips)
+          low = Array.new(BANKS * BANK_SIZE, 0xff)
+          high = Array.new(BANKS * BANK_SIZE, 0xff)
+          chips.each do |chip|
+            offset = (chip.bank & 0x3f) * BANK_SIZE
+            if chip.address >= ROMH_START
+              place(high, offset, chip.data)
+            else
+              place(low, offset, chip.data)
+              place(high, offset, chip.data[BANK_SIZE..]) if chip.data.length > BANK_SIZE
+            end
+          end
+          install_eapi(high)
+          @low_flash = Flash.new(low)
+          @high_flash = Flash.new(high)
+          [@low_flash, @high_flash].each { |flash| flash.on_change { select_bank } }
+          @io_ram = Array.new(0x100, 0xff)
+          reset
+        end
+
+        def install_eapi(high)
+          return unless high[EAPI_OFFSET, 4] == "eapi".bytes
+
+          eapi = EasyFlash.eapi
+          high[EAPI_OFFSET, eapi.length] = eapi
+        end
+
+        def place(flash_data, offset, bytes)
+          bytes = bytes.first(BANK_SIZE)
+          flash_data[offset, bytes.length] = bytes
+        end
+      end
+    end
+  end
+end

data/lib/badline/c64/cartridge/epyx_fastload.rb

@@ -0,0 +1,81 @@
+# frozen_string_literal: true
+
+module Badline
+  class C64
+    class Cartridge
+      # Epyx FastLoad: 8K. A capacitor holds the ROM in for 512 cycles after
+      # it was last discharged, by reset, a read through ROML or a read of
+      # I/O 1; once it charges, $8000-$9FFF reads RAM. I/O 2 reads the last
+      # 256 bytes of the ROM.
+      class EpyxFastload < Cartridge
+        DISCHARGED_CYCLES = 512
+
+        class Window
+          def initialize(cartridge, rom)
+            @cartridge = cartridge
+            @rom = rom
+          end
+
+          def peek(addr)
+            @cartridge.rom_visible? ? @rom.peek(addr) : @cartridge.ram_peek(addr)
+          end
+        end
+
+        def clock=(clock)
+          super
+          discharge!
+        end
+
+        def readable_io_pages
+          [0xde, 0xdf]
+        end
+
+        def peek(addr)
+          return @rom.peek(addr) if addr >= 0xdf00
+
+          discharge!
+          open_bus(addr)
+        end
+
+        # True while the capacitor holds the ROM in, discharging it again.
+        def rom_visible?
+          return true unless @clock
+          return false if @clock.call - @discharged_at >= DISCHARGED_CYCLES
+
+          discharge!
+          true
+        end
+
+        def ram_peek(addr)
+          @ram.peek(addr)
+        end
+
+        # Reset discharges the capacitor, so the ROM shows.
+        def reset
+          discharge!
+        end
+
+        private
+
+        def save_mapper(out)
+          out.int(@discharged_at)
+        end
+
+        def load_mapper(input)
+          @discharged_at = input.int
+        end
+
+        def discharge!
+          @discharged_at = @clock ? @clock.call : 0
+        end
+
+        def install_chips(chips)
+          @rom = banks_from(chips).first.compact.first || EMPTY_BANK
+          @roml = Window.new(self, @rom)
+          @discharged_at = 0
+          self.mode = :rom8k
+        end
+      end
+    end
+  end
+end

data/lib/badline/c64/cartridge/final_cartridge3.rb

@@ -0,0 +1,91 @@
+# frozen_string_literal: true
+
+module Badline
+  class C64
+    class Cartridge
+      # The Final Cartridge III: four 16K banks, or sixteen on the III+. I/O 1
+      # and I/O 2 show the last two pages of the selected ROML bank. A write
+      # to $DFFF sets the register:
+      #
+      #   bits 0-1 bank (0-3 on the III+)
+      #   bit 4    EXROM level
+      #   bit 5    GAME level
+      #   bit 6    NMI line, active low
+      #   bit 7    hides the register until the next freeze
+      #
+      # Clearing bit 6 pulls NMI without freezing, and setting it lets go of
+      # NMI after a freeze. A freeze keeps the bank and switches to Ultimax,
+      # which the VIC doesn't see until the register sets it again.
+      class FinalCartridge3 < Cartridge
+        include Freezer
+
+        REGISTER = 0xdfff
+
+        def readable_io_pages
+          [0xde, 0xdf]
+        end
+
+        def peek(addr)
+          @io_bank.peek(addr)
+        end
+
+        def poke(addr, value)
+          return unless addr == REGISTER && @register_visible
+
+          @register_visible = value.nobits?(0x80)
+          self.nmi = value.nobits?(0x40)
+          select(value & @bank_mask)
+          @exrom = (value >> 4) & 0x01
+          @game = (value >> 5) & 0x01
+          @phi1_ultimax = ultimax?
+          changed!
+        end
+
+        def phi1_ultimax?
+          @phi1_ultimax
+        end
+
+        def reset
+          @register_visible = true
+          @phi1_ultimax = false
+          self.nmi = false
+          select(0)
+          select_mode(:rom16k)
+        end
+
+        def freeze!
+          @register_visible = true
+          @phi1_ultimax = false
+          select_mode(:ultimax)
+        end
+
+        private
+
+        def save_mapper(out)
+          super
+          out.boolean(@register_visible).boolean(@phi1_ultimax)
+        end
+
+        def load_mapper(input)
+          super
+          @io_bank = @roml
+          @register_visible = input.boolean?
+          @phi1_ultimax = input.boolean?
+        end
+
+        def windows = [*@roml_banks, *@romh_banks, EMPTY_BANK]
+
+        def select(number)
+          @io_bank = @roml = bank(@roml_banks, number)
+          @romh = bank(@romh_banks, number)
+        end
+
+        def install_chips(chips)
+          @roml_banks, @romh_banks = banks_from(chips)
+          @bank_mask = @roml_banks.length > 4 ? 0x0f : 0x03
+          reset
+        end
+      end
+    end
+  end
+end

data/lib/badline/c64/cartridge/flash/saved_state.rb

@@ -0,0 +1,40 @@
+# frozen_string_literal: true
+
+module Badline
+  class C64
+    class Cartridge
+      class Flash
+        # A Flash chip's state, for a snapshot.
+        module SavedState
+          STATES = %i[read program_setup autoselect programming erase_window erasing suspended chip_erase
+                      program_error].freeze
+
+          # The array, the command state, a timed operation's end on the
+          # machine's clock, and the windows handed out so far, which load_state
+          # builds anew.
+          def save_state(out)
+            out.blob(@data).int(STATES.index(@state)).int(STATES.index(@base_state)).int(@cycle).int(@toggle)
+            out.optional_int(@done_at).optional_int(@programmed).optional_int(@remaining)
+            out.boolean(!@erasing_sectors.nil?)
+            out.ints(@erasing_sectors) if @erasing_sectors
+            out.ints(@windows.keys).ints(@status_windows.keys)
+          end
+
+          def load_state(input)
+            input.blob_into(@data)
+            @state = STATES.fetch(input.int).to_sym
+            @base_state = STATES.fetch(input.int).to_sym
+            @cycle = input.int
+            @toggle = input.int
+            @done_at = input.optional_int
+            @programmed = input.optional_int
+            @remaining = input.optional_int
+            @erasing_sectors = nil
+            @erasing_sectors = input.ints if input.boolean?
+            rebuild_windows(input.ints, input.ints)
+          end
+        end
+      end
+    end
+  end
+end