badline 0.12.0 → 0.13.0

data/lib/badline/sid.rb

@@ -1,303 +0,0 @@
-# frozen_string_literal: true
-
-require "badline/sid/waveform"
-require "badline/sid/envelope"
-require "badline/sid/voice"
-require "badline/sid/filter"
-require "badline/sid/decimator"
-require "badline/sid/catch_up"
-
-module Badline
-  # SID (Sound Interface Device) chip, in either the 6581 or the 8580
-  # revision.
-  #
-  # $D400-$D418 - Voices, filter and volume   - write only
-  # $D419-$D41A - POTX/POTY paddle inputs     - read only
-  # $D41B-$D41C - Voice 3 oscillator/envelope - read only
-  # $D41D-$D41F - Unconnected
-  #
-  # The register file mirrors every 32 bytes up to $D7FF. A second or
-  # third SID, which only the SID player fits, is built `at` another
-  # address and decodes just the 32 bytes there.
-  #
-  # Reading a write-only or unconnected register returns the last byte the
-  # SID saw on the data bus. That value fades to $00 as the capacitance
-  # holding it drains. Paddles and the 1351 mouse attach as a pots source
-  # responding to #pot_x and #pot_y; with none attached the lines read $FF.
-  #
-  # Three voices feed the filter and the master volume; #output and #sample
-  # read out the mixed result, and #record collects it at an audio rate for
-  # #drain_samples. The DSP is clocked lazily and catches up when something
-  # asks for its state.
-  #
-  # The 6581 drives its voices well above ground, so the mix carries a large
-  # DC offset that the RC network on the C64 board filters out.
-  class SID
-    include Addressable
-    include CatchUp
-
-    VOICES = 3
-
-    # Cycles the data bus holds a value, measured through SID/bitfade.
-    BUS_TTL = { mos6581: 0x1d00, mos8580: 0xa2000 }.freeze
-
-    # Scales the filter's 20-bit mix down to a signed 16-bit sample, as
-    # reSID 0.16 does: three voices at full swing and volume 15 span the
-    # whole range, on either chip.
-    SAMPLE_DIVISOR = ((0xfff * 0xff) >> 7) * 3 * 15 * 2 / (2**16)
-
-    # Writes the DSP queues between catch-ups. A full queue catches up
-    # there and then, so no write loses its timing.
-    DEFERRED_WRITES = 0x400
-
-    # Cycles the filter integrates in one step while synthesizing, after
-    # reSID's delta_t_flt. 1 makes the audio exact, at a per-cycle cost.
-    FILTER_CHUNK = 4
-
-    attr_accessor :pots
-    attr_reader :model
-
-    def initialize(model: :mos6581, pots: nil, filter_chunk: FILTER_CHUNK, at: 0xd400)
-      addressable_at(at, length: at == 0xd400 ? 2**10 : 2**5)
-      @model = model
-      @pots = pots
-      @bus_ttl_reset = BUS_TTL.fetch(model)
-      @filter = Filter.new(model:)
-      @synthesizing = false
-      @stepped = @synced = false
-      @pending_cycles = 0
-      @deferred_writes = []
-      @decimator = nil
-      @samples = []
-      @voice_samples = nil
-      @filter_chunk = filter_chunk
-      @voices = Voice.linked(VOICES, model:)
-      @voice1, @voice2, @voice3 = @voices
-      @waveform1, @waveform2, @waveform3 = @voices.map(&:waveform)
-      reset!
-    end
-
-    # Switches the chip, its filter and its voices to the other model's
-    # values. The cycles already passed run on the old model first, and the
-    # running state carries over.
-    def model=(model)
-      catch_up
-      @model = model
-      @bus_ttl_reset = BUS_TTL.fetch(model)
-      @filter.model = model
-      @voices.each { |voice| voice.model = model }
-      update_span_rules
-    end
-
-    # The RES line clears the registers, the data bus, the filter and the
-    # voices, all but their accumulators. Recording carries on across it.
-    def reset!
-      catch_up
-      @registers = Memory.new(length: 2**5)
-      @bus_value = 0x00
-      @bus_ttl = 0
-      @voices.each(&:reset!)
-      @filter.reset
-      update_span_rules
-    end
-
-    # The DSP only counts cycles as they pass. Whatever asks for its state
-    # catches it up, a span at a time: each span fast-forwards the voices
-    # and ends on one whole cycle, so everything the CPU can read stays
-    # exact. The filter only runs once something wants audio.
-    def synthesizing? = @synthesizing
-
-    def synthesize!
-      return if @synthesizing
-
-      @synthesizing = true
-      update_span_rules
-      catch_up
-    end
-
-    # Starts collecting the output, averaged down to `rate` samples a
-    # second, for #drain_samples. `filter_chunk` overrides the one the SID
-    # was built with, for a machine that built its own. `clock_hz` is the
-    # rate the SID's cycles are taken to run at.
-    def record(rate:, filter_chunk: @filter_chunk, clock_hz: TimeOfDay::CLOCK_HZ)
-      synthesize!
-      catch_up
-      @filter_chunk = filter_chunk
-      @decimator = Decimator.new(clock_hz:, rate:)
-      @samples = []
-    end
-
-    # How far the recording has got into the sample it is averaging, for
-    # a host that carries on recording from a saved state: it calls
-    # #record, then #load_recording.
-    def save_recording(out)
-      decimator = @decimator
-      raise ArgumentError, "the SID isn't recording" if decimator.nil?
-
-      out.marker("RECORDING")
-      decimator.save_state(out)
-    end
-
-    def load_recording(input)
-      decimator = @decimator
-      raise ArgumentError, "the SID isn't recording" if decimator.nil?
-
-      input.marker("RECORDING")
-      decimator.load_state(input)
-    end
-
-    # Also keeps each voice's own output, before the filter and the volume,
-    # as each recorded sample closes, for #drain_voice_samples.
-    def record_voices!
-      @voice_samples = [] if @voice_samples.nil?
-    end
-
-    # The voices' outputs since the last drain, three to a sample, in voice
-    # order, or nothing unless #record_voices! asked for them.
-    def drain_voice_samples
-      return [] if @voice_samples.nil?
-
-      catch_up
-      samples = @voice_samples
-      @voice_samples = []
-      samples
-    end
-
-    # The samples recorded since the last drain.
-    def drain_samples
-      catch_up
-      samples = @samples
-      @samples = []
-      samples
-    end
-
-    def voices
-      catch_up
-      @voices
-    end
-
-    # Runs the DSP up to the current cycle.
-    def catch_up! = catch_up
-
-    # The byte the data bus holds and the cycles until it fades.
-    def bus_state = [@bus_value, @bus_ttl]
-
-    def restore_bus(value, ttl)
-      @bus_value = value
-      @bus_ttl = ttl
-    end
-
-    def filter
-      catch_up
-      @filter
-    end
-
-    # Voice 3's oscillator and envelope, the only synthesis state the CPU
-    # can see. Programs poll OSC3 with the noise waveform selected for
-    # random numbers, and ENV3 to time hard restarts.
-    def osc3
-      catch_up
-      @waveform3.osc3 >> 4
-    end
-
-    def env3
-      catch_up
-      @voice3.envelope.env3
-    end
-
-    def output
-      synthesize!
-      catch_up
-      @filter.output
-    end
-
-    def sample
-      output
-      current_sample
-    end
-
-    def cycle!
-      age_bus if @bus_ttl != 0
-      @pending_cycles += 1
-    end
-
-    def peek(addr)
-      case offset_of(addr) % (2**5)
-      when 0x19 then latch(pots ? pots.pot_x : 0xff)
-      when 0x1a then latch(pots ? pots.pot_y : 0xff)
-      when 0x1b then latch(osc3)
-      when 0x1c then latch(env3)
-      else @bus_value
-      end
-    end
-
-    def poke(addr, value)
-      reg = offset_of(addr) % (2**5)
-      write_register(reg, value) if reg <= 0x18
-      latch(value)
-    end
-
-    # Register contents as written, for save states and debugging.
-    def register(reg) = @registers.peek(reg)
-
-    # The registers, the data bus, the voices and the filter, and the span
-    # the DSP has yet to catch up on, as it stands: saving leaves the SID
-    # as it was. Whether it synthesizes or records is the host's.
-    def save_state(out)
-      out.marker("SID")
-      @registers.save_state(out)
-      out.int(@bus_value).int(@bus_ttl).int(@pending_cycles).ints(@deferred_writes)
-      @voices.each { |voice| voice.save_state(out) }
-      @filter.save_state(out)
-    end
-
-    def load_state(input)
-      input.marker("SID")
-      @registers.load_state(input)
-      @bus_value = input.int
-      @bus_ttl = input.int
-      @pending_cycles = input.int
-      input.ints_into(@deferred_writes)
-      @voices.each { |voice| voice.load_state(input) }
-      @filter.load_state(input)
-      update_span_rules
-    end
-
-    private
-
-    def latch(value)
-      @bus_ttl = @bus_ttl_reset
-      @bus_value = value
-    end
-
-    def age_bus
-      @bus_ttl -= 1
-      @bus_value = 0x00 if @bus_ttl.zero?
-    end
-
-    def write_register(reg, value)
-      @registers.poke(reg, value)
-      catch_up if @deferred_writes.length == DEFERRED_WRITES * 3
-      @deferred_writes.push(@pending_cycles, reg, value)
-    end
-
-    def apply_write(reg, value)
-      reg < 0x15 ? write_voice(reg, value) : @filter.write(reg, value)
-    end
-
-    def write_voice(reg, value)
-      voice = @voices[reg / 7]
-      case reg % 7
-      when 0 then voice.waveform.frequency_low = value
-      when 1 then voice.waveform.frequency_high = value
-      when 2 then voice.waveform.pulse_width_low = value
-      when 3 then voice.waveform.pulse_width_high = value
-      when 4
-        voice.control = value
-        update_span_rules
-      when 5 then voice.envelope.attack_decay = value
-      when 6 then voice.envelope.sustain_release = value
-      end
-    end
-  end
-end

data/lib/badline/time_of_day.rb

@@ -1,228 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  class TimeOfDay
-    # The TOD pin is fed from the AC supply. A CIA passes its region's
-    # clock and mains frequency, and these are PAL's.
-    CLOCK_HZ = Region::PAL.clock_hz
-    MAINS_HZ = Region::PAL.mains_hz
-
-    FIELDS = %i[tenths seconds minutes hours].freeze
-
-    def initialize(clock_hz: CLOCK_HZ, mains_hz: MAINS_HZ)
-      # The accumulator advances mains_hz per cycle, so a TOD pin pulse has
-      # arrived when it reaches clock_hz. Integer math keeps it exact.
-      @cycles_per_pulse = clock_hz
-      @mains_hz = mains_hz
-      @accumulator = 0
-      @pulses = 0
-      @clock = { tenths: 0x00, seconds: 0x00, minutes: 0x00, hours: 0x01 }
-      @alarm = { tenths: 0x00, seconds: 0x00, minutes: 0x00, hours: 0x00 }
-      @latch = nil
-      @stopped = true
-      @alarm_pending = false
-      self.fifty_hz = false
-    end
-
-    # CRA bit 7 divides the TOD pin by 5 instead of 6. The divider has to
-    # match the pin frequency to keep time, so PAL software selects 50 Hz.
-    def fifty_hz=(enabled)
-      @match = enabled ? 4 : 5
-    end
-
-    # The clock and the alarm, field by field in FIELDS order, the latch,
-    # and the divider's phase.
-    def save_state(out)
-      out.int(@accumulator).int(@pulses).int(@match).boolean(@stopped).boolean(@alarm_pending)
-      FIELDS.each { |field| out.int(@clock[field]).int(@alarm[field]) }
-      out.boolean(!@latch.nil?)
-      FIELDS.each { |field| out.int(@latch[field]) } if @latch
-    end
-
-    def load_state(input)
-      @accumulator = input.int
-      @pulses = input.int
-      @match = input.int
-      @stopped = input.boolean?
-      @alarm_pending = input.boolean?
-      FIELDS.each do |field|
-        @clock[field] = input.int
-        @alarm[field] = input.int
-      end
-      @latch = input.boolean? ? FIELDS.to_h { |field| [field, input.int] } : nil
-    end
-
-    # Whether the clock is stopped, or gets no pulses on its pin, with no
-    # alarm to raise, so its cycles move only the divider's phase.
-    def quiet? = (@stopped || @mains_hz.zero?) && !@alarm_pending
-
-    # Runs +cycles+ quiet cycles at once.
-    def fast_forward(cycles)
-      @accumulator = (@accumulator + (cycles * @mains_hz)) % @cycles_per_pulse
-    end
-
-    def cycle!
-      @accumulator += @mains_hz
-      pulse! if @accumulator >= @cycles_per_pulse
-      return unless @alarm_pending
-
-      @alarm_pending = false
-      yield if block_given?
-    end
-
-    def tenths
-      value = (@latch || @clock)[:tenths]
-      @latch = nil
-      value
-    end
-
-    def seconds = (@latch || @clock)[:seconds]
-    def minutes = (@latch || @clock)[:minutes]
-
-    def hours
-      @latch ||= @clock.dup
-      @latch[:hours]
-    end
-
-    attr_reader :pulses
-
-    # The clock as a read of the tenths would see it: the latch while the
-    # clock is latched. In FIELDS order.
-    def latched_fields = FIELDS.map { |field| (@latch || @clock)[field] }
-
-    # The cycles until the clock next steps a tenth, as VICE counts them.
-    def cycles_to_tenth
-      to_pulse = (@cycles_per_pulse - @accumulator + @mains_hz - 1) / @mains_hz
-      to_pulse + ([@match - @pulses, 0].max * @cycles_per_pulse / @mains_hz)
-    end
-
-    # Sets the clock, the alarm and the latch from VICE's fields, in FIELDS
-    # order, the latch nil while unlatched.
-    def restore_fields(clock, alarm, latch)
-      FIELDS.each_with_index do |field, i|
-        @clock[field] = clock[i]
-        @alarm[field] = alarm[i]
-      end
-      @latch = latch && FIELDS.each_with_index.to_h { |field, i| [field, latch[i]] }
-    end
-
-    # Sets whether the clock is stopped, the pulses counted towards the
-    # next tenth and the cycles until it, placing the divider so the tenth
-    # lands then.
-    def restore_divider(stopped, pulses, cycles_to_tenth)
-      @stopped = stopped
-      @pulses = pulses
-      to_pulse = cycles_to_tenth - ([@match - pulses, 0].max * @cycles_per_pulse / @mains_hz)
-      @accumulator = (@cycles_per_pulse - (to_pulse * @mains_hz)).clamp(0, @cycles_per_pulse - 1)
-    end
-
-    # The clock and alarm as stored, read without latching the clock.
-    def registers
-      [@clock[:tenths], @clock[:seconds], @clock[:minutes], @clock[:hours],
-       @alarm[:tenths], @alarm[:seconds], @alarm[:minutes], @alarm[:hours],
-       @stopped ? 1 : 0, @latch ? 1 : 0]
-    end
-
-    def write(field, value, alarm:)
-      # The frequency counter is held clear while the clock is stopped, and
-      # starts counting again from the write to tenths that restarts it.
-      if field == :tenths && !alarm && @stopped
-        @pulses = 0
-        @stopped = false
-      end
-      store(field, value & (field == :tenths ? 0x0f : 0x7f), alarm: alarm)
-    end
-
-    # 12-hour BCD value, bit 7 is the AM/PM flag.
-    def write_hours(value, alarm:)
-      value &= 0x9f
-      # Writing 12 to the hour register flips the AM/PM bit, the same way a
-      # carry into 12 does. Writing the alarm hours does not.
-      value ^= 0x80 if !alarm && (value & 0x1f) == 0x12
-      # Halt the clock when writing hours, so that it doesn't
-      # advance mid-update.
-      @stopped = true unless alarm
-      store(:hours, value, alarm: alarm)
-    end
-
-    private
-
-    def store(field, value, alarm:)
-      target = alarm ? @alarm : @clock
-      return if target[field] == value
-
-      target[field] = value
-      @alarm_pending = true if alarm?
-    end
-
-    def pulse!
-      @accumulator -= @cycles_per_pulse
-      return if @stopped
-
-      # A three-bit ring counter with six states, compared against the
-      # divider on each pin pulse rather than on its way past it.
-      if @pulses == @match
-        @pulses = 0
-        advance
-      else
-        @pulses += 1
-        @pulses = 0 if @pulses > 5
-      end
-    end
-
-    def advance
-      tenths = (@clock[:tenths] + 1) & 0x0f
-      @clock[:tenths] = tenths == 10 ? 0 : tenths
-      carry_seconds if tenths == 10
-      @alarm_pending = true if alarm?
-    end
-
-    def carry_seconds
-      return unless advance_pair(:seconds)
-      return unless advance_pair(:minutes)
-
-      advance_hours
-    end
-
-    # Seconds and minutes hold a four-bit low digit that carries at ten into
-    # a three-bit high digit that carries out at six. Both are plain binary
-    # counters, so out-of-range BCD counts up from where it was written.
-    def advance_pair(field)
-      low = ((@clock[field] & 0x0f) + 1) & 0x0f
-      high = (@clock[field] >> 4) & 0x07
-      carry = false
-
-      if low == 10
-        low = 0
-        high = (high + 1) & 0x07
-        if high == 6
-          high = 0
-          carry = true
-        end
-      end
-
-      @clock[field] = (high << 4) | low
-      carry
-    end
-
-    # The hour runs 9 -> 10 and 12 -> 1 by swapping its two digits, and the
-    # AM/PM bit flips as it passes through 12.
-    def advance_hours
-      pm = @clock[:hours] & 0x80
-      high = (@clock[:hours] >> 4) & 0x01
-      low = @clock[:hours] & 0x0f
-
-      if (high == 1 && low == 2) || (high.zero? && low == 9)
-        low = high
-        high ^= 1
-      else
-        low = (low + 1) & 0x0f
-        pm ^= 0x80 if high == 1 && low == 2
-      end
-
-      @clock[:hours] = pm | (high << 4) | low
-    end
-
-    def alarm? = @clock == @alarm
-  end
-end

data/lib/badline/traps.rb

@@ -1,19 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  module Traps
-    def install_trap(addr, &handler)
-      (@traps ||= {})[addr] = handler
-    end
-
-    def remove_trap(addr)
-      @traps&.delete(addr)
-    end
-
-    private
-
-    def run_traps
-      @traps[@program_counter]&.call if @traps
-    end
-  end
-end

data/lib/badline/via/control_lines.rb

@@ -1,122 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  class VIA
-    # One port's pair of control lines, CA1 and CA2 or CB1 and CB2, set up
-    # by a nibble of the peripheral control register, and their two
-    # interrupt flags. Bit 0 picks the active edge of C1, rising when set.
-    # Bits 3-1 pick the C2 mode:
-    #
-    #   000 input, falling edge    100 handshake output
-    #   001 independent, falling   101 pulse output
-    #   010 input, rising edge     110 low output
-    #   011 independent, rising    111 high output
-    #
-    # A port access clears both flags, but an independent input keeps C2's.
-    # In handshake mode C2 goes low on a port access and back high on the
-    # next active C1 edge. In pulse mode it goes low for the cycle after the
-    # access. Port A handshakes on reads and writes, port B on writes only.
-    class ControlLines
-      attr_reader :control, :c1_high, :c2_high
-
-      # The level driven on C2, high while it is an input.
-      attr_reader :c2_output
-
-      def initialize(interrupts, c1_flag:, c2_flag:, handshake_on_read:)
-        @interrupts = interrupts
-        @c1_flag = c1_flag
-        @c2_flag = c2_flag
-        @handshake_on_read = handshake_on_read
-        @c1_high = @c2_high = true
-        reset!
-      end
-
-      # Back to input mode with both handshake outputs released. The input
-      # levels carry over.
-      def reset!
-        @control = 0
-        @handshake_low = false
-        @pulse = 0
-        drive
-      end
-
-      def control=(nibble)
-        @control = nibble & 0x0f
-        drive
-      end
-
-      # Only the pulse output needs the clock.
-      def pulsing? = @pulse.positive?
-
-      def cycle!
-        @pulse -= 1
-        drive if @pulse.zero?
-      end
-
-      def active_c1_edge?(high) = high == @control.anybits?(0x01)
-
-      # The lines' levels and mode. Which flags they set, and whether reads
-      # handshake, are the port's wiring.
-      def save_state(out)
-        out.int(@control).boolean(@c1_high).boolean(@c2_high).boolean(@handshake_low).int(@pulse).boolean(@c2_output)
-      end
-
-      def load_state(input)
-        @control = input.int
-        @c1_high = input.boolean?
-        @c2_high = input.boolean?
-        @handshake_low = input.boolean?
-        @pulse = input.int
-        @c2_output = input.boolean?
-      end
-
-      # Everything the lines hold, for comparing them at two points.
-      def state = [@control, @c1_high, @c2_high, @handshake_low, @pulse, @c2_output]
-
-      # A new C1 level. An active edge sets the flag and ends a handshake.
-      def c1=(high)
-        return if high == @c1_high
-
-        @c1_high = high
-        return unless active_c1_edge?(high)
-
-        @handshake_low = false
-        drive
-        @interrupts.set(@c1_flag)
-      end
-
-      # A new C2 level. An active edge sets the flag while C2 is an input.
-      def c2=(high)
-        return if high == @c2_high
-
-        @c2_high = high
-        @interrupts.set(@c2_flag) if @control.nobits?(0x08) && high == @control.anybits?(0x04)
-      end
-
-      # A read or write of the handshaking port register.
-      def access!(write)
-        @interrupts.clear(independent? ? @c1_flag : @c1_flag | @c2_flag)
-        return unless write || @handshake_on_read
-
-        case @control >> 1
-        when 4 then @handshake_low = true
-        when 5 then @pulse = 2
-        end
-        drive
-      end
-
-      private
-
-      def independent? = @control & 0x0a == 0x02
-
-      def drive
-        @c2_output = case @control >> 1
-                     when 4 then !@handshake_low
-                     when 5 then @pulse.zero?
-                     when 6 then false
-                     else true
-                     end
-      end
-    end
-  end
-end