badline 0.12.0 → 0.13.0

data/lib/badline/reu.rb

@@ -1,289 +0,0 @@
-# frozen_string_literal: true
-
-require "badline/reu/ram"
-require "badline/reu/dma"
-require "badline/reu/trigger"
-require "badline/reu/saved_state"
-
-module Badline
-  # A RAM Expansion Unit: the Commodore 1700 (128K), 1764 (256K) and 1750
-  # (512K), and the bigger units built around the same 8726 RAM Expansion
-  # Controller (REC), such as the CMD 1750XL, up to 16M.
-  #
-  # The REC's eleven registers sit in I/O 2 from $DF00, repeated every 32
-  # bytes up to $DFFF, as the 1764 and 1750 manuals map them. It moves
-  # bytes between the C64 and its RAM by DMA, one bus cycle each, with the
-  # CPU held off the bus. A command with the execute bit set starts a
-  # transfer, or with bit 4 clear arms the REC to start one on the next
-  # write to $FF00, so a program can bank the ROMs out first. A transfer
-  # waits for the CPU's next read cycle with BA high, and Computer then
-  # clocks it through #dma_cycle! until it hands the bus back.
-  class REU
-    include SavedState
-
-    SIZES_KB = [128, 256, 512, 1024, 2048, 4096, 8192, 16_384].freeze
-
-    # The registers, by offset.
-    STATUS = 0x00
-    COMMAND = 0x01
-    C64_LOW = 0x02
-    C64_HIGH = 0x03
-    EXPANSION_LOW = 0x04
-    EXPANSION_HIGH = 0x05
-    EXPANSION_BANK = 0x06
-    LENGTH_LOW = 0x07
-    LENGTH_HIGH = 0x08
-    INTERRUPT_MASK = 0x09
-    ADDRESS_CONTROL = 0x0a
-
-    # Status: an interrupt is pending, the block ended, a verify found a
-    # difference (the manual's fault bit), and the unit is built from 256K
-    # chips, which only the 1700 isn't. Reading the status clears the top
-    # three.
-    INTERRUPT_PENDING = 0x80
-    END_OF_BLOCK = 0x40
-    FAULT = 0x20
-    CHIPS_256K = 0x10
-
-    # Command: execute, reload the registers after the transfer, don't wait
-    # for $FF00, and the transfer type in the bottom two bits.
-    EXECUTE = 0x80
-    AUTOLOAD = 0x20
-    NO_FF00_TRIGGER = 0x10
-    TRANSFER_TYPE = 0x03
-
-    # Interrupt mask: interrupts on at all, then on the end of a block and
-    # on a fault. The low five bits aren't there and read as 1.
-    INTERRUPTS_ON = 0x80
-    INTERRUPT_ON_END = 0x40
-    INTERRUPT_ON_FAULT = 0x20
-
-    # Address control: hold the C64 address or the expansion address where
-    # it is. The low six bits aren't there and read as 1.
-    FIX_C64 = 0x80
-    FIX_EXPANSION = 0x40
-
-    # The REC's bank register has three bits, and the other five read as
-    # 1. A unit past 512K latches all eight onto its own address lines.
-    BANK_STUCK = 0xf8
-
-    attr_reader :trigger
-
-    # bus is the bus the REC reaches C64 memory through, and vic the VIC,
-    # whose phi1 fetch is what a register read finds on the bus during a
-    # transfer.
-    def initialize(size_kb, bus:, vic:)
-      raise ArgumentError, "No #{size_kb}K REU. Pick one of #{SIZES_KB.join(', ')}." unless SIZES_KB.include?(size_kb)
-
-      # The 1700's REC counts 17 address bits, the others' 19.
-      span = size_kb == 128 ? 0x20000 : 0x80000
-      @size_kb = size_kb
-      size = size_kb * 1024
-      @address_mask = [size, span].max - 1
-      @bank_bits = size > span ? 0xff : 0x07
-      @chips = size_kb == 128 ? 0 : CHIPS_256K
-      @ram = RAM.new(size, span)
-      @dma = DMA.new(@ram, span, bus)
-      @trigger = Trigger.new(self)
-      @vic = vic
-      @on_irq_change = nil
-      @on_dma = nil
-      @irq = false
-      reset!
-    end
-
-    def on_irq_change(&block)
-      @on_irq_change = block
-    end
-
-    # Called when the REC asks for the bus.
-    def on_dma(&block)
-      @on_dma = block
-    end
-
-    def irq? = @irq
-
-    # From the moment the REC asks for the bus until it hands it back.
-    def dma? = @requested || @running
-
-    # Whether the REC ran a transfer on the last cycle clocked, which it
-    # goes on doing until the cycle it lets go of the bus.
-    def holds_bus? = @running
-
-    def reset!
-      @status = @chips
-      @command = NO_FF00_TRIGGER
-      @c64 = @c64_start = 0
-      @expansion = @expansion_start = 0
-      @bank = @bank_start = 0
-      @length = @length_start = 0xffff
-      @interrupt_mask = 0x1f
-      @address_control = 0x3f
-      @armed = @requested = @running = @ba_was_low = false
-      interrupt(false)
-    end
-
-    def peek(addr)
-      return @vic.phi1_data if @running
-
-      register = addr & 0x1f
-      value = register_value(register)
-      read_status if register == STATUS
-      value
-    end
-
-    def poke(addr, value)
-      return if @running
-
-      register = addr & 0x1f
-      case register
-      when COMMAND then write_command(value)
-      when C64_LOW, C64_HIGH then @c64 = @c64_start = with_byte(@c64_start, value, register == C64_HIGH)
-      when EXPANSION_LOW, EXPANSION_HIGH
-        @expansion = @expansion_start = with_byte(@expansion_start, value, register == EXPANSION_HIGH)
-      when EXPANSION_BANK then @bank = @bank_start = value & @bank_bits
-      when LENGTH_LOW, LENGTH_HIGH
-        @length = @length_start = with_byte(@length_start, value, register == LENGTH_HIGH)
-      when INTERRUPT_MASK then write_interrupt_mask(value)
-      when ADDRESS_CONTROL then @address_control = value | 0x3f
-      end
-    end
-
-    # A write to $FF00 starts the transfer the command register armed.
-    def ff00_written
-      return unless @armed
-
-      @armed = false
-      request_bus
-    end
-
-    # Clocks the REC for a cycle, given the VIC's BA line. A requested
-    # transfer starts on the first cycle with BA high as the REC sees it,
-    # even one the CPU writes on. Pinned by REU/rmw-trigger. A fetch
-    # requested on the cycle before BA falls writes its first byte on the
-    # first BA-low cycle as well, and again when it starts. Pinned by
-    # REU/badoublewrite.
-    def dma_cycle!(ba_low)
-      late = ba_low && @vic.reu_ba_late?
-      if @requested
-        return hold_off if ba_low && !late
-
-        start_transfer
-      end
-      @dma.cycle!(ba_low, late, ba_low && @vic.reu_ba_handed_on?)
-      end_transfer unless @dma.holds_bus?
-    end
-
-    # The REU's RAM, at an address as the REC's registers give it.
-    def ram_peek(addr) = @ram.peek(addr)
-
-    def ram_poke(addr, value) = @ram.poke(addr, value)
-
-    private
-
-    def register_value(register)
-      case register
-      when STATUS then @status
-      when COMMAND then @command
-      when C64_LOW then @c64 & 0xff
-      when C64_HIGH then @c64 >> 8
-      when EXPANSION_LOW then @expansion & 0xff
-      when EXPANSION_HIGH then @expansion >> 8
-      when EXPANSION_BANK then @bank | BANK_STUCK
-      when LENGTH_LOW then @length & 0xff
-      when LENGTH_HIGH then @length >> 8
-      when INTERRUPT_MASK then @interrupt_mask
-      when ADDRESS_CONTROL then @address_control
-      else 0xff
-      end
-    end
-
-    def read_status
-      @status &= CHIPS_256K
-      interrupt(false)
-    end
-
-    # Writing either byte of an address or the length sets the value the
-    # transfer starts from, and puts the counter back to it.
-    def with_byte(word, value, high)
-      high ? (word & 0x00ff) | (value << 8) : (word & 0xff00) | value
-    end
-
-    def write_command(value)
-      @command = value
-      return if value.nobits?(EXECUTE)
-
-      @armed = value.nobits?(NO_FF00_TRIGGER)
-      request_bus unless @armed
-    end
-
-    # An interrupt enabled over a block that already ended, or a fault
-    # already found, fires at once.
-    def write_interrupt_mask(value)
-      @interrupt_mask = value | 0x1f
-      interrupt_on(@status)
-    end
-
-    def interrupt_on(events)
-      return unless @interrupt_mask.anybits?(INTERRUPTS_ON)
-      return unless (events.anybits?(END_OF_BLOCK) && @interrupt_mask.anybits?(INTERRUPT_ON_END)) ||
-                    (events.anybits?(FAULT) && @interrupt_mask.anybits?(INTERRUPT_ON_FAULT))
-
-      @status |= INTERRUPT_PENDING
-      interrupt(true)
-    end
-
-    def interrupt(level)
-      return if @irq == level
-
-      @irq = level
-      @on_irq_change&.call(level)
-    end
-
-    def request_bus
-      @requested = true
-      @ba_was_low = @vic.ba_low?
-      @on_dma&.call
-    end
-
-    def hold_off
-      @dma.write_ahead(@command & TRANSFER_TYPE, @c64, @expansion | (@bank << 16)) unless @ba_was_low
-      @ba_was_low = true
-    end
-
-    def start_transfer
-      @requested = false
-      @running = true
-      @dma.start(@command & TRANSFER_TYPE, @c64, @expansion | (@bank << 16), @length, @address_control)
-    end
-
-    # The execute bit drops and the $FF00 trigger turns off. With autoload
-    # the addresses and the length go back to where the transfer started,
-    # and otherwise they stay where it stopped.
-    def end_transfer
-      @running = false
-      @command = (@command & ~EXECUTE & 0xff) | NO_FF00_TRIGGER
-      events = @dma.events
-      @status |= events
-      @command.anybits?(AUTOLOAD) ? reload : keep_counters
-      interrupt_on(events)
-    end
-
-    def reload
-      @c64 = @c64_start
-      @expansion = @expansion_start
-      @bank = @bank_start
-      @length = @length_start
-    end
-
-    def keep_counters
-      @c64 = @dma.c64 if @address_control.nobits?(FIX_C64)
-      @length = @dma.length & 0xffff
-      return if @address_control.anybits?(FIX_EXPANSION)
-
-      address = @dma.expansion & @address_mask
-      @expansion = address & 0xffff
-      @bank = (address >> 16) & 0xff
-    end
-  end
-end

data/lib/badline/sid/catch_up.rb

@@ -1,120 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  class SID
-    # Running the DSP over the cycles that have passed since it last caught
-    # up, in spans that fast-forward the voices and end on a whole cycle.
-    module CatchUp
-      private
-
-      # Runs the cycles that have passed, landing each queued write on the
-      # cycle the CPU wrote it on.
-      def catch_up
-        replayed = 0
-        i = 0
-        while i < @deferred_writes.length
-          cycle = @deferred_writes[i]
-          run(cycle - replayed)
-          replayed = cycle
-          apply_write(@deferred_writes[i + 1], @deferred_writes[i + 2])
-          i += 3
-        end
-        run(@pending_cycles - replayed)
-        @deferred_writes.clear
-        @pending_cycles = 0
-      end
-
-      def run(cycles)
-        while cycles != 0
-          span = span(cycles)
-          fast_forward(span - 1) if span > 1
-          clock!(span)
-          cycles -= span
-        end
-      end
-
-      # The longest stretch that can be fast-forwarded. A combined waveform
-      # feeding back into its own oscillator steps cycle by cycle, and a span
-      # never runs past an MSB rise that hard-syncs the next voice, so both
-      # land on a whole cycle.
-      def span(cycles)
-        return 1 if @stepped
-
-        span = @synthesizing ? synthesis_span(cycles) : cycles
-        return span unless @synced
-
-        span = sync_span(@waveform1, span)
-        span = sync_span(@waveform2, span)
-        sync_span(@waveform3, span)
-      end
-
-      # The filter steps at most @filter_chunk cycles at a time, and never
-      # across the end of a recorded sample.
-      def synthesis_span(cycles)
-        span = [cycles, @filter_chunk].min
-        return span unless @decimator
-
-        [@decimator.cycles_to_close, span].min
-      end
-
-      # Whether a span has to step, or watch for hard sync, only changes with
-      # a voice's control register.
-      def update_span_rules
-        @stepped = @voices.any? { |voice| voice.waveform.stepped?(@synthesizing) }
-        @synced = @voices.any? { |voice| voice.waveform.sync? }
-      end
-
-      def sync_span(waveform, span)
-        return span unless waveform.sync_dest.sync?
-
-        rise = waveform.cycles_to_msb_rise
-        rise && rise < span ? rise : span
-      end
-
-      # Unrolled over the three voices: the per-cycle block calls cost
-      # measurably on the synthesis path.
-      def fast_forward(cycles)
-        @voice1.fast_forward(cycles)
-        @voice2.fast_forward(cycles)
-        @voice3.fast_forward(cycles)
-      end
-
-      # The last cycle of a span, run whole. The filter integrates the span
-      # from the voices' output at its end.
-      def clock!(span)
-        @voice1.cycle!
-        @voice2.cycle!
-        @voice3.cycle!
-        @waveform1.synchronize!
-        @waveform2.synchronize!
-        @waveform3.synchronize!
-        return unless @synthesizing
-
-        @filter.cycle!(@voices, span)
-        record_sample(span) if @decimator
-      end
-
-      def record_sample(span)
-        sample = @decimator.push(current_sample, span)
-        return unless sample
-
-        @samples << sample
-        record_voices if @voice_samples
-      end
-
-      def record_voices
-        voice_samples = @voice_samples
-        voice_samples << (@voice1.output >> 7)
-        voice_samples << (@voice2.output >> 7)
-        voice_samples << (@voice3.output >> 7)
-      end
-
-      def current_sample
-        sample = @filter.output / SAMPLE_DIVISOR
-        return sample unless sample < -0x8000 || sample > 0x7fff
-
-        sample.clamp(-0x8000, 0x7fff)
-      end
-    end
-  end
-end

data/lib/badline/sid/decimator.rb

@@ -1,64 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  class SID
-    # Reduces the SID's one-sample-per-cycle stream to an audio rate by
-    # averaging each window. Point sampling would be cheaper, but the pulse
-    # and noise waveforms carry enough energy above the output Nyquist to
-    # alias audibly.
-    #
-    # A sample can stand for several cycles at once, when the DSP has run
-    # them as one step.
-    class Decimator
-      def initialize(clock_hz:, rate:)
-        @clock_hz = clock_hz
-        @rate = rate
-        @phase = 0
-        @sum = 0
-        @count = 0
-        @cycles_to_close = window_cycles
-      end
-
-      # Cycles until the current window closes, counting the next one as 1.
-      attr_reader :cycles_to_close
-
-      # How far the current window has got. The clock and the rate are the
-      # host's.
-      def save_state(out)
-        out.int(@phase).int(@sum).int(@count).int(@cycles_to_close)
-      end
-
-      def load_state(input)
-        @phase = input.int
-        @sum = input.int
-        @count = input.int
-        @cycles_to_close = input.int
-      end
-
-      # Returns the averaged sample when these cycles close a window, and
-      # nil otherwise. They must not run past the window's end.
-      def push(sample, cycles = 1)
-        @sum += sample * cycles
-        @count += cycles
-        @phase += @rate * cycles
-        @cycles_to_close -= cycles
-        return unless @phase >= @clock_hz
-
-        @phase -= @clock_hz
-        @cycles_to_close = window_cycles
-        average
-      end
-
-      private
-
-      def window_cycles = (@clock_hz - @phase + @rate - 1) / @rate
-
-      def average
-        value = @sum.fdiv(@count).round
-        @sum = 0
-        @count = 0
-        value
-      end
-    end
-  end
-end

data/lib/badline/sid/envelope/state.rb

@@ -1,68 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  class SID
-    class Envelope
-      # A snapshot of an envelope: its rates, the gate, the state and the
-      # counters and pipelines between them, and the same fields as reSID
-      # keeps them, for VICE's SIDEXTENDED module.
-      module State
-        # The fields reSID keeps for an envelope between cycles: the rate and
-        # exponential counters, the level, the state as an index into STATES,
-        # whether it holds at zero, the two periods and the pipeline.
-        def resid_fields
-          [@rate_counter, @exponential_counter, @counter, STATES.index(@state).to_i, @hold_zero ? 1 : 0,
-           @rate_period, @exponential_period, @envelope_pipeline]
-        end
-
-        # Takes the fields resid_fields gives from `fields`, from `at` on.
-        def restore_resid_fields(fields, at)
-          @rate_counter = fields[at]
-          @exponential_counter = fields[at + 1]
-          @counter = @env3 = fields[at + 2]
-          state = fields[at + 3]
-          @state = @next_state = STATES.fetch(state.clamp(0, STATES.length - 1)).to_sym
-          @hold_zero = fields[at + 4] != 0
-          @rate_period = fields[at + 5]
-          @exponential_period = fields[at + 6]
-          @envelope_pipeline = fields[at + 7]
-        end
-
-        def save_state(out)
-          [@attack, @decay, @sustain, @release].each { |rate| out.int(rate) }
-          out.boolean(@gate).int(STATES.index(@state)).int(STATES.index(@next_state))
-          out.int(@counter).int(@env3).int(@rate_counter).int(@rate_period).boolean(@reset_rate_counter)
-          out.int(@exponential_counter).int(@exponential_period)
-          out.int(@state_pipeline).int(@envelope_pipeline).int(@exponential_pipeline).boolean(@hold_zero)
-        end
-
-        def load_state(input)
-          @attack = input.int
-          @decay = input.int
-          @sustain = input.int
-          @release = input.int
-          @gate = input.boolean?
-          @state = STATES.fetch(input.int).to_sym
-          @next_state = STATES.fetch(input.int).to_sym
-          load_counters(input)
-        end
-
-        private
-
-        def load_counters(input)
-          @counter = input.int
-          @env3 = input.int
-          @rate_counter = input.int
-          @rate_period = input.int
-          @reset_rate_counter = input.boolean?
-          @exponential_counter = input.int
-          @exponential_period = input.int
-          @state_pipeline = input.int
-          @envelope_pipeline = input.int
-          @exponential_pipeline = input.int
-          @hold_zero = input.boolean?
-        end
-      end
-    end
-  end
-end