badline 0.12.0 → 0.13.0

data/lib/badline/c64/bus/pla.rb

@@ -0,0 +1,149 @@
+# frozen_string_literal: true
+
+module Badline
+  class C64
+    class Bus
+      # The C64's PLA: what each page of the CPU's view maps to, from the
+      # CPU port's LORAM, HIRAM and CHAREN lines and the cartridge's EXROM
+      # and GAME. The bus that includes it supplies the page tables, the
+      # ROMs, the chips, #map_ram_pages, which lays out the RAM that the
+      # ROMs, the cartridge and I/O map over, and #map_io_pages, which lays
+      # out the chips at $D000-$DFFF, with #map_cartridge_io for I/O 1 and 2.
+      module PLA
+        # A chip's registers seen at another page, which reads and writes
+        # them as at the page the chip starts at.
+        class Mirror
+          def initialize(chip, start)
+            @chip = chip
+            @start = start
+          end
+
+          def peek(addr) = @chip.peek(@start | (addr & 0xff))
+          def poke(addr, value) = @chip.poke(@start | (addr & 0xff), value)
+        end
+
+        private
+
+        def map_pla_pages
+          map_ram_pages
+          @ultimax ? map_ultimax_pages : map_banked_pages
+        end
+
+        def map_banked_pages
+          map_rom_overlays
+          map_cartridge_ram
+          @write_pages.fill(@cartridge.romh_writes, 0xe0, 0x20) if @cartridge&.romh_writes
+
+          if io?
+            map_io_pages
+          elsif character?
+            @read_pages.fill(character_rom, 0xd0, 0x10)
+          end
+        end
+
+        # Ultimax mode ignores the $01 lines: 4K of RAM, ROML/ROMH windows,
+        # I/O always visible and open address space everywhere else. The ROML
+        # and ROMH selects fire on writes as well, so cartridge RAM or flash in
+        # either window takes the writes there. The MAX has 2K of RAM, and is
+        # in Ultimax mode with no cartridge too.
+        def map_ultimax_pages
+          first = @board == :max ? 0x08 : 0x10
+          @read_pages.fill(@open_bus, first, 0x100 - first)
+          @write_pages.fill(@open_bus, first, 0x100 - first)
+          map_ultimax_cartridge if @cartridge
+          map_io_pages
+          map_max_io if @board == :max
+        end
+
+        def map_ultimax_cartridge
+          @read_pages.fill(@cartridge.roml, 0x80, 0x20) if @cartridge.roml
+          map_ultimax_writes(@cartridge.roml, 0x80)
+          @read_pages.fill(@cartridge.romh, 0xe0, 0x20) if @cartridge.romh
+          map_ultimax_writes(@cartridge.romh, 0xe0)
+          map_ultimax_a000
+        end
+
+        def map_ultimax_writes(bank, first_page)
+          @write_pages.fill(bank, first_page, 0x20) if bank.respond_to?(:poke)
+        end
+
+        def map_ultimax_a000
+          return unless (window = @cartridge.ultimax_a000)
+
+          @read_pages.fill(window, 0xa0, 0x20)
+          @write_pages.fill(window, 0xa0, 0x20)
+        end
+
+        # The MAX has no CIA 2 and no I/O 2: CIA 1 answers all through
+        # $DC00-$DFFF, but for the I/O 1 page a cartridge takes.
+        def map_max_io
+          @cia1_mirror ||= Mirror.new(cia1, 0xdc00)
+          (0xdd..0xdf).each { |page| @read_pages[page] = @write_pages[page] = @cia1_mirror }
+          return unless @cartridge
+
+          @write_pages[0xde] = @cartridge
+          @read_pages[0xde] = @cartridge if @cartridge.readable_io_pages.include?(0xde)
+        end
+
+        # EXROM and GAME select the cartridge whether or not it has a chip
+        # there, and an empty socket leaves the bus floating.
+        def map_rom_overlays
+          @read_pages.fill(@cartridge.roml || @open_bus, 0x80, 0x20) if roml?
+          if romh?
+            @read_pages.fill(@cartridge.romh || @open_bus, 0xa0, 0x20)
+          elsif basic?
+            @read_pages.fill(basic_rom, 0xa0, 0x20)
+          end
+          @read_pages.fill(kernal_rom, 0xe0, 0x20) if kernal?
+        end
+
+        # Cartridge RAM in the ROML or ROMH window decodes writes itself,
+        # whatever the $01 lines say.
+        def map_cartridge_ram
+          return unless @cartridge&.exrom&.zero?
+
+          map_cartridge_ram_bank(@cartridge.roml, 0x80)
+          map_cartridge_ram_bank(@cartridge.romh, 0xa0) if @cartridge.game.zero?
+        end
+
+        def map_cartridge_ram_bank(bank, first_page)
+          @write_pages.fill(bank, first_page, 0x20) if bank.is_a?(Cartridge::RAMBank)
+        end
+
+        def map_cartridge_io
+          @write_pages.fill(@cartridge, 0xde, 2)
+          @cartridge.readable_io_pages.each { |p| @read_pages[p] = @cartridge }
+        end
+
+        def basic?
+          io_port.kernal? && io_port.basic? && game_high?
+        end
+
+        def game_high?
+          @cartridge.nil? || @cartridge.game == 1
+        end
+
+        def roml?
+          @cartridge&.exrom&.zero? && io_port.kernal? && io_port.basic?
+        end
+
+        def romh?
+          @cartridge&.exrom&.zero? && @cartridge.game.zero? && io_port.kernal?
+        end
+
+        # In 16K mode LORAM alone leaves $d000 as RAM, where it still maps I/O.
+        def character?
+          (io_port.kernal? || (io_port.basic? && game_high?)) && !io_port.io?
+        end
+
+        def io?
+          (io_port.basic? || io_port.kernal?) && io_port.io?
+        end
+
+        def kernal?
+          io_port.kernal?
+        end
+      end
+    end
+  end
+end

data/lib/badline/c64/bus/roms.rb

@@ -0,0 +1,41 @@
+# frozen_string_literal: true
+
+module Badline
+  class C64
+    class Bus
+      # The BASIC, character and KERNAL ROMs, and which KERNAL is fitted.
+      module ROMs
+        # The KERNAL ROMs a machine can be fitted with, by name: the C64's,
+        # the SX-64's, the PET 64's and the C64GS's. The C64GS's is a 16K
+        # image of its BASIC and its KERNAL, and fits both.
+        KERNALS = {
+          c64: "kernal.rom", sx64: "kernal-sx64.rom", pet64: "kernal-pet64.rom", gs: "c64gs.rom"
+        }.freeze
+
+        attr_reader :basic_rom, :character_rom, :kernal_rom, :kernal
+
+        # Fits the KERNAL ROM KERNALS names `name`, in place of the one before,
+        # with the BASIC of a 16K image or else the C64's.
+        def kernal=(name)
+          raise ArgumentError, "no KERNAL named #{name}" unless KERNALS.key?(name)
+
+          @kernal = name
+          data = ROM.read(KERNALS[name])
+          basic = data.length == 0x4000 ? data[0, 0x2000] : ROM.read("basic.rom")
+          @basic_rom = ROM.new(basic, length: 0x2000, start: 0xa000)
+          @kernal_rom = ROM.new(data[-0x2000, 0x2000], length: 0x2000, start: 0xe000)
+          update_overlays!
+        end
+
+        private
+
+        def load_roms
+          @basic_rom = ROM.load("basic.rom", 0xa000)
+          @character_rom = ROM.load("character.rom", 0xd000)
+          @kernal = :c64
+          @kernal_rom = ROM.load(KERNALS[:c64], 0xe000)
+        end
+      end
+    end
+  end
+end

data/lib/badline/c64/bus/saved_state.rb

@@ -0,0 +1,68 @@
+# frozen_string_literal: true
+
+module Badline
+  class C64
+    class Bus
+      # The bus's state for a snapshot: the CPU port, the RAM, colour RAM and
+      # a RAM expansion, the cartridge, the datasette and the chips.
+      module SavedState
+        # The RAM expansion fitted, or an Unexpanded stand-in.
+        attr_reader :ram_expansion
+
+        # Takes the cartridge out of the expansion port, as a restore does for
+        # a state without one.
+        def detach_cartridge
+          @cartridge = nil
+          update_overlays!
+        end
+
+        # The 6510 port's direction and output registers, and the charge left
+        # on its floating bits.
+        def port_state = [@cpu_port.ddr, @cpu_port.data, @cpu_port.floating]
+
+        # Sets the port as port_state reads it, as a snapshot restores it,
+        # leaving the RAM under $00 and $01 alone.
+        def restore_port(ddr, out, floating)
+          @cpu_port.restore(ddr, out, floating)
+        end
+
+        # The machine's memory and everything on the bus but the keyboard, the
+        # joysticks and the pot devices, which the host holds. A cartridge is
+        # already in the port, built from its setup (C64#load_state).
+        def save_state(out)
+          out.marker("BUS")
+          out.int(@cpu_port.ddr).int(@cpu_port.data).int(@cpu_port.floating)
+          @ram.save_state(out)
+          @color_ram.save_state(out)
+          @ram_expansion.save_state(out)
+          @cartridge&.save_state(out)
+          @datasette.save_state(out)
+          @vic.save_state(out)
+          @cia1.save_state(out)
+          @cia2.save_state(out)
+          @sid.save_state(out)
+        end
+
+        def load_state(input)
+          input.marker("BUS")
+          ddr = input.int
+          port_out = input.int
+          floating = input.int
+          @ram.load_state(input)
+          @color_ram.load_state(input)
+          @ram_expansion.load_state(input)
+          @cartridge&.load_state(input)
+          @datasette.load_state(input)
+          @cpu_port.load(ddr, port_out, floating)
+          update_overlays!
+          @vic.load_state(input)
+          @cia1.load_state(input)
+          @cia2.load_state(input)
+          @sid.load_state(input)
+        end
+      end
+
+      include SavedState
+    end
+  end
+end

data/lib/badline/c64/bus/sid_slots.rb

@@ -0,0 +1,44 @@
+# frozen_string_literal: true
+
+module Badline
+  class C64
+    class Bus
+      # Stands in for a page of I/O that a second or third SID shares: each 32
+      # bytes of it go to the SID placed there, or else to the first SID's
+      # mirrors in `$d400-$d7ff`, and to the open bus in I/O 1 and 2.
+      class SIDSlots
+        attr_reader :page
+
+        def initialize(page, first, open_bus)
+          @page = page
+          @io = page >= 0xde
+          @first = first
+          @open_bus = open_bus
+          @sids = []
+          @slots = Array.new(8, -1)
+        end
+
+        def place(sid)
+          @slots[(sid.start >> 5) & 7] = @sids.size
+          @sids << sid
+        end
+
+        def peek(addr)
+          index = @slots[(addr >> 5) & 7]
+          return @sids[index].peek(addr) unless index.negative?
+
+          @io ? @open_bus.peek(addr) : @first.peek(addr)
+        end
+
+        def poke(addr, value)
+          index = @slots[(addr >> 5) & 7]
+          if !index.negative?
+            @sids[index].poke(addr, value)
+          elsif !@io
+            @first.poke(addr, value)
+          end
+        end
+      end
+    end
+  end
+end

data/lib/badline/c64/bus.rb

@@ -0,0 +1,218 @@
+# frozen_string_literal: true
+
+require "badline/c64/bus/saved_state"
+require "badline/c64/bus/sid_slots"
+require "badline/c64/bus/extra_sids"
+require "badline/c64/bus/pla"
+require "badline/c64/bus/roms"
+require "badline/c64/bus/fittings"
+
+module Badline
+  # Memory layout:
+  #
+  # 0x0000-0x00FF - Page 0       - Zeropage
+  # 0x0100-0x01FF - Page 1       - Stack
+  # 0x0200-0x02FF - Page 2       - OS/BASIC pointers
+  # 0x0300-0x03FF - Page 3       - OS/BASIC pointers
+  # 0x0400-0x07FF - Page 4-7     - Screen memory
+  # 0x0800-0x9FFF - Page 8-159   - BASIC program storage area
+  # 0xA000-0xBFFF - Page 160-191 - Machine code program storage (ROM overlay)
+  # 0xC000-0xCFFF - Page 192-207 - Machine code program storage
+  # 0xD000-0xD3FF - Page 208-211 - VIC II registers
+  # 0xD400-0xD7FF - Page 212-215 - SID registers
+  # 0xD800-0xDBFF - Page 216-219 - Color memory
+  # 0xDC00-0xDCFF - Page 220     - CIA 1
+  # 0xDD00-0xDDFF - Page 221     - CIA 2
+  # 0xDE00-0xDEFF - Page 222     - I/O 1
+  # 0xDF00-0xDFFF - Page 223     - I/O 2
+  # 0xE000-0xFFFF - Page 224-255 - Machine code program storage (ROM overlay)
+
+  class C64
+    # Overlays:
+    #
+    # 0x8000-0x9FFF - Cartridge ROM (low) - 8kb
+    # 0xA000-0xBFFF - BASIC ROM / Cartridge ROM (high) - 8kb
+    # 0xD000-0xDFFF - Character ROM / I/O - 4kb
+    # 0xE000-0xFFFF - KERNAL ROM / Cartridge ROM (high) - 8kb
+    class Bus
+      include Addressable
+      include PLA
+      include ExtraSIDs
+      include ROMs
+      include Fittings
+
+      # I/O 1 and 2, and the Ultimax holes, with nothing on the bus. A read
+      # picks up the byte the VIC fetched in the preceding phi1 half-cycle,
+      # and a write goes nowhere.
+      class OpenBus
+        def initialize(vic)
+          @vic = vic
+        end
+
+        def peek(_addr) = @vic.phi1_data
+        def poke(_addr, _value); end
+      end
+
+      # The 6510's port pins with pull-ups, and the floating ones (CPU::Port).
+      PORT_PULLUPS  = 0b0001_0111
+      PORT_FLOATING = 0b1100_1000
+
+      # RAM powers on in runs of $00 $00 $FF $FF $FF $FF $00 $00, inverted in
+      # the second and fourth 16K: a C64C (ASSY 250469 R4) from
+      # C64/raminitpattern/readme.txt, without its occasional random bytes.
+      # See doc/pinned-behaviour.md.
+      RAM_POWER_ON = Array.new(2**16) { |addr| (((addr + 2) / 4) ^ (addr / 0x4000)).odd? ? 0xff : 0x00 }.freeze
+
+      attr_reader :io_port, :ram,
+                  :vic, :sid, :color_ram, :cia1, :cia2, :keyboard, :joystick1, :joystick2,
+                  :control_ports, :cartridge, :ultimax, :phi1_ultimax, :datasette, :region, :video_ram, :reu
+
+      # ram_expansion fits a +60K (:plus60k) or +256K (:plus256k).
+      def initialize(sid_model: :mos6581, cia_model: :mos6526, vic_model: :mos6569, region: Region::PAL,
+                     ram_expansion: nil)
+        @region = region
+        @board = :c64
+        @ram = Memory.new(RAM_POWER_ON, length: 2**16, start: 0)
+        @ram_expansion = BankedRAM.build(ram_expansion, @ram) { update_overlays! }
+        @cartridge = @reu = nil
+        @debug_register = nil
+
+        load_roms
+
+        @keyboard = Input::Keyboard.new
+        @joystick1 = Input::Joystick.new
+        @joystick2 = Input::Joystick.new
+        @control_ports = Input::ControlPorts.new(keyboard: @keyboard, joystick1: @joystick1, joystick2: @joystick2)
+        @vic  = Chips::VIC.new(model: vic_model, region:)
+        @cia1 = Chips::CIA.new(start: 0xdc00, peripheral: @control_ports, model: cia_model, region:)
+        @cia2 = Chips::CIA.new(start: 0xdd00, model: cia_model, region:)
+        @control_ports.port_a_source = @cia1
+        @cia1.on_port_b4_change { |high| @vic.lightpen_level(high) }
+        @sid = Chips::SID.new(model: sid_model, pots: @control_ports)
+        @sid_slots = []
+
+        @datasette = Drives::Datasette.new
+        @datasette.on_flag { @cia1.flag! }
+        @datasette.on_sense_change { @cpu_port.refresh }
+
+        @color_ram = ColorMemory.new(@vic)
+        @vic.vic_bank.connect(cia2: @cia2, color_ram: @color_ram)
+        @vic.vic_bank.map_character_rom(character_rom)
+        @open_bus = OpenBus.new(@vic)
+        @cpu_off_bus = false
+
+        @cpu_port = Chips::CPU::Port.new(@datasette, pullups: PORT_PULLUPS, floating: PORT_FLOATING)
+        @cpu_port.on_change { update_overlays! }
+        @io_port = @cpu_port.status
+
+        @read_pages = Array.new(256)
+        @write_pages = Array.new(256)
+        update_overlays!
+      end
+
+      def attach_cartridge(cartridge)
+        @cartridge = cartridge
+        cartridge.connect(ram: @ram, open_bus: @open_bus)
+        cartridge.on_change { update_overlays! }
+        update_overlays!
+      end
+
+      # An REU takes I/O 2 unless a cartridge claims it, and watches writes
+      # to $FF00 for the one that starts an armed transfer.
+      def attach_reu(reu)
+        @reu = reu
+        update_overlays!
+      end
+
+      def power_on!
+        @ram.clear!(RAM_POWER_ON)
+        @ram_expansion.power_on!
+      end
+
+      # The RES line clears the 6510 port's direction and output registers,
+      # and a RAM expansion's bank register. The port's floating bits keep
+      # their charge.
+      def reset!
+        @ram_expansion.reset!
+        @cpu_port.reset!
+      end
+
+      def disable_overlays!
+        poke(0, 0x2f)
+        poke(1, 0)
+      end
+
+      def install_debug_register(&)
+        @debug_register = DebugRegister.new(@sid, &)
+        update_overlays!
+      end
+
+      def peek(addr)
+        return @cpu_port.ddr if addr.zero?
+        return @io_port.value if addr == 0x01
+
+        @read_pages[addr >> 8].peek(addr)
+      end
+
+      # A write to $00 or $01 goes to the port, but the RAM below is still
+      # write-enabled, and takes whatever is left on the bus: the byte the VIC
+      # fetched in the phi1 half of the cycle.
+      def poke(addr, value)
+        if addr < 0x02
+          @ram.poke(addr, @vic.phi1_data)
+          addr.zero? ? @cpu_port.write_ddr(value) : @cpu_port.write_data(value)
+        elsif !@cpu_off_bus
+          @write_pages[addr >> 8].poke(addr, value)
+        end
+      end
+
+      # Runs a CPU cycle with the CPU off the bus, as an REU's /DMA line
+      # holds it: a write it makes reaches nothing but its own port.
+      def cycle_cpu_off_bus(cpu)
+        @cpu_off_bus = true
+        cpu.cycle!
+        @cpu_off_bus = false
+      end
+
+      def inspect
+        "#<#{self.class.name} port=#{format('0x%02x', @io_port.value)} " \
+          "cartridge=#{@cartridge ? @cartridge.class.name : 'none'} " \
+          "ultimax=#{@ultimax}>"
+      end
+
+      private
+
+      # Banking changes only on $01 writes and cartridge line/bank changes,
+      # so reads and writes dispatch through per-page handler tables instead
+      # of range checks.
+      def update_overlays!
+        max = @board == :max
+        @ultimax = max || (@cartridge ? @cartridge.ultimax? : false)
+        @phi1_ultimax = max || (@cartridge ? @cartridge.phi1_ultimax? : false)
+        @video_ram = @ram_expansion.video_ram
+        @vic.vic_bank.map(@video_ram, phi1_ultimax: @phi1_ultimax, ultimax: @ultimax, romh: @cartridge&.romh)
+
+        map_pla_pages
+        @write_pages[0xff] = @reu.trigger.wrap(@write_pages[0xff]) if @reu
+      end
+
+      def map_ram_pages
+        @ram_expansion.map(@read_pages, @write_pages)
+      end
+
+      def map_io_pages
+        {
+          vic => 0xd0..0xd3, sid => 0xd4..0xd7, color_ram => 0xd8..0xdb,
+          cia1 => 0xdc..0xdc, cia2 => 0xdd..0xdd, @open_bus => 0xde..0xdf
+        }.each do |chip, pages|
+          pages.each { |p| @read_pages[p] = @write_pages[p] = chip }
+        end
+        @ram_expansion.map_io(@read_pages, @write_pages)
+        @read_pages[0xd7] = @write_pages[0xd7] = @debug_register if @debug_register
+        @read_pages[0xdf] = @write_pages[0xdf] = @reu if @reu
+        map_cartridge_io if @cartridge
+        map_extra_sids unless @sid_slots.empty?
+      end
+    end
+  end
+end

data/lib/badline/c64/cartridge/action_replay.rb

@@ -0,0 +1,128 @@
+# frozen_string_literal: true
+
+module Badline
+  class C64
+    class Cartridge
+      # Action Replay v4.2 to v6: four 8K ROM banks and 8K of RAM. A write to
+      # I/O 1 sets the control register:
+      #
+      #   bit 0    pulls GAME low
+      #   bit 1    releases EXROM
+      #   bit 2    switches the register off until the next freeze or reset
+      #   bits 3-4 ROM bank
+      #   bit 5    RAM instead of ROM at ROML and I/O 2
+      #   bit 6    acknowledges a freeze and lets go of NMI
+      #
+      # I/O 2 shows the last page of the RAM or of the ROM bank. The register
+      # doesn't decode R/W, so a read of I/O 1 writes whatever is on the bus
+      # into it. RAM with only EXROM released ($22) selects the cartridge RAM
+      # and the C64's together at ROML. A freeze switches the cartridge back
+      # on, in Ultimax mode with the RAM at ROML and the first bank at ROMH.
+      class ActionReplay < Cartridge
+        include Freezer
+
+        CONTROL_MODES = %i[rom8k rom16k off ultimax].freeze
+        IO2_PAGE = 0x1f00
+
+        def connect(ram:, open_bus:)
+          super
+          @through.backing = ram
+          @contended.backing = ram
+        end
+
+        def readable_io_pages
+          [0xde, 0xdf]
+        end
+
+        def peek(addr)
+          return open_bus(addr) unless @active
+          return io2_peek(addr) if addr >= 0xdf00
+
+          open_bus(addr).tap { |value| control(value) }
+        end
+
+        def poke(addr, value)
+          return unless @active
+
+          if addr < 0xdf00
+            control(value)
+          elsif @io2_ram
+            @ram_data[IO2_PAGE | (addr & 0xff)] = value
+          end
+        end
+
+        def reset
+          @active = true
+          self.nmi = false
+          control(0)
+        end
+
+        def freeze!
+          @active = true
+          @rom = bank(@rom_banks, 0)
+          select(:ultimax, @isolated, io2_ram: true)
+        end
+
+        private
+
+        def save_mapper(out)
+          super
+          out.int(window_index(@rom, windows)).boolean(@active).boolean(@io2_ram).blob(@ram_data)
+        end
+
+        def load_mapper(input)
+          super
+          @rom = window_at(input.int, windows)
+          @active = input.boolean?
+          @io2_ram = input.boolean?
+          input.blob_into(@ram_data)
+        end
+
+        def windows = [@through, @isolated, @contended, *@rom_banks, EMPTY_BANK]
+
+        def io2_peek(addr)
+          @io2_ram ? @ram_data[IO2_PAGE | (addr & 0xff)] : @rom.peek(addr)
+        end
+
+        def control(value)
+          self.nmi = false if value.anybits?(0x40)
+          @rom = bank(@rom_banks, (value >> 3) & 0x03)
+          configure(value)
+          @active = false if value.anybits?(0x04)
+        end
+
+        def configure(value)
+          return select(:rom8k, @contended, io2_ram: true) if (value & 0x23) == 0x22
+
+          configure_standard(value)
+        end
+
+        def configure_standard(value)
+          mode = CONTROL_MODES[value & 0x03]
+          if value.anybits?(0x20)
+            select(mode, mode == :ultimax ? @isolated : @through, io2_ram: true)
+          else
+            select(mode, @rom, io2_ram: false)
+          end
+        end
+
+        def select(mode, roml, io2_ram:, romh: @rom)
+          self.mode = mode
+          @roml = roml
+          @romh = romh
+          @io2_ram = io2_ram
+          changed!
+        end
+
+        def install_chips(chips)
+          @rom_banks = banks_from(chips).first
+          @ram_data = Array.new(BANK_SIZE, 0)
+          @through = RAMBank.new(@ram_data)
+          @isolated = RAMBank.new(@ram_data)
+          @contended = ContendedRAM.new(@ram_data)
+          reset
+        end
+      end
+    end
+  end
+end

data/lib/badline/c64/cartridge/atomic_power.rb

@@ -0,0 +1,26 @@
+# frozen_string_literal: true
+
+module Badline
+  class C64
+    class Cartridge
+      # Atomic Power, sold as Nordic Power: an Action Replay 5 with one more
+      # configuration. RAM with only EXROM released and bits 2, 6 and 7 clear
+      # ($22) selects 16K mode with the ROM bank at ROML and the RAM at ROMH
+      # and I/O 2. Writes to that RAM don't reach the C64's. The VIC never
+      # sees Ultimax mode.
+      class AtomicPower < ActionReplay
+        def phi1_ultimax?
+          false
+        end
+
+        private
+
+        def configure(value)
+          return select(:rom16k, @rom, romh: @isolated, io2_ram: true) if (value & 0xe7) == 0x22
+
+          configure_standard(value)
+        end
+      end
+    end
+  end
+end