badline 0.12.0 → 0.13.0

data/lib/badline/via.rb

@@ -1,266 +0,0 @@
-# frozen_string_literal: true
-
-require "badline/via/control_lines"
-require "badline/via/fast_forward"
-require "badline/via/interrupt_register"
-require "badline/via/shift_register"
-require "badline/via/state"
-require "badline/via/timer1"
-require "badline/via/timer2"
-
-module Badline
-  # VIA (Versatile Interface Adapter): the MOS 6522, two ports with
-  # handshake lines, two timers and a shift register. The 1541 has two.
-  #
-  # Sixteen registers repeat across a 1 KB window. The control pins take
-  # levels from outside through ca1= and friends, and PB6 takes its pulses
-  # for timer 2 through pb6= alone: the peripheral's port B input doesn't
-  # feed the counter.
-  class VIA
-    include Addressable
-    include FastForward
-    include State
-
-    attr_reader :start, :peripheral, :shift_register, :acr, :pcr
-
-    def timer1 = @t1.counter
-
-    def timer1_latch = @t1.latch
-
-    def timer2 = @t2.counter
-
-    def interrupt_flags = @ifr.read
-
-    def interrupt_enable = @ifr.read_enable
-
-    def initialize(start: 0, peripheral: nil)
-      addressable_at(start, length: 2**10)
-
-      @peripheral = peripheral
-      @t1 = Timer1.new
-      @t2 = Timer2.new
-      @shift_register = ShiftRegister.new
-      @ifr = InterruptRegister.new
-      @ca = ControlLines.new(@ifr, c1_flag: InterruptRegister::CA1, c2_flag: InterruptRegister::CA2,
-                                   handshake_on_read: true)
-      @cb = ControlLines.new(@ifr, c1_flag: InterruptRegister::CB1, c2_flag: InterruptRegister::CB2,
-                                   handshake_on_read: false)
-      @pb6_high = true
-      @acr = 0x00
-      reset!
-    end
-
-    # The RES line clears every register but the timers and the shift
-    # register, which carry on counting, and so releases IRQ.
-    def reset!
-      @ora = @orb = @ddra = @ddrb = 0x00
-      @latch_a = @latch_b = 0xff
-      @ifr.reset!
-      @ca.reset!
-      @cb.reset!
-      write_acr(0x00)
-      @pcr = 0x00
-    end
-
-    def irq? = @ifr.irq?
-
-    def cycle!
-      @ca.cycle! if @ca.pulsing?
-      @cb.cycle! if @cb.pulsing?
-      @ifr.set(InterruptRegister::TIMER1) if @t1.cycle!(@acr.anybits?(0x40))
-      @ifr.set(InterruptRegister::TIMER2) if @t2.cycle!(@sr_uses_t2)
-      @ifr.set(InterruptRegister::SR) if @shift_register.cycle!(@t2.low_underflowed)
-    end
-
-    # Port A as driven by ORA and DDRA, input lines floating high.
-    def port_a_output = driven_lines(@ora, @ddra)
-
-    # Port B as driven by ORB and DDRB, with PB7 handed to timer 1 by ACR
-    # bit 7.
-    def port_b_output
-      lines = driven_lines(@orb, @ddrb)
-      return lines unless @acr.anybits?(0x80)
-
-      @t1.pb7 ? lines | 0x80 : lines & 0x7f
-    end
-
-    # An active CA1 edge latches port A while ACR bit 0 is set.
-    def ca1=(high)
-      return if high == @ca.c1_high
-
-      @latch_a = pins_a if @acr.anybits?(0x01) && @ca.active_c1_edge?(high)
-      @ca.c1 = high
-    end
-
-    def ca2=(high)
-      @ca.c2 = high
-    end
-
-    # An active CB1 edge latches port B while ACR bit 1 is set. CB1 also
-    # clocks the shift register in its external clock modes.
-    def cb1=(high)
-      return if high == @cb.c1_high
-
-      @ifr.set(InterruptRegister::SR) if @shift_register.cb1_edge!(high)
-      @latch_b = pins_b if @acr.anybits?(0x02) && @cb.active_c1_edge?(high)
-      @cb.c1 = high
-    end
-
-    def cb2=(high)
-      @shift_register.cb2_input = high
-      @cb.c2 = high
-    end
-
-    # A falling edge counts a pulse while timer 2 counts them.
-    def pb6=(high)
-      fell = @pb6_high && !high
-      @pb6_high = high
-      @ifr.set(InterruptRegister::TIMER2) if fell && @t2.pulse!
-    end
-
-    def ca2_output = @ca.c2_output
-
-    # The shift register's clock on CB1, or nil when CB1 is an input.
-    def cb1_output = @shift_register.cb1_output
-
-    # The shift register takes CB2 over in its shift-out modes.
-    def cb2_output
-      level = @shift_register.cb2_output
-      level.nil? ? @cb.c2_output : level
-    end
-
-    def peek(addr)
-      case offset_of(addr) & 0x0f
-      when 0x00 then read_port_b
-      when 0x01 then read_port_a(handshake: true)
-      when 0x02 then @ddrb
-      when 0x03 then @ddra
-      when 0x04 then read_timer_low(@t1.counter, InterruptRegister::TIMER1)
-      when 0x05 then high_byte(@t1.counter)
-      when 0x06 then low_byte(@t1.latch)
-      when 0x07 then high_byte(@t1.latch)
-      when 0x08 then read_timer_low(@t2.counter, InterruptRegister::TIMER2)
-      when 0x09 then high_byte(@t2.counter)
-      when 0x0a then read_shift_register
-      when 0x0b then @acr
-      when 0x0c then @pcr
-      when 0x0d then @ifr.read
-      when 0x0e then @ifr.read_enable
-      else read_port_a(handshake: false)
-      end
-    end
-
-    def poke(addr, value)
-      case offset_of(addr) & 0x0f
-      when 0x00 then write_port_b(value)
-      when 0x01 then write_port_a(value, handshake: true)
-      when 0x02 then @ddrb = value
-      when 0x03 then @ddra = value
-      when 0x04, 0x06 then @t1.write_latch_low(value)
-      when 0x05 then write_timer1_high(value, start: true)
-      when 0x07 then write_timer1_high(value, start: false)
-      when 0x08 then @t2.latch_low = value
-      when 0x09 then write_timer2_high(value)
-      when 0x0a then write_shift_register(value)
-      when 0x0b then write_acr(value)
-      when 0x0c then write_pcr(value)
-      when 0x0d then @ifr.write(value)
-      when 0x0e then @ifr.write_enable(value)
-      else write_port_a(value, handshake: false)
-      end
-    end
-
-    private
-
-    # Output bits are driven from the data register; input bits float high.
-    # External peripherals can still pull any line low (wired-AND).
-    def driven_lines(register, direction)
-      (register & direction) | (~direction & 0xff)
-    end
-
-    def pins_a
-      lines = port_a_output
-      peripheral ? lines & peripheral.read_a(lines) : lines
-    end
-
-    def pins_b
-      lines = port_b_output
-      peripheral ? lines & peripheral.read_b(lines) : lines
-    end
-
-    # Port A reads the pins, or what CA1 latched off them.
-    def read_port_a(handshake:)
-      value = @acr.anybits?(0x01) ? @latch_a : pins_a
-      @ca.access!(false) if handshake
-      value
-    end
-
-    def write_port_a(value, handshake:)
-      @ora = value
-      @ca.access!(true) if handshake
-    end
-
-    # Port B reads its output bits from ORB, or from timer 1 for PB7, and
-    # its input bits from the pins, or from what CB1 latched off them.
-    def read_port_b
-      outputs = @acr.anybits?(0x80) ? @ddrb | 0x80 : @ddrb
-      inputs = @acr.anybits?(0x02) ? @latch_b : pins_b
-      @cb.access!(false)
-      (port_b_output & outputs) | (inputs & ~outputs & 0xff)
-    end
-
-    def write_port_b(value)
-      @orb = value
-      @cb.access!(true)
-    end
-
-    # A read of either timer's low counter byte acknowledges its interrupt.
-    def read_timer_low(counter, flag)
-      @ifr.clear(flag)
-      low_byte(counter)
-    end
-
-    # $5 loads and starts the counter; $7 only writes the latch. Both
-    # acknowledge the interrupt.
-    def write_timer1_high(value, start:)
-      @t1.write_latch_high(value)
-      @t1.start! if start
-      @ifr.clear(InterruptRegister::TIMER1)
-    end
-
-    def write_timer2_high(value)
-      @t2.load(value)
-      @ifr.clear(InterruptRegister::TIMER2)
-    end
-
-    def read_shift_register
-      value = @shift_register.data
-      @shift_register.access!
-      @ifr.clear(InterruptRegister::SR)
-      value
-    end
-
-    def write_shift_register(value)
-      @shift_register.data = value
-      @shift_register.access!
-      @ifr.clear(InterruptRegister::SR)
-    end
-
-    # Bits 4-2 pick the shift register's mode. Modes 1, 4 and 5 clock off
-    # timer 2's low byte. Bit 7 turning on hands PB7 to timer 1 high.
-    def write_acr(value)
-      @t1.pb7_enabled! if value.anybits?(0x80) && @acr.nobits?(0x80)
-      @acr = value
-      @t2.count_pulses = value.anybits?(0x20)
-      mode = (value >> 2) & 0x07
-      @shift_register.mode = mode
-      @sr_uses_t2 = [1, 4, 5].include?(mode)
-    end
-
-    def write_pcr(value)
-      @pcr = value
-      @ca.control = value & 0x0f
-      @cb.control = value >> 4
-    end
-  end
-end

data/lib/badline/vic/bank.rb

@@ -1,133 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  class VIC < Cycleable
-    # The 16K window the VIC sees into RAM, selected by CIA2 $DD00, in the
-    # bank a +256K picks for it. Character
-    # ROM shadows $1000-$1FFF in banks 0 and 2.
-    #
-    # The machine's bus pushes in what the VIC sees through #connect,
-    # #map_character_rom and #map whenever it changes. Until then the bank
-    # has a CIA 2, RAM, colour RAM and character ROM of its own.
-    class Bank
-      include Addressable
-
-      # The CIA2 port A bank bits are inverted: %11 selects bank 0.
-      BANK_STARTS = [0xc000, 0x8000, 0x4000, 0x0000].freeze
-
-      attr_reader :ram, :color_ram
-
-      # The bank lines as #sample_lines last saw them.
-      attr_accessor :lines
-
-      def initialize(vic)
-        addressable_at(0x0000, length: 2**14)
-        connect(cia2: CIA.new(start: 0xdd00), color_ram: ColorMemory.new(vic))
-        map_character_rom(ROM.load("character.rom", 0xd000))
-        @base = 0
-        @starts = BANK_STARTS
-        map(Memory.new([], length: 2**16, start: 0))
-        @lines = 0b11
-        @swapped = false
-      end
-
-      # CIA 2, whose port A picks the bank, and the colour RAM, read from
-      # the address +color_base+ gives offset 0.
-      def connect(cia2:, color_ram:, color_base: 0xd800)
-        @cia2 = cia2
-        @color_ram = color_ram
-        @color_base = color_base
-      end
-
-      # The character ROM, read from the address +base+ gives offset 0. It
-      # shows in the banks whose low line is high, unless +shadow+ is false.
-      def map_character_rom(rom, base: 0xc000, shadow: true)
-        @character_rom = rom
-        @character_base = base
-        @shadow_mask = shadow ? 0b01 : 0b00
-      end
-
-      # The RAM the VIC's 64K starts at +base+ in, and the cartridge's
-      # Ultimax lines in each half of the cycle with the ROMH bank they
-      # show.
-      def map(ram, base: 0, phi1_ultimax: false, ultimax: false, romh: nil)
-        @ram = ram
-        unless base == @base
-          @base = base
-          @starts = BANK_STARTS.map { |start| base + start }.freeze
-        end
-        @phi1_ultimax = phi1_ultimax
-        @ultimax = ultimax
-        @romh = romh
-      end
-
-      # On the 8565, a port A write that swaps the two bank lines, driving
-      # one high as the other goes low, shows the VIC both lines low for the
-      # cycle after it: every access in that cycle reads bank 3. A swap that
-      # the DDR makes, releasing a line to float high, shows nothing.
-      # Called once a cycle, ahead of the cycle's accesses.
-      def sample_lines
-        lines = @cia2.port_a_lines & 0b11
-        @swapped = swap?(@lines, lines) && @cia2.port_registers[2].allbits?(0b11)
-        @lines = lines
-      end
-
-      def peek(offset)
-        return ultimax_peek(offset) if @phi1_ultimax
-
-        bits = bank_switch_register
-        if (bits & @shadow_mask) == 0b01 && (offset & 0xf000) == 0x1000
-          @character_rom.peek(@character_base + offset)
-        else
-          @ram.peek(@starts[bits] + offset)
-        end
-      end
-
-      # A fetch in the second half of the cycle, the c-access, sees the
-      # memory configuration the CPU does in that half. No cartridge drives
-      # Ultimax mode in the first half alone, so otherwise it reads as #peek.
-      def peek_phi2(offset)
-        @ultimax ? ultimax_peek(offset) : peek(offset)
-      end
-
-      def peek_color(offset)
-        @color_ram.nibble(@color_base + offset)
-      end
-
-      def poke(_addr, _value)
-        raise ReadOnlyMemoryError
-      end
-
-      # True if the VIC reads the character ROM at this offset.
-      def character_rom?(offset)
-        !@phi1_ultimax && (bank_switch_register & @shadow_mask) == 0b01 && (offset & 0xf000) == 0x1000
-      end
-
-      def start
-        BANK_STARTS[bank_switch_register]
-      end
-
-      private
-
-      # In Ultimax mode the cartridge ROMH replaces the character ROM
-      # shadow, visible at $3000-$3FFF of the window. The MAX is in
-      # Ultimax mode with no cartridge too.
-      def ultimax_peek(offset)
-        romh = @romh
-        if romh && offset.allbits?(0x3000)
-          romh.peek(0xe000 + (offset & 0x1fff))
-        else
-          @ram.peek(@starts[bank_switch_register] + offset)
-        end
-      end
-
-      def swap?(from, to) = (from ^ to) == 0b11 && from.anybits?(0b11) && to.anybits?(0b11)
-
-      def bank_switch_register
-        return 0 if @swapped
-
-        @cia2.port_a_lines & 0b11
-      end
-    end
-  end
-end

data/lib/badline/vic/border_mask.rb

@@ -1,86 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  class VIC < Cycleable
-    # Border coverage per 8-pixel group, tracked as the sequencer outputs
-    # a line.
-    #
-    # The border is repainted over composited sprites from a snapshot of
-    # the finished line, which keeps mid-line border color splits intact.
-    class BorderMask
-      FULL  = 0
-      NONE  = 1
-      MIXED = 2
-
-      # The group table and per-pixel mask are exposed so the sequencer's
-      # pixel loops can write them without a method call per column.
-      attr_reader :groups, :mask
-
-      def initialize(width)
-        @width = width
-        @groups = Array.new(width / 8, FULL)
-        @mask = Array.new(width, true)
-        @snapshot = Array.new(width, 0)
-      end
-
-      def reset
-        @groups.fill(FULL)
-      end
-
-      def save_state(out)
-        out.ints(@groups).booleans(@mask).blob(@snapshot)
-      end
-
-      def load_state(input)
-        input.ints_into(@groups)
-        input.booleans_into(@mask)
-        input.blob_into(@snapshot)
-      end
-
-      def at?(pixel_x)
-        case @groups[pixel_x >> 3]
-        when FULL then true
-        when MIXED then @mask[pixel_x]
-        else false
-        end
-      end
-
-      def snapshot(colors)
-        @snapshot[0, @width] = colors
-      end
-
-      def restore(colors)
-        group = 0
-        while group < @groups.length
-          case @groups[group]
-          when FULL then group = restore_full(colors, group)
-          when MIXED then restore_mixed(colors, group * 8)
-          end
-          group += 1
-        end
-      end
-
-      private
-
-      # Copies a run of full-border groups in one splice and returns its
-      # last group.
-      def restore_full(colors, first)
-        last = first
-        last += 1 while @groups[last + 1] == FULL
-        x_pos = first * 8
-        length = (last - first + 1) * 8
-        colors[x_pos, length] = @snapshot[x_pos, length]
-        last
-      end
-
-      def restore_mixed(colors, x_pos)
-        i = 0
-        while i < 8
-          x = x_pos + i
-          colors[x] = @snapshot[x] if @mask[x]
-          i += 1
-        end
-      end
-    end
-  end
-end

data/lib/badline/vic/collisions.rb

@@ -1,115 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  class VIC < Cycleable
-    # = Sprite collisions
-    #
-    # The $D01E/$D01F latches and the per-pixel sprite coverage that feeds
-    # them. Collisions latch as the beam passes each covered pixel, so a
-    # read mid-line sees the pixels drawn before the reading cycle and none
-    # of the ones after it.
-    class Collisions
-      # $D019 latch bits raised by the collision registers.
-      SPRITE_COLLISION_IRQ = 0x04 # IMMC, mirrors $D01E
-      DATA_COLLISION_IRQ   = 0x02 # IMBC, mirrors $D01F
-
-      # A read holds the register's reset asserted past the cycle that
-      # issued it, so the pixels drawn under it never reach the register.
-      # The read still reports only the pixels drawn before its own cycle,
-      # which is why the two numbers do not cancel out.
-      CLEAR_OVERRUN = 12
-
-      # The pixel the last fold reached, so the sprites know whether a read
-      # has anything left to latch.
-      attr_reader :folded
-
-      # One bitmask per pixel of the line, written straight by the sprite
-      # merge and read back here and by the composite.
-      attr_reader :hits
-
-      def initialize(registers, width)
-        @registers = registers
-        @width = width
-        @hits = Array.new(width, 0)
-        @folded = 0
-        @cleared_sprite = 0
-        @cleared_data = 0
-      end
-
-      def save_state(out)
-        out.blob(@hits).int(@folded).int(@cleared_sprite).int(@cleared_data)
-      end
-
-      def load_state(input)
-        input.blob_into(@hits)
-        @folded = input.int
-        @cleared_sprite = input.int
-        @cleared_data = input.int
-      end
-
-      def start_line
-        @folded = 0
-        @cleared_sprite = carry(@cleared_sprite)
-        @cleared_data = carry(@cleared_data)
-      end
-
-      # Latch every covered pixel between the last fold and the beam. The
-      # sprites' touched span bounds the scan; the coverage is zero outside
-      # it either way.
-      def fold(mask, upto, low, high)
-        from = [@folded, low].max
-        @folded = upto
-        scan(mask, from, [upto, high].min)
-      end
-
-      # A read resets its register for the pixels that follow the reading
-      # cycle as well as for everything before it.
-      def clear(reg, beam_x)
-        if reg == 0x1e
-          @cleared_sprite = beam_x + CLEAR_OVERRUN
-        else
-          @cleared_data = beam_x + CLEAR_OVERRUN
-        end
-      end
-
-      private
-
-      # Two or more sprites on a pixel collide with each other; any sprite
-      # over a foreground pixel collides with the graphics. Pixels still
-      # under a read's reset are dropped rather than latched.
-      def scan(mask, from, upto)
-        sprite_clash = 0
-        data_clash = 0
-        pos = from
-        while pos < upto
-          bits = @hits[pos]
-          unless bits.zero?
-            sprite_clash |= bits if pos >= @cleared_sprite && bits.anybits?(bits - 1)
-            data_clash |= bits if pos >= @cleared_data && mask[pos]
-          end
-          pos += 1
-        end
-        latch(sprite_clash, data_clash)
-      end
-
-      def latch(sprite_clash, data_clash)
-        latch_one(0x1e, sprite_clash, SPRITE_COLLISION_IRQ)
-        latch_one(0x1f, data_clash, DATA_COLLISION_IRQ)
-      end
-
-      # The IRQ is raised on the edge out of an empty register, so a
-      # collision folded on top of an unread one raises nothing.
-      def latch_one(reg, clash, irq)
-        return if clash.zero?
-        return unless @registers.collide!(reg, clash)
-
-        @registers.latch_irq!(irq)
-      end
-
-      # A reset still asserted at the line wrap carries into the new line.
-      def carry(cleared)
-        cleared > @width ? cleared - @width : 0
-      end
-    end
-  end
-end

data/lib/badline/vic/color_patches.rb

@@ -1,47 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  class VIC < Cycleable
-    # A mid-line color register write becomes visible one pixel into the
-    # column emitted the cycle after the write. That emit paints the whole
-    # column with the new color, so the boundary pixel is patched back to
-    # the old one before the line is finished. On the 8565 the boundary
-    # pixel shows light grey instead, the grey dot, whatever the old and new
-    # colors are.
-    class ColorPatches
-      def initialize(sequencer, grey_dots: false)
-        @sequencer = sequencer
-        @grey_dots = grey_dots
-        @patches = []
-      end
-
-      def clear = @patches.clear
-
-      # Each patch as its four numbers: the boundary pixel, the register,
-      # the old colour and the new.
-      def save_state(out)
-        out.int(@patches.length)
-        @patches.each { |patch| out.ints(patch) }
-      end
-
-      def load_state(input)
-        @patches.replace(Array.new(input.int) { input.ints })
-      end
-
-      def log(reg, old, value, boundary_x)
-        @patches << [boundary_x, reg, @grey_dots ? GREY_DOT : old & 0x0f, value & 0x0f]
-      end
-
-      def apply(colors, fg_mask)
-        @patches.each do |(x, reg, old, value)|
-          border = @sequencer.border_at?(x)
-          if reg == 0x20
-            colors[x] = old if border
-          elsif !border && !fg_mask[x] && colors[x] == value
-            colors[x] = old
-          end
-        end
-      end
-    end
-  end
-end