badline 0.12.0 → 0.13.0

data/lib/badline/chips/z80/block_io.rb

@@ -0,0 +1,60 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class Z80
+      # INI, IND, OUTI, OUTD and their repeating forms. B counts the bytes
+      # and sets S, Z, 5 and 3. The byte's bit 7 sets N, and adding it to C
+      # plus or minus one for INI and IND, or to L for OUTI and OUTD, sets H
+      # and C on a carry out and P/V from the parity of its low 3 bits
+      # exclusive-ored with B.
+      module BlockIO
+        private
+
+        def block_input(step, repeat)
+          @cycles += 1
+          port = bc
+          value = input(port)
+          @wz = (port + step) & 0xffff
+          @b = (@b - 1) & 0xff
+          write_byte(hl, value)
+          self.hl = (hl + step) & 0xffff
+          block_io_flags(value, value + ((@c + step) & 0xff), repeat)
+        end
+
+        def block_output(step, repeat)
+          @cycles += 1
+          value = read_byte(hl)
+          @b = (@b - 1) & 0xff
+          output(bc, value)
+          self.hl = (hl + step) & 0xffff
+          @wz = (bc + step) & 0xffff
+          block_io_flags(value, value + @l, repeat)
+        end
+
+        def block_io_flags(value, sum, repeat)
+          carry = sum > 0xff ? HF | CF : 0
+          assign_flags(SZ53[@b] | ((value >> 6) & NF) | carry | PARITY[(sum & 7) ^ @b])
+          return unless repeat && !@b.zero?
+
+          repeat_block
+          repeat_io_flags(value, carry)
+        end
+
+        def repeat_io_flags(value, carry)
+          flags = @f & ~HF
+          if carry.zero?
+            flags ^= PARITY[@b & 7] ^ PF
+          elsif value.anybits?(0x80)
+            flags ^= PARITY[(@b - 1) & 7] ^ PF
+            flags |= HF if @b.nobits?(0x0f)
+          else
+            flags ^= PARITY[(@b + 1) & 7] ^ PF
+            flags |= HF if @b.allbits?(0x0f)
+          end
+          assign_flags(flags)
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/z80/block_transfers.rb

@@ -0,0 +1,61 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class Z80
+      # LDI, LDD, CPI, CPD and their repeating forms. A repeating form that
+      # goes round again winds the program counter back to its ED and spends
+      # 5 T-states more, and bits 5 and 3 then come from the program
+      # counter's high byte.
+      module BlockTransfers
+        private
+
+        # ED A0-BB: the column picks LD, CP, IN or OUT, bit 3 counts down, and
+        # bit 4 repeats.
+        def block_operation(opcode)
+          step = opcode.nobits?(0x08) ? 1 : -1
+          repeat = opcode.anybits?(0x10)
+          case opcode & 3
+          when 0 then block_load(step, repeat)
+          when 1 then block_compare(step, repeat)
+          when 2 then block_input(step, repeat)
+          else block_output(step, repeat)
+          end
+        end
+
+        def block_load(step, repeat)
+          value = read_byte(hl)
+          write_byte(de, value)
+          @cycles += 2
+          self.hl = (hl + step) & 0xffff
+          self.de = (de + step) & 0xffff
+          self.bc = (bc - 1) & 0xffff
+          sum = value + @a
+          assign_flags((@f & (SF | ZF | CF)) | (sum & XF) | ((sum & 0x02) << 4) | (bc.zero? ? 0 : PF))
+          repeat_block if repeat && !bc.zero?
+        end
+
+        def block_compare(step, repeat)
+          value = read_byte(hl)
+          @cycles += 5
+          result = (@a - value) & 0xff
+          half = (@a ^ value ^ result) & HF
+          adjusted = result - (half >> 4)
+          self.hl = (hl + step) & 0xffff
+          self.bc = (bc - 1) & 0xffff
+          @wz = (@wz + step) & 0xffff
+          assign_flags((@f & CF) | NF | half | (SZ53[result] & (SF | ZF)) | (adjusted & XF) | ((adjusted & 0x02) << 4) |
+                    (bc.zero? ? 0 : PF))
+          repeat_block if repeat && !bc.zero? && !result.zero?
+        end
+
+        def repeat_block
+          @cycles += 5
+          @pc = (@pc - 2) & 0xffff
+          @wz = (@pc + 1) & 0xffff
+          assign_flags((@f & ~XYF) | ((@pc >> 8) & XYF))
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/z80/bus_cycles.rb

@@ -0,0 +1,113 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class Z80
+      # The machine cycles that reach the bus. An opcode fetch (M1) takes 4
+      # T-states and refreshes a row of DRAM, which counts up the low 7 bits
+      # of R. A memory read or write takes 3, and an I/O read or write 4,
+      # one of them the wait state the Z80 inserts itself. Each calls the bus
+      # on its first T-state, and T-states the CPU spends inside lengthen
+      # the machine cycle before them.
+      module BusCycles
+        private
+
+        def fetch_opcode
+          opcode = @bus.fetch(@pc)
+          @pc = (@pc + 1) & 0xffff
+          refresh
+          @cycles += 4
+          opcode
+        end
+
+        # A halted CPU fetches from the address after HALT, again and again,
+        # and leaves the program counter there.
+        def idle_fetch
+          @bus.fetch(@pc)
+          refresh
+          @cycles += 4
+        end
+
+        def refresh
+          @r = (@r & 0x80) | ((@r + 1) & 0x7f)
+        end
+
+        def read_byte(address)
+          value = @bus.read(address)
+          @cycles += 3
+          value
+        end
+
+        def write_byte(address, value)
+          @bus.write(address, value)
+          @cycles += 3
+        end
+
+        def read_word(address)
+          low = read_byte(address)
+          low | (read_byte((address + 1) & 0xffff) << 8)
+        end
+
+        def write_word(address, value)
+          write_byte(address, value & 0xff)
+          write_byte((address + 1) & 0xffff, value >> 8)
+        end
+
+        def input(port)
+          value = @bus.input(port)
+          @cycles += 4
+          value
+        end
+
+        def output(port, value)
+          @bus.output(port, value)
+          @cycles += 4
+        end
+
+        # The byte after the opcode.
+        def fetch_byte
+          value = read_byte(@pc)
+          @pc = (@pc + 1) & 0xffff
+          value
+        end
+
+        def fetch_word
+          low = fetch_byte
+          low | (fetch_byte << 8)
+        end
+
+        def push(value)
+          @sp = (@sp - 1) & 0xffff
+          write_byte(@sp, value >> 8)
+          @sp = (@sp - 1) & 0xffff
+          write_byte(@sp, value & 0xff)
+        end
+
+        def pop
+          low = read_byte(@sp)
+          high = read_byte((@sp + 1) & 0xffff)
+          @sp = (@sp + 2) & 0xffff
+          low | (high << 8)
+        end
+
+        # The address of an (HL) operand, or of (IX+d), whose displacement is
+        # read from after the opcode and added in 5 T-states inside.
+        def operand_address
+          return hl if @prefix.zero?
+
+          displaced
+          @cycles += 5
+          @wz
+        end
+
+        # Reads the displacement of an (IX+d) or (IY+d) operand and leaves
+        # the address in WZ.
+        def displaced
+          offset = fetch_byte
+          offset -= 256 if offset > 127
+          @wz = (index_register + offset) & 0xffff
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/z80/core.rb

@@ -0,0 +1,115 @@
+# frozen_string_literal: true
+
+require "badline/chips/z80/flags"
+require "badline/chips/z80/registers"
+require "badline/chips/z80/bus_cycles"
+require "badline/chips/z80/arithmetic"
+require "badline/chips/z80/shifts"
+require "badline/chips/z80/loads"
+require "badline/chips/z80/exchanges"
+require "badline/chips/z80/jumps"
+require "badline/chips/z80/main_page"
+require "badline/chips/z80/bit_page"
+require "badline/chips/z80/extended_page"
+require "badline/chips/z80/block_transfers"
+require "badline/chips/z80/block_io"
+require "badline/chips/z80/interrupt_acceptance"
+require "badline/chips/z80/saved_state"
+
+module Badline
+  module Chips
+    class Z80
+      # The Z80 core, on whatever bus +bus+ is. The bus answers
+      # fetch(address) for an opcode fetch (M1), read(address) and
+      # write(address, value) for memory, input(port) and output(port, value)
+      # for I/O, and acknowledge for the byte a device puts on the data bus
+      # when the CPU takes a maskable interrupt.
+      #
+      # #step! runs one instruction, prefixes and all, or takes an interrupt,
+      # or idles one opcode fetch while halted. #cycles counts T-states, and
+      # each bus call happens while it holds the T-state its machine cycle
+      # starts on.
+      module Core
+        include Flags
+        include Registers
+        include BusCycles
+        include Arithmetic
+        include Shifts
+        include Loads
+        include Exchanges
+        include Jumps
+        include MainPage
+        include BitPage
+        include ExtendedPage
+        include BlockTransfers
+        include BlockIO
+        include InterruptAcceptance
+        include SavedState
+
+        attr_reader :bus, :cycles, :nmi
+        attr_accessor :int
+
+        def initialize(bus)
+          @bus = bus
+          @cycles = 0
+          @a = @f = 0xff
+          @b = @c = @d = @e = @h = @l = 0xff
+          @af_alt = @bc_alt = @de_alt = @hl_alt = 0xffff
+          @ix = @iy = @sp = 0xffff
+          @wz = @q = @last_q = 0
+          @prefix = 0
+          @int = @nmi = @nmi_pending = false
+          reset!
+        end
+
+        # The RESET line: the program counter, I, R and the interrupt mode go
+        # to 0, and interrupts are disabled.
+        def reset!
+          @pc = @i = @r = @im = 0
+          @iff1 = @iff2 = false
+          @halted = @after_ei = @after_ld_a_ir = false
+          @nmi_pending = false
+        end
+
+        # The NMI line. Asserting it latches an interrupt, taken after the
+        # current instruction, and holding it does nothing more.
+        def nmi=(asserted)
+          @nmi_pending = true if asserted && !@nmi
+          @nmi = asserted
+        end
+
+        # The WAIT line: a bus that holds it during an access lengthens that
+        # machine cycle by +states+ T-states.
+        def wait(states)
+          @cycles += states
+        end
+
+        def step!
+          if @nmi_pending
+            take_nmi
+          elsif @int && @iff1 && !@after_ei
+            take_int
+          else
+            @after_ei = @after_ld_a_ir = false
+            @last_q = @q
+            @q = 0
+            @prefix = 0
+            @halted ? idle_fetch : execute(fetch_opcode)
+          end
+          nil
+        end
+
+        def inspect
+          "Cycles: #{@cycles}, PC: #{hex(@pc)}, SP: #{hex(@sp)}, AF: #{hex(af)}, BC: #{hex(bc)}, " \
+            "DE: #{hex(de)}, HL: #{hex(hl)}, IX: #{hex(@ix)}, IY: #{hex(@iy)}"
+        end
+
+        private
+
+        def hex(value)
+          value.to_s(16).rjust(4, "0")
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/z80/exchanges.rb

@@ -0,0 +1,52 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class Z80
+      # EX AF,AF', EXX, EX DE,HL and EX (SP),HL. Only the last swaps IX or IY
+      # after a prefix.
+      module Exchanges
+        private
+
+        def exchange_alternates
+          bc_alt = @bc_alt
+          de_alt = @de_alt
+          hl_alt = @hl_alt
+          @bc_alt = bc
+          @de_alt = de
+          @hl_alt = hl
+          self.bc = bc_alt
+          self.de = de_alt
+          self.hl = hl_alt
+        end
+
+        def exchange_af
+          af_alt = @af_alt
+          @af_alt = af
+          self.af = af_alt
+        end
+
+        def exchange_de_hl
+          d = @d
+          e = @e
+          @d = @h
+          @e = @l
+          @h = d
+          @l = e
+        end
+
+        def exchange_stack_top
+          low = read_byte(@sp)
+          high = read_byte((@sp + 1) & 0xffff)
+          @cycles += 1
+          value = hl_or_index
+          write_byte((@sp + 1) & 0xffff, value >> 8)
+          write_byte(@sp, value & 0xff)
+          @cycles += 2
+          @wz = low | (high << 8)
+          self.hl_or_index = @wz
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/z80/extended_page.rb

@@ -0,0 +1,91 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class Z80
+      # The interrupt mode each of ED 46, 4E, 56, 5E, 66, 6E, 76 and 7E sets.
+      # 4E and 6E set mode 0 on the NMOS Z80.
+      INTERRUPT_MODES = [0, 0, 1, 2, 0, 0, 1, 2].freeze
+
+      # The ED page: its second quarter, the block instructions, and 8
+      # T-states of nothing for the rest.
+      module ExtendedPage
+        private
+
+        def execute_extended(opcode)
+          case opcode >> 6
+          when 1 then extended_operation(opcode)
+          when 2 then block_operation(opcode) if (opcode & 0x24) == 0x20
+          end
+        end
+
+        def extended_operation(opcode)
+          row = (opcode >> 3) & 7
+          case opcode & 7
+          when 0 then input_register(row)
+          when 1 then output_register(row)
+          when 2 then add_pair_with_carry(row)
+          when 3 then row.nobits?(1) ? store_word(pair(row >> 1)) : set_pair(row >> 1, load_word)
+          when 4 then neg
+          when 5 then return_from_interrupt
+          when 6 then @im = INTERRUPT_MODES[row]
+          else special_register(row)
+          end
+        end
+
+        # IN r,(C), and IN F,(C) at index 6, which sets the flags alone.
+        def input_register(index)
+          port = bc
+          value = input(port)
+          @wz = (port + 1) & 0xffff
+          assign_flags((@f & CF) | SZ53P[value])
+          set_register(index, value) unless index == 6
+        end
+
+        # OUT (C),r, and at index 6 OUT (C),0.
+        def output_register(index)
+          port = bc
+          output(port, index == 6 ? 0 : register(index))
+          @wz = (port + 1) & 0xffff
+        end
+
+        def add_pair_with_carry(row)
+          row.nobits?(1) ? sbc16(pair(row >> 1)) : adc16(pair(row >> 1))
+          @cycles += 7
+        end
+
+        # RETN and RETI both restore IFF1 from IFF2.
+        def return_from_interrupt
+          @iff1 = @iff2
+          return_from_call
+        end
+
+        # LD I,A, LD R,A, LD A,I, LD A,R, RRD and RLD, and two that do
+        # nothing.
+        def special_register(row)
+          case row
+          when 0 then @i = load_ir(@a)
+          when 1 then @r = load_ir(@a)
+          when 2 then @a = load_a_from_ir(@i)
+          when 3 then @a = load_a_from_ir(@r)
+          when 4 then rotate_digits(false)
+          when 5 then rotate_digits(true)
+          end
+        end
+
+        def load_ir(value)
+          @cycles += 1
+          value
+        end
+
+        # P/V copies IFF2, and an interrupt taken next clears it again.
+        def load_a_from_ir(value)
+          @cycles += 1
+          assign_flags((@f & CF) | SZ53[value] | (@iff2 ? PF : 0))
+          @after_ld_a_ir = true
+          value
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/z80/flags.rb

@@ -0,0 +1,39 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class Z80
+      CF = 0x01
+      NF = 0x02
+      PF = 0x04
+      XF = 0x08
+      HF = 0x10
+      YF = 0x20
+      ZF = 0x40
+      SF = 0x80
+
+      # Bits 5 and 3, which most instructions copy from a result.
+      XYF = YF | XF
+
+      # S, Z, Y and X as a result byte sets them.
+      SZ53 = Array.new(256) { |v| (v & (SF | XYF)) | (v.zero? ? ZF : 0) }.freeze
+
+      # P/V as parity: set when a byte has an even number of bits set.
+      PARITY = Array.new(256) { |v| (0x6996 >> ((v ^ (v >> 4)) & 0x0f)).nobits?(1) ? PF : 0 }.freeze
+
+      SZ53P = Array.new(256) { |v| SZ53[v] | PARITY[v] }.freeze
+
+      # The flags, which the core keeps in F as the chip does. Every
+      # instruction that sets them through the ALU also latches them in Q,
+      # which SCF and CCF read on the next instruction.
+      module Flags
+        private
+
+        def assign_flags(value)
+          @f = value
+          @q = value
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/z80/interrupt_acceptance.rb

@@ -0,0 +1,48 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class Z80
+      # Taking NMI and INT between instructions. Either wakes a halted CPU,
+      # whose program counter already points past the HALT.
+      module InterruptAcceptance
+        private
+
+        # An opcode fetch whose byte is ignored, a T-state more, and a call
+        # to $0066. IFF2 keeps what IFF1 held, for RETN to restore.
+        def take_nmi
+          @nmi_pending = false
+          @halted = false
+          @iff1 = false
+          @bus.fetch(@pc)
+          refresh
+          @cycles += 5
+          push(@pc)
+          @pc = 0x66
+          @wz = 0x66
+        end
+
+        # The acknowledge cycle, an M1 with two wait states, reads a byte
+        # from the device. Mode 0 runs it as an opcode, which is a RST in
+        # practice, mode 1 calls $0038, and mode 2 calls through the vector
+        # at I and that byte.
+        def take_int
+          @halted = false
+          @f &= ~PF if @after_ld_a_ir
+          @iff1 = @iff2 = false
+          @after_ld_a_ir = false
+          @prefix = 0
+          data = @bus.acknowledge
+          refresh
+          @cycles += 6
+          return execute(data) if @im.zero?
+
+          @cycles += 1
+          push(@pc)
+          @pc = @im == 1 ? 0x38 : read_word((@i << 8) | data)
+          @wz = @pc
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/z80/jumps.rb

@@ -0,0 +1,84 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class Z80
+      # Jumps, calls and returns. Each leaves its target in WZ, and JP cc and
+      # CALL cc do whether they jump or not.
+      module Jumps
+        private
+
+        # The conditions bits 5-3 pick: NZ Z NC C PO PE P M.
+        def condition?(index)
+          case index
+          when 0 then @f.nobits?(ZF)
+          when 1 then @f.anybits?(ZF)
+          when 2 then @f.nobits?(CF)
+          when 3 then @f.anybits?(CF)
+          when 4 then @f.nobits?(PF)
+          when 5 then @f.anybits?(PF)
+          when 6 then @f.nobits?(SF)
+          else @f.anybits?(SF)
+          end
+        end
+
+        # NOP, EX AF,AF', DJNZ, JR and JR cc.
+        def relative_jump(row)
+          case row
+          when 0 then nil
+          when 1 then exchange_af
+          when 2 then decrement_and_jump
+          when 3 then jump_relative(fetch_byte)
+          else
+            offset = fetch_byte
+            jump_relative(offset) if condition?(row - 4)
+          end
+        end
+
+        def decrement_and_jump
+          @cycles += 1
+          offset = fetch_byte
+          @b = (@b - 1) & 0xff
+          jump_relative(offset) unless @b.zero?
+        end
+
+        def jump_relative(offset)
+          @cycles += 5
+          @pc = (@pc + offset - (offset > 127 ? 256 : 0)) & 0xffff
+          @wz = @pc
+        end
+
+        def jump(taken)
+          @wz = fetch_word
+          @pc = @wz if taken
+        end
+
+        def call(taken)
+          @wz = fetch_word
+          return unless taken
+
+          @cycles += 1
+          push(@pc)
+          @pc = @wz
+        end
+
+        def conditional_return(index)
+          @cycles += 1
+          return_from_call if condition?(index)
+        end
+
+        def return_from_call
+          @pc = pop
+          @wz = @pc
+        end
+
+        def restart(address)
+          @cycles += 1
+          push(@pc)
+          @pc = address
+          @wz = address
+        end
+      end
+    end
+  end
+end