badline 0.12.0 → 0.13.0

data/lib/badline/chips/sid.rb

@@ -0,0 +1,265 @@
+# frozen_string_literal: true
+
+require "badline/chips/sid/waveform"
+require "badline/chips/sid/envelope"
+require "badline/chips/sid/voice"
+require "badline/chips/sid/filter"
+require "badline/chips/sid/decimator"
+require "badline/chips/sid/catch_up"
+require "badline/chips/sid/saved_state"
+
+module Badline
+  module Chips
+    # SID (Sound Interface Device) chip, in either the 6581 or the 8580
+    # revision.
+    #
+    # $D400-$D418 - Voices, filter and volume   - write only
+    # $D419-$D41A - POTX/POTY paddle inputs     - read only
+    # $D41B-$D41C - Voice 3 oscillator/envelope - read only
+    # $D41D-$D41F - Unconnected
+    #
+    # The register file mirrors every 32 bytes up to $D7FF. A second or
+    # third SID, which only the SID player fits, is built `at` another
+    # address and decodes just the 32 bytes there.
+    #
+    # Reading a write-only or unconnected register returns the last byte the
+    # SID saw on the data bus. That value fades to $00 as the capacitance
+    # holding it drains. Paddles and the 1351 mouse attach as a pots source
+    # responding to #pot_x and #pot_y; with none attached the lines read $FF.
+    #
+    # Three voices feed the filter and the master volume; #output and #sample
+    # read out the mixed result, and #record collects it at an audio rate for
+    # #drain_samples. The DSP is clocked lazily and catches up when something
+    # asks for its state.
+    #
+    # The 6581 drives its voices well above ground, so the mix carries a large
+    # DC offset that the RC network on the C64 board filters out.
+    class SID
+      include Addressable
+      include CatchUp
+      include SavedState
+
+      VOICES = 3
+
+      # Cycles the data bus holds a value, measured through SID/bitfade.
+      BUS_TTL = { mos6581: 0x1d00, mos8580: 0xa2000 }.freeze
+
+      # Scales the filter's 20-bit mix down to a signed 16-bit sample, as
+      # reSID 0.16 does: three voices at full swing and volume 15 span the
+      # whole range, on either chip.
+      SAMPLE_DIVISOR = ((0xfff * 0xff) >> 7) * 3 * 15 * 2 / (2**16)
+
+      # Writes the DSP queues between catch-ups. A full queue catches up
+      # there and then, so no write loses its timing.
+      DEFERRED_WRITES = 0x400
+
+      # Cycles the filter integrates in one step while synthesizing, after
+      # reSID's delta_t_flt. 1 makes the audio exact, at a per-cycle cost.
+      FILTER_CHUNK = 4
+
+      attr_accessor :pots
+      attr_reader :model
+
+      def initialize(model: :mos6581, pots: nil, filter_chunk: FILTER_CHUNK, at: 0xd400)
+        addressable_at(at, length: at == 0xd400 ? 2**10 : 2**5)
+        @model = model
+        @pots = pots
+        @bus_ttl_reset = BUS_TTL.fetch(model)
+        @filter = Filter.new(model:)
+        @synthesizing = false
+        @stepped = @synced = false
+        @pending_cycles = 0
+        @deferred_writes = []
+        @decimator = nil
+        @samples = []
+        @voice_samples = nil
+        @filter_chunk = filter_chunk
+        @voices = Voice.linked(VOICES, model:)
+        @voice1, @voice2, @voice3 = @voices
+        @waveform1, @waveform2, @waveform3 = @voices.map(&:waveform)
+        reset!
+      end
+
+      # Switches the chip, its filter and its voices to the other model's
+      # values. The cycles already passed run on the old model first, and the
+      # running state carries over.
+      def model=(model)
+        catch_up
+        @model = model
+        @bus_ttl_reset = BUS_TTL.fetch(model)
+        @filter.model = model
+        @voices.each { |voice| voice.model = model }
+        update_span_rules
+      end
+
+      # The RES line clears the registers, the data bus, the filter and the
+      # voices, all but their accumulators. Recording carries on across it.
+      def reset!
+        catch_up
+        @registers = Memory.new(length: 2**5)
+        @bus_value = 0x00
+        @bus_ttl = 0
+        @voices.each(&:reset!)
+        @filter.reset
+        update_span_rules
+      end
+
+      # The DSP only counts cycles as they pass. Whatever asks for its state
+      # catches it up, a span at a time: each span fast-forwards the voices
+      # and ends on one whole cycle, so everything the CPU can read stays
+      # exact. The filter only runs once something wants audio.
+      def synthesizing? = @synthesizing
+
+      def synthesize!
+        return if @synthesizing
+
+        @synthesizing = true
+        update_span_rules
+        catch_up
+      end
+
+      # Starts collecting the output, averaged down to `rate` samples a
+      # second, for #drain_samples. `filter_chunk` overrides the one the SID
+      # was built with, for a machine that built its own. `clock_hz` is the
+      # rate the SID's cycles are taken to run at.
+      def record(rate:, filter_chunk: @filter_chunk, clock_hz: Region::PAL.clock_hz)
+        synthesize!
+        catch_up
+        @filter_chunk = filter_chunk
+        @decimator = Decimator.new(clock_hz:, rate:)
+        @samples = []
+      end
+
+      # Also keeps each voice's own output, before the filter and the volume,
+      # as each recorded sample closes, for #drain_voice_samples.
+      def record_voices!
+        @voice_samples = [] if @voice_samples.nil?
+      end
+
+      # The voices' outputs since the last drain, three to a sample, in voice
+      # order, or nothing unless #record_voices! asked for them.
+      def drain_voice_samples
+        return [] if @voice_samples.nil?
+
+        catch_up
+        samples = @voice_samples
+        @voice_samples = []
+        samples
+      end
+
+      # The samples recorded since the last drain.
+      def drain_samples
+        catch_up
+        samples = @samples
+        @samples = []
+        samples
+      end
+
+      def voices
+        catch_up
+        @voices
+      end
+
+      # Runs the DSP up to the current cycle.
+      def catch_up! = catch_up
+
+      # The byte the data bus holds and the cycles until it fades.
+      def bus_state = [@bus_value, @bus_ttl]
+
+      def restore_bus(value, ttl)
+        @bus_value = value
+        @bus_ttl = ttl
+      end
+
+      def filter
+        catch_up
+        @filter
+      end
+
+      # Voice 3's oscillator and envelope, the only synthesis state the CPU
+      # can see. Programs poll OSC3 with the noise waveform selected for
+      # random numbers, and ENV3 to time hard restarts.
+      def osc3
+        catch_up
+        @waveform3.osc3 >> 4
+      end
+
+      def env3
+        catch_up
+        @voice3.envelope.env3
+      end
+
+      def output
+        synthesize!
+        catch_up
+        @filter.output
+      end
+
+      def sample
+        output
+        current_sample
+      end
+
+      def cycle!
+        age_bus if @bus_ttl != 0
+        @pending_cycles += 1
+      end
+
+      def peek(addr)
+        case offset_of(addr) % (2**5)
+        when 0x19 then latch(pots ? pots.pot_x : 0xff)
+        when 0x1a then latch(pots ? pots.pot_y : 0xff)
+        when 0x1b then latch(osc3)
+        when 0x1c then latch(env3)
+        else @bus_value
+        end
+      end
+
+      def poke(addr, value)
+        reg = offset_of(addr) % (2**5)
+        write_register(reg, value) if reg <= 0x18
+        latch(value)
+      end
+
+      # Register contents as written, for save states and debugging.
+      def register(reg) = @registers.peek(reg)
+
+      private
+
+      def latch(value)
+        @bus_ttl = @bus_ttl_reset
+        @bus_value = value
+      end
+
+      def age_bus
+        @bus_ttl -= 1
+        @bus_value = 0x00 if @bus_ttl.zero?
+      end
+
+      def write_register(reg, value)
+        @registers.poke(reg, value)
+        catch_up if @deferred_writes.length == DEFERRED_WRITES * 3
+        @deferred_writes.push(@pending_cycles, reg, value)
+      end
+
+      def apply_write(reg, value)
+        reg < 0x15 ? write_voice(reg, value) : @filter.write(reg, value)
+      end
+
+      def write_voice(reg, value)
+        voice = @voices[reg / 7]
+        case reg % 7
+        when 0 then voice.waveform.frequency_low = value
+        when 1 then voice.waveform.frequency_high = value
+        when 2 then voice.waveform.pulse_width_low = value
+        when 3 then voice.waveform.pulse_width_high = value
+        when 4
+          voice.control = value
+          update_span_rules
+        when 5 then voice.envelope.attack_decay = value
+        when 6 then voice.envelope.sustain_release = value
+        end
+      end
+    end
+  end
+end

data/lib/badline/{c128 → chips}/vdc/memory.rb

@@ -1,7 +1,7 @@
 # frozen_string_literal: true
 
 module Badline
-  class C128
+  module Chips
     class VDC
       # The VDC's own DRAM: 16K of two 4416s (16K by 4) or 64K of 4164s or
       # 4464s, behind the 16-bit addresses the VDC computes.

data/lib/badline/{c128 → chips}/vdc/painter.rb

@@ -1,7 +1,7 @@
 # frozen_string_literal: true
 
 module Badline
-  class C128
+  module Chips
     class VDC
       # Paints the VDC's scan lines into its display, one line at a time,
       # from the registers as they stand when the line ends. Each pixel of

data/lib/badline/{c128 → chips}/vdc/raster.rb

@@ -1,7 +1,7 @@
 # frozen_string_literal: true
 
 module Badline
-  class C128
+  module Chips
     class VDC
       # The VDC's raster: R0 + 1 characters a line, R9 + 1 lines a row,
       # R4 + 1 rows a frame and then R5 more lines, with the frame's size

data/lib/badline/chips/vdc/saved_state.rb

@@ -0,0 +1,36 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class VDC
+      # The VDC's state for a snapshot.
+      module SavedState
+        # Everything the VDC holds but its display, which it paints again
+        # while it renders: the registers, the RAM, the data port and the
+        # raster. Whether it renders is the host's.
+        def save_state(out)
+          out.marker("VDC")
+          out.ints(@registers).blob(@memory.ram)
+          out.int(@selected).int(@read_latch).int(@write_data).int(@busy_until).int(@phase).int(@line_units)
+          @raster.save_state(out)
+          @painter.save_state(out)
+        end
+
+        def load_state(input)
+          input.marker("VDC")
+          input.ints_into(@registers)
+          input.blob_into(@memory.ram)
+          @memory.mode64 = @registers[28].anybits?(0x10)
+          @selected = input.int
+          @read_latch = input.int
+          @write_data = input.int
+          @busy_until = input.int
+          @phase = input.int
+          @line_units = input.int
+          @raster.load_state(input)
+          @painter.load_state(input)
+        end
+      end
+    end
+  end
+end

data/lib/badline/{c128 → chips}/vdc/window.rb

@@ -1,7 +1,7 @@
 # frozen_string_literal: true
 
 module Badline
-  class C128
+  module Chips
     class VDC
       # Paints the characters of a displayed line, R1 of them from the
       # line's first dot, in text mode or, with R25 bit 7, bitmap mode.

data/lib/badline/{c128 → chips}/vdc.rb

@@ -1,12 +1,13 @@
 # frozen_string_literal: true
 
-require "badline/c128/vdc/memory"
-require "badline/c128/vdc/window"
-require "badline/c128/vdc/painter"
-require "badline/c128/vdc/raster"
+require "badline/chips/vdc/memory"
+require "badline/chips/vdc/window"
+require "badline/chips/vdc/painter"
+require "badline/chips/vdc/raster"
+require "badline/chips/vdc/saved_state"
 
 module Badline
-  class C128
+  module Chips
     # The 8563 or 8568 VDC: the address register at $D600 and the data
     # register at $D601, mirrored through $D6FF, in front of 37 internal
     # registers (38 on the 8568), the VDC's own RAM (Memory) and its 80
@@ -33,6 +34,7 @@ module Badline
     # fills or two per byte it copies.
     class VDC
       include Addressable
+      include SavedState
 
       STATUS_READY = 0x80
       STATUS_VBLANK = 0x20
@@ -112,32 +114,6 @@ module Badline
         @painter.clear!
       end
 
-      # Everything the VDC holds but its display, which it paints again
-      # while it renders: the registers, the RAM, the data port and the
-      # raster. Whether it renders is the host's.
-      def save_state(out)
-        out.marker("VDC")
-        out.ints(@registers).blob(@memory.ram)
-        out.int(@selected).int(@read_latch).int(@write_data).int(@busy_until).int(@phase).int(@line_units)
-        @raster.save_state(out)
-        @painter.save_state(out)
-      end
-
-      def load_state(input)
-        input.marker("VDC")
-        input.ints_into(@registers)
-        input.blob_into(@memory.ram)
-        @memory.mode64 = @registers[28].anybits?(0x10)
-        @selected = input.int
-        @read_latch = input.int
-        @write_data = input.int
-        @busy_until = input.int
-        @phase = input.int
-        @line_units = input.int
-        @raster.load_state(input)
-        @painter.load_state(input)
-      end
-
       # The frames the raster has finished, which the blinking counts.
       def frame = @raster.frame
 

data/lib/badline/chips/via/control_lines.rb

@@ -0,0 +1,124 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class VIA
+      # One port's pair of control lines, CA1 and CA2 or CB1 and CB2, set up
+      # by a nibble of the peripheral control register, and their two
+      # interrupt flags. Bit 0 picks the active edge of C1, rising when set.
+      # Bits 3-1 pick the C2 mode:
+      #
+      #   000 input, falling edge    100 handshake output
+      #   001 independent, falling   101 pulse output
+      #   010 input, rising edge     110 low output
+      #   011 independent, rising    111 high output
+      #
+      # A port access clears both flags, but an independent input keeps C2's.
+      # In handshake mode C2 goes low on a port access and back high on the
+      # next active C1 edge. In pulse mode it goes low for the cycle after the
+      # access. Port A handshakes on reads and writes, port B on writes only.
+      class ControlLines
+        attr_reader :control, :c1_high, :c2_high
+
+        # The level driven on C2, high while it is an input.
+        attr_reader :c2_output
+
+        def initialize(interrupts, c1_flag:, c2_flag:, handshake_on_read:)
+          @interrupts = interrupts
+          @c1_flag = c1_flag
+          @c2_flag = c2_flag
+          @handshake_on_read = handshake_on_read
+          @c1_high = @c2_high = true
+          reset!
+        end
+
+        # Back to input mode with both handshake outputs released. The input
+        # levels carry over.
+        def reset!
+          @control = 0
+          @handshake_low = false
+          @pulse = 0
+          drive
+        end
+
+        def control=(nibble)
+          @control = nibble & 0x0f
+          drive
+        end
+
+        # Only the pulse output needs the clock.
+        def pulsing? = @pulse.positive?
+
+        def cycle!
+          @pulse -= 1
+          drive if @pulse.zero?
+        end
+
+        def active_c1_edge?(high) = high == @control.anybits?(0x01)
+
+        # The lines' levels and mode. Which flags they set, and whether reads
+        # handshake, are the port's wiring.
+        def save_state(out)
+          out.int(@control).boolean(@c1_high).boolean(@c2_high).boolean(@handshake_low).int(@pulse).boolean(@c2_output)
+        end
+
+        def load_state(input)
+          @control = input.int
+          @c1_high = input.boolean?
+          @c2_high = input.boolean?
+          @handshake_low = input.boolean?
+          @pulse = input.int
+          @c2_output = input.boolean?
+        end
+
+        # Everything the lines hold, for comparing them at two points.
+        def state = [@control, @c1_high, @c2_high, @handshake_low, @pulse, @c2_output]
+
+        # A new C1 level. An active edge sets the flag and ends a handshake.
+        def c1=(high)
+          return if high == @c1_high
+
+          @c1_high = high
+          return unless active_c1_edge?(high)
+
+          @handshake_low = false
+          drive
+          @interrupts.set(@c1_flag)
+        end
+
+        # A new C2 level. An active edge sets the flag while C2 is an input.
+        def c2=(high)
+          return if high == @c2_high
+
+          @c2_high = high
+          @interrupts.set(@c2_flag) if @control.nobits?(0x08) && high == @control.anybits?(0x04)
+        end
+
+        # A read or write of the handshaking port register.
+        def access!(write)
+          @interrupts.clear(independent? ? @c1_flag : @c1_flag | @c2_flag)
+          return unless write || @handshake_on_read
+
+          case @control >> 1
+          when 4 then @handshake_low = true
+          when 5 then @pulse = 2
+          end
+          drive
+        end
+
+        private
+
+        def independent? = @control & 0x0a == 0x02
+
+        def drive
+          @c2_output = case @control >> 1
+                       when 4 then !@handshake_low
+                       when 5 then @pulse.zero?
+                       when 6 then false
+                       else true
+                       end
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/via/fast_forward.rb

@@ -0,0 +1,55 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class VIA
+      # Running a VIA a stretch of cycles at once while nothing but its
+      # counters would change, for Drives::Engine::Idle.
+      module FastForward
+        # quiet_cycles for a VIA that will never set a flag of its own.
+        QUIET = 1 << 40
+
+        # How many cycles the VIA can run with nothing but its counters
+        # changing: no flag set, no pulse on a control line and no bit
+        # shifted. See Drives::Engine::Idle.
+        def quiet_cycles
+          return 0 if @sr_uses_t2 || @shift_register.clocking? || @ca.pulsing? || @cb.pulsing?
+
+          [@t1.quiet_cycles, @t2.quiet_cycles].min
+        end
+
+        # Runs +cycles+ cycles at once, as many as quiet_cycles allows, which
+        # moves only the counters.
+        def fast_forward(cycles)
+          return if cycles.zero?
+
+          @t1.fast_forward(cycles)
+          @t2.fast_forward(cycles)
+        end
+
+        # The counters an orbit (see Drives::Engine::Idle) has to bring back: those
+        # of the armed timers, and of the timers +touched+ names (bit 0 for
+        # timer 1, bit 1 for timer 2). The others only count.
+        def counter_state(touched)
+          [(@t1.count_state if @t1.armed? || touched.anybits?(1)),
+           (@t2.count_state if @t2.armed? || touched.anybits?(2))]
+        end
+
+        # Runs +cycles+ cycles of whole orbits at once: the counters
+        # counter_state leaves out move on, and the rest come back round.
+        def skip_orbits(cycles, touched)
+          @t1.fast_forward(cycles) unless @t1.armed? || touched.anybits?(1)
+          @t2.fast_forward(cycles) unless @t2.armed? || touched.anybits?(2)
+        end
+
+        # Everything the VIA holds but its counters, for comparing it at two
+        # points. Timer 1's PB7 level counts only while ACR bit 7 puts it on
+        # the pin: nothing reads it otherwise.
+        def idle_state
+          [@ora, @orb, @ddra, @ddrb, @latch_a, @latch_b, @acr, @pcr, @pb6_high, @ifr.flags, @ifr.enable,
+           @acr.anybits?(0x80) && @t1.pb7, *@t1.state, *@t2.state, *@ca.state, *@cb.state, *@shift_register.state]
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/via/interrupt_register.rb

@@ -0,0 +1,69 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class VIA
+      # The interrupt flag and enable registers. Each source has a flag bit,
+      # and IRQ is pulled low while any flag is set with its enable bit.
+      class InterruptRegister
+        CA2 = 0x01
+        CA1 = 0x02
+        SR = 0x04
+        CB2 = 0x08
+        CB1 = 0x10
+        TIMER2 = 0x20
+        TIMER1 = 0x40
+
+        attr_reader :flags, :enable
+
+        def initialize
+          reset!
+        end
+
+        def reset!
+          @flags = 0x00
+          @enable = 0x00
+        end
+
+        def save_state(out)
+          out.int(@flags).int(@enable)
+        end
+
+        def load_state(input)
+          @flags = input.int
+          @enable = input.int
+        end
+
+        def set(bits)
+          @flags |= bits
+        end
+
+        def clear(bits)
+          @flags &= ~bits
+        end
+
+        def irq? = @flags.anybits?(@enable)
+
+        # Bit 7 reads the IRQ output.
+        def read = irq? ? @flags | 0x80 : @flags
+
+        # Writing 1s clears the flags; bit 7 is ignored.
+        def write(value)
+          clear(value & 0x7f)
+        end
+
+        # Bit 7 reads as 1.
+        def read_enable = @enable | 0x80
+
+        # Bit 7 picks between setting and clearing the enable bits given.
+        def write_enable(value)
+          if value.anybits?(0x80)
+            @enable |= value & 0x7f
+          else
+            @enable &= ~value & 0x7f
+          end
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/via/saved_state.rb

@@ -0,0 +1,44 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class VIA
+      # Saving and restoring a VIA for a snapshot.
+      module SavedState
+        # The registers, the timers, the shift register, the interrupt flags
+        # and the control lines. The peripheral is the drive's wiring.
+        def save_state(out)
+          out.int(@ora).int(@orb).int(@ddra).int(@ddrb).int(@latch_a).int(@latch_b).int(@acr).int(@pcr)
+          out.boolean(@pb6_high).boolean(@sr_uses_t2)
+          @t1.save_state(out)
+          @t2.save_state(out)
+          @shift_register.save_state(out)
+          @ifr.save_state(out)
+          @ca.save_state(out)
+          @cb.save_state(out)
+        end
+
+        # Puts the state back without telling the peripheral, which restores
+        # its own.
+        def load_state(input)
+          @ora = input.int
+          @orb = input.int
+          @ddra = input.int
+          @ddrb = input.int
+          @latch_a = input.int
+          @latch_b = input.int
+          @acr = input.int
+          @pcr = input.int
+          @pb6_high = input.boolean?
+          @sr_uses_t2 = input.boolean?
+          @t1.load_state(input)
+          @t2.load_state(input)
+          @shift_register.load_state(input)
+          @ifr.load_state(input)
+          @ca.load_state(input)
+          @cb.load_state(input)
+        end
+      end
+    end
+  end
+end