badline 0.12.0 → 0.13.0

data/lib/badline/cpu/core.rb

@@ -1,165 +0,0 @@
-# frozen_string_literal: true
-
-require "badline/cpu/microcode"
-require "badline/cpu/addressing"
-require "badline/cpu/operations"
-require "badline/cpu/stack_operations"
-require "badline/cpu/boundary"
-require "badline/cpu/saved_state"
-
-module Badline
-  class CPU
-    STATUS_FLAGS = [:carry, :zero, :interrupt, :decimal, :break, 1, :overflow, :negative].freeze
-
-    # The 6502 core, on whatever bus +memory+ is. The C64's 6510 (CPU) and
-    # the 1541's 6502 (Drive1541::CPU) each include it.
-    module Core
-      include IntegerHelper
-      include InstructionSet
-      include Interrupts
-      include Traps
-      include Addressing
-      include Operations
-      include StackOperations
-      include Boundary
-      include SavedState
-
-      attr_reader :memory, :instructions, :boundary_crossed, :cycles, :pending_write
-      attr_accessor :program_counter, :stack_pointer, :status, :a, :x, :y, :nmi, :irq
-
-      alias pending_write? pending_write
-
-      # +ane_constant+ is ANE's magic constant, which varies from chip to
-      # chip. The default is the C64 6510's.
-      def initialize(memory, debug: false, ane_constant: 0xef)
-        @debug = debug
-        @ane_constant = ane_constant
-        @memory = memory
-        @status = CPUStatus.new(STATUS_FLAGS, value: 0b00100000)
-        reset_registers
-
-        @nmi = @irq = false
-        @irq_sample = @irq_pending = false
-        @nmi_sample = @nmi_pending = false
-        @skip_poll = false
-        @boundary_crossed = false
-        @interrupt = nil
-        @brk = false
-        @pending_write = false
-        @stalled_at = nil
-        @so_high = true
-
-        @cycles = 0
-        @instructions = 0
-        @traps = nil
-        end_sequence
-      end
-
-      def reset!
-        status.interrupt = true
-        reset_registers
-        @nmi = false
-        @irq_sample = @irq_pending = false
-        @nmi_sample = @nmi_pending = false
-        @skip_poll = false
-        @pending_write = false
-        end_sequence
-      end
-
-      def p
-        status.value
-      end
-
-      def p=(new_value)
-        status.value = new_value
-      end
-
-      def cycle!
-        poll # the interrupt lines
-
-        # Run the next step
-        index = @index
-        @index = index + 1
-        send(@plan[index])
-        @cycles += 1
-
-        # Record if the next step writes to memory
-        @pending_write = @writes[@index]
-        nil
-      end
-
-      # Called instead of #cycle! on a cycle the VIC holds the CPU through
-      # BA. Records which cycle the CPU was stalled before, and keeps
-      # sampling the interrupt lines.
-      def stall!
-        @stalled_at = @cycles
-        sample_while_stalled
-      end
-
-      # The 6502's SO (set overflow) pin, which the 6510 leaves out, so the
-      # C64 never drives it. A falling edge sets V and a held level does
-      # nothing more.
-      def so=(high)
-        @status.overflow = true if @so_high && !high
-        @so_high = high
-      end
-
-      # Pulses SO: pulls it low, which sets V, and releases it.
-      def so!
-        @status.overflow = true
-        @so_high = true
-      end
-
-      def jammed?
-        @plan.equal?(JAMMED_PLAN)
-      end
-
-      # Runs to the end of the instruction, or until the CPU jams.
-      def step!
-        cycle!
-        cycle! until @plan.equal?(FETCH_PLAN) || jammed?
-        nil
-      end
-
-      # Whether the next cycle fetches an opcode.
-      def boundary? = @index.zero? && @plan.equal?(FETCH_PLAN)
-
-      def trapped? = !@traps.nil?
-
-      def inspect
-        "Cycles: #{@cycles}, PC: #{format16(program_counter)}, " \
-          "SP: #{format8(stack_pointer)}, A: #{format8(a)}, X: #{format8(x)}, " \
-          "Y: #{format8(y)}, P: #{format8(p)}"
-      end
-
-      private
-
-      # True when the CPU was stalled right before this cycle.
-      def stalled_before_this_cycle?
-        @stalled_at == @cycles
-      end
-
-      # True when the CPU was stalled right before the cycle that preceded
-      # this one.
-      def stalled_before_previous_cycle?
-        @stalled_at == @cycles - 1
-      end
-
-      def write_byte(addr, value)
-        @memory.poke(addr, value)
-      end
-
-      def stack_address(offset = 0)
-        0x0100 | ((@stack_pointer + offset) & 0xff)
-      end
-
-      def reset_registers
-        # The program counter is initialized from the reset vector
-        @program_counter = @memory.peek16(0xfffc)
-        # Stack pointer starts at 0x01ff and grows down
-        @stack_pointer = 0xff
-        @a = @x = @y = 0x0
-      end
-    end
-  end
-end

data/lib/badline/cpu/microcode.rb

@@ -1,177 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  class CPU
-    class InvalidOpcodeError < StandardError; end
-
-    # Steps that write to memory. The CPU keeps running through BA on
-    # cycles that write, so Computer#cycle! asks before each cycle whether
-    # the next step is one of these.
-    WRITE_STEPS = %i[
-      op_mem_write op_rmw_write_original op_rmw_write_result op_push_exec op_jsr_push_high op_jsr_push_low
-      op_int_push_pch op_int_push_pcl op_int_push_status
-    ].freeze
-
-    # The steps each addressing mode takes to work out the address an
-    # instruction operates on. They run after the opcode fetch.
-    ADDRESSING_STEPS = {
-      zeropage: %i[op_zp],
-      zeropage_x: %i[op_zp op_zp_x],
-      zeropage_y: %i[op_zp op_zp_y],
-      absolute: %i[op_abs_low op_abs_high],
-      absolute_x: %i[op_abs_low op_abs_high_x op_idx_dummy],
-      absolute_y: %i[op_abs_low op_abs_high_y op_idx_dummy],
-      indirect_x: %i[op_zp_pointer op_pointer_x op_pointer_low op_pointer_high],
-      indirect_y: %i[op_zp_pointer op_pointer_low op_pointer_high_y op_idx_dummy]
-    }.freeze
-
-    # The steps that read or write that address, once it is known.
-    OPERATION_STEPS = {
-      read: %i[op_mem_read],
-      write: %i[op_mem_write],
-      rmw: %i[op_rmw_read op_rmw_write_original op_rmw_write_result]
-    }.freeze
-
-    STORES = %i[sta stx sty sax sha shx shy tas].freeze
-    READ_MODIFY_WRITES = %i[asl lsr rol ror inc dec slo sre rla rra isc dcp].freeze
-    BRANCHES = %i[bcc bcs beq bmi bne bpl bvc bvs].freeze
-
-    # The addresses a 6502 reads after a JAM opcode, before it settles into
-    # JAMMED_PLAN.
-    JAM_ADDRESSES = [0xffff, 0xfffe, 0xfffe].freeze
-
-    # The plan between instructions: the next cycle fetches an opcode.
-    FETCH_PLAN = %i[op_fetch].freeze
-
-    IMPLIED_PLAN = %i[op_fetch op_implied_exec].freeze
-    ACCUMULATOR_PLAN = %i[op_fetch op_accumulator_exec].freeze
-    IMMEDIATE_PLAN = %i[op_fetch op_immediate_read].freeze
-
-    # $10, $30, $50, $70, $90, $B0, $D0, $F0 - relative - 2+ cycles.
-    # A branch that is not taken takes 2 cycles. A taken branch takes 3,
-    # or 4 when the target is on another page.
-    BRANCH_PLAN = %i[op_fetch op_relative op_branch op_branch_fixup].freeze
-
-    # $4C - absolute - 3 cycles
-    JMP_ABSOLUTE_PLAN = %i[op_fetch op_abs_low op_jmp_high].freeze
-
-    # $6C - indirect - 5 cycles
-    JMP_INDIRECT_PLAN = %i[op_fetch op_abs_low op_abs_high op_indirect_low op_indirect_high].freeze
-
-    # $20 - absolute - 6 cycles
-    JSR_PLAN = %i[op_fetch op_jsr_low op_jsr_dummy op_jsr_push_high op_jsr_push_low op_jsr_high].freeze
-
-    # $60 - implied - 6 cycles
-    RTS_PLAN = %i[op_fetch op_implied_dummy op_pull_dummy op_pull_low op_pull_high op_rts_fixup].freeze
-
-    # $40 - implied - 6 cycles
-    RTI_PLAN = %i[op_fetch op_implied_dummy op_pull_dummy op_rti_pull_status op_pull_low op_rti_pull_high].freeze
-
-    # $08, $48 - implied - 3 cycles
-    PUSH_PLAN = %i[op_fetch op_implied_dummy op_push_exec].freeze
-
-    # $28, $68 - implied - 4 cycles
-    PULL_PLAN = %i[op_fetch op_implied_dummy op_pull_dummy op_pull_exec].freeze
-
-    # $02, $12, $22, $32, $42, $52, $62, $72, $92, $B2, $D2, $F2 - illegal
-    JAM_PLAN = [:op_fetch, :op_implied_dummy, *Array.new(JAM_ADDRESSES.length, :op_jam)].freeze
-
-    # A jammed CPU reads $FFFF on every cycle until reset. It never reaches
-    # an instruction boundary, so a pending IRQ or NMI never starts.
-    JAMMED_PLAN = %i[op_jammed].freeze
-
-    # BRK and hardware interrupts push the return address and status, then
-    # read the new PC from a vector. Only the second step differs: BRK's
-    # selects the IRQ vector and sets the break flag it pushes.
-    #
-    # $00 - implied - 7 cycles (BRK)
-    INTERRUPT_PLAN = %i[
-      op_fetch op_implied_dummy op_int_push_pch op_int_push_pcl op_int_push_status
-      op_int_vector_low op_int_vector_high
-    ].freeze
-    BRK_PLAN = %i[
-      op_fetch op_brk_dummy op_int_push_pch op_int_push_pcl op_int_push_status
-      op_int_vector_low op_int_vector_high
-    ].freeze
-
-    SPECIAL_PLANS = {
-      brk: BRK_PLAN, jam: JAM_PLAN, jsr: JSR_PLAN, rts: RTS_PLAN,
-      rti: RTI_PLAN, pha: PUSH_PLAN, php: PUSH_PLAN,
-      pla: PULL_PLAN, plp: PULL_PLAN
-    }.freeze
-
-    # Everything the CPU needs to run one opcode:
-    # - +operation+: the instruction method to call, such as :lda
-    # - +plan+: the step to run on each cycle
-    # - +writes+: which of those steps write to memory
-    # - +optional_dummy+: true for indexed reads, which skip the extra
-    #   cycle unless indexing crosses a page
-    Microcode = Struct.new(:operation, :plan, :writes, :optional_dummy) do
-      def self.table
-        Array.new(256) do |opcode|
-          instruction = Instruction.find(opcode)
-          raise InvalidOpcodeError, format("$%02x", opcode) unless instruction
-
-          build(instruction)
-        end.freeze
-      end
-
-      def self.write_mask(plan)
-        plan.map { |step| WRITE_STEPS.include?(step) }.freeze
-      end
-
-      def self.build(instruction)
-        plan = plan_for(instruction)
-        new(instruction.name, plan, write_mask(plan),
-            instruction.boundary_cycle?)
-      end
-
-      def self.plan_for(instruction)
-        case instruction.name
-        when :jmp
-          if instruction.addressing_mode == :indirect
-            JMP_INDIRECT_PLAN
-          else
-            JMP_ABSOLUTE_PLAN
-          end
-        when *BRANCHES then BRANCH_PLAN
-        else SPECIAL_PLANS[instruction.name] || addressed_plan(instruction)
-        end
-      end
-
-      def self.addressed_plan(instruction)
-        mode = instruction.addressing_mode
-        case mode
-        when :implied then IMPLIED_PLAN
-        when :accumulator then ACCUMULATOR_PLAN
-        when :immediate then IMMEDIATE_PLAN
-        else
-          [:op_fetch, *ADDRESSING_STEPS.fetch(mode),
-           *OPERATION_STEPS.fetch(operation_kind(instruction.name))].freeze
-        end
-      end
-
-      def self.operation_kind(name)
-        return :write if STORES.include?(name)
-        return :rmw if READ_MODIFY_WRITES.include?(name)
-
-        :read
-      end
-
-      private_class_method :build, :plan_for, :addressed_plan, :operation_kind
-    end
-
-    FETCH_WRITES = Microcode.write_mask(FETCH_PLAN)
-    INTERRUPT_WRITES = Microcode.write_mask(INTERRUPT_PLAN)
-    JAMMED_WRITES = Microcode.write_mask(JAMMED_PLAN)
-    MICROCODE = Microcode.table
-
-    # The instruction methods, in a fixed order a snapshot names them by.
-    OPERATIONS = MICROCODE.map(&:operation).uniq.freeze
-
-    # The plans a snapshot names that aren't an opcode's.
-    FETCH = -1
-    INTERRUPT = -2
-    JAMMED = -3
-  end
-end

data/lib/badline/cpu/operations.rb

@@ -1,88 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  class CPU
-    # Steps that read or write an instruction's operand once its address is
-    # known, plus the branch and JAM steps.
-    module Operations
-      private
-
-      def op_mem_read
-        send(@operation, @address, @memory.peek(@address))
-        end_instruction
-      end
-
-      def op_mem_write
-        send(@operation, @address, nil)
-        end_instruction
-      end
-
-      # Read-modify-write instructions (ASL, INC and the like) take three
-      # cycles here: read the value and compute the result, write the
-      # original value back, then write the result. The instruction method
-      # hands the result over through #write_modified.
-      def op_rmw_read
-        @value = @memory.peek(@address)
-        send(@operation, @address, @value)
-      end
-
-      def op_rmw_write_original
-        @memory.poke(@address, @value)
-      end
-
-      def op_rmw_write_result
-        @memory.poke(@address, @rmw_result)
-        end_instruction
-      end
-
-      def op_relative
-        offset = @memory.peek(@program_counter)
-        @program_counter = (@program_counter + 1) & 0xffff
-        @address = (@program_counter + signed_int8(offset)) & 0xffff
-        @branch_taken = false
-        send(@operation, @address, nil)
-        if @branch_taken
-          # A taken branch within the same page doesn't poll on its last cycle.
-          @skip_poll = true if same_page?
-        else
-          end_instruction
-        end
-      end
-
-      def op_branch
-        @memory.peek(@program_counter)
-        return unless same_page?
-
-        @program_counter = @address
-        end_instruction
-      end
-
-      # A branch to another page spends an extra cycle reading from the target's low byte on the old page.
-      def op_branch_fixup
-        @memory.peek((@program_counter & 0xff00) | (@address & 0xff))
-        @program_counter = @address
-        end_instruction
-      end
-
-      def same_page?
-        @address >> 8 == @program_counter >> 8
-      end
-
-      # Runs once for each address in JAM_ADDRESSES. By the time a step runs, @index already points at the next one.
-      def op_jam
-        position = @index - 2
-        @memory.peek(JAM_ADDRESSES[position - 1])
-        return unless position == JAM_ADDRESSES.length
-
-        @plan = JAMMED_PLAN
-        @writes = JAMMED_WRITES
-        @index = 0
-      end
-
-      def op_jammed
-        @index = 0
-        @memory.peek(0xffff)
-      end
-    end
-  end
-end

data/lib/badline/cpu/saved_state.rb

@@ -1,115 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  class CPU
-    # The CPU's state for a snapshot: the registers, the interrupt lines and
-    # their pipeline, and the step of the instruction in flight, named by
-    # where its plan comes from.
-    module SavedState
-      # Writes everything the CPU holds, down to the step of the instruction
-      # it is in, for load_state to put back. The interrupt lines, BA stalls
-      # and SO are state too; the traps and the debug flag belong to the host.
-      def save_state(out)
-        out.marker("CPU")
-        out.int(@program_counter).int(@stack_pointer).int(@a).int(@x).int(@y).int(@status.value)
-        [@irq, @nmi, @irq_sample, @irq_pending, @nmi_sample, @nmi_pending, @skip_poll, @boundary_irq,
-         @boundary_nmi, @boundary_crossed, @brk, @pending_write, @so_high, @optional_dummy,
-         @branch_taken].each { |flag| out.boolean(flag) }
-        out.optional_int(@interrupt).optional_int(@stalled_at).int(@cycles).int(@instructions)
-        out.int(plan_source).int(@index).int(OPERATIONS.index(@operation) || -1)
-        [@address, @dummy_address, @value, @rmw_result, @pointer].each { |register| out.optional_int(register) }
-      end
-
-      def load_state(input)
-        input.marker("CPU")
-        @program_counter = input.int
-        @stack_pointer = input.int
-        @a = input.int
-        @x = input.int
-        @y = input.int
-        @status.value = input.int
-        load_flags(input)
-        @interrupt = input.optional_int
-        @stalled_at = input.optional_int
-        @cycles = input.int
-        @instructions = input.int
-        load_plan(input.int)
-        @index = input.int
-        operation = input.int
-        @operation = operation.negative? ? nil : OPERATIONS.fetch(operation)
-        load_working_registers(input)
-      end
-
-      # Drops the instruction or interrupt sequence in flight and the
-      # interrupt lines' pipeline, so the next cycle fetches an opcode at the
-      # program counter, and sets the cycle count. A snapshot taken between
-      # instructions, as VICE's are, restores through here.
-      def resume(cycles)
-        @irq_sample = @irq_pending = false
-        @nmi_sample = @nmi_pending = false
-        @skip_poll = false
-        @interrupt = nil
-        @brk = false
-        @stalled_at = nil
-        @cycles = cycles
-        end_sequence
-        @pending_write = false
-      end
-
-      private
-
-      # Where the plan running comes from: an opcode's microcode, or FETCH,
-      # INTERRUPT or JAMMED below it.
-      def plan_source
-        return FETCH if @plan.equal?(FETCH_PLAN)
-        return INTERRUPT if @plan.equal?(INTERRUPT_PLAN)
-        return JAMMED if @plan.equal?(JAMMED_PLAN)
-
-        MICROCODE.index { |micro| micro.plan.equal?(@plan) && micro.operation == @operation } ||
-          MICROCODE.index { |micro| micro.plan.equal?(@plan) }
-      end
-
-      def load_plan(source)
-        case source
-        when FETCH then use_plan(FETCH_PLAN, FETCH_WRITES)
-        when INTERRUPT then use_plan(INTERRUPT_PLAN, INTERRUPT_WRITES)
-        when JAMMED then use_plan(JAMMED_PLAN, JAMMED_WRITES)
-        else
-          micro = MICROCODE.fetch(source)
-          use_plan(micro.plan, micro.writes)
-        end
-      end
-
-      def use_plan(plan, writes)
-        @plan = plan
-        @writes = writes
-      end
-
-      def load_flags(input)
-        @irq = input.boolean?
-        @nmi = input.boolean?
-        @irq_sample = input.boolean?
-        @irq_pending = input.boolean?
-        @nmi_sample = input.boolean?
-        @nmi_pending = input.boolean?
-        @skip_poll = input.boolean?
-        @boundary_irq = input.boolean?
-        @boundary_nmi = input.boolean?
-        @boundary_crossed = input.boolean?
-        @brk = input.boolean?
-        @pending_write = input.boolean?
-        @so_high = input.boolean?
-        @optional_dummy = input.boolean?
-        @branch_taken = input.boolean?
-      end
-
-      def load_working_registers(input)
-        @address = input.optional_int
-        @dummy_address = input.optional_int
-        @value = input.optional_int
-        @rmw_result = input.optional_int
-        @pointer = input.optional_int
-      end
-    end
-  end
-end

data/lib/badline/cpu/stack_operations.rb

@@ -1,82 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  class CPU
-    # Steps that use the stack: PHA, PHP, PLA, PLP, JSR, RTS and RTI.
-    module StackOperations
-      private
-
-      def op_push_exec
-        send(@operation, nil, nil)
-        end_instruction
-      end
-
-      def op_pull_dummy
-        @memory.peek(stack_address)
-      end
-
-      def op_pull_exec
-        send(@operation, nil, nil)
-        end_instruction
-      end
-
-      def op_pull_low
-        @stack_pointer = (@stack_pointer + 1) & 0xff
-        @address = @memory.peek(stack_address)
-      end
-
-      def op_pull_high
-        @stack_pointer = (@stack_pointer + 1) & 0xff
-        @address |= @memory.peek(stack_address) << 8
-      end
-
-      def op_rts_fixup
-        @memory.peek(@address)
-        @program_counter = (@address + 1) & 0xffff
-        end_instruction
-      end
-
-      def op_rti_pull_status
-        @stack_pointer = (@stack_pointer + 1) & 0xff
-        @status.value = @memory.peek(stack_address)
-        @status.break = false
-      end
-
-      def op_rti_pull_high
-        @stack_pointer = (@stack_pointer + 1) & 0xff
-        @program_counter = @address | (@memory.peek(stack_address) << 8)
-        end_instruction
-      end
-
-      def op_jsr_low
-        @address = @memory.peek(@program_counter)
-        @program_counter = (@program_counter + 2) & 0xffff
-      end
-
-      def op_jsr_dummy
-        @memory.peek(stack_address)
-      end
-
-      def op_jsr_push_high
-        @memory.poke(stack_address, high_byte(return_address))
-      end
-
-      def op_jsr_push_low
-        @memory.poke(stack_address(-1), low_byte(return_address))
-        @stack_pointer = (@stack_pointer - 2) & 0xff
-      end
-
-      # JSR reads its target's high byte after pushing the return address.
-      # A JSR running from the stack page can overwrite its own operand
-      # with that push, and then jumps to the overwritten address.
-      def op_jsr_high
-        @program_counter = @address | (@memory.peek(return_address) << 8)
-        end_instruction
-      end
-
-      def return_address
-        (@program_counter - 1) & 0xffff
-      end
-    end
-  end
-end

data/lib/badline/cpu.rb

@@ -1,10 +0,0 @@
-# frozen_string_literal: true
-
-require "badline/cpu/core"
-
-module Badline
-  # The C64's 6510, on the AddressBus.
-  class CPU
-    include Core
-  end
-end

data/lib/badline/cycleable.rb

@@ -1,38 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  class Cycleable
-    attr_reader :cycles
-
-    def initialize
-      @loop = Fiber.new { loop { main_loop } }
-      @cycles = 0
-      @pending_write = false
-    end
-
-    def cycle!
-      @loop.resume
-      nil
-    end
-
-    def pending_write? = @pending_write
-
-    private
-
-    def cycle(write: false)
-      @pending_write = write
-      Fiber.yield
-      poll
-      result = yield if block_given?
-      @cycles += 1
-      @pending_write = false
-      result
-    end
-
-    def poll; end
-
-    def main_loop
-      Fiber.yield
-    end
-  end
-end