badline 0.12.0 → 0.13.0

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (516) hide show
  1. checksums.yaml +4 -4
  2. data/CHANGELOG.md +25 -0
  3. data/CLAUDE.md +59 -31
  4. data/README.md +1 -1
  5. data/doc/library.md +9 -9
  6. data/doc/pinned-behaviour.md +105 -105
  7. data/doc/snapshots.md +1 -4
  8. data/lib/badline/audio/bare_player.rb +4 -4
  9. data/lib/badline/audio/cli.rb +6 -6
  10. data/lib/badline/audio/jukebox.rb +2 -2
  11. data/lib/badline/audio/machine_player.rb +2 -2
  12. data/lib/badline/{media → audio}/queue.rb +1 -1
  13. data/lib/badline/audio/queued_tune.rb +6 -6
  14. data/lib/badline/audio/renderer.rb +5 -5
  15. data/lib/badline/audio/stereo.rb +1 -1
  16. data/lib/badline/c128/{bus_state.rb → bus/saved_state.rb} +6 -6
  17. data/lib/badline/c128/bus.rb +30 -51
  18. data/lib/badline/c128/color_lines.rb +2 -2
  19. data/lib/badline/c128/cpu.rb +1 -1
  20. data/lib/badline/c128/drives.rb +10 -11
  21. data/lib/badline/c128/fast_serial.rb +5 -5
  22. data/lib/badline/c128/mmu_pages.rb +1 -1
  23. data/lib/badline/c128/modes.rb +2 -2
  24. data/lib/badline/c128/saved_state.rb +21 -47
  25. data/lib/badline/c128/z80.rb +2 -2
  26. data/lib/badline/c128.rb +18 -72
  27. data/lib/badline/{computer → c64}/attachments.rb +16 -47
  28. data/lib/badline/c64/banked_ram/banking.rb +32 -0
  29. data/lib/badline/c64/banked_ram/plus256k.rb +56 -0
  30. data/lib/badline/c64/banked_ram/plus60k.rb +45 -0
  31. data/lib/badline/c64/banked_ram/unexpanded.rb +30 -0
  32. data/lib/badline/c64/banked_ram.rb +23 -0
  33. data/lib/badline/c64/bus/extra_sids.rb +32 -0
  34. data/lib/badline/c64/bus/fittings.rb +40 -0
  35. data/lib/badline/c64/bus/pla.rb +149 -0
  36. data/lib/badline/c64/bus/roms.rb +41 -0
  37. data/lib/badline/c64/bus/saved_state.rb +68 -0
  38. data/lib/badline/c64/bus/sid_slots.rb +44 -0
  39. data/lib/badline/c64/bus.rb +218 -0
  40. data/lib/badline/c64/cartridge/action_replay.rb +128 -0
  41. data/lib/badline/c64/cartridge/atomic_power.rb +26 -0
  42. data/lib/badline/c64/cartridge/bank.rb +83 -0
  43. data/lib/badline/c64/cartridge/comal80.rb +52 -0
  44. data/lib/badline/c64/cartridge/dinamic.rb +36 -0
  45. data/lib/badline/c64/cartridge/easy_flash.rb +147 -0
  46. data/lib/badline/c64/cartridge/epyx_fastload.rb +81 -0
  47. data/lib/badline/c64/cartridge/final_cartridge3.rb +91 -0
  48. data/lib/badline/c64/cartridge/flash/saved_state.rb +40 -0
  49. data/lib/badline/c64/cartridge/flash.rb +279 -0
  50. data/lib/badline/c64/cartridge/freezer.rb +35 -0
  51. data/lib/badline/c64/cartridge/fun_play.rb +40 -0
  52. data/lib/badline/c64/cartridge/g_mod2.rb +76 -0
  53. data/lib/badline/c64/cartridge/game_system.rb +42 -0
  54. data/lib/badline/c64/cartridge/geo_ram.rb +81 -0
  55. data/lib/badline/c64/cartridge/kcs_power.rb +77 -0
  56. data/lib/badline/c64/cartridge/mach5.rb +34 -0
  57. data/lib/badline/c64/cartridge/magic_desk.rb +32 -0
  58. data/lib/badline/c64/cartridge/ocean.rb +37 -0
  59. data/lib/badline/c64/cartridge/pagefox.rb +70 -0
  60. data/lib/badline/c64/cartridge/retro_replay/saved_state.rb +47 -0
  61. data/lib/badline/c64/cartridge/retro_replay.rb +286 -0
  62. data/lib/badline/c64/cartridge/rex_utility.rb +31 -0
  63. data/lib/badline/c64/cartridge/rgcd.rb +60 -0
  64. data/lib/badline/c64/cartridge/saved_state.rb +63 -0
  65. data/lib/badline/c64/cartridge/simons_basic.rb +37 -0
  66. data/lib/badline/c64/cartridge/standard.rb +17 -0
  67. data/lib/badline/c64/cartridge/super_games.rb +50 -0
  68. data/lib/badline/c64/cartridge/westermann.rb +32 -0
  69. data/lib/badline/c64/cartridge/zaxxon.rb +68 -0
  70. data/lib/badline/c64/cartridge.rb +258 -0
  71. data/lib/badline/c64/color_memory.rb +27 -0
  72. data/lib/badline/c64/common.rb +34 -0
  73. data/lib/badline/c64/kernal_traps.rb +89 -0
  74. data/lib/badline/c64/reu/dma/saved_state.rb +52 -0
  75. data/lib/badline/c64/reu/dma.rb +275 -0
  76. data/lib/badline/c64/reu/ram.rb +109 -0
  77. data/lib/badline/c64/reu/saved_state.rb +55 -0
  78. data/lib/badline/c64/reu/trigger.rb +34 -0
  79. data/lib/badline/c64/reu.rb +291 -0
  80. data/lib/badline/{computer → c64}/saved_state.rb +13 -18
  81. data/lib/badline/{computer → c64}/true_drives.rb +20 -31
  82. data/lib/badline/{computer.rb → c64.rb} +22 -80
  83. data/lib/badline/chips/cia/fast_forward.rb +62 -0
  84. data/lib/badline/chips/cia/interrupt_register.rb +145 -0
  85. data/lib/badline/chips/cia/saved_state.rb +49 -0
  86. data/lib/badline/chips/cia/serial/saved_state.rb +45 -0
  87. data/lib/badline/chips/cia/serial.rb +250 -0
  88. data/lib/badline/chips/cia/time_of_day.rb +232 -0
  89. data/lib/badline/chips/cia/timer.rb +208 -0
  90. data/lib/badline/chips/cia.rb +281 -0
  91. data/lib/badline/chips/cpu/addressing.rb +133 -0
  92. data/lib/badline/chips/cpu/boundary.rb +56 -0
  93. data/lib/badline/chips/cpu/core.rb +167 -0
  94. data/lib/badline/chips/cpu/instruction.rb +338 -0
  95. data/lib/badline/chips/cpu/instruction_set/arithmetic.rb +118 -0
  96. data/lib/badline/chips/cpu/instruction_set/bitwise.rb +130 -0
  97. data/lib/badline/chips/cpu/instruction_set/branch.rb +83 -0
  98. data/lib/badline/chips/cpu/instruction_set/flag.rb +67 -0
  99. data/lib/badline/chips/cpu/instruction_set/illegal.rb +274 -0
  100. data/lib/badline/chips/cpu/instruction_set/inc_dec.rb +73 -0
  101. data/lib/badline/chips/cpu/instruction_set/stack.rb +56 -0
  102. data/lib/badline/chips/cpu/instruction_set/transfer.rb +141 -0
  103. data/lib/badline/chips/cpu/instruction_set.rb +59 -0
  104. data/lib/badline/chips/cpu/interrupts.rb +108 -0
  105. data/lib/badline/chips/cpu/microcode.rb +179 -0
  106. data/lib/badline/chips/cpu/operations.rb +90 -0
  107. data/lib/badline/chips/cpu/port.rb +116 -0
  108. data/lib/badline/chips/cpu/saved_state.rb +117 -0
  109. data/lib/badline/chips/cpu/stack_operations.rb +84 -0
  110. data/lib/badline/chips/cpu/traps.rb +23 -0
  111. data/lib/badline/chips/cpu.rb +12 -0
  112. data/lib/badline/chips/sid/catch_up.rb +122 -0
  113. data/lib/badline/chips/sid/decimator.rb +66 -0
  114. data/lib/badline/chips/sid/envelope/saved_state.rb +70 -0
  115. data/lib/badline/chips/sid/envelope.rb +241 -0
  116. data/lib/badline/chips/sid/filter/saved_state.rb +42 -0
  117. data/lib/badline/chips/sid/filter.rb +241 -0
  118. data/lib/badline/chips/sid/saved_state.rb +52 -0
  119. data/lib/badline/chips/sid/voice.rb +79 -0
  120. data/lib/badline/chips/sid/waveform/combined.rb +128 -0
  121. data/lib/badline/chips/sid/waveform/fast_forward.rb +107 -0
  122. data/lib/badline/chips/sid/waveform/noise_writeback.rb +124 -0
  123. data/lib/badline/chips/sid/waveform/saved_state.rb +68 -0
  124. data/lib/badline/chips/sid/waveform.rb +307 -0
  125. data/lib/badline/chips/sid.rb +265 -0
  126. data/lib/badline/{c128 → chips}/vdc/memory.rb +1 -1
  127. data/lib/badline/{c128 → chips}/vdc/painter.rb +1 -1
  128. data/lib/badline/{c128 → chips}/vdc/raster.rb +1 -1
  129. data/lib/badline/chips/vdc/saved_state.rb +36 -0
  130. data/lib/badline/{c128 → chips}/vdc/window.rb +1 -1
  131. data/lib/badline/{c128 → chips}/vdc.rb +7 -31
  132. data/lib/badline/chips/via/control_lines.rb +124 -0
  133. data/lib/badline/chips/via/fast_forward.rb +55 -0
  134. data/lib/badline/chips/via/interrupt_register.rb +69 -0
  135. data/lib/badline/chips/via/saved_state.rb +44 -0
  136. data/lib/badline/chips/via/shift_register.rb +182 -0
  137. data/lib/badline/chips/via/timer1.rb +133 -0
  138. data/lib/badline/chips/via/timer2.rb +135 -0
  139. data/lib/badline/chips/via.rb +268 -0
  140. data/lib/badline/chips/vic/bank.rb +135 -0
  141. data/lib/badline/chips/vic/border_mask.rb +88 -0
  142. data/lib/badline/chips/vic/collisions.rb +117 -0
  143. data/lib/badline/chips/vic/color_patches.rb +49 -0
  144. data/lib/badline/chips/vic/display_state.rb +187 -0
  145. data/lib/badline/chips/vic/graphics_mode.rb +166 -0
  146. data/lib/badline/chips/vic/graphics_shifter/saved_state.rb +40 -0
  147. data/lib/badline/chips/vic/graphics_shifter.rb +187 -0
  148. data/lib/badline/chips/vic/register_log.rb +83 -0
  149. data/lib/badline/chips/vic/registers.rb +197 -0
  150. data/lib/badline/chips/vic/saved_state.rb +82 -0
  151. data/lib/badline/chips/vic/sequencer/saved_state.rb +91 -0
  152. data/lib/badline/chips/vic/sequencer.rb +277 -0
  153. data/lib/badline/chips/vic/sequencer_output.rb +118 -0
  154. data/lib/badline/chips/vic/sprite/internal_bus.rb +70 -0
  155. data/lib/badline/chips/vic/sprite/saved_state.rb +66 -0
  156. data/lib/badline/chips/vic/sprite/shifter.rb +148 -0
  157. data/lib/badline/chips/vic/sprite/timing.rb +58 -0
  158. data/lib/badline/chips/vic/sprite.rb +339 -0
  159. data/lib/badline/chips/vic/sprites/saved_state.rb +59 -0
  160. data/lib/badline/chips/vic/sprites.rb +284 -0
  161. data/lib/badline/chips/vic.rb +783 -0
  162. data/lib/badline/chips/vic_i/painter/saved_state.rb +40 -0
  163. data/lib/badline/{vic20/vic → chips/vic_i}/painter.rb +6 -30
  164. data/lib/badline/{vic20/vic → chips/vic_i}/saved_state.rb +2 -2
  165. data/lib/badline/chips/vic_i/sound/output.rb +85 -0
  166. data/lib/badline/chips/vic_i/sound.rb +235 -0
  167. data/lib/badline/{vic20/vic → chips/vic_i}/text_window.rb +2 -2
  168. data/lib/badline/{vic20/vic.rb → chips/vic_i.rb} +5 -5
  169. data/lib/badline/chips/z80/arithmetic.rb +119 -0
  170. data/lib/badline/chips/z80/bit_page.rb +57 -0
  171. data/lib/badline/chips/z80/block_io.rb +60 -0
  172. data/lib/badline/chips/z80/block_transfers.rb +61 -0
  173. data/lib/badline/chips/z80/bus_cycles.rb +113 -0
  174. data/lib/badline/chips/z80/core.rb +115 -0
  175. data/lib/badline/chips/z80/exchanges.rb +52 -0
  176. data/lib/badline/chips/z80/extended_page.rb +91 -0
  177. data/lib/badline/chips/z80/flags.rb +39 -0
  178. data/lib/badline/chips/z80/interrupt_acceptance.rb +48 -0
  179. data/lib/badline/chips/z80/jumps.rb +84 -0
  180. data/lib/badline/chips/z80/loads.rb +100 -0
  181. data/lib/badline/chips/z80/main_page.rb +136 -0
  182. data/lib/badline/chips/z80/registers.rb +122 -0
  183. data/lib/badline/chips/z80/saved_state.rb +71 -0
  184. data/lib/badline/chips/z80/shifts.rb +66 -0
  185. data/lib/badline/chips/z80.rb +13 -0
  186. data/lib/badline/core.rb +27 -29
  187. data/lib/badline/drives/datasette/saved_state.rb +37 -0
  188. data/lib/badline/drives/datasette.rb +140 -0
  189. data/lib/badline/drives/engine/core.rb +149 -0
  190. data/lib/badline/drives/engine/fast_serial.rb +75 -0
  191. data/lib/badline/drives/engine/idle.rb +127 -0
  192. data/lib/badline/drives/engine/idle_cpu.rb +30 -0
  193. data/lib/badline/drives/engine/orbit.rb +81 -0
  194. data/lib/badline/drives/engine/serial_lines.rb +75 -0
  195. data/lib/badline/drives/engine/sleep.rb +114 -0
  196. data/lib/badline/drives/engine/vias.rb +86 -0
  197. data/lib/badline/drives/engine/watch.rb +152 -0
  198. data/lib/badline/drives/engine.rb +11 -0
  199. data/lib/badline/drives/model1541/bus.rb +88 -0
  200. data/lib/badline/drives/model1541/byte_ready.rb +50 -0
  201. data/lib/badline/drives/model1541/cpu.rb +13 -0
  202. data/lib/badline/drives/model1541/disk/saved_state.rb +88 -0
  203. data/lib/badline/drives/model1541/disk.rb +317 -0
  204. data/lib/badline/drives/model1541/disk_via.rb +38 -0
  205. data/lib/badline/drives/model1541/gcr.rb +59 -0
  206. data/lib/badline/drives/model1541/mechanism/saved_state.rb +72 -0
  207. data/lib/badline/drives/model1541/mechanism.rb +315 -0
  208. data/lib/badline/drives/model1541/rotation.rb +123 -0
  209. data/lib/badline/drives/model1541/saved_state.rb +44 -0
  210. data/lib/badline/drives/model1541/sector_reader.rb +78 -0
  211. data/lib/badline/drives/model1541/serial_port.rb +20 -0
  212. data/lib/badline/drives/model1541/track.rb +100 -0
  213. data/lib/badline/drives/model1541.rb +81 -0
  214. data/lib/badline/drives/model1571/bus.rb +113 -0
  215. data/lib/badline/drives/model1571/cpu.rb +13 -0
  216. data/lib/badline/drives/model1571/saved_state.rb +47 -0
  217. data/lib/badline/drives/model1571/serial_port.rb +39 -0
  218. data/lib/badline/drives/model1571/serial_via.rb +27 -0
  219. data/lib/badline/drives/model1571/wd1770.rb +122 -0
  220. data/lib/badline/drives/model1571.rb +142 -0
  221. data/lib/badline/drives/model1581/bus.rb +139 -0
  222. data/lib/badline/drives/model1581/cpu.rb +13 -0
  223. data/lib/badline/drives/model1581/disk/saved_state.rb +89 -0
  224. data/lib/badline/drives/model1581/disk.rb +137 -0
  225. data/lib/badline/drives/model1581/mechanism.rb +119 -0
  226. data/lib/badline/drives/model1581/saved_state.rb +42 -0
  227. data/lib/badline/drives/model1581/serial_port.rb +54 -0
  228. data/lib/badline/drives/model1581/slot.rb +79 -0
  229. data/lib/badline/drives/model1581/track.rb +102 -0
  230. data/lib/badline/drives/model1581/track_bytes.rb +77 -0
  231. data/lib/badline/drives/model1581/wd1772/registers.rb +91 -0
  232. data/lib/badline/drives/model1581/wd1772/saved_state.rb +68 -0
  233. data/lib/badline/drives/model1581/wd1772/sector_writes.rb +75 -0
  234. data/lib/badline/drives/model1581/wd1772/sectors.rb +152 -0
  235. data/lib/badline/drives/model1581/wd1772/stepping.rb +111 -0
  236. data/lib/badline/drives/model1581/wd1772/tracks.rb +127 -0
  237. data/lib/badline/drives/model1581/wd1772/turn.rb +75 -0
  238. data/lib/badline/drives/model1581/wd1772.rb +218 -0
  239. data/lib/badline/drives/model1581.rb +206 -0
  240. data/lib/badline/drives/serial_bus.rb +161 -0
  241. data/lib/badline/frontend/boot.rb +10 -61
  242. data/lib/badline/frontend/machine_window.rb +3 -1
  243. data/lib/badline/frontend/player/filter_view.rb +1 -1
  244. data/lib/badline/frontend/player/player_controller.rb +2 -2
  245. data/lib/badline/frontend/player/player_screen.rb +1 -0
  246. data/lib/badline/frontend/player/theme.rb +7 -7
  247. data/lib/badline/frontend/timeline.rb +3 -3
  248. data/lib/badline/input/control_ports.rb +78 -0
  249. data/lib/badline/input/joystick.rb +27 -0
  250. data/lib/badline/input/keyboard.rb +114 -0
  251. data/lib/badline/input.rb +3 -0
  252. data/lib/badline/kernal_trap/{drive → dos}/block_commands.rb +1 -1
  253. data/lib/badline/kernal_trap/dos/channel.rb +183 -0
  254. data/lib/badline/kernal_trap/{drive → dos}/channels.rb +1 -1
  255. data/lib/badline/kernal_trap/{drive → dos}/memory.rb +1 -1
  256. data/lib/badline/kernal_trap/{drive → dos}/parameters.rb +1 -1
  257. data/lib/badline/kernal_trap/{drive → dos}/status.rb +1 -1
  258. data/lib/badline/kernal_trap/{drive → dos}/write_file.rb +1 -1
  259. data/lib/badline/kernal_trap/{drive → dos}/writes.rb +1 -1
  260. data/lib/badline/kernal_trap/{drive.rb → dos.rb} +11 -10
  261. data/lib/badline/kernal_trap/{file.rb → file_routine.rb} +1 -1
  262. data/lib/badline/kernal_trap/load.rb +6 -6
  263. data/lib/badline/kernal_trap/save.rb +5 -5
  264. data/lib/badline/kernal_trap/serial.rb +7 -7
  265. data/lib/badline/kernal_trap.rb +2 -3
  266. data/lib/badline/machine/clocking.rb +50 -0
  267. data/lib/badline/machine.rb +63 -7
  268. data/lib/badline/media/boot_disk.rb +2 -2
  269. data/lib/badline/media/disk_list.rb +3 -3
  270. data/lib/badline/media/disk_set.rb +1 -1
  271. data/lib/badline/media/extensions.rb +33 -0
  272. data/lib/badline/media/program.rb +28 -0
  273. data/lib/badline/media/true_drive.rb +4 -3
  274. data/lib/badline/media/tune.rb +35 -0
  275. data/lib/badline/media/vic20_cartridge.rb +1 -7
  276. data/lib/badline/media/vic20_media.rb +38 -80
  277. data/lib/badline/media.rb +84 -81
  278. data/lib/badline/model.rb +1 -1
  279. data/lib/badline/options/event.rb +3 -1
  280. data/lib/badline/roms/README +6 -6
  281. data/lib/badline/sdl.rb +1 -0
  282. data/lib/badline/{storage/sid_file.rb → sid_tune/file.rb} +3 -3
  283. data/lib/badline/{storage → sid_tune}/hvsc.rb +7 -7
  284. data/lib/badline/{storage → sid_tune}/song_lengths.rb +2 -2
  285. data/lib/badline/{storage → sid_tune}/stil/credit.rb +1 -1
  286. data/lib/badline/{storage → sid_tune}/stil.rb +3 -3
  287. data/lib/badline/sid_tune.rb +6 -0
  288. data/lib/badline/snapshot/c128_setup.rb +43 -0
  289. data/lib/badline/snapshot/c64_setup.rb +79 -0
  290. data/lib/badline/snapshot/image.rb +5 -25
  291. data/lib/badline/snapshot/machine_state.rb +10 -2
  292. data/lib/badline/snapshot/setup.rb +22 -66
  293. data/lib/badline/snapshot/state.rb +8 -17
  294. data/lib/badline/snapshot/storage_setup.rb +68 -0
  295. data/lib/badline/snapshot/vic20_setup.rb +37 -0
  296. data/lib/badline/snapshot/vice/c64_mem.rb +1 -1
  297. data/lib/badline/snapshot/vice/restore.rb +1 -1
  298. data/lib/badline/snapshot/vice/reu1764.rb +1 -1
  299. data/lib/badline/snapshot/vice/reu_fields.rb +40 -0
  300. data/lib/badline/snapshot/vice.rb +7 -5
  301. data/lib/badline/snapshot.rb +13 -12
  302. data/lib/badline/storage/d64_image.rb +15 -9
  303. data/lib/badline/storage/d71_image.rb +0 -2
  304. data/lib/badline/storage/d81_image.rb +0 -2
  305. data/lib/badline/storage/disk_image/writing.rb +2 -2
  306. data/lib/badline/storage/disk_image.rb +3 -6
  307. data/lib/badline/storage/g64_image.rb +2 -2
  308. data/lib/badline/storage/host_directory.rb +0 -5
  309. data/lib/badline/storage/t64.rb +2 -8
  310. data/lib/badline/storage/unavailable.rb +1 -1
  311. data/lib/badline/storage.rb +0 -37
  312. data/lib/badline/support/c128_checkpoint.rb +39 -0
  313. data/lib/badline/support/checkpoint.rb +108 -0
  314. data/lib/badline/support/vic20_checkpoint.rb +38 -0
  315. data/lib/badline/support.rb +5 -0
  316. data/lib/badline/version.rb +1 -1
  317. data/lib/badline/vic20/attachments.rb +11 -81
  318. data/lib/badline/vic20/bus/saved_state.rb +35 -0
  319. data/lib/badline/vic20/bus.rb +3 -25
  320. data/lib/badline/vic20/cpu.rb +1 -1
  321. data/lib/badline/vic20/port_wiring.rb +4 -4
  322. data/lib/badline/vic20/saved_state.rb +16 -60
  323. data/lib/badline/vic20/user_via_ports.rb +2 -2
  324. data/lib/badline/vic20.rb +20 -51
  325. metadata +250 -221
  326. data/lib/badline/address_bus/extra_sids.rb +0 -30
  327. data/lib/badline/address_bus/fittings.rb +0 -38
  328. data/lib/badline/address_bus/pla.rb +0 -147
  329. data/lib/badline/address_bus/roms.rb +0 -39
  330. data/lib/badline/address_bus/saved_state.rb +0 -72
  331. data/lib/badline/address_bus/sid_slots.rb +0 -42
  332. data/lib/badline/address_bus.rb +0 -235
  333. data/lib/badline/cartridge/action_replay.rb +0 -126
  334. data/lib/badline/cartridge/atomic_power.rb +0 -24
  335. data/lib/badline/cartridge/bank.rb +0 -81
  336. data/lib/badline/cartridge/comal80.rb +0 -50
  337. data/lib/badline/cartridge/dinamic.rb +0 -34
  338. data/lib/badline/cartridge/easy_flash.rb +0 -145
  339. data/lib/badline/cartridge/epyx_fastload.rb +0 -79
  340. data/lib/badline/cartridge/final_cartridge3.rb +0 -89
  341. data/lib/badline/cartridge/flash.rb +0 -306
  342. data/lib/badline/cartridge/freezer.rb +0 -33
  343. data/lib/badline/cartridge/fun_play.rb +0 -38
  344. data/lib/badline/cartridge/g_mod2.rb +0 -74
  345. data/lib/badline/cartridge/game_system.rb +0 -40
  346. data/lib/badline/cartridge/geo_ram.rb +0 -79
  347. data/lib/badline/cartridge/kcs_power.rb +0 -75
  348. data/lib/badline/cartridge/mach5.rb +0 -32
  349. data/lib/badline/cartridge/magic_desk.rb +0 -30
  350. data/lib/badline/cartridge/ocean.rb +0 -35
  351. data/lib/badline/cartridge/pagefox.rb +0 -68
  352. data/lib/badline/cartridge/retro_replay.rb +0 -320
  353. data/lib/badline/cartridge/rex_utility.rb +0 -29
  354. data/lib/badline/cartridge/rgcd.rb +0 -58
  355. data/lib/badline/cartridge/simons_basic.rb +0 -35
  356. data/lib/badline/cartridge/standard.rb +0 -15
  357. data/lib/badline/cartridge/super_games.rb +0 -48
  358. data/lib/badline/cartridge/westermann.rb +0 -30
  359. data/lib/badline/cartridge/zaxxon.rb +0 -66
  360. data/lib/badline/cartridge.rb +0 -303
  361. data/lib/badline/checkpoint.rb +0 -98
  362. data/lib/badline/cia/fast_forward.rb +0 -60
  363. data/lib/badline/cia/interrupt_register.rb +0 -143
  364. data/lib/badline/cia/serial.rb +0 -275
  365. data/lib/badline/cia/state.rb +0 -47
  366. data/lib/badline/cia/timer.rb +0 -206
  367. data/lib/badline/cia.rb +0 -279
  368. data/lib/badline/color_memory.rb +0 -25
  369. data/lib/badline/computer/kernal_traps.rb +0 -29
  370. data/lib/badline/control_ports.rb +0 -76
  371. data/lib/badline/cpu/addressing.rb +0 -131
  372. data/lib/badline/cpu/boundary.rb +0 -54
  373. data/lib/badline/cpu/core.rb +0 -165
  374. data/lib/badline/cpu/microcode.rb +0 -177
  375. data/lib/badline/cpu/operations.rb +0 -88
  376. data/lib/badline/cpu/saved_state.rb +0 -115
  377. data/lib/badline/cpu/stack_operations.rb +0 -82
  378. data/lib/badline/cpu.rb +0 -10
  379. data/lib/badline/cycleable.rb +0 -38
  380. data/lib/badline/datasette.rb +0 -161
  381. data/lib/badline/drive/core.rb +0 -147
  382. data/lib/badline/drive/fast_serial.rb +0 -73
  383. data/lib/badline/drive/idle.rb +0 -125
  384. data/lib/badline/drive/idle_cpu.rb +0 -28
  385. data/lib/badline/drive/orbit.rb +0 -79
  386. data/lib/badline/drive/serial_lines.rb +0 -73
  387. data/lib/badline/drive/sleep.rb +0 -112
  388. data/lib/badline/drive/vias.rb +0 -84
  389. data/lib/badline/drive/watch.rb +0 -150
  390. data/lib/badline/drive.rb +0 -11
  391. data/lib/badline/drive1541/bus.rb +0 -86
  392. data/lib/badline/drive1541/byte_ready.rb +0 -48
  393. data/lib/badline/drive1541/cpu.rb +0 -11
  394. data/lib/badline/drive1541/disk.rb +0 -318
  395. data/lib/badline/drive1541/disk_state.rb +0 -94
  396. data/lib/badline/drive1541/disk_via.rb +0 -36
  397. data/lib/badline/drive1541/gcr.rb +0 -57
  398. data/lib/badline/drive1541/mechanism.rb +0 -313
  399. data/lib/badline/drive1541/mechanism_state.rb +0 -68
  400. data/lib/badline/drive1541/rotation.rb +0 -121
  401. data/lib/badline/drive1541/sector_reader.rb +0 -76
  402. data/lib/badline/drive1541/serial_port.rb +0 -18
  403. data/lib/badline/drive1541/track.rb +0 -98
  404. data/lib/badline/drive1541.rb +0 -111
  405. data/lib/badline/drive1571/bus.rb +0 -111
  406. data/lib/badline/drive1571/cpu.rb +0 -11
  407. data/lib/badline/drive1571/serial_port.rb +0 -37
  408. data/lib/badline/drive1571/serial_via.rb +0 -25
  409. data/lib/badline/drive1571/wd1770.rb +0 -120
  410. data/lib/badline/drive1571.rb +0 -175
  411. data/lib/badline/drive1581/bus.rb +0 -137
  412. data/lib/badline/drive1581/cpu.rb +0 -11
  413. data/lib/badline/drive1581/disk.rb +0 -135
  414. data/lib/badline/drive1581/disk_state.rb +0 -87
  415. data/lib/badline/drive1581/mechanism.rb +0 -117
  416. data/lib/badline/drive1581/serial_port.rb +0 -52
  417. data/lib/badline/drive1581/slot.rb +0 -78
  418. data/lib/badline/drive1581/track.rb +0 -100
  419. data/lib/badline/drive1581/track_bytes.rb +0 -75
  420. data/lib/badline/drive1581/wd1772/registers.rb +0 -89
  421. data/lib/badline/drive1581/wd1772/sector_writes.rb +0 -73
  422. data/lib/badline/drive1581/wd1772/sectors.rb +0 -150
  423. data/lib/badline/drive1581/wd1772/state.rb +0 -66
  424. data/lib/badline/drive1581/wd1772/stepping.rb +0 -109
  425. data/lib/badline/drive1581/wd1772/tracks.rb +0 -125
  426. data/lib/badline/drive1581/wd1772/turn.rb +0 -73
  427. data/lib/badline/drive1581/wd1772.rb +0 -216
  428. data/lib/badline/drive1581.rb +0 -233
  429. data/lib/badline/iec_bus.rb +0 -159
  430. data/lib/badline/instruction.rb +0 -334
  431. data/lib/badline/instruction_set/arithmetic.rb +0 -114
  432. data/lib/badline/instruction_set/bitwise.rb +0 -126
  433. data/lib/badline/instruction_set/branch.rb +0 -79
  434. data/lib/badline/instruction_set/flag.rb +0 -63
  435. data/lib/badline/instruction_set/illegal.rb +0 -270
  436. data/lib/badline/instruction_set/inc_dec.rb +0 -69
  437. data/lib/badline/instruction_set/stack.rb +0 -52
  438. data/lib/badline/instruction_set/transfer.rb +0 -137
  439. data/lib/badline/instruction_set.rb +0 -55
  440. data/lib/badline/interrupts.rb +0 -104
  441. data/lib/badline/joystick.rb +0 -25
  442. data/lib/badline/kernal_trap/channel.rb +0 -181
  443. data/lib/badline/keyboard.rb +0 -112
  444. data/lib/badline/ram_expansion/banking.rb +0 -30
  445. data/lib/badline/ram_expansion/plus256k.rb +0 -54
  446. data/lib/badline/ram_expansion/plus60k.rb +0 -43
  447. data/lib/badline/ram_expansion/unexpanded.rb +0 -28
  448. data/lib/badline/ram_expansion.rb +0 -21
  449. data/lib/badline/reu/dma/saved_state.rb +0 -50
  450. data/lib/badline/reu/dma.rb +0 -273
  451. data/lib/badline/reu/ram.rb +0 -107
  452. data/lib/badline/reu/saved_state.rb +0 -80
  453. data/lib/badline/reu/trigger.rb +0 -32
  454. data/lib/badline/reu.rb +0 -289
  455. data/lib/badline/sid/catch_up.rb +0 -120
  456. data/lib/badline/sid/decimator.rb +0 -64
  457. data/lib/badline/sid/envelope/state.rb +0 -68
  458. data/lib/badline/sid/envelope.rb +0 -239
  459. data/lib/badline/sid/filter.rb +0 -263
  460. data/lib/badline/sid/voice.rb +0 -77
  461. data/lib/badline/sid/waveform/combined.rb +0 -126
  462. data/lib/badline/sid/waveform/fast_forward.rb +0 -105
  463. data/lib/badline/sid/waveform/noise_writeback.rb +0 -122
  464. data/lib/badline/sid/waveform/state.rb +0 -66
  465. data/lib/badline/sid/waveform.rb +0 -305
  466. data/lib/badline/sid.rb +0 -303
  467. data/lib/badline/time_of_day.rb +0 -228
  468. data/lib/badline/traps.rb +0 -19
  469. data/lib/badline/via/control_lines.rb +0 -122
  470. data/lib/badline/via/fast_forward.rb +0 -53
  471. data/lib/badline/via/interrupt_register.rb +0 -67
  472. data/lib/badline/via/shift_register.rb +0 -180
  473. data/lib/badline/via/state.rb +0 -42
  474. data/lib/badline/via/timer1.rb +0 -131
  475. data/lib/badline/via/timer2.rb +0 -133
  476. data/lib/badline/via.rb +0 -266
  477. data/lib/badline/vic/bank.rb +0 -133
  478. data/lib/badline/vic/border_mask.rb +0 -86
  479. data/lib/badline/vic/collisions.rb +0 -115
  480. data/lib/badline/vic/color_patches.rb +0 -47
  481. data/lib/badline/vic/display_state.rb +0 -185
  482. data/lib/badline/vic/graphics_mode.rb +0 -164
  483. data/lib/badline/vic/graphics_shifter.rb +0 -207
  484. data/lib/badline/vic/register_log.rb +0 -81
  485. data/lib/badline/vic/registers.rb +0 -195
  486. data/lib/badline/vic/sequencer.rb +0 -275
  487. data/lib/badline/vic/sequencer_output.rb +0 -116
  488. data/lib/badline/vic/sequencer_state.rb +0 -89
  489. data/lib/badline/vic/sprite/internal_bus.rb +0 -68
  490. data/lib/badline/vic/sprite/saved_state.rb +0 -64
  491. data/lib/badline/vic/sprite/shifter.rb +0 -146
  492. data/lib/badline/vic/sprite/timing.rb +0 -56
  493. data/lib/badline/vic/sprite.rb +0 -337
  494. data/lib/badline/vic/sprites.rb +0 -282
  495. data/lib/badline/vic/sprites_state.rb +0 -57
  496. data/lib/badline/vic.rb +0 -852
  497. data/lib/badline/vic20/sound/output.rb +0 -83
  498. data/lib/badline/vic20/sound.rb +0 -233
  499. data/lib/badline/z80/arithmetic.rb +0 -117
  500. data/lib/badline/z80/bit_page.rb +0 -55
  501. data/lib/badline/z80/block_io.rb +0 -58
  502. data/lib/badline/z80/block_transfers.rb +0 -59
  503. data/lib/badline/z80/bus_cycles.rb +0 -111
  504. data/lib/badline/z80/core.rb +0 -113
  505. data/lib/badline/z80/exchanges.rb +0 -50
  506. data/lib/badline/z80/extended_page.rb +0 -89
  507. data/lib/badline/z80/flags.rb +0 -37
  508. data/lib/badline/z80/interrupt_acceptance.rb +0 -46
  509. data/lib/badline/z80/jumps.rb +0 -82
  510. data/lib/badline/z80/loads.rb +0 -98
  511. data/lib/badline/z80/main_page.rb +0 -134
  512. data/lib/badline/z80/registers.rb +0 -120
  513. data/lib/badline/z80/saved_state.rb +0 -69
  514. data/lib/badline/z80/shifts.rb +0 -64
  515. data/lib/badline/z80.rb +0 -11
  516. /data/lib/badline/snapshot/{fields.rb → vice/fields.rb} +0 -0
@@ -1,35 +0,0 @@
1
- # frozen_string_literal: true
2
-
3
- module Badline
4
- class Cartridge
5
- # Ocean: up to 64 8K banks. A write to I/O 1 selects the bank from bits
6
- # 0-5, masked to the size of the ROM.
7
- class Ocean < Cartridge
8
- def poke(addr, value)
9
- return if addr > 0xdeff
10
-
11
- select_bank(value & @bank_mask)
12
- changed!
13
- end
14
-
15
- def reset
16
- select_bank(0)
17
- changed!
18
- end
19
-
20
- private
21
-
22
- # In 16K mode the selected bank shows through ROMH as well.
23
- def select_bank(number)
24
- @roml = bank(@banks, number)
25
- @romh = @roml if game.zero?
26
- end
27
-
28
- def install_chips(chips)
29
- @banks = banks_from(chips).first
30
- @bank_mask = bank_mask(@banks) & 0x3f
31
- reset
32
- end
33
- end
34
- end
35
- end
@@ -1,68 +0,0 @@
1
- # frozen_string_literal: true
2
-
3
- module Badline
4
- class Cartridge
5
- # Pagefox: two 32K EPROMs and 32K of RAM, seen 16K at a time. A write to
6
- # $DE80-$DEFF selects the half with bit 1 and the chip with bits 2-3
7
- # (EPROM, EPROM, RAM, nothing), and switches the cartridge out with
8
- # bit 4. Writes to the RAM land in the C64's RAM as well.
9
- class Pagefox < Cartridge
10
- RAM_CHIP = 2
11
- EMPTY_CHIP = 3
12
-
13
- def connect(ram:, open_bus:)
14
- super
15
- @ram_banks.each { |b| b.backing = ram }
16
- end
17
-
18
- def poke(addr, value)
19
- return if addr < 0xde80 || addr > 0xdeff
20
-
21
- select(value)
22
- changed!
23
- end
24
-
25
- def reset
26
- select(0)
27
- changed!
28
- end
29
-
30
- private
31
-
32
- def save_mapper(out)
33
- super
34
- @ram_banks.each { |ram| out.blob(ram.data) }
35
- end
36
-
37
- def load_mapper(input)
38
- super
39
- @ram_banks.each { |ram| input.blob_into(ram.data) }
40
- end
41
-
42
- def windows = [*@roml_banks, *@romh_banks, *@ram_banks, @open_bus || EMPTY_BANK, EMPTY_BANK]
43
-
44
- def select(value)
45
- half = (value >> 1) & 0x01
46
- chip = (value >> 2) & 0x03
47
- @roml, @romh = window(chip, half)
48
- self.mode = value.anybits?(0x10) ? :off : :rom16k
49
- end
50
-
51
- def window(chip, half)
52
- case chip
53
- when RAM_CHIP then @ram_banks[half * 2, 2]
54
- when EMPTY_CHIP then [@open_bus || EMPTY_BANK] * 2
55
- else
56
- number = (chip << 1) | half
57
- [bank(@roml_banks, number), bank(@romh_banks, number)]
58
- end
59
- end
60
-
61
- def install_chips(chips)
62
- @roml_banks, @romh_banks = banks_from(chips)
63
- @ram_banks = Array.new(4) { RAMBank.new }
64
- reset
65
- end
66
- end
67
- end
68
- end
@@ -1,320 +0,0 @@
1
- # frozen_string_literal: true
2
-
3
- module Badline
4
- class Cartridge
5
- # A Retro Replay's registers, RAM and flash, for a snapshot.
6
- module RetroReplayState
7
- private
8
-
9
- def save_jumpers(out)
10
- out.boolean(true).boolean(@flash_jumper).boolean(@bank_jumper)
11
- end
12
-
13
- def save_mapper(out)
14
- [@active, @frozen, @phi1_ultimax, @ram_enabled, @ram_at_a000, @allow_bank, @no_freeze, @reu_mapping,
15
- @write_once].each { |flag| out.boolean(flag) }
16
- out.int(@bank).int(RetroReplay::CONTROL_MODES.index(@config))
17
- @ram_data.each { |data| out.blob(data) }
18
- @flash.save_state(out)
19
- end
20
-
21
- def load_mapper(input)
22
- load_flags(input)
23
- @bank = input.int
24
- @config = RetroReplay::CONTROL_MODES.fetch(input.int)
25
- @ram_data.each { |data| input.blob_into(data) }
26
- @flash.load_state(input)
27
- map_windows
28
- end
29
-
30
- def load_flags(input)
31
- @active = input.boolean?
32
- @frozen = input.boolean?
33
- @phi1_ultimax = input.boolean?
34
- @ram_enabled = input.boolean?
35
- @ram_at_a000 = input.boolean?
36
- @allow_bank = input.boolean?
37
- @no_freeze = input.boolean?
38
- @reu_mapping = input.boolean?
39
- @write_once = input.boolean?
40
- end
41
- end
42
-
43
- # Retro Replay: an Am29F010 flash chip of two 64K halves, each eight 8K
44
- # ROM banks, and four 8K RAM banks, with the Action Replay's register at
45
- # $DE00 and an extended one at $DE01. The Nordic Replay (subtype 1) adds
46
- # the Nordic Power configuration. The clock port isn't there.
47
- #
48
- # CRT banks 0-7 are the chip's upper half and banks 8-15 its lower half.
49
- # The cartridge runs from the upper half, or from the lower one with the
50
- # bank jumper set.
51
- #
52
- # $DE00 writes:
53
- # bit 0 pulls GAME low
54
- # bit 1 releases EXROM
55
- # bit 2 switches the registers off until the next freeze or reset
56
- # bits 3-4,7 bank
57
- # bit 5 RAM instead of ROM
58
- # bit 6 acknowledges a freeze: until then the cartridge stays in
59
- # Ultimax mode with nothing at ROML
60
- #
61
- # $DE01 writes the bank again, and once only AllowBank (bit 1), which
62
- # banks the RAM in I/O as well, NoFreeze (bit 2) and the REU-compatible
63
- # map (bit 6), which moves the I/O RAM from I/O 2 to I/O 1 above $DE01.
64
- # $DE00 and $DE01 read back the bank, the write-once bits and the freeze
65
- # button.
66
- #
67
- # The VIC sees Ultimax mode only from a freeze to the next $DE00 write.
68
- #
69
- # The RAM at ROML takes writes only in Ultimax mode, except on the Nordic
70
- # Replay. With RAM and only EXROM released ($22) the Retro Replay maps
71
- # nothing at ROML and keeps the RAM in I/O, and the Nordic Replay maps
72
- # the ROM at ROML and the RAM at ROMH, as the Nordic Power does. Frozen
73
- # in that configuration, the Nordic Replay maps the RAM at $A000.
74
- #
75
- # The flash jumper puts the cartridge in flash mode, which starts with
76
- # the cartridge switched off ($02) and has no freeze. $DE00 selects 8K
77
- # mode unless it switches the cartridge off, and writes to ROML reach
78
- # the flash, and the C64's RAM underneath, or the RAM when selected.
79
- # $DE01 isn't write-once and has no REU-compatible map, and with the
80
- # bank jumper set its bit 5 clear selects the other half of the flash,
81
- # until the next $DE00 write. $DE00 reads the flash jumper in bit 0 and
82
- # the half in bit 5.
83
- class RetroReplay < Cartridge
84
- include Freezer
85
- include RetroReplayState
86
-
87
- CONTROL_MODES = %i[rom8k rom16k off ultimax].freeze
88
- IO1_PAGE = 0x1e00
89
- IO2_PAGE = 0x1f00
90
-
91
- attr_reader :flash
92
-
93
- def self.from_jumpers(crt, input)
94
- input.boolean?
95
- new(crt, flash_jumper: input.boolean?, bank_jumper: input.boolean?)
96
- end
97
-
98
- def initialize(crt, flash_jumper: false, bank_jumper: false)
99
- @nordic = crt.subtype == 1
100
- @flash_jumper = flash_jumper
101
- @bank_jumper = bank_jumper
102
- super(crt)
103
- end
104
-
105
- def clock=(clock)
106
- super
107
- @flash.clock = clock
108
- end
109
-
110
- def connect(ram:, open_bus:)
111
- super
112
- @through.each { |b| b.backing = ram }
113
- configure
114
- end
115
-
116
- def readable_io_pages
117
- [0xde, 0xdf]
118
- end
119
-
120
- def peek(addr)
121
- return open_bus(addr) unless @active
122
-
123
- addr < 0xdf00 ? io1_peek(addr) : io2_peek(addr)
124
- end
125
-
126
- def poke(addr, value)
127
- return unless @active
128
-
129
- low = addr & 0xff
130
- if addr >= 0xdf00
131
- io_ram[IO2_PAGE | low] = value if io_ram_writable?(!@reu_mapping)
132
- elsif low > 1
133
- io_ram[IO1_PAGE | low] = value if io_ram_writable?(@reu_mapping)
134
- else
135
- low.zero? ? control(value) : extended_control(value)
136
- end
137
- end
138
-
139
- def phi1_ultimax? = @phi1_ultimax
140
-
141
- def ultimax_a000
142
- @isolated[ram_view_bank] if @nordic && @ram_at_a000 && @frozen
143
- end
144
-
145
- # Reset leaves the write-once bits of $DE01 as they are.
146
- def reset
147
- @active = true
148
- @frozen = false
149
- self.nmi = false
150
- control(@flash_jumper ? 0x02 : 0x00)
151
- end
152
-
153
- def freeze!
154
- @active = @frozen = @phi1_ultimax = true
155
- @ram_enabled = false
156
- @bank = 0
157
- @config = :ultimax
158
- configure
159
- end
160
-
161
- private
162
-
163
- def freeze_allowed? = !@no_freeze && !@flash_jumper
164
-
165
- def status
166
- ((@bank & 0x03) << 3) | ((@bank & 0x04) << 5) | ((@bank & 0x08) << 2) | (@flash_jumper ? 0x01 : 0) |
167
- (@allow_bank ? 0x02 : 0) | (button_pressed? ? 0x04 : 0) | (@reu_mapping ? 0x40 : 0)
168
- end
169
-
170
- def io1_peek(addr)
171
- return status if (addr & 0xff) < 2
172
- return open_bus(addr) unless @reu_mapping && !@frozen
173
-
174
- io_window(addr, IO1_PAGE)
175
- end
176
-
177
- def io2_peek(addr)
178
- return open_bus(addr) if @reu_mapping || @frozen
179
-
180
- io_window(addr, IO2_PAGE)
181
- end
182
-
183
- # The I/O RAM when selected, otherwise the ROM, which 16K and Ultimax
184
- # mode leave out.
185
- def io_window(addr, page)
186
- if @ram_enabled || @ram_at_a000
187
- io_ram[page | (addr & 0xff)]
188
- elsif @config == :rom8k || @config == :off
189
- @rom.peek(addr)
190
- else
191
- open_bus(addr)
192
- end
193
- end
194
-
195
- def io_ram
196
- @ram_data[ram_view_bank]
197
- end
198
-
199
- def io_ram_writable?(window)
200
- window && !@frozen && (@ram_enabled || (@nordic && @ram_at_a000))
201
- end
202
-
203
- def ram_view_bank
204
- @allow_bank ? @bank & 0x03 : 0
205
- end
206
-
207
- def control(value)
208
- value = flash_mode_control(value)
209
- @bank = bank_bits(value)
210
- @phi1_ultimax = false
211
- @config = CONTROL_MODES[value & 0x03]
212
- @ram_at_a000 = (value & 0x67) == 0x22
213
- if @nordic && @ram_at_a000
214
- @config = :rom16k
215
- @ram_enabled = false
216
- else
217
- acknowledge_freeze if value.anybits?(0x40)
218
- @ram_enabled = value.anybits?(0x20)
219
- @config = :off if @ram_at_a000
220
- end
221
- @config = :ultimax if @frozen
222
- configure
223
- @active = false if value.anybits?(0x04)
224
- end
225
-
226
- # Flash mode leaves 8K mode only to switch the cartridge off.
227
- def flash_mode_control(value)
228
- return value unless @flash_jumper && (value & 0x03) != 0x02
229
-
230
- value & ~0x03
231
- end
232
-
233
- def acknowledge_freeze
234
- @frozen = false
235
- self.nmi = false
236
- end
237
-
238
- def extended_control(value)
239
- unless @write_once
240
- @allow_bank = value.anybits?(0x02)
241
- @no_freeze = value.anybits?(0x04)
242
- @reu_mapping = value.anybits?(0x40) && !@flash_jumper
243
- @write_once = !@flash_jumper
244
- end
245
- @bank = bank_bits(value)
246
- @bank |= 0x08 if @flash_jumper && @bank_jumper && value.nobits?(0x20)
247
- configure
248
- end
249
-
250
- def bank_bits(value)
251
- ((value >> 3) & 0x03) | ((value >> 5) & 0x04)
252
- end
253
-
254
- def configure
255
- map_windows
256
- changed!
257
- end
258
-
259
- def map_windows
260
- self.mode = @config
261
- @rom = flash_window(@bank)
262
- @roml = roml_window
263
- @romh = romh_window
264
- end
265
-
266
- def roml_window
267
- nothing = @open_bus || EMPTY_BANK
268
- return @ram_enabled ? WriteOnlyRAM.new(@ram_data[@bank & 0x03], nothing) : nothing if @frozen
269
- return ram_window(@bank & 0x03) if @ram_enabled
270
- return flash_writes if (@nordic && @ram_at_a000) || @config != :rom16k
271
-
272
- nothing
273
- end
274
-
275
- # A RAM bank over the flash window takes writes for the chip and the
276
- # C64's RAM alike.
277
- def flash_writes
278
- return @rom unless @flash_jumper
279
-
280
- RAMBank.new(@rom).tap { |window| window.backing = @ram }
281
- end
282
-
283
- def ram_window(number)
284
- if @config == :ultimax || @flash_jumper
285
- @isolated[number]
286
- else
287
- (@nordic ? @through : @readers)[number]
288
- end
289
- end
290
-
291
- def romh_window
292
- nordic_ram = @nordic && @ram_at_a000
293
- return @isolated[ram_view_bank] if nordic_ram && !@frozen
294
- return @rom if @allow_bank || !(@ram_enabled || nordic_ram)
295
-
296
- flash_window(@bank & ~0x03)
297
- end
298
-
299
- def flash_window(number)
300
- @flash.window((@bank_jumper ? 0 : 0x10000) + (number * BANK_SIZE))
301
- end
302
-
303
- def install_chips(chips)
304
- data = Array.new(0x20000, 0xff)
305
- chips.each do |chip|
306
- bytes = chip.data.first(BANK_SIZE)
307
- data[((chip.bank & 0x0f) ^ 0x08) * BANK_SIZE, bytes.length] = bytes
308
- end
309
- @flash = Flash.new(data, model: Flash::AM29F010)
310
- @flash.on_change { configure }
311
- @ram_data = Array.new(4) { Array.new(BANK_SIZE, 0) }
312
- @through = @ram_data.map { |data| RAMBank.new(data) }
313
- @isolated = @ram_data.map { |data| RAMBank.new(data) }
314
- @readers = @ram_data.map { |data| RAMReader.new(data) }
315
- @allow_bank = @no_freeze = @reu_mapping = @write_once = false
316
- reset
317
- end
318
- end
319
- end
320
- end
@@ -1,29 +0,0 @@
1
- # frozen_string_literal: true
2
-
3
- module Badline
4
- class Cartridge
5
- # 8K. Reading $DF00-$DFBF switches the ROM out, reading $DFC0-$DFFF
6
- # switches it back in.
7
- class RexUtility < Cartridge
8
- def readable_io_pages
9
- [0xdf]
10
- end
11
-
12
- def peek(addr)
13
- select_mode((addr & 0xff) < 0xc0 ? :off : :rom8k) if addr >= 0xdf00
14
- open_bus(addr)
15
- end
16
-
17
- def reset
18
- select_mode(:rom8k)
19
- end
20
-
21
- private
22
-
23
- def install_chips(chips)
24
- @roml = banks_from(chips).first.compact.first || EMPTY_BANK
25
- reset
26
- end
27
- end
28
- end
29
- end
@@ -1,58 +0,0 @@
1
- # frozen_string_literal: true
2
-
3
- module Badline
4
- class Cartridge
5
- # RGCD: up to eight 8K banks. A write to I/O 1 selects the bank from the
6
- # low bits, and bit 3 switches the ROM out until reset. The Hucky board
7
- # (subtype 1) inverts the bank bits and decodes only as many as it has
8
- # banks.
9
- class RGCD < Cartridge
10
- def initialize(crt)
11
- @hucky = crt.subtype == 1
12
- super
13
- end
14
-
15
- def poke(addr, value)
16
- return if addr > 0xdeff || @disabled
17
-
18
- select(value)
19
- changed!
20
- end
21
-
22
- def reset
23
- @disabled = false
24
- self.mode = :rom8k
25
- select(0)
26
- changed!
27
- end
28
-
29
- private
30
-
31
- def save_mapper(out)
32
- super
33
- out.boolean(@disabled)
34
- end
35
-
36
- def load_mapper(input)
37
- super
38
- @disabled = input.boolean?
39
- end
40
-
41
- def select(value)
42
- value ^= 0x07 if @hucky
43
- if value.anybits?(0x08)
44
- @disabled = true
45
- self.mode = :off
46
- else
47
- @roml = bank(@banks, value & @bank_mask)
48
- end
49
- end
50
-
51
- def install_chips(chips)
52
- @banks = banks_from(chips).first
53
- @bank_mask = @hucky ? bank_mask(@banks) : 0x07
54
- reset
55
- end
56
- end
57
- end
58
- end
@@ -1,35 +0,0 @@
1
- # frozen_string_literal: true
2
-
3
- module Badline
4
- class Cartridge
5
- # 16K. Reading I/O 1 switches ROMH out (8K mode), writing it switches
6
- # ROMH back in.
7
- class SimonsBasic < Cartridge
8
- def readable_io_pages
9
- [0xde]
10
- end
11
-
12
- def peek(addr)
13
- select_mode(:rom8k) if addr < 0xdf00
14
- open_bus(addr)
15
- end
16
-
17
- def poke(addr, _value)
18
- select_mode(:rom16k) if addr < 0xdf00
19
- end
20
-
21
- def reset
22
- select_mode(:rom16k)
23
- end
24
-
25
- private
26
-
27
- def install_chips(chips)
28
- roml, romh = banks_from(chips)
29
- @roml = bank(roml, 0)
30
- @romh = bank(romh, 0)
31
- reset
32
- end
33
- end
34
- end
35
- end
@@ -1,15 +0,0 @@
1
- # frozen_string_literal: true
2
-
3
- module Badline
4
- class Cartridge
5
- class Standard < Cartridge
6
- private
7
-
8
- def install_chips(chips)
9
- roml, romh = banks_from(chips)
10
- @roml = roml.compact.first
11
- @romh = romh.compact.first
12
- end
13
- end
14
- end
15
- end
@@ -1,48 +0,0 @@
1
- # frozen_string_literal: true
2
-
3
- module Badline
4
- class Cartridge
5
- # Super Games: four 16K banks. A write to I/O 2 selects the bank from bits
6
- # 0-1, switches the ROM out with bit 2, and with bit 3 locks the register
7
- # until reset.
8
- class SuperGames < Cartridge
9
- def poke(addr, value)
10
- return if addr < 0xdf00 || @locked
11
-
12
- select(value)
13
- changed!
14
- end
15
-
16
- def reset
17
- select(0)
18
- changed!
19
- end
20
-
21
- private
22
-
23
- def save_mapper(out)
24
- super
25
- out.boolean(@locked)
26
- end
27
-
28
- def load_mapper(input)
29
- super
30
- @locked = input.boolean?
31
- end
32
-
33
- def windows = [*@roml_banks, *@romh_banks, EMPTY_BANK]
34
-
35
- def select(value)
36
- @roml = bank(@roml_banks, value & 0x03)
37
- @romh = bank(@romh_banks, value & 0x03)
38
- self.mode = value.anybits?(0x04) ? :off : :rom16k
39
- @locked = value.anybits?(0x08)
40
- end
41
-
42
- def install_chips(chips)
43
- @roml_banks, @romh_banks = banks_from(chips)
44
- reset
45
- end
46
- end
47
- end
48
- end
@@ -1,30 +0,0 @@
1
- # frozen_string_literal: true
2
-
3
- module Badline
4
- class Cartridge
5
- # 16K. Reading I/O 2 switches ROMH out (8K mode) until reset.
6
- class Westermann < Cartridge
7
- def readable_io_pages
8
- [0xdf]
9
- end
10
-
11
- def peek(addr)
12
- select_mode(:rom8k) if addr >= 0xdf00
13
- open_bus(addr)
14
- end
15
-
16
- def reset
17
- select_mode(:rom16k)
18
- end
19
-
20
- private
21
-
22
- def install_chips(chips)
23
- roml, romh = banks_from(chips)
24
- @roml = bank(roml, 0)
25
- @romh = bank(romh, 0)
26
- reset
27
- end
28
- end
29
- end
30
- end
@@ -1,66 +0,0 @@
1
- # frozen_string_literal: true
2
-
3
- module Badline
4
- class Cartridge
5
- # Zaxxon / Super Zaxxon: 16K mode with a 4K ROML mirrored across
6
- # $8000-$9FFF and two 8K ROMH banks. A read through ROML selects the
7
- # ROMH bank: $8000-$8FFF the first, $9000-$9FFF the second.
8
- class Zaxxon < Cartridge
9
- class Low
10
- def initialize(rom, high)
11
- @rom = rom
12
- @high = high
13
- end
14
-
15
- def peek(addr)
16
- @high.select(addr[12])
17
- @rom.peek(addr)
18
- end
19
- end
20
-
21
- class High
22
- def initialize(banks)
23
- @banks = banks
24
- select(0)
25
- end
26
-
27
- def select(number)
28
- @bank = @banks[number] || EMPTY_BANK
29
- end
30
-
31
- def peek(addr)
32
- @bank.peek(addr)
33
- end
34
-
35
- def save_state(out)
36
- out.int([*@banks, EMPTY_BANK].index { |bank| bank.equal?(@bank) })
37
- end
38
-
39
- def load_state(input)
40
- @bank = [*@banks, EMPTY_BANK].fetch(input.int)
41
- end
42
- end
43
-
44
- def reset
45
- @romh.select(0)
46
- end
47
-
48
- private
49
-
50
- def save_mapper(out)
51
- @romh.save_state(out)
52
- end
53
-
54
- def load_mapper(input)
55
- @romh.load_state(input)
56
- end
57
-
58
- def install_chips(chips)
59
- roml, romh = banks_from(chips)
60
- @romh = High.new(romh)
61
- @roml = Low.new(roml.first || EMPTY_BANK, @romh)
62
- self.mode = :rom16k
63
- end
64
- end
65
- end
66
- end