badline 0.12.0 → 0.13.0

data/lib/badline/c128/saved_state.rb

@@ -1,26 +1,17 @@
 # frozen_string_literal: true
 
+require "badline/snapshot/c128_setup"
+
 module Badline
   class C128
-    MARKER = "C128"
-
-    # The model, the SID and the mode it resets into of the machine a State
-    # from #snapshot was taken of, the arguments C128.new takes.
-    def self.setup(state)
-      input = Snapshot::StateReader.new(state)
-      input.marker(MARKER)
-      input.check_stamp
-      SavedState.read_setup(input)
-    end
+    # How the machine a State from #snapshot was taken of was built.
+    def self.setup(state) = Snapshot::C128Setup.from(state)
 
     # A new machine, built as the one a State from #snapshot was taken of,
     # at that state.
-    def self.restored(state)
-      setup = setup(state)
-      new(model: setup[0], sid_model: setup[1], mode: setup[2]).apply_state(state)
-    end
+    def self.restored(state) = setup(state).build.apply_state(state)
 
-    # The whole machine's state for a snapshot, as Computer's: the
+    # The whole machine's state for a snapshot, as C64's: the
     # machine's own latches, FAST and TEST as they last took hold, the bus with its RAM, the MMU, the chips and
     # the VDC, the CPU, the cartridge, the disk device 8 serves through the
     # traps and a true 1541. The serial lines go back into the bus from the
@@ -28,21 +19,6 @@ module Badline
     # joysticks, CAPS LOCK and 40/80 DISPLAY, the traps and callbacks, and
     # which chip renders.
     module SavedState
-      SID_MODELS = %i[mos6581 mos8580].freeze
-      MODES = %i[c64 c128].freeze
-
-      # The model's name, the SID's model and the mode.
-      def self.read_setup(input)
-        name = input.string
-        known = Model::ALL.any? { |model| model.name == name }
-        raise Snapshot::FormatError, "the state names a C128 model badline doesn't know" unless known
-
-        sid_model = SID_MODELS.fetch(input.int)
-        [name, sid_model, MODES.fetch(input.int)]
-      rescue IndexError
-        raise Snapshot::FormatError, "the state names a SID or a mode badline doesn't know"
-      end
-
       # How many more on_init handlers the machine a State was taken of had
       # yet to run than this one has. Nil until the machine is restored.
       attr_reader :init_handlers_lost
@@ -72,8 +48,8 @@ module Badline
       end
 
       def save_state(out)
-        out.marker(MARKER).stamp
-        out.string(@model.name).int(SID_MODELS.index(@sid.model)).int(@c64_built ? 0 : 1)
+        out.marker(Snapshot::C128Setup::MARKER).stamp
+        snapshot_setup.write(out)
         out.int(@cycles).int(@clock_bits).boolean(@nmi_asserted).boolean(@cartridge_nmi).boolean(@restore_pulse)
         out.boolean(!@pending_keys.nil?)
         out.ints(@pending_keys) if @pending_keys
@@ -83,14 +59,14 @@ module Badline
         @cpu.save_state(out)
         @z80.save_state(out)
         out.int(@z80_due).int(@chips_ahead).boolean(@cpu_reset_pending)
-        save_trap_drive(out)
+        save_trap_dos(out)
         save_serial_bus(out)
       end
 
       def load_state(input)
-        input.marker(MARKER)
+        input.marker(Snapshot::C128Setup::MARKER)
         input.check_stamp
-        check_setup(SavedState.read_setup(input))
+        check_setup(Snapshot::C128Setup.read(input))
         @cycles = input.int
         @clock_bits = input.int
         @nmi_asserted = input.boolean?
@@ -105,24 +81,17 @@ module Badline
         push_serial_lines
         @cpu.load_state(input)
         load_z80(input)
-        load_trap_drive(input)
+        load_trap_dos(input)
         load_serial_bus(input)
         push_fast_serial
       end
 
       private
 
-      # The Z80 and which CPU has the bus, which a state from before the
-      # Z80 leaves to the 8502. The bus, restored before it, hands the bus
-      # to its CPU without resetting the 8502.
+      # The Z80 and which CPU has the bus. The bus, restored before it,
+      # hands the bus to its CPU without resetting the 8502.
       def load_z80(input)
         @z80_running = @bus.z80?
-        @z80_turn = @z80_running
-        @z80_due = @z80.cycles
-        @chips_ahead = 0
-        @cpu_reset_pending = false
-        return unless input.schema > 6
-
         @z80.load_state(input)
         @z80_due = input.int
         @chips_ahead = input.int
@@ -130,11 +99,16 @@ module Badline
         @z80_turn = @z80_running || @chips_ahead.positive?
       end
 
+      # How this machine was built.
+      def snapshot_setup
+        Snapshot::C128Setup.new(model: @model.name, sid_model: @sid.model, mode: @c64_built ? :c64 : :c128)
+      end
+
       def check_setup(setup)
-        ours = [@model.name, @sid.model, @c64_built ? :c64 : :c128]
+        ours = snapshot_setup
         return if setup == ours
 
-        raise Snapshot::FormatError, "the state is of a #{setup.join(' with a ')}, not a #{ours.join(' with a ')}"
+        raise Snapshot::FormatError, "the state is of a #{setup}, not a #{ours}"
       end
     end
 

data/lib/badline/c128/z80.rb

@@ -1,12 +1,12 @@
 # frozen_string_literal: true
 
-require "badline/z80/core"
+require "badline/chips/z80/core"
 
 module Badline
   class C128
     # The C128's Z80A, on the Z80's side of the C128::Bus.
     class Z80
-      include Badline::Z80::Core
+      include Badline::Chips::Z80::Core
     end
 
     # The Z80's accesses, through the pages C128::Bus lays out for it

data/lib/badline/c128.rb

@@ -2,13 +2,13 @@
 
 require "badline/c128/model"
 require "badline/c128/mmu"
-require "badline/c128/vdc"
+require "badline/chips/vdc"
 require "badline/c128/mmu_pages"
 require "badline/c128/io_pages"
 require "badline/c128/z80_pages"
 require "badline/c128/color_lines"
 require "badline/c128/banks"
-require "badline/c128/bus_state"
+require "badline/c128/bus/saved_state"
 require "badline/c128/bus"
 require "badline/c128/cpu"
 require "badline/c128/z80"
@@ -18,7 +18,7 @@ require "badline/c128/keys"
 require "badline/c128/modes"
 require "badline/c128/drives"
 require "badline/c128/fast_serial"
-require "badline/drive1571"
+require "badline/drives/model1571"
 
 module Badline
   # The Commodore 128: the 8502 on the VIC-IIe's clock, two CIAs, the SID,
@@ -44,8 +44,10 @@ module Badline
   class C128
     include IntegerHelper
     include KeyboardBuffer
-    include Computer::Attachments
-    include Computer::KernalTraps
+    include Machine::Clocking
+    include C64::Common
+    include C64::Attachments
+    include C64::KernalTraps
     include Keys
     include Modes
     include Drives
@@ -54,7 +56,7 @@ module Badline
 
     # The C64's 8x8 matrix and the three rows K0-K2 select, in port B
     # column order.
-    KEYBOARD_MATRIX = (Keyboard::C64_MATRIX + [
+    KEYBOARD_MATRIX = (Input::Keyboard::C64_MATRIX + [
       %i[help keypad8 keypad5 tab keypad2 keypad4 keypad7 keypad1],
       %i[esc keypad_plus keypad_minus line_feed keypad_enter keypad6 keypad9 keypad3],
       %i[alt keypad0 keypad_period crsr_up crsr_down crsr_left crsr_right no_scroll]
@@ -71,10 +73,6 @@ module Badline
 
     attr_reader :cpu, :cycles, :drive1541, :model, :init_threshold
 
-    # The path of the disk or directory device 8 serves through the traps
-    # (Computer::Attachments), or an empty one.
-    def mounted_path = @drive.nil? ? "" : @drive.path
-
     def family = :c128
 
     def address_bus = @bus
@@ -95,6 +93,11 @@ module Badline
 
     def ram = @bus.ram
 
+    # Reads and writes memory as the CPU sees it, through the bus.
+    def peek(addr) = @bus.peek(addr)
+
+    def poke(addr, value) = @bus.poke(addr, value)
+
     def keyboard = @bus.keyboard
 
     def joystick1 = @bus.joystick1
@@ -118,7 +121,7 @@ module Badline
 
       @model = Model.named(model)
       @c64_built = mode == :c64
-      @init_threshold = @c64_built ? Computer::INIT_THRESHOLD : C128_INIT_THRESHOLD
+      @init_threshold = @c64_built ? C64::INIT_THRESHOLD : C128_INIT_THRESHOLD
       @holding_commodore = false
       @bus = Bus.new(@model, sid_model: sid_model || @model.sid_model, mode:)
       @cpu = CPU.new(@bus, debug:)
@@ -173,36 +176,6 @@ module Badline
       @cycles += 1
     end
 
-    # Runs `count` cycles, one #cycle! after another.
-    def run_cycles(count)
-      i = 0
-      while i < count
-        cycle!
-        i += 1
-      end
-    end
-
-    # Runs cycles until the block returns true or the cycle count passes
-    # `limit`, checking before each cycle.
-    def run_until(limit)
-      cycle! until yield || @cycles > limit
-    end
-
-    def on_init(&block)
-      if @cycles < init_threshold
-        @init_handlers << block
-      else
-        block.call
-      end
-    end
-
-    # The clock, the raster and the crop of the VIC-IIe's region.
-    def timing
-      region = @bus.region
-      Timing.new(clock_hz: region.clock_hz, cycles_per_line: region.cycles_per_line,
-                 lines_per_frame: region.lines_per_frame, crop: region.crop, pixel_width: 1)
-    end
-
     # The chip whose #display a front end shows: the VIC-IIe, or with
     # :vdc the VDC, whose display paints only while its #render is on.
     def video(chip = :vic) = chip == :vdc ? @vdc : @vic
@@ -217,12 +190,6 @@ module Badline
     # The chip a front end records the machine's sound from.
     def sound_source = @sid
 
-    def load_prg(data)
-      uint16(data[0], data[1]).tap do |load_addr|
-        ram.write(load_addr, data[2..])
-      end
-    end
-
     # A cartridge goes in with the power off.
     def attach_cartridge(cartridge)
       connect_cartridge(cartridge)
@@ -247,7 +214,7 @@ module Badline
       @cia2.reset!
       @sid.reset!
       @bus.cartridge&.reset
-      @drive&.reset!
+      @dos&.reset!
       @drive1541&.reset!
       @drive1571&.reset!
       @drive1581&.reset!
@@ -255,19 +222,11 @@ module Badline
       reset_z80
     end
 
-    # CHROUT is at $FFD2 in both KERNALs, and the trap follows the mode.
-    def capture_output
-      @capture_output ||= ChroutTrap.new(cpu:, bus: @bus, layout: trap_layout).tap do |trap|
-        cpu.install_trap(ChroutTrap::ADDRESS) { trap.call }
-      end
-    end
-
-    def inspect
-      "#<#{self.class.name} cycles=#{@cycles} cpu=(#{@cpu.inspect})>"
-    end
-
     private
 
+    # The bus the KERNAL traps read and write through.
+    def trap_bus = @bus
+
     # The C128 KERNAL leaves $D02F at $FF, every extra keyboard row
     # deselected, before it jumps to the C64's reset.
     def enter_c64_mode
@@ -275,15 +234,6 @@ module Badline
       @bus.control_ports.extra_rows = 0xff
     end
 
-    # The NMI line is wired-OR between CIA 2, the cartridge and RESTORE,
-    # and the CPU takes an interrupt on its falling edge.
-    def drive_nmi
-      nmi = @cia2.interrupted? || @cartridge_nmi || @restore_pulse
-      @restore_pulse = false
-      @cpu.nmi = true if nmi && !@nmi_asserted
-      @nmi_asserted = nmi
-    end
-
     # BA halts the CPU on a read cycle.
     def clock_cpu
       @cpu.pending_write? || !@vic.ba_low? ? @cpu.cycle! : @cpu.stall!
@@ -311,9 +261,5 @@ module Badline
       @cpu.cycle!
       @vic.take_cpu_bus(phi1, @bus.data, @bus.vic_access?)
     end
-
-    def handle_init
-      @init_handlers.each(&:call)
-    end
   end
 end

data/lib/badline/{computer → c64}/attachments.rb

@@ -1,10 +1,10 @@
 # frozen_string_literal: true
 
 module Badline
-  class Computer
-    # What plugs into the machine besides its chips, the cartridge, the
-    # disk device 8 serves through the traps, its true drives (TrueDrives)
-    # and an REU, and their state for a snapshot.
+  class C64
+    # What plugs into the machine besides its chips, the cartridge, its
+    # true drives (TrueDrives) and an REU, and their state for a snapshot.
+    # The disk device 8 serves through the traps is KernalTraps'.
     module Attachments
       include TrueDrives
 
@@ -17,30 +17,6 @@ module Badline
         address_bus.attach_cartridge(cartridge)
       end
 
-      # Puts the storage in device 8. Mounting again swaps the disk at any
-      # point while the machine runs: the drive keeps its RAM, which only a
-      # drive reset clears, and its status. The traps go on the KERNAL the
-      # machine runs (#trap_layout).
-      def mount(storage)
-        return @drive.insert(storage) if @drive
-
-        @drive = KernalTrap::Drive.new(storage)
-        install_kernal_traps(trap_layout)
-      end
-
-      # Takes device 8's mounted storage out, and with it the LOAD, SAVE and
-      # serial traps, so the KERNAL's routines go out over the serial bus.
-      # Mounting again starts a new drive, with its RAM cleared.
-      def unmount
-        return unless @drive
-
-        remove_kernal_traps
-        @drive = nil
-      end
-
-      # Whether device 8 serves a disk or directory through the traps.
-      def mounted? = !@drive.nil?
-
       # The serial bus, which CIA 2's port A drives through the C64's own
       # inverters and reads back on PA6 and PA7, with or without a drive on
       # it.
@@ -51,7 +27,7 @@ module Badline
       # CIA 2's port A drives the serial bus, which reads CLK and DATA back
       # into it.
       def plug_serial_bus
-        @iec_bus = IECBus.new
+        @iec_bus = Drives::SerialBus.new
         @cia2.peripheral = @iec_bus
         @cia2.on_port_a_write { push_serial_lines }
         push_serial_lines
@@ -78,26 +54,19 @@ module Badline
         end
       end
 
-      # The disk device 8 serves through the traps, with the traps' own
-      # state: open channels, the drive's status and RAM, a SAVE under way.
-      def save_trap_drive(out)
-        out.boolean(!@drive.nil?)
-        return unless @drive
-
-        @drive.save_state(out)
-        @serial_trap.save_state(out)
-        @save_trap.save_state(out)
+      # A true 1541 on the serial bus, then a 1581.
+      def save_serial_bus(out)
+        out.boolean(!@drive1541.nil?)
+        if @drive1541
+          out.int(@drive1541.device)
+          @drive1541.save_state(out)
+        end
+        save_drive1581(out)
       end
 
-      def load_trap_drive(input)
-        return unmount unless input.boolean?
-
-        storage = Storage.reopen(input)
-        unmount
-        mount(storage)
-        @drive.load_state(input)
-        @serial_trap.load_state(input)
-        @save_trap.load_state(input)
+      def load_serial_bus(input)
+        load_drive1541(input)
+        load_drive1581(input)
       end
 
       # The REU, which the setup says the machine has, and whether it has

data/lib/badline/c64/banked_ram/banking.rb

@@ -0,0 +1,32 @@
+# frozen_string_literal: true
+
+module Badline
+  class C64
+    module BankedRAM
+      # The register and page mapping the expansions share. #map lays the
+      # selected banks out in the address bus's page tables, and #map_io puts
+      # the register over the VIC's I/O page at $D100.
+      module Banking
+        attr_reader :low_ram, :high_ram, :video_ram
+
+        # The block runs whenever the register moves a bank.
+        def on_change(&block)
+          @on_change = block
+        end
+
+        def peek(_addr) = 0xff
+
+        def map(read_pages, write_pages)
+          [read_pages, write_pages].each do |pages|
+            pages.fill(@low_ram, 0x00, 0x10)
+            pages.fill(@high_ram, 0x10, 0xf0)
+          end
+        end
+
+        def map_io(read_pages, write_pages)
+          read_pages[0xd1] = write_pages[0xd1] = self
+        end
+      end
+    end
+  end
+end

data/lib/badline/c64/banked_ram/plus256k.rb

@@ -0,0 +1,56 @@
+# frozen_string_literal: true
+
+module Badline
+  class C64
+    module BankedRAM
+      # The +256K: four 64K banks, the first of them the machine's own RAM.
+      # $D100 picks one for $0000-$0FFF (bits 0-1), one for the VIC (bits 2-3)
+      # and one for $1000-$FFFF (bits 6-7). Setting bit 4 locks the register
+      # until the next reset.
+      class Plus256k
+        include Banking
+
+        def initialize(ram)
+          @banks = [ram, Memory.new, Memory.new, Memory.new]
+          @on_change = nil
+          reset!
+        end
+
+        def poke(_addr, value)
+          return if @locked
+
+          @low_ram = @banks[value & 0b11]
+          @video_ram = @banks[(value >> 2) & 0b11]
+          @high_ram = @banks[value >> 6]
+          @locked = value.anybits?(0x10)
+          @on_change&.call
+        end
+
+        def reset!
+          @low_ram = @video_ram = @high_ram = @banks[0]
+          @locked = false
+        end
+
+        def type = :plus256k
+
+        def save_state(out)
+          [@low_ram, @video_ram, @high_ram].each { |bank| out.int(@banks.index(bank)) }
+          out.boolean(@locked)
+          @banks.drop(1).each { |bank| bank.save_state(out) }
+        end
+
+        def load_state(input)
+          @low_ram = @banks.fetch(input.int)
+          @video_ram = @banks.fetch(input.int)
+          @high_ram = @banks.fetch(input.int)
+          @locked = input.boolean?
+          @banks.drop(1).each { |bank| bank.load_state(input) }
+        end
+
+        def power_on!
+          @banks.drop(1).each(&:clear!)
+        end
+      end
+    end
+  end
+end

data/lib/badline/c64/banked_ram/plus60k.rb

@@ -0,0 +1,45 @@
+# frozen_string_literal: true
+
+module Badline
+  class C64
+    module BankedRAM
+      # The +60K: a second bank of RAM behind $1000-$FFFF, selected by bit 7
+      # of $D100. $0000-$0FFF stays the machine's own RAM, and so does all of
+      # what the VIC sees.
+      class Plus60k
+        include Banking
+
+        def initialize(ram)
+          @low_ram = @video_ram = @high_ram = ram
+          @banks = [ram, Memory.new]
+          @on_change = nil
+        end
+
+        def poke(_addr, value)
+          @high_ram = @banks[value >> 7]
+          @on_change&.call
+        end
+
+        def reset!
+          @high_ram = @banks[0]
+        end
+
+        def type = :plus60k
+
+        def save_state(out)
+          out.int(@banks.index(@high_ram))
+          @banks[1].save_state(out)
+        end
+
+        def load_state(input)
+          @high_ram = @banks.fetch(input.int)
+          @banks[1].load_state(input)
+        end
+
+        def power_on!
+          @banks[1].clear!
+        end
+      end
+    end
+  end
+end

data/lib/badline/c64/banked_ram/unexpanded.rb

@@ -0,0 +1,30 @@
+# frozen_string_literal: true
+
+module Badline
+  class C64
+    module BankedRAM
+      # The machine with no expansion fitted: its own RAM everywhere, and
+      # $D100 left to the VIC.
+      class Unexpanded
+        include Banking
+
+        def initialize(ram)
+          @low_ram = @video_ram = @high_ram = ram
+          @on_change = nil
+        end
+
+        def type = nil
+
+        def map_io(_read_pages, _write_pages); end
+
+        def save_state(_out); end
+
+        def load_state(_input); end
+
+        def reset!; end
+
+        def power_on!; end
+      end
+    end
+  end
+end

data/lib/badline/c64/banked_ram.rb

@@ -0,0 +1,23 @@
+# frozen_string_literal: true
+
+require "badline/c64/banked_ram/banking"
+require "badline/c64/banked_ram/unexpanded"
+require "badline/c64/banked_ram/plus60k"
+require "badline/c64/banked_ram/plus256k"
+
+module Badline
+  class C64
+    # RAM expansions that bank extra memory in under the CPU through a
+    # register at $D100, in the VIC's I/O page. Any write to $D100-$D1FF
+    # sets the register, which reads back as $FF.
+    module BankedRAM
+      TYPES = { plus60k: Plus60k, plus256k: Plus256k }.freeze
+
+      def self.build(type, ram, &)
+        expansion = type ? TYPES.fetch(type).new(ram) : Unexpanded.new(ram)
+        expansion.on_change(&)
+        expansion
+      end
+    end
+  end
+end

data/lib/badline/c64/bus/extra_sids.rb

@@ -0,0 +1,32 @@
+# frozen_string_literal: true
+
+module Badline
+  class C64
+    class Bus
+      # The second and third SIDs the SID player fits for a tune written for
+      # them, each over its 32 bytes of the I/O area (SIDSlots). The SID
+      # player's machine has nothing else in I/O 1 and 2, so the rest of a
+      # page there reads the open bus.
+      module ExtraSIDs
+        # Fits a SID at the address it was built at, where it takes its 32
+        # bytes over from whatever maps there.
+        def add_sid(sid)
+          page = sid.start >> 8
+          slots = @sid_slots.find { |candidate| candidate.page == page }
+          if slots.nil?
+            slots = SIDSlots.new(page, @sid, @open_bus)
+            @sid_slots << slots
+          end
+          slots.place(sid)
+          update_overlays!
+        end
+
+        private
+
+        def map_extra_sids
+          @sid_slots.each { |slots| @read_pages[slots.page] = @write_pages[slots.page] = slots }
+        end
+      end
+    end
+  end
+end

data/lib/badline/c64/bus/fittings.rb

@@ -0,0 +1,40 @@
+# frozen_string_literal: true
+
+module Badline
+  class C64
+    class Bus
+      # What a model fits around the chips: its KERNAL, a datasette or none,
+      # and the board and case they sit in.
+      module Fittings
+        # The keywords #fit takes.
+        NAMES = %i[kernal datasette board].freeze
+
+        # The C64's board and case, the PET 64's, whose built-in monitor
+        # shows the VIC's output in shades of green, the C64GS's, which has
+        # no keyboard, or the MAX Machine's (:max): 2K of RAM, no ROMs, CIA 1
+        # alone at $DC00-$DFFF and the cartridge port in Ultimax mode.
+        BOARDS = %i[c64 pet64 gs max].freeze
+
+        attr_reader :board
+
+        # Fits the KERNAL ROM ROMs::KERNALS names, leaves the cassette port
+        # empty unless `datasette`, and puts the chips in the board BOARDS
+        # names.
+        def fit(kernal: :c64, datasette: true, board: :c64)
+          self.kernal = kernal unless kernal == :c64
+          @datasette.disconnect! unless datasette
+          self.board = board unless board == :c64
+        end
+
+        def board=(name)
+          raise ArgumentError, "no board named #{name}" unless BOARDS.include?(name)
+
+          @board = name
+          vic.palette = name == :pet64 ? Chips::VIC::GREEN_PALETTE : Chips::VIC::PALETTE
+          keyboard.connected = name != :gs
+          update_overlays!
+        end
+      end
+    end
+  end
+end