arduino_ci 0.1.3 → 0.1.4
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- checksums.yaml +4 -4
- data/README.md +77 -1
- data/cpp/arduino/Arduino.cpp +17 -7
- data/cpp/arduino/Arduino.h +151 -5
- data/cpp/arduino/ArduinoDefines.h +90 -0
- data/cpp/arduino/AvrMath.h +18 -28
- data/cpp/arduino/Godmode.cpp +62 -0
- data/cpp/arduino/Godmode.h +74 -0
- data/cpp/arduino/HardwareSerial.h +81 -0
- data/cpp/arduino/Print.h +67 -0
- data/cpp/arduino/Stream.h +210 -0
- data/cpp/arduino/WCharacter.h +96 -0
- data/cpp/arduino/WString.h +164 -0
- data/cpp/arduino/binary.h +518 -0
- data/cpp/arduino/include/README.md +3 -0
- data/cpp/arduino/include/common.h +333 -0
- data/cpp/arduino/include/fuse.h +274 -0
- data/cpp/arduino/include/io.h +643 -0
- data/cpp/arduino/include/io1200.h +274 -0
- data/cpp/arduino/include/io2313.h +385 -0
- data/cpp/arduino/include/io2323.h +210 -0
- data/cpp/arduino/include/io2333.h +461 -0
- data/cpp/arduino/include/io2343.h +214 -0
- data/cpp/arduino/include/io43u32x.h +440 -0
- data/cpp/arduino/include/io43u35x.h +432 -0
- data/cpp/arduino/include/io4414.h +500 -0
- data/cpp/arduino/include/io4433.h +489 -0
- data/cpp/arduino/include/io4434.h +588 -0
- data/cpp/arduino/include/io76c711.h +499 -0
- data/cpp/arduino/include/io8515.h +501 -0
- data/cpp/arduino/include/io8534.h +217 -0
- data/cpp/arduino/include/io8535.h +589 -0
- data/cpp/arduino/include/io86r401.h +309 -0
- data/cpp/arduino/include/io90pwm1.h +1157 -0
- data/cpp/arduino/include/io90pwm161.h +918 -0
- data/cpp/arduino/include/io90pwm216.h +1225 -0
- data/cpp/arduino/include/io90pwm2b.h +1466 -0
- data/cpp/arduino/include/io90pwm316.h +1272 -0
- data/cpp/arduino/include/io90pwm3b.h +1466 -0
- data/cpp/arduino/include/io90pwm81.h +1036 -0
- data/cpp/arduino/include/io90pwmx.h +1415 -0
- data/cpp/arduino/include/io90scr100.h +1719 -0
- data/cpp/arduino/include/ioa5272.h +803 -0
- data/cpp/arduino/include/ioa5505.h +803 -0
- data/cpp/arduino/include/ioa5702m322.h +2591 -0
- data/cpp/arduino/include/ioa5782.h +1843 -0
- data/cpp/arduino/include/ioa5790.h +907 -0
- data/cpp/arduino/include/ioa5790n.h +922 -0
- data/cpp/arduino/include/ioa5791.h +923 -0
- data/cpp/arduino/include/ioa5795.h +756 -0
- data/cpp/arduino/include/ioa5831.h +1949 -0
- data/cpp/arduino/include/ioa6285.h +740 -0
- data/cpp/arduino/include/ioa6286.h +740 -0
- data/cpp/arduino/include/ioa6289.h +847 -0
- data/cpp/arduino/include/ioa6612c.h +795 -0
- data/cpp/arduino/include/ioa6613c.h +795 -0
- data/cpp/arduino/include/ioa6614q.h +798 -0
- data/cpp/arduino/include/ioa6616c.h +865 -0
- data/cpp/arduino/include/ioa6617c.h +865 -0
- data/cpp/arduino/include/ioa664251.h +857 -0
- data/cpp/arduino/include/ioa8210.h +1843 -0
- data/cpp/arduino/include/ioa8510.h +1949 -0
- data/cpp/arduino/include/ioat94k.h +565 -0
- data/cpp/arduino/include/iocan128.h +100 -0
- data/cpp/arduino/include/iocan32.h +100 -0
- data/cpp/arduino/include/iocan64.h +100 -0
- data/cpp/arduino/include/iocanxx.h +2020 -0
- data/cpp/arduino/include/iom103.h +735 -0
- data/cpp/arduino/include/iom128.h +1299 -0
- data/cpp/arduino/include/iom1280.h +101 -0
- data/cpp/arduino/include/iom1281.h +101 -0
- data/cpp/arduino/include/iom1284.h +1099 -0
- data/cpp/arduino/include/iom1284p.h +1219 -0
- data/cpp/arduino/include/iom1284rfr2.h +2690 -0
- data/cpp/arduino/include/iom128a.h +1070 -0
- data/cpp/arduino/include/iom128rfa1.h +5385 -0
- data/cpp/arduino/include/iom128rfr2.h +2706 -0
- data/cpp/arduino/include/iom16.h +676 -0
- data/cpp/arduino/include/iom161.h +726 -0
- data/cpp/arduino/include/iom162.h +1022 -0
- data/cpp/arduino/include/iom163.h +686 -0
- data/cpp/arduino/include/iom164.h +101 -0
- data/cpp/arduino/include/iom164a.h +34 -0
- data/cpp/arduino/include/iom164p.h +34 -0
- data/cpp/arduino/include/iom164pa.h +1016 -0
- data/cpp/arduino/include/iom165.h +887 -0
- data/cpp/arduino/include/iom165a.h +832 -0
- data/cpp/arduino/include/iom165p.h +889 -0
- data/cpp/arduino/include/iom165pa.h +948 -0
- data/cpp/arduino/include/iom168.h +97 -0
- data/cpp/arduino/include/iom168a.h +35 -0
- data/cpp/arduino/include/iom168p.h +942 -0
- data/cpp/arduino/include/iom168pa.h +843 -0
- data/cpp/arduino/include/iom168pb.h +899 -0
- data/cpp/arduino/include/iom169.h +1174 -0
- data/cpp/arduino/include/iom169a.h +44 -0
- data/cpp/arduino/include/iom169p.h +1097 -0
- data/cpp/arduino/include/iom169pa.h +1485 -0
- data/cpp/arduino/include/iom16a.h +923 -0
- data/cpp/arduino/include/iom16hva.h +80 -0
- data/cpp/arduino/include/iom16hva2.h +883 -0
- data/cpp/arduino/include/iom16hvb.h +1052 -0
- data/cpp/arduino/include/iom16hvbrevb.h +1052 -0
- data/cpp/arduino/include/iom16m1.h +1571 -0
- data/cpp/arduino/include/iom16u2.h +1000 -0
- data/cpp/arduino/include/iom16u4.h +1423 -0
- data/cpp/arduino/include/iom2560.h +101 -0
- data/cpp/arduino/include/iom2561.h +101 -0
- data/cpp/arduino/include/iom2564rfr2.h +2691 -0
- data/cpp/arduino/include/iom256rfr2.h +2707 -0
- data/cpp/arduino/include/iom3000.h +237 -0
- data/cpp/arduino/include/iom32.h +755 -0
- data/cpp/arduino/include/iom323.h +744 -0
- data/cpp/arduino/include/iom324a.h +1014 -0
- data/cpp/arduino/include/iom324p.h +1016 -0
- data/cpp/arduino/include/iom324pa.h +1372 -0
- data/cpp/arduino/include/iom325.h +886 -0
- data/cpp/arduino/include/iom3250.h +982 -0
- data/cpp/arduino/include/iom3250a.h +34 -0
- data/cpp/arduino/include/iom3250p.h +34 -0
- data/cpp/arduino/include/iom3250pa.h +1042 -0
- data/cpp/arduino/include/iom325a.h +34 -0
- data/cpp/arduino/include/iom325p.h +34 -0
- data/cpp/arduino/include/iom325pa.h +937 -0
- data/cpp/arduino/include/iom328.h +34 -0
- data/cpp/arduino/include/iom328p.h +948 -0
- data/cpp/arduino/include/iom329.h +1069 -0
- data/cpp/arduino/include/iom3290.h +1227 -0
- data/cpp/arduino/include/iom3290a.h +34 -0
- data/cpp/arduino/include/iom3290pa.h +1123 -0
- data/cpp/arduino/include/iom329a.h +34 -0
- data/cpp/arduino/include/iom329p.h +1164 -0
- data/cpp/arduino/include/iom329pa.h +34 -0
- data/cpp/arduino/include/iom32a.h +686 -0
- data/cpp/arduino/include/iom32c1.h +1320 -0
- data/cpp/arduino/include/iom32hvb.h +1052 -0
- data/cpp/arduino/include/iom32hvbrevb.h +953 -0
- data/cpp/arduino/include/iom32m1.h +1625 -0
- data/cpp/arduino/include/iom32u2.h +1000 -0
- data/cpp/arduino/include/iom32u4.h +1512 -0
- data/cpp/arduino/include/iom32u6.h +1431 -0
- data/cpp/arduino/include/iom406.h +783 -0
- data/cpp/arduino/include/iom48.h +93 -0
- data/cpp/arduino/include/iom48a.h +35 -0
- data/cpp/arduino/include/iom48p.h +936 -0
- data/cpp/arduino/include/iom48pa.h +839 -0
- data/cpp/arduino/include/iom48pb.h +890 -0
- data/cpp/arduino/include/iom64.h +1311 -0
- data/cpp/arduino/include/iom640.h +101 -0
- data/cpp/arduino/include/iom644.h +101 -0
- data/cpp/arduino/include/iom644a.h +34 -0
- data/cpp/arduino/include/iom644p.h +101 -0
- data/cpp/arduino/include/iom644pa.h +1387 -0
- data/cpp/arduino/include/iom644rfr2.h +2685 -0
- data/cpp/arduino/include/iom645.h +881 -0
- data/cpp/arduino/include/iom6450.h +978 -0
- data/cpp/arduino/include/iom6450a.h +34 -0
- data/cpp/arduino/include/iom6450p.h +34 -0
- data/cpp/arduino/include/iom645a.h +34 -0
- data/cpp/arduino/include/iom645p.h +34 -0
- data/cpp/arduino/include/iom649.h +1061 -0
- data/cpp/arduino/include/iom6490.h +1182 -0
- data/cpp/arduino/include/iom6490a.h +34 -0
- data/cpp/arduino/include/iom6490p.h +34 -0
- data/cpp/arduino/include/iom649a.h +34 -0
- data/cpp/arduino/include/iom649p.h +1490 -0
- data/cpp/arduino/include/iom64a.h +1084 -0
- data/cpp/arduino/include/iom64c1.h +1321 -0
- data/cpp/arduino/include/iom64hve.h +1034 -0
- data/cpp/arduino/include/iom64hve2.h +767 -0
- data/cpp/arduino/include/iom64m1.h +1572 -0
- data/cpp/arduino/include/iom64rfr2.h +2701 -0
- data/cpp/arduino/include/iom8.h +665 -0
- data/cpp/arduino/include/iom8515.h +687 -0
- data/cpp/arduino/include/iom8535.h +772 -0
- data/cpp/arduino/include/iom88.h +97 -0
- data/cpp/arduino/include/iom88a.h +35 -0
- data/cpp/arduino/include/iom88p.h +941 -0
- data/cpp/arduino/include/iom88pa.h +1185 -0
- data/cpp/arduino/include/iom88pb.h +899 -0
- data/cpp/arduino/include/iom8a.h +621 -0
- data/cpp/arduino/include/iom8hva.h +76 -0
- data/cpp/arduino/include/iom8u2.h +997 -0
- data/cpp/arduino/include/iomx8.h +808 -0
- data/cpp/arduino/include/iomxx0_1.h +1692 -0
- data/cpp/arduino/include/iomxx4.h +954 -0
- data/cpp/arduino/include/iomxxhva.h +550 -0
- data/cpp/arduino/include/iotn10.h +512 -0
- data/cpp/arduino/include/iotn11.h +255 -0
- data/cpp/arduino/include/iotn12.h +288 -0
- data/cpp/arduino/include/iotn13.h +395 -0
- data/cpp/arduino/include/iotn13a.h +394 -0
- data/cpp/arduino/include/iotn15.h +363 -0
- data/cpp/arduino/include/iotn1634.h +914 -0
- data/cpp/arduino/include/iotn167.h +883 -0
- data/cpp/arduino/include/iotn20.h +776 -0
- data/cpp/arduino/include/iotn22.h +221 -0
- data/cpp/arduino/include/iotn2313.h +702 -0
- data/cpp/arduino/include/iotn2313a.h +812 -0
- data/cpp/arduino/include/iotn24.h +94 -0
- data/cpp/arduino/include/iotn24a.h +846 -0
- data/cpp/arduino/include/iotn25.h +93 -0
- data/cpp/arduino/include/iotn26.h +422 -0
- data/cpp/arduino/include/iotn261.h +93 -0
- data/cpp/arduino/include/iotn261a.h +987 -0
- data/cpp/arduino/include/iotn28.h +297 -0
- data/cpp/arduino/include/iotn4.h +477 -0
- data/cpp/arduino/include/iotn40.h +767 -0
- data/cpp/arduino/include/iotn4313.h +813 -0
- data/cpp/arduino/include/iotn43u.h +604 -0
- data/cpp/arduino/include/iotn44.h +94 -0
- data/cpp/arduino/include/iotn441.h +903 -0
- data/cpp/arduino/include/iotn44a.h +844 -0
- data/cpp/arduino/include/iotn45.h +93 -0
- data/cpp/arduino/include/iotn461.h +94 -0
- data/cpp/arduino/include/iotn461a.h +987 -0
- data/cpp/arduino/include/iotn48.h +806 -0
- data/cpp/arduino/include/iotn5.h +512 -0
- data/cpp/arduino/include/iotn828.h +911 -0
- data/cpp/arduino/include/iotn84.h +94 -0
- data/cpp/arduino/include/iotn841.h +903 -0
- data/cpp/arduino/include/iotn84a.h +844 -0
- data/cpp/arduino/include/iotn85.h +93 -0
- data/cpp/arduino/include/iotn861.h +94 -0
- data/cpp/arduino/include/iotn861a.h +988 -0
- data/cpp/arduino/include/iotn87.h +859 -0
- data/cpp/arduino/include/iotn88.h +806 -0
- data/cpp/arduino/include/iotn9.h +477 -0
- data/cpp/arduino/include/iotnx4.h +482 -0
- data/cpp/arduino/include/iotnx5.h +442 -0
- data/cpp/arduino/include/iotnx61.h +541 -0
- data/cpp/arduino/include/iousb1286.h +101 -0
- data/cpp/arduino/include/iousb1287.h +101 -0
- data/cpp/arduino/include/iousb162.h +101 -0
- data/cpp/arduino/include/iousb646.h +102 -0
- data/cpp/arduino/include/iousb647.h +102 -0
- data/cpp/arduino/include/iousb82.h +95 -0
- data/cpp/arduino/include/iousbxx2.h +807 -0
- data/cpp/arduino/include/iousbxx6_7.h +1336 -0
- data/cpp/arduino/include/iox128a1.h +7236 -0
- data/cpp/arduino/include/iox128a1u.h +8305 -0
- data/cpp/arduino/include/iox128a3.h +6987 -0
- data/cpp/arduino/include/iox128a3u.h +7697 -0
- data/cpp/arduino/include/iox128a4u.h +7309 -0
- data/cpp/arduino/include/iox128b1.h +6872 -0
- data/cpp/arduino/include/iox128b3.h +6288 -0
- data/cpp/arduino/include/iox128c3.h +6264 -0
- data/cpp/arduino/include/iox128d3.h +5749 -0
- data/cpp/arduino/include/iox128d4.h +5562 -0
- data/cpp/arduino/include/iox16a4.h +6748 -0
- data/cpp/arduino/include/iox16a4u.h +7309 -0
- data/cpp/arduino/include/iox16c4.h +6078 -0
- data/cpp/arduino/include/iox16d4.h +5717 -0
- data/cpp/arduino/include/iox16e5.h +7699 -0
- data/cpp/arduino/include/iox192a3.h +6987 -0
- data/cpp/arduino/include/iox192a3u.h +7697 -0
- data/cpp/arduino/include/iox192c3.h +6264 -0
- data/cpp/arduino/include/iox192d3.h +5749 -0
- data/cpp/arduino/include/iox256a3.h +6987 -0
- data/cpp/arduino/include/iox256a3b.h +6983 -0
- data/cpp/arduino/include/iox256a3bu.h +7706 -0
- data/cpp/arduino/include/iox256a3u.h +7697 -0
- data/cpp/arduino/include/iox256c3.h +6264 -0
- data/cpp/arduino/include/iox256d3.h +5709 -0
- data/cpp/arduino/include/iox32a4.h +6747 -0
- data/cpp/arduino/include/iox32a4u.h +7309 -0
- data/cpp/arduino/include/iox32c3.h +6264 -0
- data/cpp/arduino/include/iox32c4.h +6078 -0
- data/cpp/arduino/include/iox32d3.h +5105 -0
- data/cpp/arduino/include/iox32d4.h +5685 -0
- data/cpp/arduino/include/iox32e5.h +7699 -0
- data/cpp/arduino/include/iox384c3.h +6849 -0
- data/cpp/arduino/include/iox384d3.h +5833 -0
- data/cpp/arduino/include/iox64a1.h +7236 -0
- data/cpp/arduino/include/iox64a1u.h +8305 -0
- data/cpp/arduino/include/iox64a3.h +6987 -0
- data/cpp/arduino/include/iox64a3u.h +7697 -0
- data/cpp/arduino/include/iox64a4u.h +7309 -0
- data/cpp/arduino/include/iox64b1.h +6454 -0
- data/cpp/arduino/include/iox64b3.h +6288 -0
- data/cpp/arduino/include/iox64c3.h +6264 -0
- data/cpp/arduino/include/iox64d3.h +5764 -0
- data/cpp/arduino/include/iox64d4.h +5555 -0
- data/cpp/arduino/include/iox8e5.h +7699 -0
- data/cpp/arduino/include/lock.h +239 -0
- data/cpp/arduino/include/portpins.h +549 -0
- data/cpp/arduino/include/version.h +90 -0
- data/cpp/arduino/include/xmega.h +71 -0
- data/cpp/unittest/Assertion.h +9 -4
- data/cpp/unittest/Compare.h +93 -0
- data/lib/arduino_ci/arduino_installation.rb +1 -1
- data/lib/arduino_ci/cpp_library.rb +4 -1
- data/lib/arduino_ci/version.rb +1 -1
- data/misc/default.yaml +7 -0
- metadata +285 -2
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/* Copyright (c) 2005 Anatoly Sokolov
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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* Neither the name of the copyright holders nor the names of
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE. */
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/* $Id */
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/* avr/iom2560.h - definitions for ATmega2560 */
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#ifndef _AVR_IOM2560_H_
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#define _AVR_IOM2560_H_ 1
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#include "iomxx0_1.h"
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/* Constants */
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#define SPM_PAGESIZE 256
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#define RAMSTART 0x200
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#define RAMEND 0x21FF
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#define XRAMEND 0xFFFF
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#define E2END 0xFFF
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#define E2PAGESIZE 8
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#define FLASHEND 0x3FFFF
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/* Fuses */
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#define FUSE_MEMORY_SIZE 3
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/* Low Fuse Byte */
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#define FUSE_CKSEL0 (unsigned char)~_BV(0)
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#define FUSE_CKSEL1 (unsigned char)~_BV(1)
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#define FUSE_CKSEL2 (unsigned char)~_BV(2)
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#define FUSE_CKSEL3 (unsigned char)~_BV(3)
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#define FUSE_SUT0 (unsigned char)~_BV(4)
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#define FUSE_SUT1 (unsigned char)~_BV(5)
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#define FUSE_CKOUT (unsigned char)~_BV(6)
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#define FUSE_CKDIV8 (unsigned char)~_BV(7)
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#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
|
64
|
+
|
65
|
+
/* High Fuse Byte */
|
66
|
+
#define FUSE_BOOTRST (unsigned char)~_BV(0)
|
67
|
+
#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
|
68
|
+
#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
|
69
|
+
#define FUSE_EESAVE (unsigned char)~_BV(3)
|
70
|
+
#define FUSE_WDTON (unsigned char)~_BV(4)
|
71
|
+
#define FUSE_SPIEN (unsigned char)~_BV(5)
|
72
|
+
#define FUSE_JTAGEN (unsigned char)~_BV(6)
|
73
|
+
#define FUSE_OCDEN (unsigned char)~_BV(7)
|
74
|
+
#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
|
75
|
+
|
76
|
+
/* Extended Fuse Byte */
|
77
|
+
#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
|
78
|
+
#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
|
79
|
+
#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
|
80
|
+
#define EFUSE_DEFAULT (0xFF)
|
81
|
+
|
82
|
+
|
83
|
+
/* Lock Bits */
|
84
|
+
#define __LOCK_BITS_EXIST
|
85
|
+
#define __BOOT_LOCK_BITS_0_EXIST
|
86
|
+
#define __BOOT_LOCK_BITS_1_EXIST
|
87
|
+
|
88
|
+
|
89
|
+
/* Signature */
|
90
|
+
#define SIGNATURE_0 0x1E
|
91
|
+
#define SIGNATURE_1 0x98
|
92
|
+
#define SIGNATURE_2 0x01
|
93
|
+
|
94
|
+
#define SLEEP_MODE_IDLE (0x00<<1)
|
95
|
+
#define SLEEP_MODE_ADC (0x01<<1)
|
96
|
+
#define SLEEP_MODE_PWR_DOWN (0x02<<1)
|
97
|
+
#define SLEEP_MODE_PWR_SAVE (0x03<<1)
|
98
|
+
#define SLEEP_MODE_STANDBY (0x06<<1)
|
99
|
+
#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
|
100
|
+
|
101
|
+
#endif /* _AVR_IOM2560_H_ */
|
@@ -0,0 +1,101 @@
|
|
1
|
+
/* Copyright (c) 2005 Anatoly Sokolov
|
2
|
+
All rights reserved.
|
3
|
+
|
4
|
+
Redistribution and use in source and binary forms, with or without
|
5
|
+
modification, are permitted provided that the following conditions are met:
|
6
|
+
|
7
|
+
* Redistributions of source code must retain the above copyright
|
8
|
+
notice, this list of conditions and the following disclaimer.
|
9
|
+
|
10
|
+
* Redistributions in binary form must reproduce the above copyright
|
11
|
+
notice, this list of conditions and the following disclaimer in
|
12
|
+
the documentation and/or other materials provided with the
|
13
|
+
distribution.
|
14
|
+
|
15
|
+
* Neither the name of the copyright holders nor the names of
|
16
|
+
contributors may be used to endorse or promote products derived
|
17
|
+
from this software without specific prior written permission.
|
18
|
+
|
19
|
+
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
20
|
+
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
21
|
+
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
22
|
+
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
23
|
+
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
24
|
+
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
25
|
+
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
26
|
+
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
27
|
+
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
28
|
+
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
29
|
+
POSSIBILITY OF SUCH DAMAGE. */
|
30
|
+
|
31
|
+
/* $Id */
|
32
|
+
|
33
|
+
/* avr/iom2561.h - definitions for ATmega2561 */
|
34
|
+
|
35
|
+
#ifndef _AVR_IOM2561_H_
|
36
|
+
#define _AVR_IOM2561_H_ 1
|
37
|
+
|
38
|
+
#include "iomxx0_1.h"
|
39
|
+
|
40
|
+
/* Constants */
|
41
|
+
#define SPM_PAGESIZE 256
|
42
|
+
#define RAMSTART 0x200
|
43
|
+
#define RAMEND 0x21FF
|
44
|
+
#define XRAMEND 0xFFFF
|
45
|
+
#define E2END 0xFFF
|
46
|
+
#define E2PAGESIZE 8
|
47
|
+
#define FLASHEND 0x3FFFF
|
48
|
+
|
49
|
+
|
50
|
+
/* Fuses */
|
51
|
+
|
52
|
+
#define FUSE_MEMORY_SIZE 3
|
53
|
+
|
54
|
+
/* Low Fuse Byte */
|
55
|
+
#define FUSE_CKSEL0 (unsigned char)~_BV(0)
|
56
|
+
#define FUSE_CKSEL1 (unsigned char)~_BV(1)
|
57
|
+
#define FUSE_CKSEL2 (unsigned char)~_BV(2)
|
58
|
+
#define FUSE_CKSEL3 (unsigned char)~_BV(3)
|
59
|
+
#define FUSE_SUT0 (unsigned char)~_BV(4)
|
60
|
+
#define FUSE_SUT1 (unsigned char)~_BV(5)
|
61
|
+
#define FUSE_CKOUT (unsigned char)~_BV(6)
|
62
|
+
#define FUSE_CKDIV8 (unsigned char)~_BV(7)
|
63
|
+
#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
|
64
|
+
|
65
|
+
/* High Fuse Byte */
|
66
|
+
#define FUSE_BOOTRST (unsigned char)~_BV(0)
|
67
|
+
#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
|
68
|
+
#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
|
69
|
+
#define FUSE_EESAVE (unsigned char)~_BV(3)
|
70
|
+
#define FUSE_WDTON (unsigned char)~_BV(4)
|
71
|
+
#define FUSE_SPIEN (unsigned char)~_BV(5)
|
72
|
+
#define FUSE_JTAGEN (unsigned char)~_BV(6)
|
73
|
+
#define FUSE_OCDEN (unsigned char)~_BV(7)
|
74
|
+
#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
|
75
|
+
|
76
|
+
/* Extended Fuse Byte */
|
77
|
+
#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
|
78
|
+
#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
|
79
|
+
#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
|
80
|
+
#define EFUSE_DEFAULT (0xFF)
|
81
|
+
|
82
|
+
|
83
|
+
/* Lock Bits */
|
84
|
+
#define __LOCK_BITS_EXIST
|
85
|
+
#define __BOOT_LOCK_BITS_0_EXIST
|
86
|
+
#define __BOOT_LOCK_BITS_1_EXIST
|
87
|
+
|
88
|
+
|
89
|
+
/* Signature */
|
90
|
+
#define SIGNATURE_0 0x1E
|
91
|
+
#define SIGNATURE_1 0x98
|
92
|
+
#define SIGNATURE_2 0x02
|
93
|
+
|
94
|
+
#define SLEEP_MODE_IDLE (0x00<<1)
|
95
|
+
#define SLEEP_MODE_ADC (0x01<<1)
|
96
|
+
#define SLEEP_MODE_PWR_DOWN (0x02<<1)
|
97
|
+
#define SLEEP_MODE_PWR_SAVE (0x03<<1)
|
98
|
+
#define SLEEP_MODE_STANDBY (0x06<<1)
|
99
|
+
#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
|
100
|
+
|
101
|
+
#endif /* _AVR_IOM2561_H_ */
|
@@ -0,0 +1,2691 @@
|
|
1
|
+
/*****************************************************************************
|
2
|
+
*
|
3
|
+
* Copyright (C) 2016 Atmel Corporation
|
4
|
+
* All rights reserved.
|
5
|
+
*
|
6
|
+
* Redistribution and use in source and binary forms, with or without
|
7
|
+
* modification, are permitted provided that the following conditions are met:
|
8
|
+
*
|
9
|
+
* * Redistributions of source code must retain the above copyright
|
10
|
+
* notice, this list of conditions and the following disclaimer.
|
11
|
+
*
|
12
|
+
* * Redistributions in binary form must reproduce the above copyright
|
13
|
+
* notice, this list of conditions and the following disclaimer in
|
14
|
+
* the documentation and/or other materials provided with the
|
15
|
+
* distribution.
|
16
|
+
*
|
17
|
+
* * Neither the name of the copyright holders nor the names of
|
18
|
+
* contributors may be used to endorse or promote products derived
|
19
|
+
* from this software without specific prior written permission.
|
20
|
+
*
|
21
|
+
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
22
|
+
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
23
|
+
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
24
|
+
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
25
|
+
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
26
|
+
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
27
|
+
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
28
|
+
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
29
|
+
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
30
|
+
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
31
|
+
* POSSIBILITY OF SUCH DAMAGE.
|
32
|
+
****************************************************************************/
|
33
|
+
|
34
|
+
|
35
|
+
#ifndef _AVR_ATMEGA2564RFR2_H_INCLUDED
|
36
|
+
#define _AVR_ATMEGA2564RFR2_H_INCLUDED
|
37
|
+
|
38
|
+
|
39
|
+
#ifndef _AVR_IO_H_
|
40
|
+
# error "Include <avr/io.h> instead of this file."
|
41
|
+
#endif
|
42
|
+
|
43
|
+
#ifndef _AVR_IOXXX_H_
|
44
|
+
# define _AVR_IOXXX_H_ "iom2564rfr2.h"
|
45
|
+
#else
|
46
|
+
# error "Attempt to include more than one <avr/ioXXX.h> file."
|
47
|
+
#endif
|
48
|
+
|
49
|
+
/* Registers and associated bit numbers */
|
50
|
+
|
51
|
+
#define PINA _SFR_IO8(0x00)
|
52
|
+
#define PINA7 7
|
53
|
+
#define PINA6 6
|
54
|
+
#define PINA5 5
|
55
|
+
#define PINA4 4
|
56
|
+
#define PINA3 3
|
57
|
+
#define PINA2 2
|
58
|
+
#define PINA1 1
|
59
|
+
#define PINA0 0
|
60
|
+
|
61
|
+
#define DDRA _SFR_IO8(0x01)
|
62
|
+
#define DDRA7 7
|
63
|
+
// Inserted "DDA7" from "DDRA7" due to compatibility
|
64
|
+
#define DDA7 7
|
65
|
+
#define DDRA6 6
|
66
|
+
// Inserted "DDA6" from "DDRA6" due to compatibility
|
67
|
+
#define DDA6 6
|
68
|
+
#define DDRA5 5
|
69
|
+
// Inserted "DDA5" from "DDRA5" due to compatibility
|
70
|
+
#define DDA5 5
|
71
|
+
#define DDRA4 4
|
72
|
+
// Inserted "DDA4" from "DDRA4" due to compatibility
|
73
|
+
#define DDA4 4
|
74
|
+
#define DDRA3 3
|
75
|
+
// Inserted "DDA3" from "DDRA3" due to compatibility
|
76
|
+
#define DDA3 3
|
77
|
+
#define DDRA2 2
|
78
|
+
// Inserted "DDA2" from "DDRA2" due to compatibility
|
79
|
+
#define DDA2 2
|
80
|
+
#define DDRA1 1
|
81
|
+
// Inserted "DDA1" from "DDRA1" due to compatibility
|
82
|
+
#define DDA1 1
|
83
|
+
#define DDRA0 0
|
84
|
+
// Inserted "DDA0" from "DDRA0" due to compatibility
|
85
|
+
#define DDA0 0
|
86
|
+
|
87
|
+
#define PORTA _SFR_IO8(0x02)
|
88
|
+
#define PORTA7 7
|
89
|
+
#define PORTA6 6
|
90
|
+
#define PORTA5 5
|
91
|
+
#define PORTA4 4
|
92
|
+
#define PORTA3 3
|
93
|
+
#define PORTA2 2
|
94
|
+
#define PORTA1 1
|
95
|
+
#define PORTA0 0
|
96
|
+
|
97
|
+
#define PINB _SFR_IO8(0x03)
|
98
|
+
#define PINB7 7
|
99
|
+
#define PINB6 6
|
100
|
+
#define PINB5 5
|
101
|
+
#define PINB4 4
|
102
|
+
#define PINB3 3
|
103
|
+
#define PINB2 2
|
104
|
+
#define PINB1 1
|
105
|
+
#define PINB0 0
|
106
|
+
|
107
|
+
#define DDRB _SFR_IO8(0x04)
|
108
|
+
#define DDRB7 7
|
109
|
+
// Inserted "DDB7" from "DDRB7" due to compatibility
|
110
|
+
#define DDB7 7
|
111
|
+
#define DDRB6 6
|
112
|
+
// Inserted "DDB6" from "DDRB6" due to compatibility
|
113
|
+
#define DDB6 6
|
114
|
+
#define DDRB5 5
|
115
|
+
// Inserted "DDB5" from "DDRB5" due to compatibility
|
116
|
+
#define DDB5 5
|
117
|
+
#define DDRB4 4
|
118
|
+
// Inserted "DDB4" from "DDRB4" due to compatibility
|
119
|
+
#define DDB4 4
|
120
|
+
#define DDRB3 3
|
121
|
+
// Inserted "DDB3" from "DDRB3" due to compatibility
|
122
|
+
#define DDB3 3
|
123
|
+
#define DDRB2 2
|
124
|
+
// Inserted "DDB2" from "DDRB2" due to compatibility
|
125
|
+
#define DDB2 2
|
126
|
+
#define DDRB1 1
|
127
|
+
// Inserted "DDB1" from "DDRB1" due to compatibility
|
128
|
+
#define DDB1 1
|
129
|
+
#define DDRB0 0
|
130
|
+
// Inserted "DDB0" from "DDRB0" due to compatibility
|
131
|
+
#define DDB0 0
|
132
|
+
|
133
|
+
#define PORTB _SFR_IO8(0x05)
|
134
|
+
#define PORTB7 7
|
135
|
+
#define PORTB6 6
|
136
|
+
#define PORTB5 5
|
137
|
+
#define PORTB4 4
|
138
|
+
#define PORTB3 3
|
139
|
+
#define PORTB2 2
|
140
|
+
#define PORTB1 1
|
141
|
+
#define PORTB0 0
|
142
|
+
|
143
|
+
#define PINC _SFR_IO8(0x06)
|
144
|
+
#define PINC7 7
|
145
|
+
#define PINC6 6
|
146
|
+
#define PINC5 5
|
147
|
+
#define PINC4 4
|
148
|
+
#define PINC3 3
|
149
|
+
#define PINC2 2
|
150
|
+
#define PINC1 1
|
151
|
+
#define PINC0 0
|
152
|
+
|
153
|
+
#define DDRC _SFR_IO8(0x07)
|
154
|
+
#define DDRC7 7
|
155
|
+
// Inserted "DDC7" from "DDRC7" due to compatibility
|
156
|
+
#define DDC7 7
|
157
|
+
#define DDRC6 6
|
158
|
+
// Inserted "DDC6" from "DDRC6" due to compatibility
|
159
|
+
#define DDC6 6
|
160
|
+
#define DDRC5 5
|
161
|
+
// Inserted "DDC5" from "DDRC5" due to compatibility
|
162
|
+
#define DDC5 5
|
163
|
+
#define DDRC4 4
|
164
|
+
// Inserted "DDC4" from "DDRC4" due to compatibility
|
165
|
+
#define DDC4 4
|
166
|
+
#define DDRC3 3
|
167
|
+
// Inserted "DDC3" from "DDRC3" due to compatibility
|
168
|
+
#define DDC3 3
|
169
|
+
#define DDRC2 2
|
170
|
+
// Inserted "DDC2" from "DDRC2" due to compatibility
|
171
|
+
#define DDC2 2
|
172
|
+
#define DDRC1 1
|
173
|
+
// Inserted "DDC1" from "DDRC1" due to compatibility
|
174
|
+
#define DDC1 1
|
175
|
+
#define DDRC0 0
|
176
|
+
// Inserted "DDC0" from "DDRC0" due to compatibility
|
177
|
+
#define DDC0 0
|
178
|
+
|
179
|
+
#define PORTC _SFR_IO8(0x08)
|
180
|
+
#define PORTC7 7
|
181
|
+
#define PORTC6 6
|
182
|
+
#define PORTC5 5
|
183
|
+
#define PORTC4 4
|
184
|
+
#define PORTC3 3
|
185
|
+
#define PORTC2 2
|
186
|
+
#define PORTC1 1
|
187
|
+
#define PORTC0 0
|
188
|
+
|
189
|
+
#define PIND _SFR_IO8(0x09)
|
190
|
+
#define PIND7 7
|
191
|
+
#define PIND6 6
|
192
|
+
#define PIND5 5
|
193
|
+
#define PIND4 4
|
194
|
+
#define PIND3 3
|
195
|
+
#define PIND2 2
|
196
|
+
#define PIND1 1
|
197
|
+
#define PIND0 0
|
198
|
+
|
199
|
+
#define DDRD _SFR_IO8(0x0A)
|
200
|
+
#define DDRD7 7
|
201
|
+
// Inserted "DDD7" from "DDRD7" due to compatibility
|
202
|
+
#define DDD7 7
|
203
|
+
#define DDRD6 6
|
204
|
+
// Inserted "DDD6" from "DDRD6" due to compatibility
|
205
|
+
#define DDD6 6
|
206
|
+
#define DDRD5 5
|
207
|
+
// Inserted "DDD5" from "DDRD5" due to compatibility
|
208
|
+
#define DDD5 5
|
209
|
+
#define DDRD4 4
|
210
|
+
// Inserted "DDD4" from "DDRD4" due to compatibility
|
211
|
+
#define DDD4 4
|
212
|
+
#define DDRD3 3
|
213
|
+
// Inserted "DDD3" from "DDRD3" due to compatibility
|
214
|
+
#define DDD3 3
|
215
|
+
#define DDRD2 2
|
216
|
+
// Inserted "DDD2" from "DDRD2" due to compatibility
|
217
|
+
#define DDD2 2
|
218
|
+
#define DDRD1 1
|
219
|
+
// Inserted "DDD1" from "DDRD1" due to compatibility
|
220
|
+
#define DDD1 1
|
221
|
+
#define DDRD0 0
|
222
|
+
// Inserted "DDD0" from "DDRD0" due to compatibility
|
223
|
+
#define DDD0 0
|
224
|
+
|
225
|
+
#define PORTD _SFR_IO8(0x0B)
|
226
|
+
#define PORTD7 7
|
227
|
+
#define PORTD6 6
|
228
|
+
#define PORTD5 5
|
229
|
+
#define PORTD4 4
|
230
|
+
#define PORTD3 3
|
231
|
+
#define PORTD2 2
|
232
|
+
#define PORTD1 1
|
233
|
+
#define PORTD0 0
|
234
|
+
|
235
|
+
#define PINE _SFR_IO8(0x0C)
|
236
|
+
#define PINE7 7
|
237
|
+
#define PINE6 6
|
238
|
+
#define PINE5 5
|
239
|
+
#define PINE4 4
|
240
|
+
#define PINE3 3
|
241
|
+
#define PINE2 2
|
242
|
+
#define PINE1 1
|
243
|
+
#define PINE0 0
|
244
|
+
|
245
|
+
#define DDRE _SFR_IO8(0x0D)
|
246
|
+
#define DDRE7 7
|
247
|
+
// Inserted "DDE7" from "DDRE7" due to compatibility
|
248
|
+
#define DDE7 7
|
249
|
+
#define DDRE6 6
|
250
|
+
// Inserted "DDE6" from "DDRE6" due to compatibility
|
251
|
+
#define DDE6 6
|
252
|
+
#define DDRE5 5
|
253
|
+
// Inserted "DDE5" from "DDRE5" due to compatibility
|
254
|
+
#define DDE5 5
|
255
|
+
#define DDRE4 4
|
256
|
+
// Inserted "DDE4" from "DDRE4" due to compatibility
|
257
|
+
#define DDE4 4
|
258
|
+
#define DDRE3 3
|
259
|
+
// Inserted "DDE3" from "DDRE3" due to compatibility
|
260
|
+
#define DDE3 3
|
261
|
+
#define DDRE2 2
|
262
|
+
// Inserted "DDE2" from "DDRE2" due to compatibility
|
263
|
+
#define DDE2 2
|
264
|
+
#define DDRE1 1
|
265
|
+
// Inserted "DDE1" from "DDRE1" due to compatibility
|
266
|
+
#define DDE1 1
|
267
|
+
#define DDRE0 0
|
268
|
+
// Inserted "DDE0" from "DDRE0" due to compatibility
|
269
|
+
#define DDE0 0
|
270
|
+
|
271
|
+
#define PORTE _SFR_IO8(0x0E)
|
272
|
+
#define PORTE7 7
|
273
|
+
#define PORTE6 6
|
274
|
+
#define PORTE5 5
|
275
|
+
#define PORTE4 4
|
276
|
+
#define PORTE3 3
|
277
|
+
#define PORTE2 2
|
278
|
+
#define PORTE1 1
|
279
|
+
#define PORTE0 0
|
280
|
+
|
281
|
+
#define PINF _SFR_IO8(0x0F)
|
282
|
+
#define PINF7 7
|
283
|
+
#define PINF6 6
|
284
|
+
#define PINF5 5
|
285
|
+
#define PINF4 4
|
286
|
+
#define PINF3 3
|
287
|
+
#define PINF2 2
|
288
|
+
#define PINF1 1
|
289
|
+
#define PINF0 0
|
290
|
+
|
291
|
+
#define DDRF _SFR_IO8(0x10)
|
292
|
+
#define DDRF7 7
|
293
|
+
// Inserted "DDF7" from "DDRF7" due to compatibility
|
294
|
+
#define DDF7 7
|
295
|
+
#define DDRF6 6
|
296
|
+
// Inserted "DDF6" from "DDRF6" due to compatibility
|
297
|
+
#define DDF6 6
|
298
|
+
#define DDRF5 5
|
299
|
+
// Inserted "DDF5" from "DDRF5" due to compatibility
|
300
|
+
#define DDF5 5
|
301
|
+
#define DDRF4 4
|
302
|
+
// Inserted "DDF4" from "DDRF4" due to compatibility
|
303
|
+
#define DDF4 4
|
304
|
+
#define DDRF3 3
|
305
|
+
// Inserted "DDF3" from "DDRF3" due to compatibility
|
306
|
+
#define DDF3 3
|
307
|
+
#define DDRF2 2
|
308
|
+
// Inserted "DDF2" from "DDRF2" due to compatibility
|
309
|
+
#define DDF2 2
|
310
|
+
#define DDRF1 1
|
311
|
+
// Inserted "DDF1" from "DDRF1" due to compatibility
|
312
|
+
#define DDF1 1
|
313
|
+
#define DDRF0 0
|
314
|
+
// Inserted "DDF0" from "DDRF0" due to compatibility
|
315
|
+
#define DDF0 0
|
316
|
+
|
317
|
+
#define PORTF _SFR_IO8(0x11)
|
318
|
+
#define PORTF7 7
|
319
|
+
#define PORTF6 6
|
320
|
+
#define PORTF5 5
|
321
|
+
#define PORTF4 4
|
322
|
+
#define PORTF3 3
|
323
|
+
#define PORTF2 2
|
324
|
+
#define PORTF1 1
|
325
|
+
#define PORTF0 0
|
326
|
+
|
327
|
+
#define PING _SFR_IO8(0x12)
|
328
|
+
#define PING7 7
|
329
|
+
#define PING6 6
|
330
|
+
#define PING5 5
|
331
|
+
#define PING4 4
|
332
|
+
#define PING3 3
|
333
|
+
#define PING2 2
|
334
|
+
#define PING1 1
|
335
|
+
#define PING0 0
|
336
|
+
|
337
|
+
#define DDRG _SFR_IO8(0x13)
|
338
|
+
#define DDRG7 7
|
339
|
+
// Inserted "DDG7" from "DDRG7" due to compatibility
|
340
|
+
#define DDG7 7
|
341
|
+
#define DDRG6 6
|
342
|
+
// Inserted "DDG6" from "DDRG6" due to compatibility
|
343
|
+
#define DDG6 6
|
344
|
+
#define DDRG5 5
|
345
|
+
// Inserted "DDG5" from "DDRG5" due to compatibility
|
346
|
+
#define DDG5 5
|
347
|
+
#define DDRG4 4
|
348
|
+
// Inserted "DDG4" from "DDRG4" due to compatibility
|
349
|
+
#define DDG4 4
|
350
|
+
#define DDRG3 3
|
351
|
+
// Inserted "DDG3" from "DDRG3" due to compatibility
|
352
|
+
#define DDG3 3
|
353
|
+
#define DDRG2 2
|
354
|
+
// Inserted "DDG2" from "DDRG2" due to compatibility
|
355
|
+
#define DDG2 2
|
356
|
+
#define DDRG1 1
|
357
|
+
// Inserted "DDG1" from "DDRG1" due to compatibility
|
358
|
+
#define DDG1 1
|
359
|
+
#define DDRG0 0
|
360
|
+
// Inserted "DDG0" from "DDRG0" due to compatibility
|
361
|
+
#define DDG0 0
|
362
|
+
|
363
|
+
#define PORTG _SFR_IO8(0x14)
|
364
|
+
#define PORTG7 7
|
365
|
+
#define PORTG6 6
|
366
|
+
#define PORTG5 5
|
367
|
+
#define PORTG4 4
|
368
|
+
#define PORTG3 3
|
369
|
+
#define PORTG2 2
|
370
|
+
#define PORTG1 1
|
371
|
+
#define PORTG0 0
|
372
|
+
|
373
|
+
#define TIFR0 _SFR_IO8(0x15)
|
374
|
+
#define TOV0 0
|
375
|
+
#define OCF0A 1
|
376
|
+
#define OCF0B 2
|
377
|
+
#define Res0 3
|
378
|
+
#define Res1 4
|
379
|
+
#define Res2 5
|
380
|
+
#define Res3 6
|
381
|
+
#define Res4 7
|
382
|
+
|
383
|
+
#define TIFR1 _SFR_IO8(0x16)
|
384
|
+
#define TOV1 0
|
385
|
+
#define OCF1A 1
|
386
|
+
#define OCF1B 2
|
387
|
+
#define OCF1C 3
|
388
|
+
#define ICF1 5
|
389
|
+
|
390
|
+
#define TIFR2 _SFR_IO8(0x17)
|
391
|
+
#define TOV2 0
|
392
|
+
#define OCF2A 1
|
393
|
+
#define OCF2B 2
|
394
|
+
|
395
|
+
#define TIFR3 _SFR_IO8(0x18)
|
396
|
+
#define TOV3 0
|
397
|
+
#define OCF3A 1
|
398
|
+
#define OCF3B 2
|
399
|
+
#define OCF3C 3
|
400
|
+
#define ICF3 5
|
401
|
+
|
402
|
+
#define TIFR4 _SFR_IO8(0x19)
|
403
|
+
#define TOV4 0
|
404
|
+
#define OCF4A 1
|
405
|
+
#define OCF4B 2
|
406
|
+
#define OCF4C 3
|
407
|
+
#define ICF4 5
|
408
|
+
|
409
|
+
#define TIFR5 _SFR_IO8(0x1A)
|
410
|
+
#define TOV5 0
|
411
|
+
#define OCF5A 1
|
412
|
+
#define OCF5B 2
|
413
|
+
#define OCF5C 3
|
414
|
+
#define ICF5 5
|
415
|
+
|
416
|
+
#define PCIFR _SFR_IO8(0x1B)
|
417
|
+
#define PCIF0 0
|
418
|
+
#define PCIF1 1
|
419
|
+
#define PCIF2 2
|
420
|
+
|
421
|
+
#define EIFR _SFR_IO8(0x1C)
|
422
|
+
#define INTF0 0
|
423
|
+
#define INTF1 1
|
424
|
+
#define INTF2 2
|
425
|
+
#define INTF3 3
|
426
|
+
#define INTF4 4
|
427
|
+
#define INTF5 5
|
428
|
+
#define INTF6 6
|
429
|
+
#define INTF7 7
|
430
|
+
|
431
|
+
#define EIMSK _SFR_IO8(0x1D)
|
432
|
+
#define INT0 0
|
433
|
+
#define INT1 1
|
434
|
+
#define INT2 2
|
435
|
+
#define INT3 3
|
436
|
+
#define INT4 4
|
437
|
+
#define INT5 5
|
438
|
+
#define INT6 6
|
439
|
+
#define INT7 7
|
440
|
+
|
441
|
+
#define GPIOR0 _SFR_IO8(0x1E)
|
442
|
+
#define GPIOR00 0
|
443
|
+
#define GPIOR01 1
|
444
|
+
#define GPIOR02 2
|
445
|
+
#define GPIOR03 3
|
446
|
+
#define GPIOR04 4
|
447
|
+
#define GPIOR05 5
|
448
|
+
#define GPIOR06 6
|
449
|
+
#define GPIOR07 7
|
450
|
+
|
451
|
+
#define EECR _SFR_IO8(0x1F)
|
452
|
+
#define EERE 0
|
453
|
+
#define EEPE 1
|
454
|
+
#define EEMPE 2
|
455
|
+
#define EERIE 3
|
456
|
+
#define EEPM0 4
|
457
|
+
#define EEPM1 5
|
458
|
+
|
459
|
+
#define EEDR _SFR_IO8(0x20)
|
460
|
+
|
461
|
+
/* Combine EEARL and EEARH */
|
462
|
+
#define EEAR _SFR_IO16(0x21)
|
463
|
+
|
464
|
+
#define EEARL _SFR_IO8(0x21)
|
465
|
+
#define EEARH _SFR_IO8(0x22)
|
466
|
+
|
467
|
+
#define GTCCR _SFR_IO8(0x23)
|
468
|
+
#define PSRSYNC 0
|
469
|
+
#define PSRASY 1
|
470
|
+
#define TSM 7
|
471
|
+
|
472
|
+
#define TCCR0A _SFR_IO8(0x24)
|
473
|
+
#define WGM00 0
|
474
|
+
#define WGM01 1
|
475
|
+
#define COM0B0 4
|
476
|
+
#define COM0B1 5
|
477
|
+
#define COM0A0 6
|
478
|
+
#define COM0A1 7
|
479
|
+
|
480
|
+
#define TCCR0B _SFR_IO8(0x25)
|
481
|
+
#define CS00 0
|
482
|
+
#define CS01 1
|
483
|
+
#define CS02 2
|
484
|
+
#define WGM02 3
|
485
|
+
#define FOC0B 6
|
486
|
+
#define FOC0A 7
|
487
|
+
|
488
|
+
#define TCNT0 _SFR_IO8(0x26)
|
489
|
+
|
490
|
+
#define OCR0A _SFR_IO8(0x27)
|
491
|
+
|
492
|
+
#define OCR0B _SFR_IO8(0x28)
|
493
|
+
|
494
|
+
/* Reserved [0x29] */
|
495
|
+
|
496
|
+
#define GPIOR1 _SFR_IO8(0x2A)
|
497
|
+
#define GPIOR10 0
|
498
|
+
#define GPIOR11 1
|
499
|
+
#define GPIOR12 2
|
500
|
+
#define GPIOR13 3
|
501
|
+
#define GPIOR14 4
|
502
|
+
#define GPIOR15 5
|
503
|
+
#define GPIOR16 6
|
504
|
+
#define GPIOR17 7
|
505
|
+
|
506
|
+
#define GPIOR2 _SFR_IO8(0x2B)
|
507
|
+
#define GPIOR20 0
|
508
|
+
#define GPIOR21 1
|
509
|
+
#define GPIOR22 2
|
510
|
+
#define GPIOR23 3
|
511
|
+
#define GPIOR24 4
|
512
|
+
#define GPIOR25 5
|
513
|
+
#define GPIOR26 6
|
514
|
+
#define GPIOR27 7
|
515
|
+
|
516
|
+
#define SPCR _SFR_IO8(0x2C)
|
517
|
+
#define SPR0 0
|
518
|
+
#define SPR1 1
|
519
|
+
#define CPHA 2
|
520
|
+
#define CPOL 3
|
521
|
+
#define MSTR 4
|
522
|
+
#define DORD 5
|
523
|
+
#define SPE 6
|
524
|
+
#define SPIE 7
|
525
|
+
|
526
|
+
#define SPSR _SFR_IO8(0x2D)
|
527
|
+
#define SPI2X 0
|
528
|
+
#define WCOL 6
|
529
|
+
#define SPIF 7
|
530
|
+
|
531
|
+
#define SPDR _SFR_IO8(0x2E)
|
532
|
+
|
533
|
+
/* Reserved [0x2F] */
|
534
|
+
|
535
|
+
#define ACSR _SFR_IO8(0x30)
|
536
|
+
#define ACIS0 0
|
537
|
+
#define ACIS1 1
|
538
|
+
#define ACIC 2
|
539
|
+
#define ACIE 3
|
540
|
+
#define ACI 4
|
541
|
+
#define ACO 5
|
542
|
+
#define ACBG 6
|
543
|
+
#define ACD 7
|
544
|
+
|
545
|
+
#define OCDR _SFR_IO8(0x31)
|
546
|
+
#define OCDR0 0
|
547
|
+
#define OCDR1 1
|
548
|
+
#define OCDR2 2
|
549
|
+
#define OCDR3 3
|
550
|
+
#define OCDR4 4
|
551
|
+
#define OCDR5 5
|
552
|
+
#define OCDR6 6
|
553
|
+
#define OCDR7 7
|
554
|
+
|
555
|
+
/* Reserved [0x32] */
|
556
|
+
|
557
|
+
#define SMCR _SFR_IO8(0x33)
|
558
|
+
#define SE 0
|
559
|
+
#define SM0 1
|
560
|
+
#define SM1 2
|
561
|
+
#define SM2 3
|
562
|
+
|
563
|
+
#define MCUSR _SFR_IO8(0x34)
|
564
|
+
#define JTRF 4
|
565
|
+
#define PORF 0
|
566
|
+
#define EXTRF 1
|
567
|
+
#define BORF 2
|
568
|
+
#define WDRF 3
|
569
|
+
|
570
|
+
#define MCUCR _SFR_IO8(0x35)
|
571
|
+
#define JTD 7
|
572
|
+
#define IVCE 0
|
573
|
+
#define IVSEL 1
|
574
|
+
#define PUD 4
|
575
|
+
|
576
|
+
/* Reserved [0x36] */
|
577
|
+
|
578
|
+
#define SPMCSR _SFR_IO8(0x37)
|
579
|
+
#define SPMEN 0
|
580
|
+
#define PGERS 1
|
581
|
+
#define PGWRT 2
|
582
|
+
#define BLBSET 3
|
583
|
+
#define RWWSRE 4
|
584
|
+
#define SIGRD 5
|
585
|
+
#define RWWSB 6
|
586
|
+
#define SPMIE 7
|
587
|
+
|
588
|
+
/* Reserved [0x38..0x3A] */
|
589
|
+
|
590
|
+
#define RAMPZ _SFR_IO8(0x3B)
|
591
|
+
#define RAMPZ0 0
|
592
|
+
#define RAMPZ1 1
|
593
|
+
#define Res5 7
|
594
|
+
|
595
|
+
#define EIND _SFR_IO8(0x3C)
|
596
|
+
|
597
|
+
/* SP [0x3D..0x3E] */
|
598
|
+
|
599
|
+
/* SREG [0x3F] */
|
600
|
+
|
601
|
+
#define WDTCSR _SFR_MEM8(0x60)
|
602
|
+
#define WDE 3
|
603
|
+
#define WDCE 4
|
604
|
+
#define WDP0 0
|
605
|
+
#define WDP1 1
|
606
|
+
#define WDP2 2
|
607
|
+
#define WDP3 5
|
608
|
+
#define WDIE 6
|
609
|
+
#define WDIF 7
|
610
|
+
|
611
|
+
#define CLKPR _SFR_MEM8(0x61)
|
612
|
+
#define CLKPS0 0
|
613
|
+
#define CLKPS1 1
|
614
|
+
#define CLKPS2 2
|
615
|
+
#define CLKPS3 3
|
616
|
+
#define CLKPCE 7
|
617
|
+
|
618
|
+
/* Reserved [0x62] */
|
619
|
+
|
620
|
+
#define PRR2 _SFR_MEM8(0x63)
|
621
|
+
#define PRRAM0 0
|
622
|
+
#define PRRAM1 1
|
623
|
+
#define PRRAM2 2
|
624
|
+
#define PRRAM3 3
|
625
|
+
|
626
|
+
#define __AVR_HAVE_PRR2 ((1<<PRRAM0)|(1<<PRRAM1)|(1<<PRRAM2)|(1<<PRRAM3))
|
627
|
+
#define __AVR_HAVE_PRR2_PRRAM0
|
628
|
+
#define __AVR_HAVE_PRR2_PRRAM1
|
629
|
+
#define __AVR_HAVE_PRR2_PRRAM2
|
630
|
+
#define __AVR_HAVE_PRR2_PRRAM3
|
631
|
+
|
632
|
+
#define PRR0 _SFR_MEM8(0x64)
|
633
|
+
#define PRADC 0
|
634
|
+
#define PRUSART0 1
|
635
|
+
#define PRSPI 2
|
636
|
+
#define PRTIM1 3
|
637
|
+
#define PRPGA 4
|
638
|
+
#define PRTIM0 5
|
639
|
+
#define PRTIM2 6
|
640
|
+
#define PRTWI 7
|
641
|
+
|
642
|
+
#define __AVR_HAVE_PRR0 ((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRPGA)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
|
643
|
+
#define __AVR_HAVE_PRR0_PRADC
|
644
|
+
#define __AVR_HAVE_PRR0_PRUSART0
|
645
|
+
#define __AVR_HAVE_PRR0_PRSPI
|
646
|
+
#define __AVR_HAVE_PRR0_PRTIM1
|
647
|
+
#define __AVR_HAVE_PRR0_PRPGA
|
648
|
+
#define __AVR_HAVE_PRR0_PRTIM0
|
649
|
+
#define __AVR_HAVE_PRR0_PRTIM2
|
650
|
+
#define __AVR_HAVE_PRR0_PRTWI
|
651
|
+
|
652
|
+
#define PRR1 _SFR_MEM8(0x65)
|
653
|
+
#define PRUSART1 0
|
654
|
+
#define PRTIM3 3
|
655
|
+
#define PRTIM4 4
|
656
|
+
#define PRTIM5 5
|
657
|
+
#define PRTRX24 6
|
658
|
+
#define Res 7
|
659
|
+
|
660
|
+
#define __AVR_HAVE_PRR1 ((1<<PRUSART1)|(1<<PRTIM3)|(1<<PRTIM4)|(1<<PRTIM5)|(1<<PRTRX24))
|
661
|
+
#define __AVR_HAVE_PRR1_PRUSART1
|
662
|
+
#define __AVR_HAVE_PRR1_PRTIM3
|
663
|
+
#define __AVR_HAVE_PRR1_PRTIM4
|
664
|
+
#define __AVR_HAVE_PRR1_PRTIM5
|
665
|
+
#define __AVR_HAVE_PRR1_PRTRX24
|
666
|
+
|
667
|
+
#define OSCCAL _SFR_MEM8(0x66)
|
668
|
+
#define CAL0 0
|
669
|
+
#define CAL1 1
|
670
|
+
#define CAL2 2
|
671
|
+
#define CAL3 3
|
672
|
+
#define CAL4 4
|
673
|
+
#define CAL5 5
|
674
|
+
#define CAL6 6
|
675
|
+
#define CAL7 7
|
676
|
+
|
677
|
+
#define BGCR _SFR_MEM8(0x67)
|
678
|
+
#define BGCAL0 0
|
679
|
+
#define BGCAL1 1
|
680
|
+
#define BGCAL2 2
|
681
|
+
#define BGCAL_FINE0 3
|
682
|
+
#define BGCAL_FINE1 4
|
683
|
+
#define BGCAL_FINE2 5
|
684
|
+
#define BGCAL_FINE3 6
|
685
|
+
|
686
|
+
#define PCICR _SFR_MEM8(0x68)
|
687
|
+
#define PCIE0 0
|
688
|
+
#define PCIE1 1
|
689
|
+
#define PCIE2 2
|
690
|
+
|
691
|
+
#define EICRA _SFR_MEM8(0x69)
|
692
|
+
#define ISC00 0
|
693
|
+
#define ISC01 1
|
694
|
+
#define ISC10 2
|
695
|
+
#define ISC11 3
|
696
|
+
#define ISC20 4
|
697
|
+
#define ISC21 5
|
698
|
+
#define ISC30 6
|
699
|
+
#define ISC31 7
|
700
|
+
|
701
|
+
#define EICRB _SFR_MEM8(0x6A)
|
702
|
+
#define ISC40 0
|
703
|
+
#define ISC41 1
|
704
|
+
#define ISC50 2
|
705
|
+
#define ISC51 3
|
706
|
+
#define ISC60 4
|
707
|
+
#define ISC61 5
|
708
|
+
#define ISC70 6
|
709
|
+
#define ISC71 7
|
710
|
+
|
711
|
+
#define PCMSK0 _SFR_MEM8(0x6B)
|
712
|
+
|
713
|
+
#define PCMSK1 _SFR_MEM8(0x6C)
|
714
|
+
#define PCINT8 0
|
715
|
+
#define PCINT9 1
|
716
|
+
#define PCINT10 2
|
717
|
+
#define PCINT11 3
|
718
|
+
#define PCINT12 4
|
719
|
+
#define PCINT13 5
|
720
|
+
#define PCINT14 6
|
721
|
+
#define PCINT15 7
|
722
|
+
|
723
|
+
#define PCMSK2 _SFR_MEM8(0x6D)
|
724
|
+
#define PCINT16 0
|
725
|
+
#define PCINT17 1
|
726
|
+
#define PCINT18 2
|
727
|
+
#define PCINT19 3
|
728
|
+
#define PCINT20 4
|
729
|
+
#define PCINT21 5
|
730
|
+
#define PCINT22 6
|
731
|
+
#define PCINT23 7
|
732
|
+
|
733
|
+
#define TIMSK0 _SFR_MEM8(0x6E)
|
734
|
+
#define TOIE0 0
|
735
|
+
#define OCIE0A 1
|
736
|
+
#define OCIE0B 2
|
737
|
+
|
738
|
+
#define TIMSK1 _SFR_MEM8(0x6F)
|
739
|
+
#define TOIE1 0
|
740
|
+
#define OCIE1A 1
|
741
|
+
#define OCIE1B 2
|
742
|
+
#define OCIE1C 3
|
743
|
+
#define ICIE1 5
|
744
|
+
|
745
|
+
#define TIMSK2 _SFR_MEM8(0x70)
|
746
|
+
#define TOIE2 0
|
747
|
+
#define OCIE2A 1
|
748
|
+
#define OCIE2B 2
|
749
|
+
|
750
|
+
#define TIMSK3 _SFR_MEM8(0x71)
|
751
|
+
#define TOIE3 0
|
752
|
+
#define OCIE3A 1
|
753
|
+
#define OCIE3B 2
|
754
|
+
#define OCIE3C 3
|
755
|
+
#define ICIE3 5
|
756
|
+
|
757
|
+
#define TIMSK4 _SFR_MEM8(0x72)
|
758
|
+
#define TOIE4 0
|
759
|
+
#define OCIE4A 1
|
760
|
+
#define OCIE4B 2
|
761
|
+
#define OCIE4C 3
|
762
|
+
#define ICIE4 5
|
763
|
+
|
764
|
+
#define TIMSK5 _SFR_MEM8(0x73)
|
765
|
+
#define TOIE5 0
|
766
|
+
#define OCIE5A 1
|
767
|
+
#define OCIE5B 2
|
768
|
+
#define OCIE5C 3
|
769
|
+
#define ICIE5 5
|
770
|
+
|
771
|
+
/* Reserved [0x74] */
|
772
|
+
|
773
|
+
#define NEMCR _SFR_MEM8(0x75)
|
774
|
+
#define AEAM0 4
|
775
|
+
#define AEAM1 5
|
776
|
+
#define ENEAM 6
|
777
|
+
|
778
|
+
/* Reserved [0x76] */
|
779
|
+
|
780
|
+
#define ADCSRC _SFR_MEM8(0x77)
|
781
|
+
#define ADSUT0 0
|
782
|
+
#define ADSUT1 1
|
783
|
+
#define ADSUT2 2
|
784
|
+
#define ADSUT3 3
|
785
|
+
#define ADSUT4 4
|
786
|
+
#define ADTHT0 6
|
787
|
+
#define ADTHT1 7
|
788
|
+
|
789
|
+
/* Combine ADCL and ADCH */
|
790
|
+
#ifndef __ASSEMBLER__
|
791
|
+
#define ADC _SFR_MEM16(0x78)
|
792
|
+
#endif
|
793
|
+
#define ADCW _SFR_MEM16(0x78)
|
794
|
+
|
795
|
+
#define ADCL _SFR_MEM8(0x78)
|
796
|
+
#define ADCH _SFR_MEM8(0x79)
|
797
|
+
|
798
|
+
#define ADCSRA _SFR_MEM8(0x7A)
|
799
|
+
#define ADPS0 0
|
800
|
+
#define ADPS1 1
|
801
|
+
#define ADPS2 2
|
802
|
+
#define ADIE 3
|
803
|
+
#define ADIF 4
|
804
|
+
#define ADATE 5
|
805
|
+
#define ADSC 6
|
806
|
+
#define ADEN 7
|
807
|
+
|
808
|
+
#define ADCSRB _SFR_MEM8(0x7B)
|
809
|
+
#define ACME 6
|
810
|
+
#define ADTS0 0
|
811
|
+
#define ADTS1 1
|
812
|
+
#define ADTS2 2
|
813
|
+
#define MUX5 3
|
814
|
+
#define ACCH 4
|
815
|
+
#define REFOK 5
|
816
|
+
#define AVDDOK 7
|
817
|
+
|
818
|
+
#define ADMUX _SFR_MEM8(0x7C)
|
819
|
+
#define MUX0 0
|
820
|
+
#define MUX1 1
|
821
|
+
#define MUX2 2
|
822
|
+
#define MUX3 3
|
823
|
+
#define MUX4 4
|
824
|
+
#define ADLAR 5
|
825
|
+
#define REFS0 6
|
826
|
+
#define REFS1 7
|
827
|
+
|
828
|
+
#define DIDR2 _SFR_MEM8(0x7D)
|
829
|
+
#define ADC8D 0
|
830
|
+
#define ADC9D 1
|
831
|
+
#define ADC10D 2
|
832
|
+
#define ADC11D 3
|
833
|
+
#define ADC12D 4
|
834
|
+
#define ADC13D 5
|
835
|
+
#define ADC14D 6
|
836
|
+
#define ADC15D 7
|
837
|
+
|
838
|
+
#define DIDR0 _SFR_MEM8(0x7E)
|
839
|
+
#define ADC0D 0
|
840
|
+
#define ADC1D 1
|
841
|
+
#define ADC2D 2
|
842
|
+
#define ADC3D 3
|
843
|
+
#define ADC4D 4
|
844
|
+
#define ADC5D 5
|
845
|
+
#define ADC6D 6
|
846
|
+
#define ADC7D 7
|
847
|
+
|
848
|
+
#define DIDR1 _SFR_MEM8(0x7F)
|
849
|
+
#define AIN0D 0
|
850
|
+
#define AIN1D 1
|
851
|
+
|
852
|
+
#define TCCR1A _SFR_MEM8(0x80)
|
853
|
+
#define WGM10 0
|
854
|
+
#define WGM11 1
|
855
|
+
#define COM1C0 2
|
856
|
+
#define COM1C1 3
|
857
|
+
#define COM1B0 4
|
858
|
+
#define COM1B1 5
|
859
|
+
#define COM1A0 6
|
860
|
+
#define COM1A1 7
|
861
|
+
|
862
|
+
#define TCCR1B _SFR_MEM8(0x81)
|
863
|
+
#define CS10 0
|
864
|
+
#define CS11 1
|
865
|
+
#define CS12 2
|
866
|
+
#define WGM12 3
|
867
|
+
#define WGM13 4
|
868
|
+
#define ICES1 6
|
869
|
+
#define ICNC1 7
|
870
|
+
|
871
|
+
#define TCCR1C _SFR_MEM8(0x82)
|
872
|
+
#define FOC1C 5
|
873
|
+
#define FOC1B 6
|
874
|
+
#define FOC1A 7
|
875
|
+
|
876
|
+
/* Reserved [0x83] */
|
877
|
+
|
878
|
+
/* Combine TCNT1L and TCNT1H */
|
879
|
+
#define TCNT1 _SFR_MEM16(0x84)
|
880
|
+
|
881
|
+
#define TCNT1L _SFR_MEM8(0x84)
|
882
|
+
#define TCNT1H _SFR_MEM8(0x85)
|
883
|
+
|
884
|
+
/* Combine ICR1L and ICR1H */
|
885
|
+
#define ICR1 _SFR_MEM16(0x86)
|
886
|
+
|
887
|
+
#define ICR1L _SFR_MEM8(0x86)
|
888
|
+
#define ICR1H _SFR_MEM8(0x87)
|
889
|
+
|
890
|
+
/* Combine OCR1AL and OCR1AH */
|
891
|
+
#define OCR1A _SFR_MEM16(0x88)
|
892
|
+
|
893
|
+
#define OCR1AL _SFR_MEM8(0x88)
|
894
|
+
#define OCR1AH _SFR_MEM8(0x89)
|
895
|
+
|
896
|
+
/* Combine OCR1BL and OCR1BH */
|
897
|
+
#define OCR1B _SFR_MEM16(0x8A)
|
898
|
+
|
899
|
+
#define OCR1BL _SFR_MEM8(0x8A)
|
900
|
+
#define OCR1BH _SFR_MEM8(0x8B)
|
901
|
+
|
902
|
+
/* Combine OCR1CL and OCR1CH */
|
903
|
+
#define OCR1C _SFR_MEM16(0x8C)
|
904
|
+
|
905
|
+
#define OCR1CL _SFR_MEM8(0x8C)
|
906
|
+
#define OCR1CH _SFR_MEM8(0x8D)
|
907
|
+
|
908
|
+
/* Reserved [0x8E..0x8F] */
|
909
|
+
|
910
|
+
#define TCCR3A _SFR_MEM8(0x90)
|
911
|
+
#define WGM30 0
|
912
|
+
#define WGM31 1
|
913
|
+
#define COM3C0 2
|
914
|
+
#define COM3C1 3
|
915
|
+
#define COM3B0 4
|
916
|
+
#define COM3B1 5
|
917
|
+
#define COM3A0 6
|
918
|
+
#define COM3A1 7
|
919
|
+
|
920
|
+
#define TCCR3B _SFR_MEM8(0x91)
|
921
|
+
#define CS30 0
|
922
|
+
#define CS31 1
|
923
|
+
#define CS32 2
|
924
|
+
#define WGM32 3
|
925
|
+
#define WGM33 4
|
926
|
+
#define ICES3 6
|
927
|
+
#define ICNC3 7
|
928
|
+
|
929
|
+
#define TCCR3C _SFR_MEM8(0x92)
|
930
|
+
#define FOC3C 5
|
931
|
+
#define FOC3B 6
|
932
|
+
#define FOC3A 7
|
933
|
+
|
934
|
+
/* Reserved [0x93] */
|
935
|
+
|
936
|
+
/* Combine TCNT3L and TCNT3H */
|
937
|
+
#define TCNT3 _SFR_MEM16(0x94)
|
938
|
+
|
939
|
+
#define TCNT3L _SFR_MEM8(0x94)
|
940
|
+
#define TCNT3H _SFR_MEM8(0x95)
|
941
|
+
|
942
|
+
/* Combine ICR3L and ICR3H */
|
943
|
+
#define ICR3 _SFR_MEM16(0x96)
|
944
|
+
|
945
|
+
#define ICR3L _SFR_MEM8(0x96)
|
946
|
+
#define ICR3H _SFR_MEM8(0x97)
|
947
|
+
|
948
|
+
/* Combine OCR3AL and OCR3AH */
|
949
|
+
#define OCR3A _SFR_MEM16(0x98)
|
950
|
+
|
951
|
+
#define OCR3AL _SFR_MEM8(0x98)
|
952
|
+
#define OCR3AH _SFR_MEM8(0x99)
|
953
|
+
|
954
|
+
/* Combine OCR3BL and OCR3BH */
|
955
|
+
#define OCR3B _SFR_MEM16(0x9A)
|
956
|
+
|
957
|
+
#define OCR3BL _SFR_MEM8(0x9A)
|
958
|
+
#define OCR3BH _SFR_MEM8(0x9B)
|
959
|
+
|
960
|
+
/* Combine OCR3CL and OCR3CH */
|
961
|
+
#define OCR3C _SFR_MEM16(0x9C)
|
962
|
+
|
963
|
+
#define OCR3CL _SFR_MEM8(0x9C)
|
964
|
+
#define OCR3CH _SFR_MEM8(0x9D)
|
965
|
+
|
966
|
+
/* Reserved [0x9E..0x9F] */
|
967
|
+
|
968
|
+
#define TCCR4A _SFR_MEM8(0xA0)
|
969
|
+
#define WGM40 0
|
970
|
+
#define WGM41 1
|
971
|
+
#define COM4C0 2
|
972
|
+
#define COM4C1 3
|
973
|
+
#define COM4B0 4
|
974
|
+
#define COM4B1 5
|
975
|
+
#define COM4A0 6
|
976
|
+
#define COM4A1 7
|
977
|
+
|
978
|
+
#define TCCR4B _SFR_MEM8(0xA1)
|
979
|
+
#define CS40 0
|
980
|
+
#define CS41 1
|
981
|
+
#define CS42 2
|
982
|
+
#define WGM42 3
|
983
|
+
#define WGM43 4
|
984
|
+
#define ICES4 6
|
985
|
+
#define ICNC4 7
|
986
|
+
|
987
|
+
#define TCCR4C _SFR_MEM8(0xA2)
|
988
|
+
#define FOC4C 5
|
989
|
+
#define FOC4B 6
|
990
|
+
#define FOC4A 7
|
991
|
+
|
992
|
+
/* Reserved [0xA3] */
|
993
|
+
|
994
|
+
/* Combine TCNT4L and TCNT4H */
|
995
|
+
#define TCNT4 _SFR_MEM16(0xA4)
|
996
|
+
|
997
|
+
#define TCNT4L _SFR_MEM8(0xA4)
|
998
|
+
#define TCNT4H _SFR_MEM8(0xA5)
|
999
|
+
|
1000
|
+
/* Combine ICR4L and ICR4H */
|
1001
|
+
#define ICR4 _SFR_MEM16(0xA6)
|
1002
|
+
|
1003
|
+
#define ICR4L _SFR_MEM8(0xA6)
|
1004
|
+
#define ICR4H _SFR_MEM8(0xA7)
|
1005
|
+
|
1006
|
+
/* Combine OCR4AL and OCR4AH */
|
1007
|
+
#define OCR4A _SFR_MEM16(0xA8)
|
1008
|
+
|
1009
|
+
#define OCR4AL _SFR_MEM8(0xA8)
|
1010
|
+
#define OCR4AH _SFR_MEM8(0xA9)
|
1011
|
+
|
1012
|
+
/* Combine OCR4BL and OCR4BH */
|
1013
|
+
#define OCR4B _SFR_MEM16(0xAA)
|
1014
|
+
|
1015
|
+
#define OCR4BL _SFR_MEM8(0xAA)
|
1016
|
+
#define OCR4BH _SFR_MEM8(0xAB)
|
1017
|
+
|
1018
|
+
/* Combine OCR4CL and OCR4CH */
|
1019
|
+
#define OCR4C _SFR_MEM16(0xAC)
|
1020
|
+
|
1021
|
+
#define OCR4CL _SFR_MEM8(0xAC)
|
1022
|
+
#define OCR4CH _SFR_MEM8(0xAD)
|
1023
|
+
|
1024
|
+
/* Reserved [0xAE..0xAF] */
|
1025
|
+
|
1026
|
+
#define TCCR2A _SFR_MEM8(0xB0)
|
1027
|
+
#define WGM20 0
|
1028
|
+
#define WGM21 1
|
1029
|
+
#define COM2B0 4
|
1030
|
+
#define COM2B1 5
|
1031
|
+
#define COM2A0 6
|
1032
|
+
#define COM2A1 7
|
1033
|
+
|
1034
|
+
#define TCCR2B _SFR_MEM8(0xB1)
|
1035
|
+
#define CS20 0
|
1036
|
+
#define CS21 1
|
1037
|
+
#define CS22 2
|
1038
|
+
#define WGM22 3
|
1039
|
+
#define FOC2B 6
|
1040
|
+
#define FOC2A 7
|
1041
|
+
|
1042
|
+
#define TCNT2 _SFR_MEM8(0xB2)
|
1043
|
+
|
1044
|
+
#define OCR2A _SFR_MEM8(0xB3)
|
1045
|
+
|
1046
|
+
#define OCR2B _SFR_MEM8(0xB4)
|
1047
|
+
|
1048
|
+
/* Reserved [0xB5] */
|
1049
|
+
|
1050
|
+
#define ASSR _SFR_MEM8(0xB6)
|
1051
|
+
#define TCR2BUB 0
|
1052
|
+
#define TCR2AUB 1
|
1053
|
+
#define OCR2BUB 2
|
1054
|
+
#define OCR2AUB 3
|
1055
|
+
#define TCN2UB 4
|
1056
|
+
#define AS2 5
|
1057
|
+
#define EXCLK 6
|
1058
|
+
#define EXCLKAMR 7
|
1059
|
+
|
1060
|
+
/* Reserved [0xB7] */
|
1061
|
+
|
1062
|
+
#define TWBR _SFR_MEM8(0xB8)
|
1063
|
+
|
1064
|
+
#define TWSR _SFR_MEM8(0xB9)
|
1065
|
+
#define TWPS0 0
|
1066
|
+
#define TWPS1 1
|
1067
|
+
#define TWS3 3
|
1068
|
+
#define TWS4 4
|
1069
|
+
#define TWS5 5
|
1070
|
+
#define TWS6 6
|
1071
|
+
#define TWS7 7
|
1072
|
+
|
1073
|
+
#define TWAR _SFR_MEM8(0xBA)
|
1074
|
+
#define TWGCE 0
|
1075
|
+
#define TWA0 1
|
1076
|
+
#define TWA1 2
|
1077
|
+
#define TWA2 3
|
1078
|
+
#define TWA3 4
|
1079
|
+
#define TWA4 5
|
1080
|
+
#define TWA5 6
|
1081
|
+
#define TWA6 7
|
1082
|
+
|
1083
|
+
#define TWDR _SFR_MEM8(0xBB)
|
1084
|
+
|
1085
|
+
#define TWCR _SFR_MEM8(0xBC)
|
1086
|
+
#define TWIE 0
|
1087
|
+
#define TWEN 2
|
1088
|
+
#define TWWC 3
|
1089
|
+
#define TWSTO 4
|
1090
|
+
#define TWSTA 5
|
1091
|
+
#define TWEA 6
|
1092
|
+
#define TWINT 7
|
1093
|
+
|
1094
|
+
#define TWAMR _SFR_MEM8(0xBD)
|
1095
|
+
#define TWAM0 1
|
1096
|
+
#define TWAM1 2
|
1097
|
+
#define TWAM2 3
|
1098
|
+
#define TWAM3 4
|
1099
|
+
#define TWAM4 5
|
1100
|
+
#define TWAM5 6
|
1101
|
+
#define TWAM6 7
|
1102
|
+
|
1103
|
+
#define IRQ_MASK1 _SFR_MEM8(0xBE)
|
1104
|
+
#define TX_START_EN 0
|
1105
|
+
#define MAF_0_AMI_EN 1
|
1106
|
+
#define MAF_1_AMI_EN 2
|
1107
|
+
#define MAF_2_AMI_EN 3
|
1108
|
+
#define MAF_3_AMI_EN 4
|
1109
|
+
|
1110
|
+
#define IRQ_STATUS1 _SFR_MEM8(0xBF)
|
1111
|
+
#define TX_START 0
|
1112
|
+
#define MAF_0_AMI 1
|
1113
|
+
#define MAF_1_AMI 2
|
1114
|
+
#define MAF_2_AMI 3
|
1115
|
+
#define MAF_3_AMI 4
|
1116
|
+
|
1117
|
+
#define UCSR0A _SFR_MEM8(0xC0)
|
1118
|
+
#define MPCM0 0
|
1119
|
+
#define U2X0 1
|
1120
|
+
#define UPE0 2
|
1121
|
+
#define DOR0 3
|
1122
|
+
#define FE0 4
|
1123
|
+
#define UDRE0 5
|
1124
|
+
#define TXC0 6
|
1125
|
+
#define RXC0 7
|
1126
|
+
|
1127
|
+
#define UCSR0B _SFR_MEM8(0xC1)
|
1128
|
+
#define TXB80 0
|
1129
|
+
#define RXB80 1
|
1130
|
+
#define UCSZ02 2
|
1131
|
+
#define TXEN0 3
|
1132
|
+
#define RXEN0 4
|
1133
|
+
#define UDRIE0 5
|
1134
|
+
#define TXCIE0 6
|
1135
|
+
#define RXCIE0 7
|
1136
|
+
|
1137
|
+
#define UCSR0C _SFR_MEM8(0xC2)
|
1138
|
+
#define UCPOL0 0
|
1139
|
+
#define UCSZ00 1
|
1140
|
+
#define UCSZ01 2
|
1141
|
+
#define USBS0 3
|
1142
|
+
#define UPM00 4
|
1143
|
+
#define UPM01 5
|
1144
|
+
#define UMSEL00 6
|
1145
|
+
#define UMSEL01 7
|
1146
|
+
#define UCPHA0 1
|
1147
|
+
#define UDORD0 2
|
1148
|
+
|
1149
|
+
/* Reserved [0xC3] */
|
1150
|
+
|
1151
|
+
/* Combine UBRR0L and UBRR0H */
|
1152
|
+
#define UBRR0 _SFR_MEM16(0xC4)
|
1153
|
+
|
1154
|
+
#define UBRR0L _SFR_MEM8(0xC4)
|
1155
|
+
#define UBRR0H _SFR_MEM8(0xC5)
|
1156
|
+
|
1157
|
+
#define UDR0 _SFR_MEM8(0xC6)
|
1158
|
+
|
1159
|
+
/* Reserved [0xC7] */
|
1160
|
+
|
1161
|
+
#define UCSR1A _SFR_MEM8(0xC8)
|
1162
|
+
#define MPCM1 0
|
1163
|
+
#define U2X1 1
|
1164
|
+
#define UPE1 2
|
1165
|
+
#define DOR1 3
|
1166
|
+
#define FE1 4
|
1167
|
+
#define UDRE1 5
|
1168
|
+
#define TXC1 6
|
1169
|
+
#define RXC1 7
|
1170
|
+
|
1171
|
+
#define UCSR1B _SFR_MEM8(0xC9)
|
1172
|
+
#define TXB81 0
|
1173
|
+
#define RXB81 1
|
1174
|
+
#define UCSZ12 2
|
1175
|
+
#define TXEN1 3
|
1176
|
+
#define RXEN1 4
|
1177
|
+
#define UDRIE1 5
|
1178
|
+
#define TXCIE1 6
|
1179
|
+
#define RXCIE1 7
|
1180
|
+
|
1181
|
+
#define UCSR1C _SFR_MEM8(0xCA)
|
1182
|
+
#define UCPOL1 0
|
1183
|
+
#define UCSZ10 1
|
1184
|
+
#define UCSZ11 2
|
1185
|
+
#define USBS1 3
|
1186
|
+
#define UPM10 4
|
1187
|
+
#define UPM11 5
|
1188
|
+
#define UMSEL10 6
|
1189
|
+
#define UMSEL11 7
|
1190
|
+
#define UCPHA1 1
|
1191
|
+
#define UDORD1 2
|
1192
|
+
|
1193
|
+
/* Reserved [0xCB] */
|
1194
|
+
|
1195
|
+
/* Combine UBRR1L and UBRR1H */
|
1196
|
+
#define UBRR1 _SFR_MEM16(0xCC)
|
1197
|
+
|
1198
|
+
#define UBRR1L _SFR_MEM8(0xCC)
|
1199
|
+
#define UBRR1H _SFR_MEM8(0xCD)
|
1200
|
+
|
1201
|
+
#define UDR1 _SFR_MEM8(0xCE)
|
1202
|
+
|
1203
|
+
/* Reserved [0xCF..0xD6] */
|
1204
|
+
|
1205
|
+
#define SCRSTRLL _SFR_MEM8(0xD7)
|
1206
|
+
#define SCRSTRLL0 0
|
1207
|
+
#define SCRSTRLL1 1
|
1208
|
+
#define SCRSTRLL2 2
|
1209
|
+
#define SCRSTRLL3 3
|
1210
|
+
#define SCRSTRLL4 4
|
1211
|
+
#define SCRSTRLL5 5
|
1212
|
+
#define SCRSTRLL6 6
|
1213
|
+
#define SCRSTRLL7 7
|
1214
|
+
|
1215
|
+
#define SCRSTRLH _SFR_MEM8(0xD8)
|
1216
|
+
#define SCRSTRLH0 0
|
1217
|
+
#define SCRSTRLH1 1
|
1218
|
+
#define SCRSTRLH2 2
|
1219
|
+
#define SCRSTRLH3 3
|
1220
|
+
#define SCRSTRLH4 4
|
1221
|
+
#define SCRSTRLH5 5
|
1222
|
+
#define SCRSTRLH6 6
|
1223
|
+
#define SCRSTRLH7 7
|
1224
|
+
|
1225
|
+
#define SCRSTRHL _SFR_MEM8(0xD9)
|
1226
|
+
#define SCRSTRHL0 0
|
1227
|
+
#define SCRSTRHL1 1
|
1228
|
+
#define SCRSTRHL2 2
|
1229
|
+
#define SCRSTRHL3 3
|
1230
|
+
#define SCRSTRHL4 4
|
1231
|
+
#define SCRSTRHL5 5
|
1232
|
+
#define SCRSTRHL6 6
|
1233
|
+
#define SCRSTRHL7 7
|
1234
|
+
|
1235
|
+
#define SCRSTRHH _SFR_MEM8(0xDA)
|
1236
|
+
#define SCRSTRHH0 0
|
1237
|
+
#define SCRSTRHH1 1
|
1238
|
+
#define SCRSTRHH2 2
|
1239
|
+
#define SCRSTRHH3 3
|
1240
|
+
#define SCRSTRHH4 4
|
1241
|
+
#define SCRSTRHH5 5
|
1242
|
+
#define SCRSTRHH6 6
|
1243
|
+
#define SCRSTRHH7 7
|
1244
|
+
|
1245
|
+
#define SCCSR _SFR_MEM8(0xDB)
|
1246
|
+
#define SCCS10 0
|
1247
|
+
#define SCCS11 1
|
1248
|
+
#define SCCS20 2
|
1249
|
+
#define SCCS21 3
|
1250
|
+
#define SCCS30 4
|
1251
|
+
#define SCCS31 5
|
1252
|
+
|
1253
|
+
#define SCCR0 _SFR_MEM8(0xDC)
|
1254
|
+
#define SCCMP1 0
|
1255
|
+
#define SCCMP2 1
|
1256
|
+
#define SCCMP3 2
|
1257
|
+
#define SCTSE 3
|
1258
|
+
#define SCCKSEL 4
|
1259
|
+
#define SCEN 5
|
1260
|
+
#define SCMBTS 6
|
1261
|
+
#define SCRES 7
|
1262
|
+
|
1263
|
+
#define SCCR1 _SFR_MEM8(0xDD)
|
1264
|
+
#define SCENBO 0
|
1265
|
+
#define SCEECLK 1
|
1266
|
+
#define SCCKDIV0 2
|
1267
|
+
#define SCCKDIV1 3
|
1268
|
+
#define SCCKDIV2 4
|
1269
|
+
#define SCBTSM 5
|
1270
|
+
#define Res6 7
|
1271
|
+
|
1272
|
+
#define SCSR _SFR_MEM8(0xDE)
|
1273
|
+
#define SCBSY 0
|
1274
|
+
|
1275
|
+
#define SCIRQM _SFR_MEM8(0xDF)
|
1276
|
+
#define IRQMCP1 0
|
1277
|
+
#define IRQMCP2 1
|
1278
|
+
#define IRQMCP3 2
|
1279
|
+
#define IRQMOF 3
|
1280
|
+
#define IRQMBO 4
|
1281
|
+
|
1282
|
+
#define SCIRQS _SFR_MEM8(0xE0)
|
1283
|
+
#define IRQSCP1 0
|
1284
|
+
#define IRQSCP2 1
|
1285
|
+
#define IRQSCP3 2
|
1286
|
+
#define IRQSOF 3
|
1287
|
+
#define IRQSBO 4
|
1288
|
+
|
1289
|
+
#define SCCNTLL _SFR_MEM8(0xE1)
|
1290
|
+
#define SCCNTLL0 0
|
1291
|
+
#define SCCNTLL1 1
|
1292
|
+
#define SCCNTLL2 2
|
1293
|
+
#define SCCNTLL3 3
|
1294
|
+
#define SCCNTLL4 4
|
1295
|
+
#define SCCNTLL5 5
|
1296
|
+
#define SCCNTLL6 6
|
1297
|
+
#define SCCNTLL7 7
|
1298
|
+
|
1299
|
+
#define SCCNTLH _SFR_MEM8(0xE2)
|
1300
|
+
#define SCCNTLH0 0
|
1301
|
+
#define SCCNTLH1 1
|
1302
|
+
#define SCCNTLH2 2
|
1303
|
+
#define SCCNTLH3 3
|
1304
|
+
#define SCCNTLH4 4
|
1305
|
+
#define SCCNTLH5 5
|
1306
|
+
#define SCCNTLH6 6
|
1307
|
+
#define SCCNTLH7 7
|
1308
|
+
|
1309
|
+
#define SCCNTHL _SFR_MEM8(0xE3)
|
1310
|
+
#define SCCNTHL0 0
|
1311
|
+
#define SCCNTHL1 1
|
1312
|
+
#define SCCNTHL2 2
|
1313
|
+
#define SCCNTHL3 3
|
1314
|
+
#define SCCNTHL4 4
|
1315
|
+
#define SCCNTHL5 5
|
1316
|
+
#define SCCNTHL6 6
|
1317
|
+
#define SCCNTHL7 7
|
1318
|
+
|
1319
|
+
#define SCCNTHH _SFR_MEM8(0xE4)
|
1320
|
+
#define SCCNTHH0 0
|
1321
|
+
#define SCCNTHH1 1
|
1322
|
+
#define SCCNTHH2 2
|
1323
|
+
#define SCCNTHH3 3
|
1324
|
+
#define SCCNTHH4 4
|
1325
|
+
#define SCCNTHH5 5
|
1326
|
+
#define SCCNTHH6 6
|
1327
|
+
#define SCCNTHH7 7
|
1328
|
+
|
1329
|
+
#define SCBTSRLL _SFR_MEM8(0xE5)
|
1330
|
+
#define SCBTSRLL0 0
|
1331
|
+
#define SCBTSRLL1 1
|
1332
|
+
#define SCBTSRLL2 2
|
1333
|
+
#define SCBTSRLL3 3
|
1334
|
+
#define SCBTSRLL4 4
|
1335
|
+
#define SCBTSRLL5 5
|
1336
|
+
#define SCBTSRLL6 6
|
1337
|
+
#define SCBTSRLL7 7
|
1338
|
+
|
1339
|
+
#define SCBTSRLH _SFR_MEM8(0xE6)
|
1340
|
+
#define SCBTSRLH0 0
|
1341
|
+
#define SCBTSRLH1 1
|
1342
|
+
#define SCBTSRLH2 2
|
1343
|
+
#define SCBTSRLH3 3
|
1344
|
+
#define SCBTSRLH4 4
|
1345
|
+
#define SCBTSRLH5 5
|
1346
|
+
#define SCBTSRLH6 6
|
1347
|
+
#define SCBTSRLH7 7
|
1348
|
+
|
1349
|
+
#define SCBTSRHL _SFR_MEM8(0xE7)
|
1350
|
+
#define SCBTSRHL0 0
|
1351
|
+
#define SCBTSRHL1 1
|
1352
|
+
#define SCBTSRHL2 2
|
1353
|
+
#define SCBTSRHL3 3
|
1354
|
+
#define SCBTSRHL4 4
|
1355
|
+
#define SCBTSRHL5 5
|
1356
|
+
#define SCBTSRHL6 6
|
1357
|
+
#define SCBTSRHL7 7
|
1358
|
+
|
1359
|
+
#define SCBTSRHH _SFR_MEM8(0xE8)
|
1360
|
+
#define SCBTSRHH0 0
|
1361
|
+
#define SCBTSRHH1 1
|
1362
|
+
#define SCBTSRHH2 2
|
1363
|
+
#define SCBTSRHH3 3
|
1364
|
+
#define SCBTSRHH4 4
|
1365
|
+
#define SCBTSRHH5 5
|
1366
|
+
#define SCBTSRHH6 6
|
1367
|
+
#define SCBTSRHH7 7
|
1368
|
+
|
1369
|
+
#define SCTSRLL _SFR_MEM8(0xE9)
|
1370
|
+
#define SCTSRLL0 0
|
1371
|
+
#define SCTSRLL1 1
|
1372
|
+
#define SCTSRLL2 2
|
1373
|
+
#define SCTSRLL3 3
|
1374
|
+
#define SCTSRLL4 4
|
1375
|
+
#define SCTSRLL5 5
|
1376
|
+
#define SCTSRLL6 6
|
1377
|
+
#define SCTSRLL7 7
|
1378
|
+
|
1379
|
+
#define SCTSRLH _SFR_MEM8(0xEA)
|
1380
|
+
#define SCTSRLH0 0
|
1381
|
+
#define SCTSRLH1 1
|
1382
|
+
#define SCTSRLH2 2
|
1383
|
+
#define SCTSRLH3 3
|
1384
|
+
#define SCTSRLH4 4
|
1385
|
+
#define SCTSRLH5 5
|
1386
|
+
#define SCTSRLH6 6
|
1387
|
+
#define SCTSRLH7 7
|
1388
|
+
|
1389
|
+
#define SCTSRHL _SFR_MEM8(0xEB)
|
1390
|
+
#define SCTSRHL0 0
|
1391
|
+
#define SCTSRHL1 1
|
1392
|
+
#define SCTSRHL2 2
|
1393
|
+
#define SCTSRHL3 3
|
1394
|
+
#define SCTSRHL4 4
|
1395
|
+
#define SCTSRHL5 5
|
1396
|
+
#define SCTSRHL6 6
|
1397
|
+
#define SCTSRHL7 7
|
1398
|
+
|
1399
|
+
#define SCTSRHH _SFR_MEM8(0xEC)
|
1400
|
+
#define SCTSRHH0 0
|
1401
|
+
#define SCTSRHH1 1
|
1402
|
+
#define SCTSRHH2 2
|
1403
|
+
#define SCTSRHH3 3
|
1404
|
+
#define SCTSRHH4 4
|
1405
|
+
#define SCTSRHH5 5
|
1406
|
+
#define SCTSRHH6 6
|
1407
|
+
#define SCTSRHH7 7
|
1408
|
+
|
1409
|
+
#define SCOCR3LL _SFR_MEM8(0xED)
|
1410
|
+
#define SCOCR3LL0 0
|
1411
|
+
#define SCOCR3LL1 1
|
1412
|
+
#define SCOCR3LL2 2
|
1413
|
+
#define SCOCR3LL3 3
|
1414
|
+
#define SCOCR3LL4 4
|
1415
|
+
#define SCOCR3LL5 5
|
1416
|
+
#define SCOCR3LL6 6
|
1417
|
+
#define SCOCR3LL7 7
|
1418
|
+
|
1419
|
+
#define SCOCR3LH _SFR_MEM8(0xEE)
|
1420
|
+
#define SCOCR3LH0 0
|
1421
|
+
#define SCOCR3LH1 1
|
1422
|
+
#define SCOCR3LH2 2
|
1423
|
+
#define SCOCR3LH3 3
|
1424
|
+
#define SCOCR3LH4 4
|
1425
|
+
#define SCOCR3LH5 5
|
1426
|
+
#define SCOCR3LH6 6
|
1427
|
+
#define SCOCR3LH7 7
|
1428
|
+
|
1429
|
+
#define SCOCR3HL _SFR_MEM8(0xEF)
|
1430
|
+
#define SCOCR3HL0 0
|
1431
|
+
#define SCOCR3HL1 1
|
1432
|
+
#define SCOCR3HL2 2
|
1433
|
+
#define SCOCR3HL3 3
|
1434
|
+
#define SCOCR3HL4 4
|
1435
|
+
#define SCOCR3HL5 5
|
1436
|
+
#define SCOCR3HL6 6
|
1437
|
+
#define SCOCR3HL7 7
|
1438
|
+
|
1439
|
+
#define SCOCR3HH _SFR_MEM8(0xF0)
|
1440
|
+
#define SCOCR3HH0 0
|
1441
|
+
#define SCOCR3HH1 1
|
1442
|
+
#define SCOCR3HH2 2
|
1443
|
+
#define SCOCR3HH3 3
|
1444
|
+
#define SCOCR3HH4 4
|
1445
|
+
#define SCOCR3HH5 5
|
1446
|
+
#define SCOCR3HH6 6
|
1447
|
+
#define SCOCR3HH7 7
|
1448
|
+
|
1449
|
+
#define SCOCR2LL _SFR_MEM8(0xF1)
|
1450
|
+
#define SCOCR2LL0 0
|
1451
|
+
#define SCOCR2LL1 1
|
1452
|
+
#define SCOCR2LL2 2
|
1453
|
+
#define SCOCR2LL3 3
|
1454
|
+
#define SCOCR2LL4 4
|
1455
|
+
#define SCOCR2LL5 5
|
1456
|
+
#define SCOCR2LL6 6
|
1457
|
+
#define SCOCR2LL7 7
|
1458
|
+
|
1459
|
+
#define SCOCR2LH _SFR_MEM8(0xF2)
|
1460
|
+
#define SCOCR2LH0 0
|
1461
|
+
#define SCOCR2LH1 1
|
1462
|
+
#define SCOCR2LH2 2
|
1463
|
+
#define SCOCR2LH3 3
|
1464
|
+
#define SCOCR2LH4 4
|
1465
|
+
#define SCOCR2LH5 5
|
1466
|
+
#define SCOCR2LH6 6
|
1467
|
+
#define SCOCR2LH7 7
|
1468
|
+
|
1469
|
+
#define SCOCR2HL _SFR_MEM8(0xF3)
|
1470
|
+
#define SCOCR2HL0 0
|
1471
|
+
#define SCOCR2HL1 1
|
1472
|
+
#define SCOCR2HL2 2
|
1473
|
+
#define SCOCR2HL3 3
|
1474
|
+
#define SCOCR2HL4 4
|
1475
|
+
#define SCOCR2HL5 5
|
1476
|
+
#define SCOCR2HL6 6
|
1477
|
+
#define SCOCR2HL7 7
|
1478
|
+
|
1479
|
+
#define SCOCR2HH _SFR_MEM8(0xF4)
|
1480
|
+
#define SCOCR2HH0 0
|
1481
|
+
#define SCOCR2HH1 1
|
1482
|
+
#define SCOCR2HH2 2
|
1483
|
+
#define SCOCR2HH3 3
|
1484
|
+
#define SCOCR2HH4 4
|
1485
|
+
#define SCOCR2HH5 5
|
1486
|
+
#define SCOCR2HH6 6
|
1487
|
+
#define SCOCR2HH7 7
|
1488
|
+
|
1489
|
+
#define SCOCR1LL _SFR_MEM8(0xF5)
|
1490
|
+
#define SCOCR1LL0 0
|
1491
|
+
#define SCOCR1LL1 1
|
1492
|
+
#define SCOCR1LL2 2
|
1493
|
+
#define SCOCR1LL3 3
|
1494
|
+
#define SCOCR1LL4 4
|
1495
|
+
#define SCOCR1LL5 5
|
1496
|
+
#define SCOCR1LL6 6
|
1497
|
+
#define SCOCR1LL7 7
|
1498
|
+
|
1499
|
+
#define SCOCR1LH _SFR_MEM8(0xF6)
|
1500
|
+
#define SCOCR1LH0 0
|
1501
|
+
#define SCOCR1LH1 1
|
1502
|
+
#define SCOCR1LH2 2
|
1503
|
+
#define SCOCR1LH3 3
|
1504
|
+
#define SCOCR1LH4 4
|
1505
|
+
#define SCOCR1LH5 5
|
1506
|
+
#define SCOCR1LH6 6
|
1507
|
+
#define SCOCR1LH7 7
|
1508
|
+
|
1509
|
+
#define SCOCR1HL _SFR_MEM8(0xF7)
|
1510
|
+
#define SCOCR1HL0 0
|
1511
|
+
#define SCOCR1HL1 1
|
1512
|
+
#define SCOCR1HL2 2
|
1513
|
+
#define SCOCR1HL3 3
|
1514
|
+
#define SCOCR1HL4 4
|
1515
|
+
#define SCOCR1HL5 5
|
1516
|
+
#define SCOCR1HL6 6
|
1517
|
+
#define SCOCR1HL7 7
|
1518
|
+
|
1519
|
+
#define SCOCR1HH _SFR_MEM8(0xF8)
|
1520
|
+
#define SCOCR1HH0 0
|
1521
|
+
#define SCOCR1HH1 1
|
1522
|
+
#define SCOCR1HH2 2
|
1523
|
+
#define SCOCR1HH3 3
|
1524
|
+
#define SCOCR1HH4 4
|
1525
|
+
#define SCOCR1HH5 5
|
1526
|
+
#define SCOCR1HH6 6
|
1527
|
+
#define SCOCR1HH7 7
|
1528
|
+
|
1529
|
+
#define SCTSTRLL _SFR_MEM8(0xF9)
|
1530
|
+
#define SCTSTRLL0 0
|
1531
|
+
#define SCTSTRLL1 1
|
1532
|
+
#define SCTSTRLL2 2
|
1533
|
+
#define SCTSTRLL3 3
|
1534
|
+
#define SCTSTRLL4 4
|
1535
|
+
#define SCTSTRLL5 5
|
1536
|
+
#define SCTSTRLL6 6
|
1537
|
+
#define SCTSTRLL7 7
|
1538
|
+
|
1539
|
+
#define SCTSTRLH _SFR_MEM8(0xFA)
|
1540
|
+
#define SCTSTRLH0 0
|
1541
|
+
#define SCTSTRLH1 1
|
1542
|
+
#define SCTSTRLH2 2
|
1543
|
+
#define SCTSTRLH3 3
|
1544
|
+
#define SCTSTRLH4 4
|
1545
|
+
#define SCTSTRLH5 5
|
1546
|
+
#define SCTSTRLH6 6
|
1547
|
+
#define SCTSTRLH7 7
|
1548
|
+
|
1549
|
+
#define SCTSTRHL _SFR_MEM8(0xFB)
|
1550
|
+
#define SCTSTRHL0 0
|
1551
|
+
#define SCTSTRHL1 1
|
1552
|
+
#define SCTSTRHL2 2
|
1553
|
+
#define SCTSTRHL3 3
|
1554
|
+
#define SCTSTRHL4 4
|
1555
|
+
#define SCTSTRHL5 5
|
1556
|
+
#define SCTSTRHL6 6
|
1557
|
+
#define SCTSTRHL7 7
|
1558
|
+
|
1559
|
+
#define SCTSTRHH _SFR_MEM8(0xFC)
|
1560
|
+
#define SCTSTRHH0 0
|
1561
|
+
#define SCTSTRHH1 1
|
1562
|
+
#define SCTSTRHH2 2
|
1563
|
+
#define SCTSTRHH3 3
|
1564
|
+
#define SCTSTRHH4 4
|
1565
|
+
#define SCTSTRHH5 5
|
1566
|
+
#define SCTSTRHH6 6
|
1567
|
+
#define SCTSTRHH7 7
|
1568
|
+
|
1569
|
+
/* Reserved [0xFD..0x10B] */
|
1570
|
+
|
1571
|
+
#define MAFCR0 _SFR_MEM8(0x10C)
|
1572
|
+
#define MAF0EN 0
|
1573
|
+
#define MAF1EN 1
|
1574
|
+
#define MAF2EN 2
|
1575
|
+
#define MAF3EN 3
|
1576
|
+
|
1577
|
+
#define MAFCR1 _SFR_MEM8(0x10D)
|
1578
|
+
#define AACK_0_I_AM_COORD 0
|
1579
|
+
#define AACK_0_SET_PD 1
|
1580
|
+
#define AACK_1_I_AM_COORD 2
|
1581
|
+
#define AACK_1_SET_PD 3
|
1582
|
+
#define AACK_2_I_AM_COORD 4
|
1583
|
+
#define AACK_2_SET_PD 5
|
1584
|
+
#define AACK_3_I_AM_COORD 6
|
1585
|
+
#define AACK_3_SET_PD 7
|
1586
|
+
|
1587
|
+
#define MAFSA0L _SFR_MEM8(0x10E)
|
1588
|
+
#define MAFSA0L0 0
|
1589
|
+
#define MAFSA0L1 1
|
1590
|
+
#define MAFSA0L2 2
|
1591
|
+
#define MAFSA0L3 3
|
1592
|
+
#define MAFSA0L4 4
|
1593
|
+
#define MAFSA0L5 5
|
1594
|
+
#define MAFSA0L6 6
|
1595
|
+
#define MAFSA0L7 7
|
1596
|
+
|
1597
|
+
#define MAFSA0H _SFR_MEM8(0x10F)
|
1598
|
+
#define MAFSA0H0 0
|
1599
|
+
#define MAFSA0H1 1
|
1600
|
+
#define MAFSA0H2 2
|
1601
|
+
#define MAFSA0H3 3
|
1602
|
+
#define MAFSA0H4 4
|
1603
|
+
#define MAFSA0H5 5
|
1604
|
+
#define MAFSA0H6 6
|
1605
|
+
#define MAFSA0H7 7
|
1606
|
+
|
1607
|
+
#define MAFPA0L _SFR_MEM8(0x110)
|
1608
|
+
#define MAFPA0L0 0
|
1609
|
+
#define MAFPA0L1 1
|
1610
|
+
#define MAFPA0L2 2
|
1611
|
+
#define MAFPA0L3 3
|
1612
|
+
#define MAFPA0L4 4
|
1613
|
+
#define MAFPA0L5 5
|
1614
|
+
#define MAFPA0L6 6
|
1615
|
+
#define MAFPA0L7 7
|
1616
|
+
|
1617
|
+
#define MAFPA0H _SFR_MEM8(0x111)
|
1618
|
+
#define MAFPA0H0 0
|
1619
|
+
#define MAFPA0H1 1
|
1620
|
+
#define MAFPA0H2 2
|
1621
|
+
#define MAFPA0H3 3
|
1622
|
+
#define MAFPA0H4 4
|
1623
|
+
#define MAFPA0H5 5
|
1624
|
+
#define MAFPA0H6 6
|
1625
|
+
#define MAFPA0H7 7
|
1626
|
+
|
1627
|
+
#define MAFSA1L _SFR_MEM8(0x112)
|
1628
|
+
#define MAFSA1L0 0
|
1629
|
+
#define MAFSA1L1 1
|
1630
|
+
#define MAFSA1L2 2
|
1631
|
+
#define MAFSA1L3 3
|
1632
|
+
#define MAFSA1L4 4
|
1633
|
+
#define MAFSA1L5 5
|
1634
|
+
#define MAFSA1L6 6
|
1635
|
+
#define MAFSA1L7 7
|
1636
|
+
|
1637
|
+
#define MAFSA1H _SFR_MEM8(0x113)
|
1638
|
+
#define MAFSA1H0 0
|
1639
|
+
#define MAFSA1H1 1
|
1640
|
+
#define MAFSA1H2 2
|
1641
|
+
#define MAFSA1H3 3
|
1642
|
+
#define MAFSA1H4 4
|
1643
|
+
#define MAFSA1H5 5
|
1644
|
+
#define MAFSA1H6 6
|
1645
|
+
#define MAFSA1H7 7
|
1646
|
+
|
1647
|
+
#define MAFPA1L _SFR_MEM8(0x114)
|
1648
|
+
#define MAFPA1L0 0
|
1649
|
+
#define MAFPA1L1 1
|
1650
|
+
#define MAFPA1L2 2
|
1651
|
+
#define MAFPA1L3 3
|
1652
|
+
#define MAFPA1L4 4
|
1653
|
+
#define MAFPA1L5 5
|
1654
|
+
#define MAFPA1L6 6
|
1655
|
+
#define MAFPA1L7 7
|
1656
|
+
|
1657
|
+
#define MAFPA1H _SFR_MEM8(0x115)
|
1658
|
+
#define MAFPA1H0 0
|
1659
|
+
#define MAFPA1H1 1
|
1660
|
+
#define MAFPA1H2 2
|
1661
|
+
#define MAFPA1H3 3
|
1662
|
+
#define MAFPA1H4 4
|
1663
|
+
#define MAFPA1H5 5
|
1664
|
+
#define MAFPA1H6 6
|
1665
|
+
#define MAFPA1H7 7
|
1666
|
+
|
1667
|
+
#define MAFSA2L _SFR_MEM8(0x116)
|
1668
|
+
#define MAFSA2L0 0
|
1669
|
+
#define MAFSA2L1 1
|
1670
|
+
#define MAFSA2L2 2
|
1671
|
+
#define MAFSA2L3 3
|
1672
|
+
#define MAFSA2L4 4
|
1673
|
+
#define MAFSA2L5 5
|
1674
|
+
#define MAFSA2L6 6
|
1675
|
+
#define MAFSA2L7 7
|
1676
|
+
|
1677
|
+
#define MAFSA2H _SFR_MEM8(0x117)
|
1678
|
+
#define MAFSA2H0 0
|
1679
|
+
#define MAFSA2H1 1
|
1680
|
+
#define MAFSA2H2 2
|
1681
|
+
#define MAFSA2H3 3
|
1682
|
+
#define MAFSA2H4 4
|
1683
|
+
#define MAFSA2H5 5
|
1684
|
+
#define MAFSA2H6 6
|
1685
|
+
#define MAFSA2H7 7
|
1686
|
+
|
1687
|
+
#define MAFPA2L _SFR_MEM8(0x118)
|
1688
|
+
#define MAFPA2L0 0
|
1689
|
+
#define MAFPA2L1 1
|
1690
|
+
#define MAFPA2L2 2
|
1691
|
+
#define MAFPA2L3 3
|
1692
|
+
#define MAFPA2L4 4
|
1693
|
+
#define MAFPA2L5 5
|
1694
|
+
#define MAFPA2L6 6
|
1695
|
+
#define MAFPA2L7 7
|
1696
|
+
|
1697
|
+
#define MAFPA2H _SFR_MEM8(0x119)
|
1698
|
+
#define MAFPA2H0 0
|
1699
|
+
#define MAFPA2H1 1
|
1700
|
+
#define MAFPA2H2 2
|
1701
|
+
#define MAFPA2H3 3
|
1702
|
+
#define MAFPA2H4 4
|
1703
|
+
#define MAFPA2H5 5
|
1704
|
+
#define MAFPA2H6 6
|
1705
|
+
#define MAFPA2H7 7
|
1706
|
+
|
1707
|
+
#define MAFSA3L _SFR_MEM8(0x11A)
|
1708
|
+
#define MAFSA3L0 0
|
1709
|
+
#define MAFSA3L1 1
|
1710
|
+
#define MAFSA3L2 2
|
1711
|
+
#define MAFSA3L3 3
|
1712
|
+
#define MAFSA3L4 4
|
1713
|
+
#define MAFSA3L5 5
|
1714
|
+
#define MAFSA3L6 6
|
1715
|
+
#define MAFSA3L7 7
|
1716
|
+
|
1717
|
+
#define MAFSA3H _SFR_MEM8(0x11B)
|
1718
|
+
#define MAFSA3H0 0
|
1719
|
+
#define MAFSA3H1 1
|
1720
|
+
#define MAFSA3H2 2
|
1721
|
+
#define MAFSA3H3 3
|
1722
|
+
#define MAFSA3H4 4
|
1723
|
+
#define MAFSA3H5 5
|
1724
|
+
#define MAFSA3H6 6
|
1725
|
+
#define MAFSA3H7 7
|
1726
|
+
|
1727
|
+
#define MAFPA3L _SFR_MEM8(0x11C)
|
1728
|
+
#define MAFPA3L0 0
|
1729
|
+
#define MAFPA3L1 1
|
1730
|
+
#define MAFPA3L2 2
|
1731
|
+
#define MAFPA3L3 3
|
1732
|
+
#define MAFPA3L4 4
|
1733
|
+
#define MAFPA3L5 5
|
1734
|
+
#define MAFPA3L6 6
|
1735
|
+
#define MAFPA3L7 7
|
1736
|
+
|
1737
|
+
#define MAFPA3H _SFR_MEM8(0x11D)
|
1738
|
+
#define MAFPA3H0 0
|
1739
|
+
#define MAFPA3H1 1
|
1740
|
+
#define MAFPA3H2 2
|
1741
|
+
#define MAFPA3H3 3
|
1742
|
+
#define MAFPA3H4 4
|
1743
|
+
#define MAFPA3H5 5
|
1744
|
+
#define MAFPA3H6 6
|
1745
|
+
#define MAFPA3H7 7
|
1746
|
+
|
1747
|
+
/* Reserved [0x11E..0x11F] */
|
1748
|
+
|
1749
|
+
#define TCCR5A _SFR_MEM8(0x120)
|
1750
|
+
#define WGM50 0
|
1751
|
+
#define WGM51 1
|
1752
|
+
#define COM5C0 2
|
1753
|
+
#define COM5C1 3
|
1754
|
+
#define COM5B0 4
|
1755
|
+
#define COM5B1 5
|
1756
|
+
#define COM5A0 6
|
1757
|
+
#define COM5A1 7
|
1758
|
+
|
1759
|
+
#define TCCR5B _SFR_MEM8(0x121)
|
1760
|
+
#define CS50 0
|
1761
|
+
#define CS51 1
|
1762
|
+
#define CS52 2
|
1763
|
+
#define WGM52 3
|
1764
|
+
#define WGM53 4
|
1765
|
+
#define ICES5 6
|
1766
|
+
#define ICNC5 7
|
1767
|
+
|
1768
|
+
#define TCCR5C _SFR_MEM8(0x122)
|
1769
|
+
#define FOC5C 5
|
1770
|
+
#define FOC5B 6
|
1771
|
+
#define FOC5A 7
|
1772
|
+
|
1773
|
+
/* Reserved [0x123] */
|
1774
|
+
|
1775
|
+
/* Combine TCNT5L and TCNT5H */
|
1776
|
+
#define TCNT5 _SFR_MEM16(0x124)
|
1777
|
+
|
1778
|
+
#define TCNT5L _SFR_MEM8(0x124)
|
1779
|
+
#define TCNT5H _SFR_MEM8(0x125)
|
1780
|
+
|
1781
|
+
/* Combine ICR5L and ICR5H */
|
1782
|
+
#define ICR5 _SFR_MEM16(0x126)
|
1783
|
+
|
1784
|
+
#define ICR5L _SFR_MEM8(0x126)
|
1785
|
+
#define ICR5H _SFR_MEM8(0x127)
|
1786
|
+
|
1787
|
+
/* Combine OCR5AL and OCR5AH */
|
1788
|
+
#define OCR5A _SFR_MEM16(0x128)
|
1789
|
+
|
1790
|
+
#define OCR5AL _SFR_MEM8(0x128)
|
1791
|
+
#define OCR5AH _SFR_MEM8(0x129)
|
1792
|
+
|
1793
|
+
/* Combine OCR5BL and OCR5BH */
|
1794
|
+
#define OCR5B _SFR_MEM16(0x12A)
|
1795
|
+
|
1796
|
+
#define OCR5BL _SFR_MEM8(0x12A)
|
1797
|
+
#define OCR5BH _SFR_MEM8(0x12B)
|
1798
|
+
|
1799
|
+
/* Combine OCR5CL and OCR5CH */
|
1800
|
+
#define OCR5C _SFR_MEM16(0x12C)
|
1801
|
+
|
1802
|
+
#define OCR5CL _SFR_MEM8(0x12C)
|
1803
|
+
#define OCR5CH _SFR_MEM8(0x12D)
|
1804
|
+
|
1805
|
+
/* Reserved [0x12E] */
|
1806
|
+
|
1807
|
+
#define LLCR _SFR_MEM8(0x12F)
|
1808
|
+
#define LLENCAL 0
|
1809
|
+
#define LLSHORT 1
|
1810
|
+
#define LLTCO 2
|
1811
|
+
#define LLCAL 3
|
1812
|
+
#define LLCOMP 4
|
1813
|
+
#define LLDONE 5
|
1814
|
+
|
1815
|
+
#define LLDRL _SFR_MEM8(0x130)
|
1816
|
+
#define LLDRL0 0
|
1817
|
+
#define LLDRL1 1
|
1818
|
+
#define LLDRL2 2
|
1819
|
+
#define LLDRL3 3
|
1820
|
+
|
1821
|
+
#define LLDRH _SFR_MEM8(0x131)
|
1822
|
+
#define LLDRH0 0
|
1823
|
+
#define LLDRH1 1
|
1824
|
+
#define LLDRH2 2
|
1825
|
+
#define LLDRH3 3
|
1826
|
+
#define LLDRH4 4
|
1827
|
+
|
1828
|
+
#define DRTRAM3 _SFR_MEM8(0x132)
|
1829
|
+
#define ENDRT 4
|
1830
|
+
#define DRTSWOK 5
|
1831
|
+
|
1832
|
+
#define DRTRAM2 _SFR_MEM8(0x133)
|
1833
|
+
|
1834
|
+
#define DRTRAM1 _SFR_MEM8(0x134)
|
1835
|
+
|
1836
|
+
#define DRTRAM0 _SFR_MEM8(0x135)
|
1837
|
+
|
1838
|
+
#define DPDS0 _SFR_MEM8(0x136)
|
1839
|
+
#define PBDRV0 0
|
1840
|
+
#define PBDRV1 1
|
1841
|
+
#define PDDRV0 2
|
1842
|
+
#define PDDRV1 3
|
1843
|
+
#define PEDRV0 4
|
1844
|
+
#define PEDRV1 5
|
1845
|
+
#define PFDRV0 6
|
1846
|
+
#define PFDRV1 7
|
1847
|
+
|
1848
|
+
#define DPDS1 _SFR_MEM8(0x137)
|
1849
|
+
#define PGDRV0 0
|
1850
|
+
#define PGDRV1 1
|
1851
|
+
|
1852
|
+
#define PARCR _SFR_MEM8(0x138)
|
1853
|
+
#define PARUFI 0
|
1854
|
+
#define PARDFI 1
|
1855
|
+
#define PALTU0 2
|
1856
|
+
#define PALTU1 3
|
1857
|
+
#define PALTU2 4
|
1858
|
+
#define PALTD0 5
|
1859
|
+
#define PALTD1 6
|
1860
|
+
#define PALTD2 7
|
1861
|
+
|
1862
|
+
#define TRXPR _SFR_MEM8(0x139)
|
1863
|
+
#define TRXRST 0
|
1864
|
+
#define SLPTR 1
|
1865
|
+
|
1866
|
+
/* Reserved [0x13A..0x13B] */
|
1867
|
+
|
1868
|
+
#define AES_CTRL _SFR_MEM8(0x13C)
|
1869
|
+
#define AES_IM 2
|
1870
|
+
#define AES_DIR 3
|
1871
|
+
#define AES_MODE 5
|
1872
|
+
#define AES_REQUEST 7
|
1873
|
+
|
1874
|
+
#define AES_STATUS _SFR_MEM8(0x13D)
|
1875
|
+
#define AES_DONE 0
|
1876
|
+
#define AES_ER 7
|
1877
|
+
|
1878
|
+
#define AES_STATE _SFR_MEM8(0x13E)
|
1879
|
+
#define AES_STATE0 0
|
1880
|
+
#define AES_STATE1 1
|
1881
|
+
#define AES_STATE2 2
|
1882
|
+
#define AES_STATE3 3
|
1883
|
+
#define AES_STATE4 4
|
1884
|
+
#define AES_STATE5 5
|
1885
|
+
#define AES_STATE6 6
|
1886
|
+
#define AES_STATE7 7
|
1887
|
+
|
1888
|
+
#define AES_KEY _SFR_MEM8(0x13F)
|
1889
|
+
#define AES_KEY0 0
|
1890
|
+
#define AES_KEY1 1
|
1891
|
+
#define AES_KEY2 2
|
1892
|
+
#define AES_KEY3 3
|
1893
|
+
#define AES_KEY4 4
|
1894
|
+
#define AES_KEY5 5
|
1895
|
+
#define AES_KEY6 6
|
1896
|
+
#define AES_KEY7 7
|
1897
|
+
|
1898
|
+
/* Reserved [0x140] */
|
1899
|
+
|
1900
|
+
#define TRX_STATUS _SFR_MEM8(0x141)
|
1901
|
+
#define TRX_STATUS0 0
|
1902
|
+
#define TRX_STATUS1 1
|
1903
|
+
#define TRX_STATUS2 2
|
1904
|
+
#define TRX_STATUS3 3
|
1905
|
+
#define TRX_STATUS4 4
|
1906
|
+
#define TST_STATUS 5
|
1907
|
+
#define CCA_STATUS 6
|
1908
|
+
#define CCA_DONE 7
|
1909
|
+
|
1910
|
+
#define TRX_STATE _SFR_MEM8(0x142)
|
1911
|
+
#define TRX_CMD0 0
|
1912
|
+
#define TRX_CMD1 1
|
1913
|
+
#define TRX_CMD2 2
|
1914
|
+
#define TRX_CMD3 3
|
1915
|
+
#define TRX_CMD4 4
|
1916
|
+
#define TRAC_STATUS0 5
|
1917
|
+
#define TRAC_STATUS1 6
|
1918
|
+
#define TRAC_STATUS2 7
|
1919
|
+
|
1920
|
+
#define TRX_CTRL_0 _SFR_MEM8(0x143)
|
1921
|
+
#define PMU_IF_INV 4
|
1922
|
+
#define PMU_START 5
|
1923
|
+
#define PMU_EN 6
|
1924
|
+
#define Res7 7
|
1925
|
+
|
1926
|
+
#define TRX_CTRL_1 _SFR_MEM8(0x144)
|
1927
|
+
#define PLL_TX_FLT 4
|
1928
|
+
#define TX_AUTO_CRC_ON 5
|
1929
|
+
#define IRQ_2_EXT_EN 6
|
1930
|
+
#define PA_EXT_EN 7
|
1931
|
+
|
1932
|
+
#define PHY_TX_PWR _SFR_MEM8(0x145)
|
1933
|
+
#define TX_PWR0 0
|
1934
|
+
#define TX_PWR1 1
|
1935
|
+
#define TX_PWR2 2
|
1936
|
+
#define TX_PWR3 3
|
1937
|
+
|
1938
|
+
#define PHY_RSSI _SFR_MEM8(0x146)
|
1939
|
+
#define RSSI0 0
|
1940
|
+
#define RSSI1 1
|
1941
|
+
#define RSSI2 2
|
1942
|
+
#define RSSI3 3
|
1943
|
+
#define RSSI4 4
|
1944
|
+
#define RND_VALUE0 5
|
1945
|
+
#define RND_VALUE1 6
|
1946
|
+
#define RX_CRC_VALID 7
|
1947
|
+
|
1948
|
+
#define PHY_ED_LEVEL _SFR_MEM8(0x147)
|
1949
|
+
#define ED_LEVEL0 0
|
1950
|
+
#define ED_LEVEL1 1
|
1951
|
+
#define ED_LEVEL2 2
|
1952
|
+
#define ED_LEVEL3 3
|
1953
|
+
#define ED_LEVEL4 4
|
1954
|
+
#define ED_LEVEL5 5
|
1955
|
+
#define ED_LEVEL6 6
|
1956
|
+
#define ED_LEVEL7 7
|
1957
|
+
|
1958
|
+
#define PHY_CC_CCA _SFR_MEM8(0x148)
|
1959
|
+
#define CHANNEL0 0
|
1960
|
+
#define CHANNEL1 1
|
1961
|
+
#define CHANNEL2 2
|
1962
|
+
#define CHANNEL3 3
|
1963
|
+
#define CHANNEL4 4
|
1964
|
+
#define CCA_MODE0 5
|
1965
|
+
#define CCA_MODE1 6
|
1966
|
+
#define CCA_REQUEST 7
|
1967
|
+
|
1968
|
+
#define CCA_THRES _SFR_MEM8(0x149)
|
1969
|
+
#define CCA_ED_THRES0 0
|
1970
|
+
#define CCA_ED_THRES1 1
|
1971
|
+
#define CCA_ED_THRES2 2
|
1972
|
+
#define CCA_ED_THRES3 3
|
1973
|
+
#define CCA_CS_THRES0 4
|
1974
|
+
#define CCA_CS_THRES1 5
|
1975
|
+
#define CCA_CS_THRES2 6
|
1976
|
+
#define CCA_CS_THRES3 7
|
1977
|
+
|
1978
|
+
#define RX_CTRL _SFR_MEM8(0x14A)
|
1979
|
+
#define PDT_THRES0 0
|
1980
|
+
#define PDT_THRES1 1
|
1981
|
+
#define PDT_THRES2 2
|
1982
|
+
#define PDT_THRES3 3
|
1983
|
+
|
1984
|
+
#define SFD_VALUE _SFR_MEM8(0x14B)
|
1985
|
+
#define SFD_VALUE0 0
|
1986
|
+
#define SFD_VALUE1 1
|
1987
|
+
#define SFD_VALUE2 2
|
1988
|
+
#define SFD_VALUE3 3
|
1989
|
+
#define SFD_VALUE4 4
|
1990
|
+
#define SFD_VALUE5 5
|
1991
|
+
#define SFD_VALUE6 6
|
1992
|
+
#define SFD_VALUE7 7
|
1993
|
+
|
1994
|
+
#define TRX_CTRL_2 _SFR_MEM8(0x14C)
|
1995
|
+
#define OQPSK_DATA_RATE0 0
|
1996
|
+
#define OQPSK_DATA_RATE1 1
|
1997
|
+
#define RX_SAFE_MODE 7
|
1998
|
+
|
1999
|
+
#define ANT_DIV _SFR_MEM8(0x14D)
|
2000
|
+
#define ANT_CTRL0 0
|
2001
|
+
#define ANT_CTRL1 1
|
2002
|
+
#define ANT_EXT_SW_EN 2
|
2003
|
+
#define ANT_DIV_EN 3
|
2004
|
+
#define ANT_SEL 7
|
2005
|
+
|
2006
|
+
#define IRQ_MASK _SFR_MEM8(0x14E)
|
2007
|
+
#define PLL_LOCK_EN 0
|
2008
|
+
#define PLL_UNLOCK_EN 1
|
2009
|
+
#define RX_START_EN 2
|
2010
|
+
#define RX_END_EN 3
|
2011
|
+
#define CCA_ED_DONE_EN 4
|
2012
|
+
#define AMI_EN 5
|
2013
|
+
#define TX_END_EN 6
|
2014
|
+
#define AWAKE_EN 7
|
2015
|
+
|
2016
|
+
#define IRQ_STATUS _SFR_MEM8(0x14F)
|
2017
|
+
#define PLL_LOCK 0
|
2018
|
+
#define PLL_UNLOCK 1
|
2019
|
+
#define RX_START 2
|
2020
|
+
#define RX_END 3
|
2021
|
+
#define CCA_ED_DONE 4
|
2022
|
+
#define AMI 5
|
2023
|
+
#define TX_END 6
|
2024
|
+
#define AWAKE 7
|
2025
|
+
|
2026
|
+
#define VREG_CTRL _SFR_MEM8(0x150)
|
2027
|
+
#define DVDD_OK 2
|
2028
|
+
#define DVREG_EXT 3
|
2029
|
+
#define AVDD_OK 6
|
2030
|
+
#define AVREG_EXT 7
|
2031
|
+
|
2032
|
+
#define BATMON _SFR_MEM8(0x151)
|
2033
|
+
#define BATMON_VTH0 0
|
2034
|
+
#define BATMON_VTH1 1
|
2035
|
+
#define BATMON_VTH2 2
|
2036
|
+
#define BATMON_VTH3 3
|
2037
|
+
#define BATMON_HR 4
|
2038
|
+
#define BATMON_OK 5
|
2039
|
+
#define BAT_LOW_EN 6
|
2040
|
+
#define BAT_LOW 7
|
2041
|
+
|
2042
|
+
#define XOSC_CTRL _SFR_MEM8(0x152)
|
2043
|
+
#define XTAL_TRIM0 0
|
2044
|
+
#define XTAL_TRIM1 1
|
2045
|
+
#define XTAL_TRIM2 2
|
2046
|
+
#define XTAL_TRIM3 3
|
2047
|
+
#define XTAL_MODE0 4
|
2048
|
+
#define XTAL_MODE1 5
|
2049
|
+
#define XTAL_MODE2 6
|
2050
|
+
#define XTAL_MODE3 7
|
2051
|
+
|
2052
|
+
#define CC_CTRL_0 _SFR_MEM8(0x153)
|
2053
|
+
#define CC_NUMBER0 0
|
2054
|
+
#define CC_NUMBER1 1
|
2055
|
+
#define CC_NUMBER2 2
|
2056
|
+
#define CC_NUMBER3 3
|
2057
|
+
#define CC_NUMBER4 4
|
2058
|
+
#define CC_NUMBER5 5
|
2059
|
+
#define CC_NUMBER6 6
|
2060
|
+
#define CC_NUMBER7 7
|
2061
|
+
|
2062
|
+
#define CC_CTRL_1 _SFR_MEM8(0x154)
|
2063
|
+
#define CC_BAND0 0
|
2064
|
+
#define CC_BAND1 1
|
2065
|
+
#define CC_BAND2 2
|
2066
|
+
#define CC_BAND3 3
|
2067
|
+
|
2068
|
+
#define RX_SYN _SFR_MEM8(0x155)
|
2069
|
+
#define RX_PDT_LEVEL0 0
|
2070
|
+
#define RX_PDT_LEVEL1 1
|
2071
|
+
#define RX_PDT_LEVEL2 2
|
2072
|
+
#define RX_PDT_LEVEL3 3
|
2073
|
+
#define RX_OVERRIDE 6
|
2074
|
+
#define RX_PDT_DIS 7
|
2075
|
+
|
2076
|
+
#define TRX_RPC _SFR_MEM8(0x156)
|
2077
|
+
#define XAH_RPC_EN 0
|
2078
|
+
#define IPAN_RPC_EN 1
|
2079
|
+
#define PLL_RPC_EN 3
|
2080
|
+
#define PDT_RPC_EN 4
|
2081
|
+
#define RX_RPC_EN 5
|
2082
|
+
#define RX_RPC_CTRL0 6
|
2083
|
+
#define RX_RPC_CTRL1 7
|
2084
|
+
|
2085
|
+
#define XAH_CTRL_1 _SFR_MEM8(0x157)
|
2086
|
+
#define AACK_PROM_MODE 1
|
2087
|
+
#define AACK_ACK_TIME 2
|
2088
|
+
#define AACK_UPLD_RES_FT 4
|
2089
|
+
#define AACK_FLTR_RES_FT 5
|
2090
|
+
|
2091
|
+
#define FTN_CTRL _SFR_MEM8(0x158)
|
2092
|
+
#define FTN_START 7
|
2093
|
+
|
2094
|
+
/* Reserved [0x159] */
|
2095
|
+
|
2096
|
+
#define PLL_CF _SFR_MEM8(0x15A)
|
2097
|
+
#define PLL_CF_START 7
|
2098
|
+
|
2099
|
+
#define PLL_DCU _SFR_MEM8(0x15B)
|
2100
|
+
#define PLL_DCU_START 7
|
2101
|
+
|
2102
|
+
#define PART_NUM _SFR_MEM8(0x15C)
|
2103
|
+
#define PART_NUM0 0
|
2104
|
+
#define PART_NUM1 1
|
2105
|
+
#define PART_NUM2 2
|
2106
|
+
#define PART_NUM3 3
|
2107
|
+
#define PART_NUM4 4
|
2108
|
+
#define PART_NUM5 5
|
2109
|
+
#define PART_NUM6 6
|
2110
|
+
#define PART_NUM7 7
|
2111
|
+
|
2112
|
+
#define VERSION_NUM _SFR_MEM8(0x15D)
|
2113
|
+
#define VERSION_NUM0 0
|
2114
|
+
#define VERSION_NUM1 1
|
2115
|
+
#define VERSION_NUM2 2
|
2116
|
+
#define VERSION_NUM3 3
|
2117
|
+
#define VERSION_NUM4 4
|
2118
|
+
#define VERSION_NUM5 5
|
2119
|
+
#define VERSION_NUM6 6
|
2120
|
+
#define VERSION_NUM7 7
|
2121
|
+
|
2122
|
+
#define MAN_ID_0 _SFR_MEM8(0x15E)
|
2123
|
+
#define MAN_ID_00 0
|
2124
|
+
#define MAN_ID_01 1
|
2125
|
+
#define MAN_ID_02 2
|
2126
|
+
#define MAN_ID_03 3
|
2127
|
+
#define MAN_ID_04 4
|
2128
|
+
#define MAN_ID_05 5
|
2129
|
+
#define MAN_ID_06 6
|
2130
|
+
#define MAN_ID_07 7
|
2131
|
+
|
2132
|
+
#define MAN_ID_1 _SFR_MEM8(0x15F)
|
2133
|
+
#define MAN_ID_10 0
|
2134
|
+
#define MAN_ID_11 1
|
2135
|
+
#define MAN_ID_12 2
|
2136
|
+
#define MAN_ID_13 3
|
2137
|
+
#define MAN_ID_14 4
|
2138
|
+
#define MAN_ID_15 5
|
2139
|
+
#define MAN_ID_16 6
|
2140
|
+
#define MAN_ID_17 7
|
2141
|
+
|
2142
|
+
#define SHORT_ADDR_0 _SFR_MEM8(0x160)
|
2143
|
+
#define SHORT_ADDR_00 0
|
2144
|
+
#define SHORT_ADDR_01 1
|
2145
|
+
#define SHORT_ADDR_02 2
|
2146
|
+
#define SHORT_ADDR_03 3
|
2147
|
+
#define SHORT_ADDR_04 4
|
2148
|
+
#define SHORT_ADDR_05 5
|
2149
|
+
#define SHORT_ADDR_06 6
|
2150
|
+
#define SHORT_ADDR_07 7
|
2151
|
+
|
2152
|
+
#define SHORT_ADDR_1 _SFR_MEM8(0x161)
|
2153
|
+
#define SHORT_ADDR_10 0
|
2154
|
+
#define SHORT_ADDR_11 1
|
2155
|
+
#define SHORT_ADDR_12 2
|
2156
|
+
#define SHORT_ADDR_13 3
|
2157
|
+
#define SHORT_ADDR_14 4
|
2158
|
+
#define SHORT_ADDR_15 5
|
2159
|
+
#define SHORT_ADDR_16 6
|
2160
|
+
#define SHORT_ADDR_17 7
|
2161
|
+
|
2162
|
+
#define PAN_ID_0 _SFR_MEM8(0x162)
|
2163
|
+
#define PAN_ID_00 0
|
2164
|
+
#define PAN_ID_01 1
|
2165
|
+
#define PAN_ID_02 2
|
2166
|
+
#define PAN_ID_03 3
|
2167
|
+
#define PAN_ID_04 4
|
2168
|
+
#define PAN_ID_05 5
|
2169
|
+
#define PAN_ID_06 6
|
2170
|
+
#define PAN_ID_07 7
|
2171
|
+
|
2172
|
+
#define PAN_ID_1 _SFR_MEM8(0x163)
|
2173
|
+
#define PAN_ID_10 0
|
2174
|
+
#define PAN_ID_11 1
|
2175
|
+
#define PAN_ID_12 2
|
2176
|
+
#define PAN_ID_13 3
|
2177
|
+
#define PAN_ID_14 4
|
2178
|
+
#define PAN_ID_15 5
|
2179
|
+
#define PAN_ID_16 6
|
2180
|
+
#define PAN_ID_17 7
|
2181
|
+
|
2182
|
+
#define IEEE_ADDR_0 _SFR_MEM8(0x164)
|
2183
|
+
#define IEEE_ADDR_00 0
|
2184
|
+
#define IEEE_ADDR_01 1
|
2185
|
+
#define IEEE_ADDR_02 2
|
2186
|
+
#define IEEE_ADDR_03 3
|
2187
|
+
#define IEEE_ADDR_04 4
|
2188
|
+
#define IEEE_ADDR_05 5
|
2189
|
+
#define IEEE_ADDR_06 6
|
2190
|
+
#define IEEE_ADDR_07 7
|
2191
|
+
|
2192
|
+
#define IEEE_ADDR_1 _SFR_MEM8(0x165)
|
2193
|
+
#define IEEE_ADDR_10 0
|
2194
|
+
#define IEEE_ADDR_11 1
|
2195
|
+
#define IEEE_ADDR_12 2
|
2196
|
+
#define IEEE_ADDR_13 3
|
2197
|
+
#define IEEE_ADDR_14 4
|
2198
|
+
#define IEEE_ADDR_15 5
|
2199
|
+
#define IEEE_ADDR_16 6
|
2200
|
+
#define IEEE_ADDR_17 7
|
2201
|
+
|
2202
|
+
#define IEEE_ADDR_2 _SFR_MEM8(0x166)
|
2203
|
+
#define IEEE_ADDR_20 0
|
2204
|
+
#define IEEE_ADDR_21 1
|
2205
|
+
#define IEEE_ADDR_22 2
|
2206
|
+
#define IEEE_ADDR_23 3
|
2207
|
+
#define IEEE_ADDR_24 4
|
2208
|
+
#define IEEE_ADDR_25 5
|
2209
|
+
#define IEEE_ADDR_26 6
|
2210
|
+
#define IEEE_ADDR_27 7
|
2211
|
+
|
2212
|
+
#define IEEE_ADDR_3 _SFR_MEM8(0x167)
|
2213
|
+
#define IEEE_ADDR_30 0
|
2214
|
+
#define IEEE_ADDR_31 1
|
2215
|
+
#define IEEE_ADDR_32 2
|
2216
|
+
#define IEEE_ADDR_33 3
|
2217
|
+
#define IEEE_ADDR_34 4
|
2218
|
+
#define IEEE_ADDR_35 5
|
2219
|
+
#define IEEE_ADDR_36 6
|
2220
|
+
#define IEEE_ADDR_37 7
|
2221
|
+
|
2222
|
+
#define IEEE_ADDR_4 _SFR_MEM8(0x168)
|
2223
|
+
#define IEEE_ADDR_40 0
|
2224
|
+
#define IEEE_ADDR_41 1
|
2225
|
+
#define IEEE_ADDR_42 2
|
2226
|
+
#define IEEE_ADDR_43 3
|
2227
|
+
#define IEEE_ADDR_44 4
|
2228
|
+
#define IEEE_ADDR_45 5
|
2229
|
+
#define IEEE_ADDR_46 6
|
2230
|
+
#define IEEE_ADDR_47 7
|
2231
|
+
|
2232
|
+
#define IEEE_ADDR_5 _SFR_MEM8(0x169)
|
2233
|
+
#define IEEE_ADDR_50 0
|
2234
|
+
#define IEEE_ADDR_51 1
|
2235
|
+
#define IEEE_ADDR_52 2
|
2236
|
+
#define IEEE_ADDR_53 3
|
2237
|
+
#define IEEE_ADDR_54 4
|
2238
|
+
#define IEEE_ADDR_55 5
|
2239
|
+
#define IEEE_ADDR_56 6
|
2240
|
+
#define IEEE_ADDR_57 7
|
2241
|
+
|
2242
|
+
#define IEEE_ADDR_6 _SFR_MEM8(0x16A)
|
2243
|
+
#define IEEE_ADDR_60 0
|
2244
|
+
#define IEEE_ADDR_61 1
|
2245
|
+
#define IEEE_ADDR_62 2
|
2246
|
+
#define IEEE_ADDR_63 3
|
2247
|
+
#define IEEE_ADDR_64 4
|
2248
|
+
#define IEEE_ADDR_65 5
|
2249
|
+
#define IEEE_ADDR_66 6
|
2250
|
+
#define IEEE_ADDR_67 7
|
2251
|
+
|
2252
|
+
#define IEEE_ADDR_7 _SFR_MEM8(0x16B)
|
2253
|
+
#define IEEE_ADDR_70 0
|
2254
|
+
#define IEEE_ADDR_71 1
|
2255
|
+
#define IEEE_ADDR_72 2
|
2256
|
+
#define IEEE_ADDR_73 3
|
2257
|
+
#define IEEE_ADDR_74 4
|
2258
|
+
#define IEEE_ADDR_75 5
|
2259
|
+
#define IEEE_ADDR_76 6
|
2260
|
+
#define IEEE_ADDR_77 7
|
2261
|
+
|
2262
|
+
#define XAH_CTRL_0 _SFR_MEM8(0x16C)
|
2263
|
+
#define SLOTTED_OPERATION 0
|
2264
|
+
#define MAX_CSMA_RETRIES0 1
|
2265
|
+
#define MAX_CSMA_RETRIES1 2
|
2266
|
+
#define MAX_CSMA_RETRIES2 3
|
2267
|
+
#define MAX_FRAME_RETRIES0 4
|
2268
|
+
#define MAX_FRAME_RETRIES1 5
|
2269
|
+
#define MAX_FRAME_RETRIES2 6
|
2270
|
+
#define MAX_FRAME_RETRIES3 7
|
2271
|
+
|
2272
|
+
#define CSMA_SEED_0 _SFR_MEM8(0x16D)
|
2273
|
+
#define CSMA_SEED_00 0
|
2274
|
+
#define CSMA_SEED_01 1
|
2275
|
+
#define CSMA_SEED_02 2
|
2276
|
+
#define CSMA_SEED_03 3
|
2277
|
+
#define CSMA_SEED_04 4
|
2278
|
+
#define CSMA_SEED_05 5
|
2279
|
+
#define CSMA_SEED_06 6
|
2280
|
+
#define CSMA_SEED_07 7
|
2281
|
+
|
2282
|
+
#define CSMA_SEED_1 _SFR_MEM8(0x16E)
|
2283
|
+
#define CSMA_SEED_10 0
|
2284
|
+
#define CSMA_SEED_11 1
|
2285
|
+
#define CSMA_SEED_12 2
|
2286
|
+
#define AACK_I_AM_COORD 3
|
2287
|
+
#define AACK_DIS_ACK 4
|
2288
|
+
#define AACK_SET_PD 5
|
2289
|
+
#define AACK_FVN_MODE0 6
|
2290
|
+
#define AACK_FVN_MODE1 7
|
2291
|
+
|
2292
|
+
#define CSMA_BE _SFR_MEM8(0x16F)
|
2293
|
+
#define MIN_BE0 0
|
2294
|
+
#define MIN_BE1 1
|
2295
|
+
#define MIN_BE2 2
|
2296
|
+
#define MIN_BE3 3
|
2297
|
+
#define MAX_BE0 4
|
2298
|
+
#define MAX_BE1 5
|
2299
|
+
#define MAX_BE2 6
|
2300
|
+
#define MAX_BE3 7
|
2301
|
+
|
2302
|
+
/* Reserved [0x170..0x175] */
|
2303
|
+
|
2304
|
+
#define TST_CTRL_DIGI _SFR_MEM8(0x176)
|
2305
|
+
#define TST_CTRL_DIG0 0
|
2306
|
+
#define TST_CTRL_DIG1 1
|
2307
|
+
#define TST_CTRL_DIG2 2
|
2308
|
+
#define TST_CTRL_DIG3 3
|
2309
|
+
|
2310
|
+
/* Reserved [0x177..0x17A] */
|
2311
|
+
|
2312
|
+
#define TST_RX_LENGTH _SFR_MEM8(0x17B)
|
2313
|
+
#define RX_LENGTH0 0
|
2314
|
+
#define RX_LENGTH1 1
|
2315
|
+
#define RX_LENGTH2 2
|
2316
|
+
#define RX_LENGTH3 3
|
2317
|
+
#define RX_LENGTH4 4
|
2318
|
+
#define RX_LENGTH5 5
|
2319
|
+
#define RX_LENGTH6 6
|
2320
|
+
#define RX_LENGTH7 7
|
2321
|
+
|
2322
|
+
/* Reserved [0x17C..0x17F] */
|
2323
|
+
|
2324
|
+
#define TRXFBST _SFR_MEM8(0x180)
|
2325
|
+
|
2326
|
+
/* Reserved [0x181..0x1FE] */
|
2327
|
+
|
2328
|
+
#define TRXFBEND _SFR_MEM8(0x1FF)
|
2329
|
+
|
2330
|
+
|
2331
|
+
|
2332
|
+
/* Values and associated defines */
|
2333
|
+
|
2334
|
+
|
2335
|
+
#define SLEEP_MODE_IDLE (0x00<<1)
|
2336
|
+
#define SLEEP_MODE_ADC (0x01<<1)
|
2337
|
+
#define SLEEP_MODE_PWR_DOWN (0x02<<1)
|
2338
|
+
#define SLEEP_MODE_PWR_SAVE (0x03<<1)
|
2339
|
+
#define SLEEP_MODE_STANDBY (0x06<<1)
|
2340
|
+
#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
|
2341
|
+
|
2342
|
+
/* Interrupt vectors */
|
2343
|
+
/* Vector 0 is the reset vector */
|
2344
|
+
/* External Interrupt Request 0 */
|
2345
|
+
#define INT0_vect _VECTOR(1)
|
2346
|
+
#define INT0_vect_num 1
|
2347
|
+
|
2348
|
+
/* External Interrupt Request 1 */
|
2349
|
+
#define INT1_vect _VECTOR(2)
|
2350
|
+
#define INT1_vect_num 2
|
2351
|
+
|
2352
|
+
/* External Interrupt Request 2 */
|
2353
|
+
#define INT2_vect _VECTOR(3)
|
2354
|
+
#define INT2_vect_num 3
|
2355
|
+
|
2356
|
+
/* External Interrupt Request 3 */
|
2357
|
+
#define INT3_vect _VECTOR(4)
|
2358
|
+
#define INT3_vect_num 4
|
2359
|
+
|
2360
|
+
/* External Interrupt Request 4 */
|
2361
|
+
#define INT4_vect _VECTOR(5)
|
2362
|
+
#define INT4_vect_num 5
|
2363
|
+
|
2364
|
+
/* External Interrupt Request 5 */
|
2365
|
+
#define INT5_vect _VECTOR(6)
|
2366
|
+
#define INT5_vect_num 6
|
2367
|
+
|
2368
|
+
/* External Interrupt Request 6 */
|
2369
|
+
#define INT6_vect _VECTOR(7)
|
2370
|
+
#define INT6_vect_num 7
|
2371
|
+
|
2372
|
+
/* External Interrupt Request 7 */
|
2373
|
+
#define INT7_vect _VECTOR(8)
|
2374
|
+
#define INT7_vect_num 8
|
2375
|
+
|
2376
|
+
/* Pin Change Interrupt Request 0 */
|
2377
|
+
#define PCINT0_vect _VECTOR(9)
|
2378
|
+
#define PCINT0_vect_num 9
|
2379
|
+
|
2380
|
+
/* Pin Change Interrupt Request 1 */
|
2381
|
+
#define PCINT1_vect _VECTOR(10)
|
2382
|
+
#define PCINT1_vect_num 10
|
2383
|
+
|
2384
|
+
/* Pin Change Interrupt Request 2 */
|
2385
|
+
#define PCINT2_vect _VECTOR(11)
|
2386
|
+
#define PCINT2_vect_num 11
|
2387
|
+
|
2388
|
+
/* Watchdog Time-out Interrupt */
|
2389
|
+
#define WDT_vect _VECTOR(12)
|
2390
|
+
#define WDT_vect_num 12
|
2391
|
+
|
2392
|
+
/* Timer/Counter2 Compare Match A */
|
2393
|
+
#define TIMER2_COMPA_vect _VECTOR(13)
|
2394
|
+
#define TIMER2_COMPA_vect_num 13
|
2395
|
+
|
2396
|
+
/* Timer/Counter2 Compare Match B */
|
2397
|
+
#define TIMER2_COMPB_vect _VECTOR(14)
|
2398
|
+
#define TIMER2_COMPB_vect_num 14
|
2399
|
+
|
2400
|
+
/* Timer/Counter2 Overflow */
|
2401
|
+
#define TIMER2_OVF_vect _VECTOR(15)
|
2402
|
+
#define TIMER2_OVF_vect_num 15
|
2403
|
+
|
2404
|
+
/* Timer/Counter1 Capture Event */
|
2405
|
+
#define TIMER1_CAPT_vect _VECTOR(16)
|
2406
|
+
#define TIMER1_CAPT_vect_num 16
|
2407
|
+
|
2408
|
+
/* Timer/Counter1 Compare Match A */
|
2409
|
+
#define TIMER1_COMPA_vect _VECTOR(17)
|
2410
|
+
#define TIMER1_COMPA_vect_num 17
|
2411
|
+
|
2412
|
+
/* Timer/Counter1 Compare Match B */
|
2413
|
+
#define TIMER1_COMPB_vect _VECTOR(18)
|
2414
|
+
#define TIMER1_COMPB_vect_num 18
|
2415
|
+
|
2416
|
+
/* Timer/Counter1 Compare Match C */
|
2417
|
+
#define TIMER1_COMPC_vect _VECTOR(19)
|
2418
|
+
#define TIMER1_COMPC_vect_num 19
|
2419
|
+
|
2420
|
+
/* Timer/Counter1 Overflow */
|
2421
|
+
#define TIMER1_OVF_vect _VECTOR(20)
|
2422
|
+
#define TIMER1_OVF_vect_num 20
|
2423
|
+
|
2424
|
+
/* Timer/Counter0 Compare Match A */
|
2425
|
+
#define TIMER0_COMPA_vect _VECTOR(21)
|
2426
|
+
#define TIMER0_COMPA_vect_num 21
|
2427
|
+
|
2428
|
+
/* Timer/Counter0 Compare Match B */
|
2429
|
+
#define TIMER0_COMPB_vect _VECTOR(22)
|
2430
|
+
#define TIMER0_COMPB_vect_num 22
|
2431
|
+
|
2432
|
+
/* Timer/Counter0 Overflow */
|
2433
|
+
#define TIMER0_OVF_vect _VECTOR(23)
|
2434
|
+
#define TIMER0_OVF_vect_num 23
|
2435
|
+
|
2436
|
+
/* SPI Serial Transfer Complete */
|
2437
|
+
#define SPI_STC_vect _VECTOR(24)
|
2438
|
+
#define SPI_STC_vect_num 24
|
2439
|
+
|
2440
|
+
/* USART0, Rx Complete */
|
2441
|
+
#define USART0_RX_vect _VECTOR(25)
|
2442
|
+
#define USART0_RX_vect_num 25
|
2443
|
+
|
2444
|
+
/* USART0 Data register Empty */
|
2445
|
+
#define USART0_UDRE_vect _VECTOR(26)
|
2446
|
+
#define USART0_UDRE_vect_num 26
|
2447
|
+
|
2448
|
+
/* USART0, Tx Complete */
|
2449
|
+
#define USART0_TX_vect _VECTOR(27)
|
2450
|
+
#define USART0_TX_vect_num 27
|
2451
|
+
|
2452
|
+
/* Analog Comparator */
|
2453
|
+
#define ANALOG_COMP_vect _VECTOR(28)
|
2454
|
+
#define ANALOG_COMP_vect_num 28
|
2455
|
+
|
2456
|
+
/* ADC Conversion Complete */
|
2457
|
+
#define ADC_vect _VECTOR(29)
|
2458
|
+
#define ADC_vect_num 29
|
2459
|
+
|
2460
|
+
/* EEPROM Ready */
|
2461
|
+
#define EE_READY_vect _VECTOR(30)
|
2462
|
+
#define EE_READY_vect_num 30
|
2463
|
+
|
2464
|
+
/* Timer/Counter3 Capture Event */
|
2465
|
+
#define TIMER3_CAPT_vect _VECTOR(31)
|
2466
|
+
#define TIMER3_CAPT_vect_num 31
|
2467
|
+
|
2468
|
+
/* Timer/Counter3 Compare Match A */
|
2469
|
+
#define TIMER3_COMPA_vect _VECTOR(32)
|
2470
|
+
#define TIMER3_COMPA_vect_num 32
|
2471
|
+
|
2472
|
+
/* Timer/Counter3 Compare Match B */
|
2473
|
+
#define TIMER3_COMPB_vect _VECTOR(33)
|
2474
|
+
#define TIMER3_COMPB_vect_num 33
|
2475
|
+
|
2476
|
+
/* Timer/Counter3 Compare Match C */
|
2477
|
+
#define TIMER3_COMPC_vect _VECTOR(34)
|
2478
|
+
#define TIMER3_COMPC_vect_num 34
|
2479
|
+
|
2480
|
+
/* Timer/Counter3 Overflow */
|
2481
|
+
#define TIMER3_OVF_vect _VECTOR(35)
|
2482
|
+
#define TIMER3_OVF_vect_num 35
|
2483
|
+
|
2484
|
+
/* USART1, Rx Complete */
|
2485
|
+
#define USART1_RX_vect _VECTOR(36)
|
2486
|
+
#define USART1_RX_vect_num 36
|
2487
|
+
|
2488
|
+
/* USART1 Data register Empty */
|
2489
|
+
#define USART1_UDRE_vect _VECTOR(37)
|
2490
|
+
#define USART1_UDRE_vect_num 37
|
2491
|
+
|
2492
|
+
/* USART1, Tx Complete */
|
2493
|
+
#define USART1_TX_vect _VECTOR(38)
|
2494
|
+
#define USART1_TX_vect_num 38
|
2495
|
+
|
2496
|
+
/* 2-wire Serial Interface */
|
2497
|
+
#define TWI_vect _VECTOR(39)
|
2498
|
+
#define TWI_vect_num 39
|
2499
|
+
|
2500
|
+
/* Store Program Memory Read */
|
2501
|
+
#define SPM_READY_vect _VECTOR(40)
|
2502
|
+
#define SPM_READY_vect_num 40
|
2503
|
+
|
2504
|
+
/* Timer/Counter4 Capture Event */
|
2505
|
+
#define TIMER4_CAPT_vect _VECTOR(41)
|
2506
|
+
#define TIMER4_CAPT_vect_num 41
|
2507
|
+
|
2508
|
+
/* Timer/Counter4 Compare Match A */
|
2509
|
+
#define TIMER4_COMPA_vect _VECTOR(42)
|
2510
|
+
#define TIMER4_COMPA_vect_num 42
|
2511
|
+
|
2512
|
+
/* Timer/Counter4 Compare Match B */
|
2513
|
+
#define TIMER4_COMPB_vect _VECTOR(43)
|
2514
|
+
#define TIMER4_COMPB_vect_num 43
|
2515
|
+
|
2516
|
+
/* Timer/Counter4 Compare Match C */
|
2517
|
+
#define TIMER4_COMPC_vect _VECTOR(44)
|
2518
|
+
#define TIMER4_COMPC_vect_num 44
|
2519
|
+
|
2520
|
+
/* Timer/Counter4 Overflow */
|
2521
|
+
#define TIMER4_OVF_vect _VECTOR(45)
|
2522
|
+
#define TIMER4_OVF_vect_num 45
|
2523
|
+
|
2524
|
+
/* Timer/Counter5 Capture Event */
|
2525
|
+
#define TIMER5_CAPT_vect _VECTOR(46)
|
2526
|
+
#define TIMER5_CAPT_vect_num 46
|
2527
|
+
|
2528
|
+
/* Timer/Counter5 Compare Match A */
|
2529
|
+
#define TIMER5_COMPA_vect _VECTOR(47)
|
2530
|
+
#define TIMER5_COMPA_vect_num 47
|
2531
|
+
|
2532
|
+
/* Timer/Counter5 Compare Match B */
|
2533
|
+
#define TIMER5_COMPB_vect _VECTOR(48)
|
2534
|
+
#define TIMER5_COMPB_vect_num 48
|
2535
|
+
|
2536
|
+
/* Timer/Counter5 Compare Match C */
|
2537
|
+
#define TIMER5_COMPC_vect _VECTOR(49)
|
2538
|
+
#define TIMER5_COMPC_vect_num 49
|
2539
|
+
|
2540
|
+
/* Timer/Counter5 Overflow */
|
2541
|
+
#define TIMER5_OVF_vect _VECTOR(50)
|
2542
|
+
#define TIMER5_OVF_vect_num 50
|
2543
|
+
|
2544
|
+
/* TRX24 - PLL lock interrupt */
|
2545
|
+
#define TRX24_PLL_LOCK_vect _VECTOR(57)
|
2546
|
+
#define TRX24_PLL_LOCK_vect_num 57
|
2547
|
+
|
2548
|
+
/* TRX24 - PLL unlock interrupt */
|
2549
|
+
#define TRX24_PLL_UNLOCK_vect _VECTOR(58)
|
2550
|
+
#define TRX24_PLL_UNLOCK_vect_num 58
|
2551
|
+
|
2552
|
+
/* TRX24 - Receive start interrupt */
|
2553
|
+
#define TRX24_RX_START_vect _VECTOR(59)
|
2554
|
+
#define TRX24_RX_START_vect_num 59
|
2555
|
+
|
2556
|
+
/* TRX24 - RX_END interrupt */
|
2557
|
+
#define TRX24_RX_END_vect _VECTOR(60)
|
2558
|
+
#define TRX24_RX_END_vect_num 60
|
2559
|
+
|
2560
|
+
/* TRX24 - CCA/ED done interrupt */
|
2561
|
+
#define TRX24_CCA_ED_DONE_vect _VECTOR(61)
|
2562
|
+
#define TRX24_CCA_ED_DONE_vect_num 61
|
2563
|
+
|
2564
|
+
/* TRX24 - XAH - AMI */
|
2565
|
+
#define TRX24_XAH_AMI_vect _VECTOR(62)
|
2566
|
+
#define TRX24_XAH_AMI_vect_num 62
|
2567
|
+
|
2568
|
+
/* TRX24 - TX_END interrupt */
|
2569
|
+
#define TRX24_TX_END_vect _VECTOR(63)
|
2570
|
+
#define TRX24_TX_END_vect_num 63
|
2571
|
+
|
2572
|
+
/* TRX24 AWAKE - tranceiver is reaching state TRX_OFF */
|
2573
|
+
#define TRX24_AWAKE_vect _VECTOR(64)
|
2574
|
+
#define TRX24_AWAKE_vect_num 64
|
2575
|
+
|
2576
|
+
/* Symbol counter - compare match 1 interrupt */
|
2577
|
+
#define SCNT_CMP1_vect _VECTOR(65)
|
2578
|
+
#define SCNT_CMP1_vect_num 65
|
2579
|
+
|
2580
|
+
/* Symbol counter - compare match 2 interrupt */
|
2581
|
+
#define SCNT_CMP2_vect _VECTOR(66)
|
2582
|
+
#define SCNT_CMP2_vect_num 66
|
2583
|
+
|
2584
|
+
/* Symbol counter - compare match 3 interrupt */
|
2585
|
+
#define SCNT_CMP3_vect _VECTOR(67)
|
2586
|
+
#define SCNT_CMP3_vect_num 67
|
2587
|
+
|
2588
|
+
/* Symbol counter - overflow interrupt */
|
2589
|
+
#define SCNT_OVFL_vect _VECTOR(68)
|
2590
|
+
#define SCNT_OVFL_vect_num 68
|
2591
|
+
|
2592
|
+
/* Symbol counter - backoff interrupt */
|
2593
|
+
#define SCNT_BACKOFF_vect _VECTOR(69)
|
2594
|
+
#define SCNT_BACKOFF_vect_num 69
|
2595
|
+
|
2596
|
+
/* AES engine ready interrupt */
|
2597
|
+
#define AES_READY_vect _VECTOR(70)
|
2598
|
+
#define AES_READY_vect_num 70
|
2599
|
+
|
2600
|
+
/* Battery monitor indicates supply voltage below threshold */
|
2601
|
+
#define BAT_LOW_vect _VECTOR(71)
|
2602
|
+
#define BAT_LOW_vect_num 71
|
2603
|
+
|
2604
|
+
/* TRX24 TX start interrupt */
|
2605
|
+
#define TRX24_TX_START_vect _VECTOR(72)
|
2606
|
+
#define TRX24_TX_START_vect_num 72
|
2607
|
+
|
2608
|
+
/* Address match interrupt of address filter 0 */
|
2609
|
+
#define TRX24_AMI0_vect _VECTOR(73)
|
2610
|
+
#define TRX24_AMI0_vect_num 73
|
2611
|
+
|
2612
|
+
/* Address match interrupt of address filter 1 */
|
2613
|
+
#define TRX24_AMI1_vect _VECTOR(74)
|
2614
|
+
#define TRX24_AMI1_vect_num 74
|
2615
|
+
|
2616
|
+
/* Address match interrupt of address filter 2 */
|
2617
|
+
#define TRX24_AMI2_vect _VECTOR(75)
|
2618
|
+
#define TRX24_AMI2_vect_num 75
|
2619
|
+
|
2620
|
+
/* Address match interrupt of address filter 3 */
|
2621
|
+
#define TRX24_AMI3_vect _VECTOR(76)
|
2622
|
+
#define TRX24_AMI3_vect_num 76
|
2623
|
+
|
2624
|
+
#define _VECTORS_SIZE 308
|
2625
|
+
|
2626
|
+
|
2627
|
+
/* Constants */
|
2628
|
+
|
2629
|
+
#define SPM_PAGESIZE 256
|
2630
|
+
#define FLASHSTART 0x0000
|
2631
|
+
#define FLASHEND 0x3FFFF
|
2632
|
+
#define RAMSTART 0x0200
|
2633
|
+
#define RAMSIZE 32768
|
2634
|
+
#define RAMEND 0x81FF
|
2635
|
+
#define E2START 0
|
2636
|
+
#define E2SIZE 8192
|
2637
|
+
#define E2PAGESIZE 8
|
2638
|
+
#define E2END 0x1FFF
|
2639
|
+
#define XRAMEND RAMEND
|
2640
|
+
|
2641
|
+
|
2642
|
+
/* Fuses */
|
2643
|
+
|
2644
|
+
#define FUSE_MEMORY_SIZE 3
|
2645
|
+
|
2646
|
+
/* Low Fuse Byte */
|
2647
|
+
#define FUSE_CKSEL_SUT0 (unsigned char)~_BV(0)
|
2648
|
+
#define FUSE_CKSEL_SUT1 (unsigned char)~_BV(1)
|
2649
|
+
#define FUSE_CKSEL_SUT2 (unsigned char)~_BV(2)
|
2650
|
+
#define FUSE_CKSEL_SUT3 (unsigned char)~_BV(3)
|
2651
|
+
#define FUSE_CKSEL_SUT4 (unsigned char)~_BV(4)
|
2652
|
+
#define FUSE_CKSEL_SUT5 (unsigned char)~_BV(5)
|
2653
|
+
#define FUSE_CKOUT (unsigned char)~_BV(6)
|
2654
|
+
#define FUSE_CKDIV8 (unsigned char)~_BV(7)
|
2655
|
+
#define LFUSE_DEFAULT (FUSE_CKSEL_SUT0 & FUSE_CKSEL_SUT2 & FUSE_CKSEL_SUT3 & FUSE_CKSEL_SUT4 & FUSE_CKDIV8)
|
2656
|
+
|
2657
|
+
|
2658
|
+
/* High Fuse Byte */
|
2659
|
+
#define FUSE_BOOTRST (unsigned char)~_BV(0)
|
2660
|
+
#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
|
2661
|
+
#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
|
2662
|
+
#define FUSE_EESAVE (unsigned char)~_BV(3)
|
2663
|
+
#define FUSE_WDTON (unsigned char)~_BV(4)
|
2664
|
+
#define FUSE_SPIEN (unsigned char)~_BV(5)
|
2665
|
+
#define FUSE_JTAGEN (unsigned char)~_BV(6)
|
2666
|
+
#define FUSE_OCDEN (unsigned char)~_BV(7)
|
2667
|
+
#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
|
2668
|
+
|
2669
|
+
|
2670
|
+
/* Extended Fuse Byte */
|
2671
|
+
#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
|
2672
|
+
#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
|
2673
|
+
#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
|
2674
|
+
#define EFUSE_DEFAULT (FUSE_BODLEVEL0)
|
2675
|
+
|
2676
|
+
|
2677
|
+
|
2678
|
+
/* Lock Bits */
|
2679
|
+
#define __LOCK_BITS_EXIST
|
2680
|
+
#define __BOOT_LOCK_BITS_0_EXIST
|
2681
|
+
#define __BOOT_LOCK_BITS_1_EXIST
|
2682
|
+
|
2683
|
+
|
2684
|
+
/* Signature */
|
2685
|
+
#define SIGNATURE_0 0x1E
|
2686
|
+
#define SIGNATURE_1 0xA8
|
2687
|
+
#define SIGNATURE_2 0x03
|
2688
|
+
|
2689
|
+
|
2690
|
+
#endif /* #ifdef _AVR_ATMEGA2564RFR2_H_INCLUDED */
|
2691
|
+
|