arduino_ci 0.1.3 → 0.1.4

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Files changed (295) hide show
  1. checksums.yaml +4 -4
  2. data/README.md +77 -1
  3. data/cpp/arduino/Arduino.cpp +17 -7
  4. data/cpp/arduino/Arduino.h +151 -5
  5. data/cpp/arduino/ArduinoDefines.h +90 -0
  6. data/cpp/arduino/AvrMath.h +18 -28
  7. data/cpp/arduino/Godmode.cpp +62 -0
  8. data/cpp/arduino/Godmode.h +74 -0
  9. data/cpp/arduino/HardwareSerial.h +81 -0
  10. data/cpp/arduino/Print.h +67 -0
  11. data/cpp/arduino/Stream.h +210 -0
  12. data/cpp/arduino/WCharacter.h +96 -0
  13. data/cpp/arduino/WString.h +164 -0
  14. data/cpp/arduino/binary.h +518 -0
  15. data/cpp/arduino/include/README.md +3 -0
  16. data/cpp/arduino/include/common.h +333 -0
  17. data/cpp/arduino/include/fuse.h +274 -0
  18. data/cpp/arduino/include/io.h +643 -0
  19. data/cpp/arduino/include/io1200.h +274 -0
  20. data/cpp/arduino/include/io2313.h +385 -0
  21. data/cpp/arduino/include/io2323.h +210 -0
  22. data/cpp/arduino/include/io2333.h +461 -0
  23. data/cpp/arduino/include/io2343.h +214 -0
  24. data/cpp/arduino/include/io43u32x.h +440 -0
  25. data/cpp/arduino/include/io43u35x.h +432 -0
  26. data/cpp/arduino/include/io4414.h +500 -0
  27. data/cpp/arduino/include/io4433.h +489 -0
  28. data/cpp/arduino/include/io4434.h +588 -0
  29. data/cpp/arduino/include/io76c711.h +499 -0
  30. data/cpp/arduino/include/io8515.h +501 -0
  31. data/cpp/arduino/include/io8534.h +217 -0
  32. data/cpp/arduino/include/io8535.h +589 -0
  33. data/cpp/arduino/include/io86r401.h +309 -0
  34. data/cpp/arduino/include/io90pwm1.h +1157 -0
  35. data/cpp/arduino/include/io90pwm161.h +918 -0
  36. data/cpp/arduino/include/io90pwm216.h +1225 -0
  37. data/cpp/arduino/include/io90pwm2b.h +1466 -0
  38. data/cpp/arduino/include/io90pwm316.h +1272 -0
  39. data/cpp/arduino/include/io90pwm3b.h +1466 -0
  40. data/cpp/arduino/include/io90pwm81.h +1036 -0
  41. data/cpp/arduino/include/io90pwmx.h +1415 -0
  42. data/cpp/arduino/include/io90scr100.h +1719 -0
  43. data/cpp/arduino/include/ioa5272.h +803 -0
  44. data/cpp/arduino/include/ioa5505.h +803 -0
  45. data/cpp/arduino/include/ioa5702m322.h +2591 -0
  46. data/cpp/arduino/include/ioa5782.h +1843 -0
  47. data/cpp/arduino/include/ioa5790.h +907 -0
  48. data/cpp/arduino/include/ioa5790n.h +922 -0
  49. data/cpp/arduino/include/ioa5791.h +923 -0
  50. data/cpp/arduino/include/ioa5795.h +756 -0
  51. data/cpp/arduino/include/ioa5831.h +1949 -0
  52. data/cpp/arduino/include/ioa6285.h +740 -0
  53. data/cpp/arduino/include/ioa6286.h +740 -0
  54. data/cpp/arduino/include/ioa6289.h +847 -0
  55. data/cpp/arduino/include/ioa6612c.h +795 -0
  56. data/cpp/arduino/include/ioa6613c.h +795 -0
  57. data/cpp/arduino/include/ioa6614q.h +798 -0
  58. data/cpp/arduino/include/ioa6616c.h +865 -0
  59. data/cpp/arduino/include/ioa6617c.h +865 -0
  60. data/cpp/arduino/include/ioa664251.h +857 -0
  61. data/cpp/arduino/include/ioa8210.h +1843 -0
  62. data/cpp/arduino/include/ioa8510.h +1949 -0
  63. data/cpp/arduino/include/ioat94k.h +565 -0
  64. data/cpp/arduino/include/iocan128.h +100 -0
  65. data/cpp/arduino/include/iocan32.h +100 -0
  66. data/cpp/arduino/include/iocan64.h +100 -0
  67. data/cpp/arduino/include/iocanxx.h +2020 -0
  68. data/cpp/arduino/include/iom103.h +735 -0
  69. data/cpp/arduino/include/iom128.h +1299 -0
  70. data/cpp/arduino/include/iom1280.h +101 -0
  71. data/cpp/arduino/include/iom1281.h +101 -0
  72. data/cpp/arduino/include/iom1284.h +1099 -0
  73. data/cpp/arduino/include/iom1284p.h +1219 -0
  74. data/cpp/arduino/include/iom1284rfr2.h +2690 -0
  75. data/cpp/arduino/include/iom128a.h +1070 -0
  76. data/cpp/arduino/include/iom128rfa1.h +5385 -0
  77. data/cpp/arduino/include/iom128rfr2.h +2706 -0
  78. data/cpp/arduino/include/iom16.h +676 -0
  79. data/cpp/arduino/include/iom161.h +726 -0
  80. data/cpp/arduino/include/iom162.h +1022 -0
  81. data/cpp/arduino/include/iom163.h +686 -0
  82. data/cpp/arduino/include/iom164.h +101 -0
  83. data/cpp/arduino/include/iom164a.h +34 -0
  84. data/cpp/arduino/include/iom164p.h +34 -0
  85. data/cpp/arduino/include/iom164pa.h +1016 -0
  86. data/cpp/arduino/include/iom165.h +887 -0
  87. data/cpp/arduino/include/iom165a.h +832 -0
  88. data/cpp/arduino/include/iom165p.h +889 -0
  89. data/cpp/arduino/include/iom165pa.h +948 -0
  90. data/cpp/arduino/include/iom168.h +97 -0
  91. data/cpp/arduino/include/iom168a.h +35 -0
  92. data/cpp/arduino/include/iom168p.h +942 -0
  93. data/cpp/arduino/include/iom168pa.h +843 -0
  94. data/cpp/arduino/include/iom168pb.h +899 -0
  95. data/cpp/arduino/include/iom169.h +1174 -0
  96. data/cpp/arduino/include/iom169a.h +44 -0
  97. data/cpp/arduino/include/iom169p.h +1097 -0
  98. data/cpp/arduino/include/iom169pa.h +1485 -0
  99. data/cpp/arduino/include/iom16a.h +923 -0
  100. data/cpp/arduino/include/iom16hva.h +80 -0
  101. data/cpp/arduino/include/iom16hva2.h +883 -0
  102. data/cpp/arduino/include/iom16hvb.h +1052 -0
  103. data/cpp/arduino/include/iom16hvbrevb.h +1052 -0
  104. data/cpp/arduino/include/iom16m1.h +1571 -0
  105. data/cpp/arduino/include/iom16u2.h +1000 -0
  106. data/cpp/arduino/include/iom16u4.h +1423 -0
  107. data/cpp/arduino/include/iom2560.h +101 -0
  108. data/cpp/arduino/include/iom2561.h +101 -0
  109. data/cpp/arduino/include/iom2564rfr2.h +2691 -0
  110. data/cpp/arduino/include/iom256rfr2.h +2707 -0
  111. data/cpp/arduino/include/iom3000.h +237 -0
  112. data/cpp/arduino/include/iom32.h +755 -0
  113. data/cpp/arduino/include/iom323.h +744 -0
  114. data/cpp/arduino/include/iom324a.h +1014 -0
  115. data/cpp/arduino/include/iom324p.h +1016 -0
  116. data/cpp/arduino/include/iom324pa.h +1372 -0
  117. data/cpp/arduino/include/iom325.h +886 -0
  118. data/cpp/arduino/include/iom3250.h +982 -0
  119. data/cpp/arduino/include/iom3250a.h +34 -0
  120. data/cpp/arduino/include/iom3250p.h +34 -0
  121. data/cpp/arduino/include/iom3250pa.h +1042 -0
  122. data/cpp/arduino/include/iom325a.h +34 -0
  123. data/cpp/arduino/include/iom325p.h +34 -0
  124. data/cpp/arduino/include/iom325pa.h +937 -0
  125. data/cpp/arduino/include/iom328.h +34 -0
  126. data/cpp/arduino/include/iom328p.h +948 -0
  127. data/cpp/arduino/include/iom329.h +1069 -0
  128. data/cpp/arduino/include/iom3290.h +1227 -0
  129. data/cpp/arduino/include/iom3290a.h +34 -0
  130. data/cpp/arduino/include/iom3290pa.h +1123 -0
  131. data/cpp/arduino/include/iom329a.h +34 -0
  132. data/cpp/arduino/include/iom329p.h +1164 -0
  133. data/cpp/arduino/include/iom329pa.h +34 -0
  134. data/cpp/arduino/include/iom32a.h +686 -0
  135. data/cpp/arduino/include/iom32c1.h +1320 -0
  136. data/cpp/arduino/include/iom32hvb.h +1052 -0
  137. data/cpp/arduino/include/iom32hvbrevb.h +953 -0
  138. data/cpp/arduino/include/iom32m1.h +1625 -0
  139. data/cpp/arduino/include/iom32u2.h +1000 -0
  140. data/cpp/arduino/include/iom32u4.h +1512 -0
  141. data/cpp/arduino/include/iom32u6.h +1431 -0
  142. data/cpp/arduino/include/iom406.h +783 -0
  143. data/cpp/arduino/include/iom48.h +93 -0
  144. data/cpp/arduino/include/iom48a.h +35 -0
  145. data/cpp/arduino/include/iom48p.h +936 -0
  146. data/cpp/arduino/include/iom48pa.h +839 -0
  147. data/cpp/arduino/include/iom48pb.h +890 -0
  148. data/cpp/arduino/include/iom64.h +1311 -0
  149. data/cpp/arduino/include/iom640.h +101 -0
  150. data/cpp/arduino/include/iom644.h +101 -0
  151. data/cpp/arduino/include/iom644a.h +34 -0
  152. data/cpp/arduino/include/iom644p.h +101 -0
  153. data/cpp/arduino/include/iom644pa.h +1387 -0
  154. data/cpp/arduino/include/iom644rfr2.h +2685 -0
  155. data/cpp/arduino/include/iom645.h +881 -0
  156. data/cpp/arduino/include/iom6450.h +978 -0
  157. data/cpp/arduino/include/iom6450a.h +34 -0
  158. data/cpp/arduino/include/iom6450p.h +34 -0
  159. data/cpp/arduino/include/iom645a.h +34 -0
  160. data/cpp/arduino/include/iom645p.h +34 -0
  161. data/cpp/arduino/include/iom649.h +1061 -0
  162. data/cpp/arduino/include/iom6490.h +1182 -0
  163. data/cpp/arduino/include/iom6490a.h +34 -0
  164. data/cpp/arduino/include/iom6490p.h +34 -0
  165. data/cpp/arduino/include/iom649a.h +34 -0
  166. data/cpp/arduino/include/iom649p.h +1490 -0
  167. data/cpp/arduino/include/iom64a.h +1084 -0
  168. data/cpp/arduino/include/iom64c1.h +1321 -0
  169. data/cpp/arduino/include/iom64hve.h +1034 -0
  170. data/cpp/arduino/include/iom64hve2.h +767 -0
  171. data/cpp/arduino/include/iom64m1.h +1572 -0
  172. data/cpp/arduino/include/iom64rfr2.h +2701 -0
  173. data/cpp/arduino/include/iom8.h +665 -0
  174. data/cpp/arduino/include/iom8515.h +687 -0
  175. data/cpp/arduino/include/iom8535.h +772 -0
  176. data/cpp/arduino/include/iom88.h +97 -0
  177. data/cpp/arduino/include/iom88a.h +35 -0
  178. data/cpp/arduino/include/iom88p.h +941 -0
  179. data/cpp/arduino/include/iom88pa.h +1185 -0
  180. data/cpp/arduino/include/iom88pb.h +899 -0
  181. data/cpp/arduino/include/iom8a.h +621 -0
  182. data/cpp/arduino/include/iom8hva.h +76 -0
  183. data/cpp/arduino/include/iom8u2.h +997 -0
  184. data/cpp/arduino/include/iomx8.h +808 -0
  185. data/cpp/arduino/include/iomxx0_1.h +1692 -0
  186. data/cpp/arduino/include/iomxx4.h +954 -0
  187. data/cpp/arduino/include/iomxxhva.h +550 -0
  188. data/cpp/arduino/include/iotn10.h +512 -0
  189. data/cpp/arduino/include/iotn11.h +255 -0
  190. data/cpp/arduino/include/iotn12.h +288 -0
  191. data/cpp/arduino/include/iotn13.h +395 -0
  192. data/cpp/arduino/include/iotn13a.h +394 -0
  193. data/cpp/arduino/include/iotn15.h +363 -0
  194. data/cpp/arduino/include/iotn1634.h +914 -0
  195. data/cpp/arduino/include/iotn167.h +883 -0
  196. data/cpp/arduino/include/iotn20.h +776 -0
  197. data/cpp/arduino/include/iotn22.h +221 -0
  198. data/cpp/arduino/include/iotn2313.h +702 -0
  199. data/cpp/arduino/include/iotn2313a.h +812 -0
  200. data/cpp/arduino/include/iotn24.h +94 -0
  201. data/cpp/arduino/include/iotn24a.h +846 -0
  202. data/cpp/arduino/include/iotn25.h +93 -0
  203. data/cpp/arduino/include/iotn26.h +422 -0
  204. data/cpp/arduino/include/iotn261.h +93 -0
  205. data/cpp/arduino/include/iotn261a.h +987 -0
  206. data/cpp/arduino/include/iotn28.h +297 -0
  207. data/cpp/arduino/include/iotn4.h +477 -0
  208. data/cpp/arduino/include/iotn40.h +767 -0
  209. data/cpp/arduino/include/iotn4313.h +813 -0
  210. data/cpp/arduino/include/iotn43u.h +604 -0
  211. data/cpp/arduino/include/iotn44.h +94 -0
  212. data/cpp/arduino/include/iotn441.h +903 -0
  213. data/cpp/arduino/include/iotn44a.h +844 -0
  214. data/cpp/arduino/include/iotn45.h +93 -0
  215. data/cpp/arduino/include/iotn461.h +94 -0
  216. data/cpp/arduino/include/iotn461a.h +987 -0
  217. data/cpp/arduino/include/iotn48.h +806 -0
  218. data/cpp/arduino/include/iotn5.h +512 -0
  219. data/cpp/arduino/include/iotn828.h +911 -0
  220. data/cpp/arduino/include/iotn84.h +94 -0
  221. data/cpp/arduino/include/iotn841.h +903 -0
  222. data/cpp/arduino/include/iotn84a.h +844 -0
  223. data/cpp/arduino/include/iotn85.h +93 -0
  224. data/cpp/arduino/include/iotn861.h +94 -0
  225. data/cpp/arduino/include/iotn861a.h +988 -0
  226. data/cpp/arduino/include/iotn87.h +859 -0
  227. data/cpp/arduino/include/iotn88.h +806 -0
  228. data/cpp/arduino/include/iotn9.h +477 -0
  229. data/cpp/arduino/include/iotnx4.h +482 -0
  230. data/cpp/arduino/include/iotnx5.h +442 -0
  231. data/cpp/arduino/include/iotnx61.h +541 -0
  232. data/cpp/arduino/include/iousb1286.h +101 -0
  233. data/cpp/arduino/include/iousb1287.h +101 -0
  234. data/cpp/arduino/include/iousb162.h +101 -0
  235. data/cpp/arduino/include/iousb646.h +102 -0
  236. data/cpp/arduino/include/iousb647.h +102 -0
  237. data/cpp/arduino/include/iousb82.h +95 -0
  238. data/cpp/arduino/include/iousbxx2.h +807 -0
  239. data/cpp/arduino/include/iousbxx6_7.h +1336 -0
  240. data/cpp/arduino/include/iox128a1.h +7236 -0
  241. data/cpp/arduino/include/iox128a1u.h +8305 -0
  242. data/cpp/arduino/include/iox128a3.h +6987 -0
  243. data/cpp/arduino/include/iox128a3u.h +7697 -0
  244. data/cpp/arduino/include/iox128a4u.h +7309 -0
  245. data/cpp/arduino/include/iox128b1.h +6872 -0
  246. data/cpp/arduino/include/iox128b3.h +6288 -0
  247. data/cpp/arduino/include/iox128c3.h +6264 -0
  248. data/cpp/arduino/include/iox128d3.h +5749 -0
  249. data/cpp/arduino/include/iox128d4.h +5562 -0
  250. data/cpp/arduino/include/iox16a4.h +6748 -0
  251. data/cpp/arduino/include/iox16a4u.h +7309 -0
  252. data/cpp/arduino/include/iox16c4.h +6078 -0
  253. data/cpp/arduino/include/iox16d4.h +5717 -0
  254. data/cpp/arduino/include/iox16e5.h +7699 -0
  255. data/cpp/arduino/include/iox192a3.h +6987 -0
  256. data/cpp/arduino/include/iox192a3u.h +7697 -0
  257. data/cpp/arduino/include/iox192c3.h +6264 -0
  258. data/cpp/arduino/include/iox192d3.h +5749 -0
  259. data/cpp/arduino/include/iox256a3.h +6987 -0
  260. data/cpp/arduino/include/iox256a3b.h +6983 -0
  261. data/cpp/arduino/include/iox256a3bu.h +7706 -0
  262. data/cpp/arduino/include/iox256a3u.h +7697 -0
  263. data/cpp/arduino/include/iox256c3.h +6264 -0
  264. data/cpp/arduino/include/iox256d3.h +5709 -0
  265. data/cpp/arduino/include/iox32a4.h +6747 -0
  266. data/cpp/arduino/include/iox32a4u.h +7309 -0
  267. data/cpp/arduino/include/iox32c3.h +6264 -0
  268. data/cpp/arduino/include/iox32c4.h +6078 -0
  269. data/cpp/arduino/include/iox32d3.h +5105 -0
  270. data/cpp/arduino/include/iox32d4.h +5685 -0
  271. data/cpp/arduino/include/iox32e5.h +7699 -0
  272. data/cpp/arduino/include/iox384c3.h +6849 -0
  273. data/cpp/arduino/include/iox384d3.h +5833 -0
  274. data/cpp/arduino/include/iox64a1.h +7236 -0
  275. data/cpp/arduino/include/iox64a1u.h +8305 -0
  276. data/cpp/arduino/include/iox64a3.h +6987 -0
  277. data/cpp/arduino/include/iox64a3u.h +7697 -0
  278. data/cpp/arduino/include/iox64a4u.h +7309 -0
  279. data/cpp/arduino/include/iox64b1.h +6454 -0
  280. data/cpp/arduino/include/iox64b3.h +6288 -0
  281. data/cpp/arduino/include/iox64c3.h +6264 -0
  282. data/cpp/arduino/include/iox64d3.h +5764 -0
  283. data/cpp/arduino/include/iox64d4.h +5555 -0
  284. data/cpp/arduino/include/iox8e5.h +7699 -0
  285. data/cpp/arduino/include/lock.h +239 -0
  286. data/cpp/arduino/include/portpins.h +549 -0
  287. data/cpp/arduino/include/version.h +90 -0
  288. data/cpp/arduino/include/xmega.h +71 -0
  289. data/cpp/unittest/Assertion.h +9 -4
  290. data/cpp/unittest/Compare.h +93 -0
  291. data/lib/arduino_ci/arduino_installation.rb +1 -1
  292. data/lib/arduino_ci/cpp_library.rb +4 -1
  293. data/lib/arduino_ci/version.rb +1 -1
  294. data/misc/default.yaml +7 -0
  295. metadata +285 -2
@@ -0,0 +1,2706 @@
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+ /*****************************************************************************
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+ *
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+ * Copyright (C) 2016 Atmel Corporation
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+ * All rights reserved.
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+ *
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+ * Redistribution and use in source and binary forms, with or without
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+ * modification, are permitted provided that the following conditions are met:
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+ *
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+ * * Redistributions of source code must retain the above copyright
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+ * notice, this list of conditions and the following disclaimer.
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+ *
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+ * * Redistributions in binary form must reproduce the above copyright
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+ * notice, this list of conditions and the following disclaimer in
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+ * the documentation and/or other materials provided with the
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+ * distribution.
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+ *
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+ * * Neither the name of the copyright holders nor the names of
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+ * contributors may be used to endorse or promote products derived
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+ * from this software without specific prior written permission.
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+ *
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+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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+ * POSSIBILITY OF SUCH DAMAGE.
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+ ****************************************************************************/
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+
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+
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+ #ifndef _AVR_ATMEGA128RFR2_H_INCLUDED
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+ #define _AVR_ATMEGA128RFR2_H_INCLUDED
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+
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+
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+ #ifndef _AVR_IO_H_
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+ # error "Include <avr/io.h> instead of this file."
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+ #endif
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+
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+ #ifndef _AVR_IOXXX_H_
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+ # define _AVR_IOXXX_H_ "iom128rfr2.h"
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+ #else
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+ # error "Attempt to include more than one <avr/ioXXX.h> file."
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+ #endif
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+
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+ /* Registers and associated bit numbers */
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+
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+ #define PINA _SFR_IO8(0x00)
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+ #define PINA7 7
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+ #define PINA6 6
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+ #define PINA5 5
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+ #define PINA4 4
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+ #define PINA3 3
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+ #define PINA2 2
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+ #define PINA1 1
59
+ #define PINA0 0
60
+
61
+ #define DDRA _SFR_IO8(0x01)
62
+ #define DDRA7 7
63
+ // Inserted "DDA7" from "DDRA7" due to compatibility
64
+ #define DDA7 7
65
+ #define DDRA6 6
66
+ // Inserted "DDA6" from "DDRA6" due to compatibility
67
+ #define DDA6 6
68
+ #define DDRA5 5
69
+ // Inserted "DDA5" from "DDRA5" due to compatibility
70
+ #define DDA5 5
71
+ #define DDRA4 4
72
+ // Inserted "DDA4" from "DDRA4" due to compatibility
73
+ #define DDA4 4
74
+ #define DDRA3 3
75
+ // Inserted "DDA3" from "DDRA3" due to compatibility
76
+ #define DDA3 3
77
+ #define DDRA2 2
78
+ // Inserted "DDA2" from "DDRA2" due to compatibility
79
+ #define DDA2 2
80
+ #define DDRA1 1
81
+ // Inserted "DDA1" from "DDRA1" due to compatibility
82
+ #define DDA1 1
83
+ #define DDRA0 0
84
+ // Inserted "DDA0" from "DDRA0" due to compatibility
85
+ #define DDA0 0
86
+
87
+ #define PORTA _SFR_IO8(0x02)
88
+ #define PORTA7 7
89
+ #define PORTA6 6
90
+ #define PORTA5 5
91
+ #define PORTA4 4
92
+ #define PORTA3 3
93
+ #define PORTA2 2
94
+ #define PORTA1 1
95
+ #define PORTA0 0
96
+
97
+ #define PINB _SFR_IO8(0x03)
98
+ #define PINB7 7
99
+ #define PINB6 6
100
+ #define PINB5 5
101
+ #define PINB4 4
102
+ #define PINB3 3
103
+ #define PINB2 2
104
+ #define PINB1 1
105
+ #define PINB0 0
106
+
107
+ #define DDRB _SFR_IO8(0x04)
108
+ #define DDRB7 7
109
+ // Inserted "DDB7" from "DDRB7" due to compatibility
110
+ #define DDB7 7
111
+ #define DDRB6 6
112
+ // Inserted "DDB6" from "DDRB6" due to compatibility
113
+ #define DDB6 6
114
+ #define DDRB5 5
115
+ // Inserted "DDB5" from "DDRB5" due to compatibility
116
+ #define DDB5 5
117
+ #define DDRB4 4
118
+ // Inserted "DDB4" from "DDRB4" due to compatibility
119
+ #define DDB4 4
120
+ #define DDRB3 3
121
+ // Inserted "DDB3" from "DDRB3" due to compatibility
122
+ #define DDB3 3
123
+ #define DDRB2 2
124
+ // Inserted "DDB2" from "DDRB2" due to compatibility
125
+ #define DDB2 2
126
+ #define DDRB1 1
127
+ // Inserted "DDB1" from "DDRB1" due to compatibility
128
+ #define DDB1 1
129
+ #define DDRB0 0
130
+ // Inserted "DDB0" from "DDRB0" due to compatibility
131
+ #define DDB0 0
132
+
133
+ #define PORTB _SFR_IO8(0x05)
134
+ #define PORTB7 7
135
+ #define PORTB6 6
136
+ #define PORTB5 5
137
+ #define PORTB4 4
138
+ #define PORTB3 3
139
+ #define PORTB2 2
140
+ #define PORTB1 1
141
+ #define PORTB0 0
142
+
143
+ #define PINC _SFR_IO8(0x06)
144
+ #define PINC7 7
145
+ #define PINC6 6
146
+ #define PINC5 5
147
+ #define PINC4 4
148
+ #define PINC3 3
149
+ #define PINC2 2
150
+ #define PINC1 1
151
+ #define PINC0 0
152
+
153
+ #define DDRC _SFR_IO8(0x07)
154
+ #define DDRC7 7
155
+ // Inserted "DDC7" from "DDRC7" due to compatibility
156
+ #define DDC7 7
157
+ #define DDRC6 6
158
+ // Inserted "DDC6" from "DDRC6" due to compatibility
159
+ #define DDC6 6
160
+ #define DDRC5 5
161
+ // Inserted "DDC5" from "DDRC5" due to compatibility
162
+ #define DDC5 5
163
+ #define DDRC4 4
164
+ // Inserted "DDC4" from "DDRC4" due to compatibility
165
+ #define DDC4 4
166
+ #define DDRC3 3
167
+ // Inserted "DDC3" from "DDRC3" due to compatibility
168
+ #define DDC3 3
169
+ #define DDRC2 2
170
+ // Inserted "DDC2" from "DDRC2" due to compatibility
171
+ #define DDC2 2
172
+ #define DDRC1 1
173
+ // Inserted "DDC1" from "DDRC1" due to compatibility
174
+ #define DDC1 1
175
+ #define DDRC0 0
176
+ // Inserted "DDC0" from "DDRC0" due to compatibility
177
+ #define DDC0 0
178
+
179
+ #define PORTC _SFR_IO8(0x08)
180
+ #define PORTC7 7
181
+ #define PORTC6 6
182
+ #define PORTC5 5
183
+ #define PORTC4 4
184
+ #define PORTC3 3
185
+ #define PORTC2 2
186
+ #define PORTC1 1
187
+ #define PORTC0 0
188
+
189
+ #define PIND _SFR_IO8(0x09)
190
+ #define PIND7 7
191
+ #define PIND6 6
192
+ #define PIND5 5
193
+ #define PIND4 4
194
+ #define PIND3 3
195
+ #define PIND2 2
196
+ #define PIND1 1
197
+ #define PIND0 0
198
+
199
+ #define DDRD _SFR_IO8(0x0A)
200
+ #define DDRD7 7
201
+ // Inserted "DDD7" from "DDRD7" due to compatibility
202
+ #define DDD7 7
203
+ #define DDRD6 6
204
+ // Inserted "DDD6" from "DDRD6" due to compatibility
205
+ #define DDD6 6
206
+ #define DDRD5 5
207
+ // Inserted "DDD5" from "DDRD5" due to compatibility
208
+ #define DDD5 5
209
+ #define DDRD4 4
210
+ // Inserted "DDD4" from "DDRD4" due to compatibility
211
+ #define DDD4 4
212
+ #define DDRD3 3
213
+ // Inserted "DDD3" from "DDRD3" due to compatibility
214
+ #define DDD3 3
215
+ #define DDRD2 2
216
+ // Inserted "DDD2" from "DDRD2" due to compatibility
217
+ #define DDD2 2
218
+ #define DDRD1 1
219
+ // Inserted "DDD1" from "DDRD1" due to compatibility
220
+ #define DDD1 1
221
+ #define DDRD0 0
222
+ // Inserted "DDD0" from "DDRD0" due to compatibility
223
+ #define DDD0 0
224
+
225
+ #define PORTD _SFR_IO8(0x0B)
226
+ #define PORTD7 7
227
+ #define PORTD6 6
228
+ #define PORTD5 5
229
+ #define PORTD4 4
230
+ #define PORTD3 3
231
+ #define PORTD2 2
232
+ #define PORTD1 1
233
+ #define PORTD0 0
234
+
235
+ #define PINE _SFR_IO8(0x0C)
236
+ #define PINE7 7
237
+ #define PINE6 6
238
+ #define PINE5 5
239
+ #define PINE4 4
240
+ #define PINE3 3
241
+ #define PINE2 2
242
+ #define PINE1 1
243
+ #define PINE0 0
244
+
245
+ #define DDRE _SFR_IO8(0x0D)
246
+ #define DDRE7 7
247
+ // Inserted "DDE7" from "DDRE7" due to compatibility
248
+ #define DDE7 7
249
+ #define DDRE6 6
250
+ // Inserted "DDE6" from "DDRE6" due to compatibility
251
+ #define DDE6 6
252
+ #define DDRE5 5
253
+ // Inserted "DDE5" from "DDRE5" due to compatibility
254
+ #define DDE5 5
255
+ #define DDRE4 4
256
+ // Inserted "DDE4" from "DDRE4" due to compatibility
257
+ #define DDE4 4
258
+ #define DDRE3 3
259
+ // Inserted "DDE3" from "DDRE3" due to compatibility
260
+ #define DDE3 3
261
+ #define DDRE2 2
262
+ // Inserted "DDE2" from "DDRE2" due to compatibility
263
+ #define DDE2 2
264
+ #define DDRE1 1
265
+ // Inserted "DDE1" from "DDRE1" due to compatibility
266
+ #define DDE1 1
267
+ #define DDRE0 0
268
+ // Inserted "DDE0" from "DDRE0" due to compatibility
269
+ #define DDE0 0
270
+
271
+ #define PORTE _SFR_IO8(0x0E)
272
+ #define PORTE7 7
273
+ #define PORTE6 6
274
+ #define PORTE5 5
275
+ #define PORTE4 4
276
+ #define PORTE3 3
277
+ #define PORTE2 2
278
+ #define PORTE1 1
279
+ #define PORTE0 0
280
+
281
+ #define PINF _SFR_IO8(0x0F)
282
+ #define PINF7 7
283
+ #define PINF6 6
284
+ #define PINF5 5
285
+ #define PINF4 4
286
+ #define PINF3 3
287
+ #define PINF2 2
288
+ #define PINF1 1
289
+ #define PINF0 0
290
+
291
+ #define DDRF _SFR_IO8(0x10)
292
+ #define DDRF7 7
293
+ // Inserted "DDF7" from "DDRF7" due to compatibility
294
+ #define DDF7 7
295
+ #define DDRF6 6
296
+ // Inserted "DDF6" from "DDRF6" due to compatibility
297
+ #define DDF6 6
298
+ #define DDRF5 5
299
+ // Inserted "DDF5" from "DDRF5" due to compatibility
300
+ #define DDF5 5
301
+ #define DDRF4 4
302
+ // Inserted "DDF4" from "DDRF4" due to compatibility
303
+ #define DDF4 4
304
+ #define DDRF3 3
305
+ // Inserted "DDF3" from "DDRF3" due to compatibility
306
+ #define DDF3 3
307
+ #define DDRF2 2
308
+ // Inserted "DDF2" from "DDRF2" due to compatibility
309
+ #define DDF2 2
310
+ #define DDRF1 1
311
+ // Inserted "DDF1" from "DDRF1" due to compatibility
312
+ #define DDF1 1
313
+ #define DDRF0 0
314
+ // Inserted "DDF0" from "DDRF0" due to compatibility
315
+ #define DDF0 0
316
+
317
+ #define PORTF _SFR_IO8(0x11)
318
+ #define PORTF7 7
319
+ #define PORTF6 6
320
+ #define PORTF5 5
321
+ #define PORTF4 4
322
+ #define PORTF3 3
323
+ #define PORTF2 2
324
+ #define PORTF1 1
325
+ #define PORTF0 0
326
+
327
+ #define PING _SFR_IO8(0x12)
328
+ #define PING7 7
329
+ #define PING6 6
330
+ #define PING5 5
331
+ #define PING4 4
332
+ #define PING3 3
333
+ #define PING2 2
334
+ #define PING1 1
335
+ #define PING0 0
336
+
337
+ #define DDRG _SFR_IO8(0x13)
338
+ #define DDRG7 7
339
+ // Inserted "DDG7" from "DDRG7" due to compatibility
340
+ #define DDG7 7
341
+ #define DDRG6 6
342
+ // Inserted "DDG6" from "DDRG6" due to compatibility
343
+ #define DDG6 6
344
+ #define DDRG5 5
345
+ // Inserted "DDG5" from "DDRG5" due to compatibility
346
+ #define DDG5 5
347
+ #define DDRG4 4
348
+ // Inserted "DDG4" from "DDRG4" due to compatibility
349
+ #define DDG4 4
350
+ #define DDRG3 3
351
+ // Inserted "DDG3" from "DDRG3" due to compatibility
352
+ #define DDG3 3
353
+ #define DDRG2 2
354
+ // Inserted "DDG2" from "DDRG2" due to compatibility
355
+ #define DDG2 2
356
+ #define DDRG1 1
357
+ // Inserted "DDG1" from "DDRG1" due to compatibility
358
+ #define DDG1 1
359
+ #define DDRG0 0
360
+ // Inserted "DDG0" from "DDRG0" due to compatibility
361
+ #define DDG0 0
362
+
363
+ #define PORTG _SFR_IO8(0x14)
364
+ #define PORTG7 7
365
+ #define PORTG6 6
366
+ #define PORTG5 5
367
+ #define PORTG4 4
368
+ #define PORTG3 3
369
+ #define PORTG2 2
370
+ #define PORTG1 1
371
+ #define PORTG0 0
372
+
373
+ #define TIFR0 _SFR_IO8(0x15)
374
+ #define TOV0 0
375
+ #define OCF0A 1
376
+ #define OCF0B 2
377
+ #define Res0 3
378
+ #define Res1 4
379
+ #define Res2 5
380
+ #define Res3 6
381
+ #define Res4 7
382
+
383
+ #define TIFR1 _SFR_IO8(0x16)
384
+ #define TOV1 0
385
+ #define OCF1A 1
386
+ #define OCF1B 2
387
+ #define OCF1C 3
388
+ #define ICF1 5
389
+
390
+ #define TIFR2 _SFR_IO8(0x17)
391
+ #define TOV2 0
392
+ #define OCF2A 1
393
+ #define OCF2B 2
394
+
395
+ #define TIFR3 _SFR_IO8(0x18)
396
+ #define TOV3 0
397
+ #define OCF3A 1
398
+ #define OCF3B 2
399
+ #define OCF3C 3
400
+ #define ICF3 5
401
+
402
+ #define TIFR4 _SFR_IO8(0x19)
403
+ #define TOV4 0
404
+ #define OCF4A 1
405
+ #define OCF4B 2
406
+ #define OCF4C 3
407
+ #define ICF4 5
408
+
409
+ #define TIFR5 _SFR_IO8(0x1A)
410
+ #define TOV5 0
411
+ #define OCF5A 1
412
+ #define OCF5B 2
413
+ #define OCF5C 3
414
+ #define ICF5 5
415
+
416
+ #define PCIFR _SFR_IO8(0x1B)
417
+ #define PCIF0 0
418
+ #define PCIF1 1
419
+ #define PCIF2 2
420
+
421
+ #define EIFR _SFR_IO8(0x1C)
422
+ #define INTF0 0
423
+ #define INTF1 1
424
+ #define INTF2 2
425
+ #define INTF3 3
426
+ #define INTF4 4
427
+ #define INTF5 5
428
+ #define INTF6 6
429
+ #define INTF7 7
430
+
431
+ #define EIMSK _SFR_IO8(0x1D)
432
+ #define INT0 0
433
+ #define INT1 1
434
+ #define INT2 2
435
+ #define INT3 3
436
+ #define INT4 4
437
+ #define INT5 5
438
+ #define INT6 6
439
+ #define INT7 7
440
+
441
+ #define GPIOR0 _SFR_IO8(0x1E)
442
+ #define GPIOR00 0
443
+ #define GPIOR01 1
444
+ #define GPIOR02 2
445
+ #define GPIOR03 3
446
+ #define GPIOR04 4
447
+ #define GPIOR05 5
448
+ #define GPIOR06 6
449
+ #define GPIOR07 7
450
+
451
+ #define EECR _SFR_IO8(0x1F)
452
+ #define EERE 0
453
+ #define EEPE 1
454
+ #define EEMPE 2
455
+ #define EERIE 3
456
+ #define EEPM0 4
457
+ #define EEPM1 5
458
+
459
+ #define EEDR _SFR_IO8(0x20)
460
+
461
+ /* Combine EEARL and EEARH */
462
+ #define EEAR _SFR_IO16(0x21)
463
+
464
+ #define EEARL _SFR_IO8(0x21)
465
+ #define EEARH _SFR_IO8(0x22)
466
+
467
+ #define GTCCR _SFR_IO8(0x23)
468
+ #define PSRSYNC 0
469
+ #define PSRASY 1
470
+ #define TSM 7
471
+
472
+ #define TCCR0A _SFR_IO8(0x24)
473
+ #define WGM00 0
474
+ #define WGM01 1
475
+ #define COM0B0 4
476
+ #define COM0B1 5
477
+ #define COM0A0 6
478
+ #define COM0A1 7
479
+
480
+ #define TCCR0B _SFR_IO8(0x25)
481
+ #define CS00 0
482
+ #define CS01 1
483
+ #define CS02 2
484
+ #define WGM02 3
485
+ #define FOC0B 6
486
+ #define FOC0A 7
487
+
488
+ #define TCNT0 _SFR_IO8(0x26)
489
+
490
+ #define OCR0A _SFR_IO8(0x27)
491
+
492
+ #define OCR0B _SFR_IO8(0x28)
493
+
494
+ /* Reserved [0x29] */
495
+
496
+ #define GPIOR1 _SFR_IO8(0x2A)
497
+ #define GPIOR10 0
498
+ #define GPIOR11 1
499
+ #define GPIOR12 2
500
+ #define GPIOR13 3
501
+ #define GPIOR14 4
502
+ #define GPIOR15 5
503
+ #define GPIOR16 6
504
+ #define GPIOR17 7
505
+
506
+ #define GPIOR2 _SFR_IO8(0x2B)
507
+ #define GPIOR20 0
508
+ #define GPIOR21 1
509
+ #define GPIOR22 2
510
+ #define GPIOR23 3
511
+ #define GPIOR24 4
512
+ #define GPIOR25 5
513
+ #define GPIOR26 6
514
+ #define GPIOR27 7
515
+
516
+ #define SPCR _SFR_IO8(0x2C)
517
+ #define SPR0 0
518
+ #define SPR1 1
519
+ #define CPHA 2
520
+ #define CPOL 3
521
+ #define MSTR 4
522
+ #define DORD 5
523
+ #define SPE 6
524
+ #define SPIE 7
525
+
526
+ #define SPSR _SFR_IO8(0x2D)
527
+ #define SPI2X 0
528
+ #define WCOL 6
529
+ #define SPIF 7
530
+
531
+ #define SPDR _SFR_IO8(0x2E)
532
+
533
+ /* Reserved [0x2F] */
534
+
535
+ #define ACSR _SFR_IO8(0x30)
536
+ #define ACIS0 0
537
+ #define ACIS1 1
538
+ #define ACIC 2
539
+ #define ACIE 3
540
+ #define ACI 4
541
+ #define ACO 5
542
+ #define ACBG 6
543
+ #define ACD 7
544
+
545
+ #define OCDR _SFR_IO8(0x31)
546
+ #define OCDR0 0
547
+ #define OCDR1 1
548
+ #define OCDR2 2
549
+ #define OCDR3 3
550
+ #define OCDR4 4
551
+ #define OCDR5 5
552
+ #define OCDR6 6
553
+ #define OCDR7 7
554
+
555
+ /* Reserved [0x32] */
556
+
557
+ #define SMCR _SFR_IO8(0x33)
558
+ #define SE 0
559
+ #define SM0 1
560
+ #define SM1 2
561
+ #define SM2 3
562
+
563
+ #define MCUSR _SFR_IO8(0x34)
564
+ #define JTRF 4
565
+ #define PORF 0
566
+ #define EXTRF 1
567
+ #define BORF 2
568
+ #define WDRF 3
569
+
570
+ #define MCUCR _SFR_IO8(0x35)
571
+ #define JTD 7
572
+ #define IVCE 0
573
+ #define IVSEL 1
574
+ #define PUD 4
575
+
576
+ /* Reserved [0x36] */
577
+
578
+ #define SPMCSR _SFR_IO8(0x37)
579
+ #define SPMEN 0
580
+ #define PGERS 1
581
+ #define PGWRT 2
582
+ #define BLBSET 3
583
+ #define RWWSRE 4
584
+ #define SIGRD 5
585
+ #define RWWSB 6
586
+ #define SPMIE 7
587
+
588
+ /* Reserved [0x38..0x3A] */
589
+
590
+ #define RAMPZ _SFR_IO8(0x3B)
591
+ #define RAMPZ0 0
592
+ #define Res5 6
593
+ #define Res6 7
594
+
595
+ /* Reserved [0x3C] */
596
+
597
+ /* SP [0x3D..0x3E] */
598
+
599
+ /* SREG [0x3F] */
600
+
601
+ #define WDTCSR _SFR_MEM8(0x60)
602
+ #define WDE 3
603
+ #define WDCE 4
604
+ #define WDP0 0
605
+ #define WDP1 1
606
+ #define WDP2 2
607
+ #define WDP3 5
608
+ #define WDIE 6
609
+ #define WDIF 7
610
+
611
+ #define CLKPR _SFR_MEM8(0x61)
612
+ #define CLKPS0 0
613
+ #define CLKPS1 1
614
+ #define CLKPS2 2
615
+ #define CLKPS3 3
616
+ #define CLKPCE 7
617
+
618
+ /* Reserved [0x62] */
619
+
620
+ #define PRR2 _SFR_MEM8(0x63)
621
+ #define PRRAM0 0
622
+ #define PRRAM1 1
623
+ #define PRRAM2 2
624
+ #define PRRAM3 3
625
+
626
+ #define __AVR_HAVE_PRR2 ((1<<PRRAM0)|(1<<PRRAM1)|(1<<PRRAM2)|(1<<PRRAM3))
627
+ #define __AVR_HAVE_PRR2_PRRAM0
628
+ #define __AVR_HAVE_PRR2_PRRAM1
629
+ #define __AVR_HAVE_PRR2_PRRAM2
630
+ #define __AVR_HAVE_PRR2_PRRAM3
631
+
632
+ #define PRR0 _SFR_MEM8(0x64)
633
+ #define PRADC 0
634
+ #define PRUSART0 1
635
+ #define PRSPI 2
636
+ #define PRTIM1 3
637
+ #define PRPGA 4
638
+ #define PRTIM0 5
639
+ #define PRTIM2 6
640
+ #define PRTWI 7
641
+
642
+ #define __AVR_HAVE_PRR0 ((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRPGA)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
643
+ #define __AVR_HAVE_PRR0_PRADC
644
+ #define __AVR_HAVE_PRR0_PRUSART0
645
+ #define __AVR_HAVE_PRR0_PRSPI
646
+ #define __AVR_HAVE_PRR0_PRTIM1
647
+ #define __AVR_HAVE_PRR0_PRPGA
648
+ #define __AVR_HAVE_PRR0_PRTIM0
649
+ #define __AVR_HAVE_PRR0_PRTIM2
650
+ #define __AVR_HAVE_PRR0_PRTWI
651
+
652
+ #define PRR1 _SFR_MEM8(0x65)
653
+ #define PRUSART1 0
654
+ #define PRTIM3 3
655
+ #define PRTIM4 4
656
+ #define PRTIM5 5
657
+ #define PRTRX24 6
658
+ #define Res 7
659
+
660
+ #define __AVR_HAVE_PRR1 ((1<<PRUSART1)|(1<<PRTIM3)|(1<<PRTIM4)|(1<<PRTIM5)|(1<<PRTRX24))
661
+ #define __AVR_HAVE_PRR1_PRUSART1
662
+ #define __AVR_HAVE_PRR1_PRTIM3
663
+ #define __AVR_HAVE_PRR1_PRTIM4
664
+ #define __AVR_HAVE_PRR1_PRTIM5
665
+ #define __AVR_HAVE_PRR1_PRTRX24
666
+
667
+ #define OSCCAL _SFR_MEM8(0x66)
668
+ #define CAL0 0
669
+ #define CAL1 1
670
+ #define CAL2 2
671
+ #define CAL3 3
672
+ #define CAL4 4
673
+ #define CAL5 5
674
+ #define CAL6 6
675
+ #define CAL7 7
676
+ #define OSCCAL0 0
677
+ #define OSCCAL1 1
678
+ #define OSCCAL2 2
679
+ #define OSCCAL3 3
680
+ #define OSCCAL4 4
681
+ #define OSCCAL5 5
682
+ #define OSCCAL6 6
683
+ #define OSCCAL7 7
684
+
685
+ #define BGCR _SFR_MEM8(0x67)
686
+ #define BGCAL0 0
687
+ #define BGCAL1 1
688
+ #define BGCAL2 2
689
+ #define BGCAL_FINE0 3
690
+ #define BGCAL_FINE1 4
691
+ #define BGCAL_FINE2 5
692
+ #define BGCAL_FINE3 6
693
+
694
+ #define PCICR _SFR_MEM8(0x68)
695
+ #define PCIE0 0
696
+ #define PCIE1 1
697
+ #define PCIE2 2
698
+
699
+ #define EICRA _SFR_MEM8(0x69)
700
+ #define ISC00 0
701
+ #define ISC01 1
702
+ #define ISC10 2
703
+ #define ISC11 3
704
+ #define ISC20 4
705
+ #define ISC21 5
706
+ #define ISC30 6
707
+ #define ISC31 7
708
+
709
+ #define EICRB _SFR_MEM8(0x6A)
710
+ #define ISC40 0
711
+ #define ISC41 1
712
+ #define ISC50 2
713
+ #define ISC51 3
714
+ #define ISC60 4
715
+ #define ISC61 5
716
+ #define ISC70 6
717
+ #define ISC71 7
718
+
719
+ #define PCMSK0 _SFR_MEM8(0x6B)
720
+ #define PCINT0 0
721
+ #define PCINT1 1
722
+ #define PCINT2 2
723
+ #define PCINT3 3
724
+ #define PCINT4 4
725
+ #define PCINT5 5
726
+ #define PCINT6 6
727
+ #define PCINT7 7
728
+
729
+ #define PCMSK1 _SFR_MEM8(0x6C)
730
+ #define PCINT8 0
731
+ #define PCINT9 1
732
+ #define PCINT10 2
733
+ #define PCINT11 3
734
+ #define PCINT12 4
735
+ #define PCINT13 5
736
+ #define PCINT14 6
737
+ #define PCINT15 7
738
+
739
+ #define PCMSK2 _SFR_MEM8(0x6D)
740
+ #define PCINT16 0
741
+ #define PCINT17 1
742
+ #define PCINT18 2
743
+ #define PCINT19 3
744
+ #define PCINT20 4
745
+ #define PCINT21 5
746
+ #define PCINT22 6
747
+ #define PCINT23 7
748
+
749
+ #define TIMSK0 _SFR_MEM8(0x6E)
750
+ #define TOIE0 0
751
+ #define OCIE0A 1
752
+ #define OCIE0B 2
753
+
754
+ #define TIMSK1 _SFR_MEM8(0x6F)
755
+ #define TOIE1 0
756
+ #define OCIE1A 1
757
+ #define OCIE1B 2
758
+ #define OCIE1C 3
759
+ #define ICIE1 5
760
+
761
+ #define TIMSK2 _SFR_MEM8(0x70)
762
+ #define TOIE2 0
763
+ #define OCIE2A 1
764
+ #define OCIE2B 2
765
+
766
+ #define TIMSK3 _SFR_MEM8(0x71)
767
+ #define TOIE3 0
768
+ #define OCIE3A 1
769
+ #define OCIE3B 2
770
+ #define OCIE3C 3
771
+ #define ICIE3 5
772
+
773
+ #define TIMSK4 _SFR_MEM8(0x72)
774
+ #define TOIE4 0
775
+ #define OCIE4A 1
776
+ #define OCIE4B 2
777
+ #define OCIE4C 3
778
+ #define ICIE4 5
779
+
780
+ #define TIMSK5 _SFR_MEM8(0x73)
781
+ #define TOIE5 0
782
+ #define OCIE5A 1
783
+ #define OCIE5B 2
784
+ #define OCIE5C 3
785
+ #define ICIE5 5
786
+
787
+ /* Reserved [0x74] */
788
+
789
+ #define NEMCR _SFR_MEM8(0x75)
790
+ #define AEAM0 4
791
+ #define AEAM1 5
792
+ #define ENEAM 6
793
+
794
+ /* Reserved [0x76] */
795
+
796
+ #define ADCSRC _SFR_MEM8(0x77)
797
+ #define ADSUT0 0
798
+ #define ADSUT1 1
799
+ #define ADSUT2 2
800
+ #define ADSUT3 3
801
+ #define ADSUT4 4
802
+ #define ADTHT0 6
803
+ #define ADTHT1 7
804
+
805
+ /* Combine ADCL and ADCH */
806
+ #ifndef __ASSEMBLER__
807
+ #define ADC _SFR_MEM16(0x78)
808
+ #endif
809
+ #define ADCW _SFR_MEM16(0x78)
810
+
811
+ #define ADCL _SFR_MEM8(0x78)
812
+ #define ADCH _SFR_MEM8(0x79)
813
+
814
+ #define ADCSRA _SFR_MEM8(0x7A)
815
+ #define ADPS0 0
816
+ #define ADPS1 1
817
+ #define ADPS2 2
818
+ #define ADIE 3
819
+ #define ADIF 4
820
+ #define ADATE 5
821
+ #define ADSC 6
822
+ #define ADEN 7
823
+
824
+ #define ADCSRB _SFR_MEM8(0x7B)
825
+ #define ACME 6
826
+ #define ADTS0 0
827
+ #define ADTS1 1
828
+ #define ADTS2 2
829
+ #define MUX5 3
830
+ #define ACCH 4
831
+ #define REFOK 5
832
+ #define AVDDOK 7
833
+
834
+ #define ADMUX _SFR_MEM8(0x7C)
835
+ #define MUX0 0
836
+ #define MUX1 1
837
+ #define MUX2 2
838
+ #define MUX3 3
839
+ #define MUX4 4
840
+ #define ADLAR 5
841
+ #define REFS0 6
842
+ #define REFS1 7
843
+
844
+ #define DIDR2 _SFR_MEM8(0x7D)
845
+ #define ADC8D 0
846
+ #define ADC9D 1
847
+ #define ADC10D 2
848
+ #define ADC11D 3
849
+ #define ADC12D 4
850
+ #define ADC13D 5
851
+ #define ADC14D 6
852
+ #define ADC15D 7
853
+
854
+ #define DIDR0 _SFR_MEM8(0x7E)
855
+ #define ADC0D 0
856
+ #define ADC1D 1
857
+ #define ADC2D 2
858
+ #define ADC3D 3
859
+ #define ADC4D 4
860
+ #define ADC5D 5
861
+ #define ADC6D 6
862
+ #define ADC7D 7
863
+
864
+ #define DIDR1 _SFR_MEM8(0x7F)
865
+ #define AIN0D 0
866
+ #define AIN1D 1
867
+
868
+ #define TCCR1A _SFR_MEM8(0x80)
869
+ #define WGM10 0
870
+ #define WGM11 1
871
+ #define COM1C0 2
872
+ #define COM1C1 3
873
+ #define COM1B0 4
874
+ #define COM1B1 5
875
+ #define COM1A0 6
876
+ #define COM1A1 7
877
+
878
+ #define TCCR1B _SFR_MEM8(0x81)
879
+ #define CS10 0
880
+ #define CS11 1
881
+ #define CS12 2
882
+ #define WGM12 3
883
+ #define WGM13 4
884
+ #define ICES1 6
885
+ #define ICNC1 7
886
+
887
+ #define TCCR1C _SFR_MEM8(0x82)
888
+ #define FOC1C 5
889
+ #define FOC1B 6
890
+ #define FOC1A 7
891
+
892
+ /* Reserved [0x83] */
893
+
894
+ /* Combine TCNT1L and TCNT1H */
895
+ #define TCNT1 _SFR_MEM16(0x84)
896
+
897
+ #define TCNT1L _SFR_MEM8(0x84)
898
+ #define TCNT1H _SFR_MEM8(0x85)
899
+
900
+ /* Combine ICR1L and ICR1H */
901
+ #define ICR1 _SFR_MEM16(0x86)
902
+
903
+ #define ICR1L _SFR_MEM8(0x86)
904
+ #define ICR1H _SFR_MEM8(0x87)
905
+
906
+ /* Combine OCR1AL and OCR1AH */
907
+ #define OCR1A _SFR_MEM16(0x88)
908
+
909
+ #define OCR1AL _SFR_MEM8(0x88)
910
+ #define OCR1AH _SFR_MEM8(0x89)
911
+
912
+ /* Combine OCR1BL and OCR1BH */
913
+ #define OCR1B _SFR_MEM16(0x8A)
914
+
915
+ #define OCR1BL _SFR_MEM8(0x8A)
916
+ #define OCR1BH _SFR_MEM8(0x8B)
917
+
918
+ /* Combine OCR1CL and OCR1CH */
919
+ #define OCR1C _SFR_MEM16(0x8C)
920
+
921
+ #define OCR1CL _SFR_MEM8(0x8C)
922
+ #define OCR1CH _SFR_MEM8(0x8D)
923
+
924
+ /* Reserved [0x8E..0x8F] */
925
+
926
+ #define TCCR3A _SFR_MEM8(0x90)
927
+ #define WGM30 0
928
+ #define WGM31 1
929
+ #define COM3C0 2
930
+ #define COM3C1 3
931
+ #define COM3B0 4
932
+ #define COM3B1 5
933
+ #define COM3A0 6
934
+ #define COM3A1 7
935
+
936
+ #define TCCR3B _SFR_MEM8(0x91)
937
+ #define CS30 0
938
+ #define CS31 1
939
+ #define CS32 2
940
+ #define WGM32 3
941
+ #define WGM33 4
942
+ #define ICES3 6
943
+ #define ICNC3 7
944
+
945
+ #define TCCR3C _SFR_MEM8(0x92)
946
+ #define FOC3C 5
947
+ #define FOC3B 6
948
+ #define FOC3A 7
949
+
950
+ /* Reserved [0x93] */
951
+
952
+ /* Combine TCNT3L and TCNT3H */
953
+ #define TCNT3 _SFR_MEM16(0x94)
954
+
955
+ #define TCNT3L _SFR_MEM8(0x94)
956
+ #define TCNT3H _SFR_MEM8(0x95)
957
+
958
+ /* Combine ICR3L and ICR3H */
959
+ #define ICR3 _SFR_MEM16(0x96)
960
+
961
+ #define ICR3L _SFR_MEM8(0x96)
962
+ #define ICR3H _SFR_MEM8(0x97)
963
+
964
+ /* Combine OCR3AL and OCR3AH */
965
+ #define OCR3A _SFR_MEM16(0x98)
966
+
967
+ #define OCR3AL _SFR_MEM8(0x98)
968
+ #define OCR3AH _SFR_MEM8(0x99)
969
+
970
+ /* Combine OCR3BL and OCR3BH */
971
+ #define OCR3B _SFR_MEM16(0x9A)
972
+
973
+ #define OCR3BL _SFR_MEM8(0x9A)
974
+ #define OCR3BH _SFR_MEM8(0x9B)
975
+
976
+ /* Combine OCR3CL and OCR3CH */
977
+ #define OCR3C _SFR_MEM16(0x9C)
978
+
979
+ #define OCR3CL _SFR_MEM8(0x9C)
980
+ #define OCR3CH _SFR_MEM8(0x9D)
981
+
982
+ /* Reserved [0x9E..0x9F] */
983
+
984
+ #define TCCR4A _SFR_MEM8(0xA0)
985
+ #define WGM40 0
986
+ #define WGM41 1
987
+ #define COM4C0 2
988
+ #define COM4C1 3
989
+ #define COM4B0 4
990
+ #define COM4B1 5
991
+ #define COM4A0 6
992
+ #define COM4A1 7
993
+
994
+ #define TCCR4B _SFR_MEM8(0xA1)
995
+ #define CS40 0
996
+ #define CS41 1
997
+ #define CS42 2
998
+ #define WGM42 3
999
+ #define WGM43 4
1000
+ #define ICES4 6
1001
+ #define ICNC4 7
1002
+
1003
+ #define TCCR4C _SFR_MEM8(0xA2)
1004
+ #define FOC4C 5
1005
+ #define FOC4B 6
1006
+ #define FOC4A 7
1007
+
1008
+ /* Reserved [0xA3] */
1009
+
1010
+ /* Combine TCNT4L and TCNT4H */
1011
+ #define TCNT4 _SFR_MEM16(0xA4)
1012
+
1013
+ #define TCNT4L _SFR_MEM8(0xA4)
1014
+ #define TCNT4H _SFR_MEM8(0xA5)
1015
+
1016
+ /* Combine ICR4L and ICR4H */
1017
+ #define ICR4 _SFR_MEM16(0xA6)
1018
+
1019
+ #define ICR4L _SFR_MEM8(0xA6)
1020
+ #define ICR4H _SFR_MEM8(0xA7)
1021
+
1022
+ /* Combine OCR4AL and OCR4AH */
1023
+ #define OCR4A _SFR_MEM16(0xA8)
1024
+
1025
+ #define OCR4AL _SFR_MEM8(0xA8)
1026
+ #define OCR4AH _SFR_MEM8(0xA9)
1027
+
1028
+ /* Combine OCR4BL and OCR4BH */
1029
+ #define OCR4B _SFR_MEM16(0xAA)
1030
+
1031
+ #define OCR4BL _SFR_MEM8(0xAA)
1032
+ #define OCR4BH _SFR_MEM8(0xAB)
1033
+
1034
+ /* Combine OCR4CL and OCR4CH */
1035
+ #define OCR4C _SFR_MEM16(0xAC)
1036
+
1037
+ #define OCR4CL _SFR_MEM8(0xAC)
1038
+ #define OCR4CH _SFR_MEM8(0xAD)
1039
+
1040
+ /* Reserved [0xAE..0xAF] */
1041
+
1042
+ #define TCCR2A _SFR_MEM8(0xB0)
1043
+ #define WGM20 0
1044
+ #define WGM21 1
1045
+ #define COM2B0 4
1046
+ #define COM2B1 5
1047
+ #define COM2A0 6
1048
+ #define COM2A1 7
1049
+
1050
+ #define TCCR2B _SFR_MEM8(0xB1)
1051
+ #define CS20 0
1052
+ #define CS21 1
1053
+ #define CS22 2
1054
+ #define WGM22 3
1055
+ #define FOC2B 6
1056
+ #define FOC2A 7
1057
+
1058
+ #define TCNT2 _SFR_MEM8(0xB2)
1059
+
1060
+ #define OCR2A _SFR_MEM8(0xB3)
1061
+
1062
+ #define OCR2B _SFR_MEM8(0xB4)
1063
+
1064
+ /* Reserved [0xB5] */
1065
+
1066
+ #define ASSR _SFR_MEM8(0xB6)
1067
+ #define TCR2BUB 0
1068
+ #define TCR2AUB 1
1069
+ #define OCR2BUB 2
1070
+ #define OCR2AUB 3
1071
+ #define TCN2UB 4
1072
+ #define AS2 5
1073
+ #define EXCLK 6
1074
+ #define EXCLKAMR 7
1075
+
1076
+ /* Reserved [0xB7] */
1077
+
1078
+ #define TWBR _SFR_MEM8(0xB8)
1079
+
1080
+ #define TWSR _SFR_MEM8(0xB9)
1081
+ #define TWPS0 0
1082
+ #define TWPS1 1
1083
+ #define TWS3 3
1084
+ #define TWS4 4
1085
+ #define TWS5 5
1086
+ #define TWS6 6
1087
+ #define TWS7 7
1088
+
1089
+ #define TWAR _SFR_MEM8(0xBA)
1090
+ #define TWGCE 0
1091
+ #define TWA0 1
1092
+ #define TWA1 2
1093
+ #define TWA2 3
1094
+ #define TWA3 4
1095
+ #define TWA4 5
1096
+ #define TWA5 6
1097
+ #define TWA6 7
1098
+
1099
+ #define TWDR _SFR_MEM8(0xBB)
1100
+
1101
+ #define TWCR _SFR_MEM8(0xBC)
1102
+ #define TWIE 0
1103
+ #define TWEN 2
1104
+ #define TWWC 3
1105
+ #define TWSTO 4
1106
+ #define TWSTA 5
1107
+ #define TWEA 6
1108
+ #define TWINT 7
1109
+
1110
+ #define TWAMR _SFR_MEM8(0xBD)
1111
+ #define TWAM0 1
1112
+ #define TWAM1 2
1113
+ #define TWAM2 3
1114
+ #define TWAM3 4
1115
+ #define TWAM4 5
1116
+ #define TWAM5 6
1117
+ #define TWAM6 7
1118
+
1119
+ #define IRQ_MASK1 _SFR_MEM8(0xBE)
1120
+ #define TX_START_EN 0
1121
+ #define MAF_0_AMI_EN 1
1122
+ #define MAF_1_AMI_EN 2
1123
+ #define MAF_2_AMI_EN 3
1124
+ #define MAF_3_AMI_EN 4
1125
+
1126
+ #define IRQ_STATUS1 _SFR_MEM8(0xBF)
1127
+ #define TX_START 0
1128
+ #define MAF_0_AMI 1
1129
+ #define MAF_1_AMI 2
1130
+ #define MAF_2_AMI 3
1131
+ #define MAF_3_AMI 4
1132
+
1133
+ #define UCSR0A _SFR_MEM8(0xC0)
1134
+ #define MPCM0 0
1135
+ #define U2X0 1
1136
+ #define UPE0 2
1137
+ #define DOR0 3
1138
+ #define FE0 4
1139
+ #define UDRE0 5
1140
+ #define TXC0 6
1141
+ #define RXC0 7
1142
+
1143
+ #define UCSR0B _SFR_MEM8(0xC1)
1144
+ #define TXB80 0
1145
+ #define RXB80 1
1146
+ #define UCSZ02 2
1147
+ #define TXEN0 3
1148
+ #define RXEN0 4
1149
+ #define UDRIE0 5
1150
+ #define TXCIE0 6
1151
+ #define RXCIE0 7
1152
+
1153
+ #define UCSR0C _SFR_MEM8(0xC2)
1154
+ #define UCPOL0 0
1155
+ #define UCSZ00 1
1156
+ #define UCSZ01 2
1157
+ #define USBS0 3
1158
+ #define UPM00 4
1159
+ #define UPM01 5
1160
+ #define UMSEL00 6
1161
+ #define UMSEL01 7
1162
+ #define UCPHA0 1
1163
+ #define UDORD0 2
1164
+
1165
+ /* Reserved [0xC3] */
1166
+
1167
+ /* Combine UBRR0L and UBRR0H */
1168
+ #define UBRR0 _SFR_MEM16(0xC4)
1169
+
1170
+ #define UBRR0L _SFR_MEM8(0xC4)
1171
+ #define UBRR0H _SFR_MEM8(0xC5)
1172
+
1173
+ #define UDR0 _SFR_MEM8(0xC6)
1174
+
1175
+ /* Reserved [0xC7] */
1176
+
1177
+ #define UCSR1A _SFR_MEM8(0xC8)
1178
+ #define MPCM1 0
1179
+ #define U2X1 1
1180
+ #define UPE1 2
1181
+ #define DOR1 3
1182
+ #define FE1 4
1183
+ #define UDRE1 5
1184
+ #define TXC1 6
1185
+ #define RXC1 7
1186
+
1187
+ #define UCSR1B _SFR_MEM8(0xC9)
1188
+ #define TXB81 0
1189
+ #define RXB81 1
1190
+ #define UCSZ12 2
1191
+ #define TXEN1 3
1192
+ #define RXEN1 4
1193
+ #define UDRIE1 5
1194
+ #define TXCIE1 6
1195
+ #define RXCIE1 7
1196
+
1197
+ #define UCSR1C _SFR_MEM8(0xCA)
1198
+ #define UCPOL1 0
1199
+ #define UCSZ10 1
1200
+ #define UCSZ11 2
1201
+ #define USBS1 3
1202
+ #define UPM10 4
1203
+ #define UPM11 5
1204
+ #define UMSEL10 6
1205
+ #define UMSEL11 7
1206
+ #define UCPHA1 1
1207
+ #define UDORD1 2
1208
+
1209
+ /* Reserved [0xCB] */
1210
+
1211
+ /* Combine UBRR1L and UBRR1H */
1212
+ #define UBRR1 _SFR_MEM16(0xCC)
1213
+
1214
+ #define UBRR1L _SFR_MEM8(0xCC)
1215
+ #define UBRR1H _SFR_MEM8(0xCD)
1216
+
1217
+ #define UDR1 _SFR_MEM8(0xCE)
1218
+
1219
+ /* Reserved [0xCF..0xD6] */
1220
+
1221
+ #define SCRSTRLL _SFR_MEM8(0xD7)
1222
+ #define SCRSTRLL0 0
1223
+ #define SCRSTRLL1 1
1224
+ #define SCRSTRLL2 2
1225
+ #define SCRSTRLL3 3
1226
+ #define SCRSTRLL4 4
1227
+ #define SCRSTRLL5 5
1228
+ #define SCRSTRLL6 6
1229
+ #define SCRSTRLL7 7
1230
+
1231
+ #define SCRSTRLH _SFR_MEM8(0xD8)
1232
+ #define SCRSTRLH0 0
1233
+ #define SCRSTRLH1 1
1234
+ #define SCRSTRLH2 2
1235
+ #define SCRSTRLH3 3
1236
+ #define SCRSTRLH4 4
1237
+ #define SCRSTRLH5 5
1238
+ #define SCRSTRLH6 6
1239
+ #define SCRSTRLH7 7
1240
+
1241
+ #define SCRSTRHL _SFR_MEM8(0xD9)
1242
+ #define SCRSTRHL0 0
1243
+ #define SCRSTRHL1 1
1244
+ #define SCRSTRHL2 2
1245
+ #define SCRSTRHL3 3
1246
+ #define SCRSTRHL4 4
1247
+ #define SCRSTRHL5 5
1248
+ #define SCRSTRHL6 6
1249
+ #define SCRSTRHL7 7
1250
+
1251
+ #define SCRSTRHH _SFR_MEM8(0xDA)
1252
+ #define SCRSTRHH0 0
1253
+ #define SCRSTRHH1 1
1254
+ #define SCRSTRHH2 2
1255
+ #define SCRSTRHH3 3
1256
+ #define SCRSTRHH4 4
1257
+ #define SCRSTRHH5 5
1258
+ #define SCRSTRHH6 6
1259
+ #define SCRSTRHH7 7
1260
+
1261
+ #define SCCSR _SFR_MEM8(0xDB)
1262
+ #define SCCS10 0
1263
+ #define SCCS11 1
1264
+ #define SCCS20 2
1265
+ #define SCCS21 3
1266
+ #define SCCS30 4
1267
+ #define SCCS31 5
1268
+
1269
+ #define SCCR0 _SFR_MEM8(0xDC)
1270
+ #define SCCMP1 0
1271
+ #define SCCMP2 1
1272
+ #define SCCMP3 2
1273
+ #define SCTSE 3
1274
+ #define SCCKSEL 4
1275
+ #define SCEN 5
1276
+ #define SCMBTS 6
1277
+ #define SCRES 7
1278
+
1279
+ #define SCCR1 _SFR_MEM8(0xDD)
1280
+ #define SCENBO 0
1281
+ #define SCEECLK 1
1282
+ #define SCCKDIV0 2
1283
+ #define SCCKDIV1 3
1284
+ #define SCCKDIV2 4
1285
+ #define SCBTSM 5
1286
+
1287
+ #define SCSR _SFR_MEM8(0xDE)
1288
+ #define SCBSY 0
1289
+
1290
+ #define SCIRQM _SFR_MEM8(0xDF)
1291
+ #define IRQMCP1 0
1292
+ #define IRQMCP2 1
1293
+ #define IRQMCP3 2
1294
+ #define IRQMOF 3
1295
+ #define IRQMBO 4
1296
+
1297
+ #define SCIRQS _SFR_MEM8(0xE0)
1298
+ #define IRQSCP1 0
1299
+ #define IRQSCP2 1
1300
+ #define IRQSCP3 2
1301
+ #define IRQSOF 3
1302
+ #define IRQSBO 4
1303
+
1304
+ #define SCCNTLL _SFR_MEM8(0xE1)
1305
+ #define SCCNTLL0 0
1306
+ #define SCCNTLL1 1
1307
+ #define SCCNTLL2 2
1308
+ #define SCCNTLL3 3
1309
+ #define SCCNTLL4 4
1310
+ #define SCCNTLL5 5
1311
+ #define SCCNTLL6 6
1312
+ #define SCCNTLL7 7
1313
+
1314
+ #define SCCNTLH _SFR_MEM8(0xE2)
1315
+ #define SCCNTLH0 0
1316
+ #define SCCNTLH1 1
1317
+ #define SCCNTLH2 2
1318
+ #define SCCNTLH3 3
1319
+ #define SCCNTLH4 4
1320
+ #define SCCNTLH5 5
1321
+ #define SCCNTLH6 6
1322
+ #define SCCNTLH7 7
1323
+
1324
+ #define SCCNTHL _SFR_MEM8(0xE3)
1325
+ #define SCCNTHL0 0
1326
+ #define SCCNTHL1 1
1327
+ #define SCCNTHL2 2
1328
+ #define SCCNTHL3 3
1329
+ #define SCCNTHL4 4
1330
+ #define SCCNTHL5 5
1331
+ #define SCCNTHL6 6
1332
+ #define SCCNTHL7 7
1333
+
1334
+ #define SCCNTHH _SFR_MEM8(0xE4)
1335
+ #define SCCNTHH0 0
1336
+ #define SCCNTHH1 1
1337
+ #define SCCNTHH2 2
1338
+ #define SCCNTHH3 3
1339
+ #define SCCNTHH4 4
1340
+ #define SCCNTHH5 5
1341
+ #define SCCNTHH6 6
1342
+ #define SCCNTHH7 7
1343
+
1344
+ #define SCBTSRLL _SFR_MEM8(0xE5)
1345
+ #define SCBTSRLL0 0
1346
+ #define SCBTSRLL1 1
1347
+ #define SCBTSRLL2 2
1348
+ #define SCBTSRLL3 3
1349
+ #define SCBTSRLL4 4
1350
+ #define SCBTSRLL5 5
1351
+ #define SCBTSRLL6 6
1352
+ #define SCBTSRLL7 7
1353
+
1354
+ #define SCBTSRLH _SFR_MEM8(0xE6)
1355
+ #define SCBTSRLH0 0
1356
+ #define SCBTSRLH1 1
1357
+ #define SCBTSRLH2 2
1358
+ #define SCBTSRLH3 3
1359
+ #define SCBTSRLH4 4
1360
+ #define SCBTSRLH5 5
1361
+ #define SCBTSRLH6 6
1362
+ #define SCBTSRLH7 7
1363
+
1364
+ #define SCBTSRHL _SFR_MEM8(0xE7)
1365
+ #define SCBTSRHL0 0
1366
+ #define SCBTSRHL1 1
1367
+ #define SCBTSRHL2 2
1368
+ #define SCBTSRHL3 3
1369
+ #define SCBTSRHL4 4
1370
+ #define SCBTSRHL5 5
1371
+ #define SCBTSRHL6 6
1372
+ #define SCBTSRHL7 7
1373
+
1374
+ #define SCBTSRHH _SFR_MEM8(0xE8)
1375
+ #define SCBTSRHH0 0
1376
+ #define SCBTSRHH1 1
1377
+ #define SCBTSRHH2 2
1378
+ #define SCBTSRHH3 3
1379
+ #define SCBTSRHH4 4
1380
+ #define SCBTSRHH5 5
1381
+ #define SCBTSRHH6 6
1382
+ #define SCBTSRHH7 7
1383
+
1384
+ #define SCTSRLL _SFR_MEM8(0xE9)
1385
+ #define SCTSRLL0 0
1386
+ #define SCTSRLL1 1
1387
+ #define SCTSRLL2 2
1388
+ #define SCTSRLL3 3
1389
+ #define SCTSRLL4 4
1390
+ #define SCTSRLL5 5
1391
+ #define SCTSRLL6 6
1392
+ #define SCTSRLL7 7
1393
+
1394
+ #define SCTSRLH _SFR_MEM8(0xEA)
1395
+ #define SCTSRLH0 0
1396
+ #define SCTSRLH1 1
1397
+ #define SCTSRLH2 2
1398
+ #define SCTSRLH3 3
1399
+ #define SCTSRLH4 4
1400
+ #define SCTSRLH5 5
1401
+ #define SCTSRLH6 6
1402
+ #define SCTSRLH7 7
1403
+
1404
+ #define SCTSRHL _SFR_MEM8(0xEB)
1405
+ #define SCTSRHL0 0
1406
+ #define SCTSRHL1 1
1407
+ #define SCTSRHL2 2
1408
+ #define SCTSRHL3 3
1409
+ #define SCTSRHL4 4
1410
+ #define SCTSRHL5 5
1411
+ #define SCTSRHL6 6
1412
+ #define SCTSRHL7 7
1413
+
1414
+ #define SCTSRHH _SFR_MEM8(0xEC)
1415
+ #define SCTSRHH0 0
1416
+ #define SCTSRHH1 1
1417
+ #define SCTSRHH2 2
1418
+ #define SCTSRHH3 3
1419
+ #define SCTSRHH4 4
1420
+ #define SCTSRHH5 5
1421
+ #define SCTSRHH6 6
1422
+ #define SCTSRHH7 7
1423
+
1424
+ #define SCOCR3LL _SFR_MEM8(0xED)
1425
+ #define SCOCR3LL0 0
1426
+ #define SCOCR3LL1 1
1427
+ #define SCOCR3LL2 2
1428
+ #define SCOCR3LL3 3
1429
+ #define SCOCR3LL4 4
1430
+ #define SCOCR3LL5 5
1431
+ #define SCOCR3LL6 6
1432
+ #define SCOCR3LL7 7
1433
+
1434
+ #define SCOCR3LH _SFR_MEM8(0xEE)
1435
+ #define SCOCR3LH0 0
1436
+ #define SCOCR3LH1 1
1437
+ #define SCOCR3LH2 2
1438
+ #define SCOCR3LH3 3
1439
+ #define SCOCR3LH4 4
1440
+ #define SCOCR3LH5 5
1441
+ #define SCOCR3LH6 6
1442
+ #define SCOCR3LH7 7
1443
+
1444
+ #define SCOCR3HL _SFR_MEM8(0xEF)
1445
+ #define SCOCR3HL0 0
1446
+ #define SCOCR3HL1 1
1447
+ #define SCOCR3HL2 2
1448
+ #define SCOCR3HL3 3
1449
+ #define SCOCR3HL4 4
1450
+ #define SCOCR3HL5 5
1451
+ #define SCOCR3HL6 6
1452
+ #define SCOCR3HL7 7
1453
+
1454
+ #define SCOCR3HH _SFR_MEM8(0xF0)
1455
+ #define SCOCR3HH0 0
1456
+ #define SCOCR3HH1 1
1457
+ #define SCOCR3HH2 2
1458
+ #define SCOCR3HH3 3
1459
+ #define SCOCR3HH4 4
1460
+ #define SCOCR3HH5 5
1461
+ #define SCOCR3HH6 6
1462
+ #define SCOCR3HH7 7
1463
+
1464
+ #define SCOCR2LL _SFR_MEM8(0xF1)
1465
+ #define SCOCR2LL0 0
1466
+ #define SCOCR2LL1 1
1467
+ #define SCOCR2LL2 2
1468
+ #define SCOCR2LL3 3
1469
+ #define SCOCR2LL4 4
1470
+ #define SCOCR2LL5 5
1471
+ #define SCOCR2LL6 6
1472
+ #define SCOCR2LL7 7
1473
+
1474
+ #define SCOCR2LH _SFR_MEM8(0xF2)
1475
+ #define SCOCR2LH0 0
1476
+ #define SCOCR2LH1 1
1477
+ #define SCOCR2LH2 2
1478
+ #define SCOCR2LH3 3
1479
+ #define SCOCR2LH4 4
1480
+ #define SCOCR2LH5 5
1481
+ #define SCOCR2LH6 6
1482
+ #define SCOCR2LH7 7
1483
+
1484
+ #define SCOCR2HL _SFR_MEM8(0xF3)
1485
+ #define SCOCR2HL0 0
1486
+ #define SCOCR2HL1 1
1487
+ #define SCOCR2HL2 2
1488
+ #define SCOCR2HL3 3
1489
+ #define SCOCR2HL4 4
1490
+ #define SCOCR2HL5 5
1491
+ #define SCOCR2HL6 6
1492
+ #define SCOCR2HL7 7
1493
+
1494
+ #define SCOCR2HH _SFR_MEM8(0xF4)
1495
+ #define SCOCR2HH0 0
1496
+ #define SCOCR2HH1 1
1497
+ #define SCOCR2HH2 2
1498
+ #define SCOCR2HH3 3
1499
+ #define SCOCR2HH4 4
1500
+ #define SCOCR2HH5 5
1501
+ #define SCOCR2HH6 6
1502
+ #define SCOCR2HH7 7
1503
+
1504
+ #define SCOCR1LL _SFR_MEM8(0xF5)
1505
+ #define SCOCR1LL0 0
1506
+ #define SCOCR1LL1 1
1507
+ #define SCOCR1LL2 2
1508
+ #define SCOCR1LL3 3
1509
+ #define SCOCR1LL4 4
1510
+ #define SCOCR1LL5 5
1511
+ #define SCOCR1LL6 6
1512
+ #define SCOCR1LL7 7
1513
+
1514
+ #define SCOCR1LH _SFR_MEM8(0xF6)
1515
+ #define SCOCR1LH0 0
1516
+ #define SCOCR1LH1 1
1517
+ #define SCOCR1LH2 2
1518
+ #define SCOCR1LH3 3
1519
+ #define SCOCR1LH4 4
1520
+ #define SCOCR1LH5 5
1521
+ #define SCOCR1LH6 6
1522
+ #define SCOCR1LH7 7
1523
+
1524
+ #define SCOCR1HL _SFR_MEM8(0xF7)
1525
+ #define SCOCR1HL0 0
1526
+ #define SCOCR1HL1 1
1527
+ #define SCOCR1HL2 2
1528
+ #define SCOCR1HL3 3
1529
+ #define SCOCR1HL4 4
1530
+ #define SCOCR1HL5 5
1531
+ #define SCOCR1HL6 6
1532
+ #define SCOCR1HL7 7
1533
+
1534
+ #define SCOCR1HH _SFR_MEM8(0xF8)
1535
+ #define SCOCR1HH0 0
1536
+ #define SCOCR1HH1 1
1537
+ #define SCOCR1HH2 2
1538
+ #define SCOCR1HH3 3
1539
+ #define SCOCR1HH4 4
1540
+ #define SCOCR1HH5 5
1541
+ #define SCOCR1HH6 6
1542
+ #define SCOCR1HH7 7
1543
+
1544
+ #define SCTSTRLL _SFR_MEM8(0xF9)
1545
+ #define SCTSTRLL0 0
1546
+ #define SCTSTRLL1 1
1547
+ #define SCTSTRLL2 2
1548
+ #define SCTSTRLL3 3
1549
+ #define SCTSTRLL4 4
1550
+ #define SCTSTRLL5 5
1551
+ #define SCTSTRLL6 6
1552
+ #define SCTSTRLL7 7
1553
+
1554
+ #define SCTSTRLH _SFR_MEM8(0xFA)
1555
+ #define SCTSTRLH0 0
1556
+ #define SCTSTRLH1 1
1557
+ #define SCTSTRLH2 2
1558
+ #define SCTSTRLH3 3
1559
+ #define SCTSTRLH4 4
1560
+ #define SCTSTRLH5 5
1561
+ #define SCTSTRLH6 6
1562
+ #define SCTSTRLH7 7
1563
+
1564
+ #define SCTSTRHL _SFR_MEM8(0xFB)
1565
+ #define SCTSTRHL0 0
1566
+ #define SCTSTRHL1 1
1567
+ #define SCTSTRHL2 2
1568
+ #define SCTSTRHL3 3
1569
+ #define SCTSTRHL4 4
1570
+ #define SCTSTRHL5 5
1571
+ #define SCTSTRHL6 6
1572
+ #define SCTSTRHL7 7
1573
+
1574
+ #define SCTSTRHH _SFR_MEM8(0xFC)
1575
+ #define SCTSTRHH0 0
1576
+ #define SCTSTRHH1 1
1577
+ #define SCTSTRHH2 2
1578
+ #define SCTSTRHH3 3
1579
+ #define SCTSTRHH4 4
1580
+ #define SCTSTRHH5 5
1581
+ #define SCTSTRHH6 6
1582
+ #define SCTSTRHH7 7
1583
+
1584
+ /* Reserved [0xFD..0x10B] */
1585
+
1586
+ #define MAFCR0 _SFR_MEM8(0x10C)
1587
+ #define MAF0EN 0
1588
+ #define MAF1EN 1
1589
+ #define MAF2EN 2
1590
+ #define MAF3EN 3
1591
+
1592
+ #define MAFCR1 _SFR_MEM8(0x10D)
1593
+ #define AACK_0_I_AM_COORD 0
1594
+ #define AACK_0_SET_PD 1
1595
+ #define AACK_1_I_AM_COORD 2
1596
+ #define AACK_1_SET_PD 3
1597
+ #define AACK_2_I_AM_COORD 4
1598
+ #define AACK_2_SET_PD 5
1599
+ #define AACK_3_I_AM_COORD 6
1600
+ #define AACK_3_SET_PD 7
1601
+
1602
+ #define MAFSA0L _SFR_MEM8(0x10E)
1603
+ #define MAFSA0L0 0
1604
+ #define MAFSA0L1 1
1605
+ #define MAFSA0L2 2
1606
+ #define MAFSA0L3 3
1607
+ #define MAFSA0L4 4
1608
+ #define MAFSA0L5 5
1609
+ #define MAFSA0L6 6
1610
+ #define MAFSA0L7 7
1611
+
1612
+ #define MAFSA0H _SFR_MEM8(0x10F)
1613
+ #define MAFSA0H0 0
1614
+ #define MAFSA0H1 1
1615
+ #define MAFSA0H2 2
1616
+ #define MAFSA0H3 3
1617
+ #define MAFSA0H4 4
1618
+ #define MAFSA0H5 5
1619
+ #define MAFSA0H6 6
1620
+ #define MAFSA0H7 7
1621
+
1622
+ #define MAFPA0L _SFR_MEM8(0x110)
1623
+ #define MAFPA0L0 0
1624
+ #define MAFPA0L1 1
1625
+ #define MAFPA0L2 2
1626
+ #define MAFPA0L3 3
1627
+ #define MAFPA0L4 4
1628
+ #define MAFPA0L5 5
1629
+ #define MAFPA0L6 6
1630
+ #define MAFPA0L7 7
1631
+
1632
+ #define MAFPA0H _SFR_MEM8(0x111)
1633
+ #define MAFPA0H0 0
1634
+ #define MAFPA0H1 1
1635
+ #define MAFPA0H2 2
1636
+ #define MAFPA0H3 3
1637
+ #define MAFPA0H4 4
1638
+ #define MAFPA0H5 5
1639
+ #define MAFPA0H6 6
1640
+ #define MAFPA0H7 7
1641
+
1642
+ #define MAFSA1L _SFR_MEM8(0x112)
1643
+ #define MAFSA1L0 0
1644
+ #define MAFSA1L1 1
1645
+ #define MAFSA1L2 2
1646
+ #define MAFSA1L3 3
1647
+ #define MAFSA1L4 4
1648
+ #define MAFSA1L5 5
1649
+ #define MAFSA1L6 6
1650
+ #define MAFSA1L7 7
1651
+
1652
+ #define MAFSA1H _SFR_MEM8(0x113)
1653
+ #define MAFSA1H0 0
1654
+ #define MAFSA1H1 1
1655
+ #define MAFSA1H2 2
1656
+ #define MAFSA1H3 3
1657
+ #define MAFSA1H4 4
1658
+ #define MAFSA1H5 5
1659
+ #define MAFSA1H6 6
1660
+ #define MAFSA1H7 7
1661
+
1662
+ #define MAFPA1L _SFR_MEM8(0x114)
1663
+ #define MAFPA1L0 0
1664
+ #define MAFPA1L1 1
1665
+ #define MAFPA1L2 2
1666
+ #define MAFPA1L3 3
1667
+ #define MAFPA1L4 4
1668
+ #define MAFPA1L5 5
1669
+ #define MAFPA1L6 6
1670
+ #define MAFPA1L7 7
1671
+
1672
+ #define MAFPA1H _SFR_MEM8(0x115)
1673
+ #define MAFPA1H0 0
1674
+ #define MAFPA1H1 1
1675
+ #define MAFPA1H2 2
1676
+ #define MAFPA1H3 3
1677
+ #define MAFPA1H4 4
1678
+ #define MAFPA1H5 5
1679
+ #define MAFPA1H6 6
1680
+ #define MAFPA1H7 7
1681
+
1682
+ #define MAFSA2L _SFR_MEM8(0x116)
1683
+ #define MAFSA2L0 0
1684
+ #define MAFSA2L1 1
1685
+ #define MAFSA2L2 2
1686
+ #define MAFSA2L3 3
1687
+ #define MAFSA2L4 4
1688
+ #define MAFSA2L5 5
1689
+ #define MAFSA2L6 6
1690
+ #define MAFSA2L7 7
1691
+
1692
+ #define MAFSA2H _SFR_MEM8(0x117)
1693
+ #define MAFSA2H0 0
1694
+ #define MAFSA2H1 1
1695
+ #define MAFSA2H2 2
1696
+ #define MAFSA2H3 3
1697
+ #define MAFSA2H4 4
1698
+ #define MAFSA2H5 5
1699
+ #define MAFSA2H6 6
1700
+ #define MAFSA2H7 7
1701
+
1702
+ #define MAFPA2L _SFR_MEM8(0x118)
1703
+ #define MAFPA2L0 0
1704
+ #define MAFPA2L1 1
1705
+ #define MAFPA2L2 2
1706
+ #define MAFPA2L3 3
1707
+ #define MAFPA2L4 4
1708
+ #define MAFPA2L5 5
1709
+ #define MAFPA2L6 6
1710
+ #define MAFPA2L7 7
1711
+
1712
+ #define MAFPA2H _SFR_MEM8(0x119)
1713
+ #define MAFPA2H0 0
1714
+ #define MAFPA2H1 1
1715
+ #define MAFPA2H2 2
1716
+ #define MAFPA2H3 3
1717
+ #define MAFPA2H4 4
1718
+ #define MAFPA2H5 5
1719
+ #define MAFPA2H6 6
1720
+ #define MAFPA2H7 7
1721
+
1722
+ #define MAFSA3L _SFR_MEM8(0x11A)
1723
+ #define MAFSA3L0 0
1724
+ #define MAFSA3L1 1
1725
+ #define MAFSA3L2 2
1726
+ #define MAFSA3L3 3
1727
+ #define MAFSA3L4 4
1728
+ #define MAFSA3L5 5
1729
+ #define MAFSA3L6 6
1730
+ #define MAFSA3L7 7
1731
+
1732
+ #define MAFSA3H _SFR_MEM8(0x11B)
1733
+ #define MAFSA3H0 0
1734
+ #define MAFSA3H1 1
1735
+ #define MAFSA3H2 2
1736
+ #define MAFSA3H3 3
1737
+ #define MAFSA3H4 4
1738
+ #define MAFSA3H5 5
1739
+ #define MAFSA3H6 6
1740
+ #define MAFSA3H7 7
1741
+
1742
+ #define MAFPA3L _SFR_MEM8(0x11C)
1743
+ #define MAFPA3L0 0
1744
+ #define MAFPA3L1 1
1745
+ #define MAFPA3L2 2
1746
+ #define MAFPA3L3 3
1747
+ #define MAFPA3L4 4
1748
+ #define MAFPA3L5 5
1749
+ #define MAFPA3L6 6
1750
+ #define MAFPA3L7 7
1751
+
1752
+ #define MAFPA3H _SFR_MEM8(0x11D)
1753
+ #define MAFPA3H0 0
1754
+ #define MAFPA3H1 1
1755
+ #define MAFPA3H2 2
1756
+ #define MAFPA3H3 3
1757
+ #define MAFPA3H4 4
1758
+ #define MAFPA3H5 5
1759
+ #define MAFPA3H6 6
1760
+ #define MAFPA3H7 7
1761
+
1762
+ /* Reserved [0x11E..0x11F] */
1763
+
1764
+ #define TCCR5A _SFR_MEM8(0x120)
1765
+ #define WGM50 0
1766
+ #define WGM51 1
1767
+ #define COM5C0 2
1768
+ #define COM5C1 3
1769
+ #define COM5B0 4
1770
+ #define COM5B1 5
1771
+ #define COM5A0 6
1772
+ #define COM5A1 7
1773
+
1774
+ #define TCCR5B _SFR_MEM8(0x121)
1775
+ #define CS50 0
1776
+ #define CS51 1
1777
+ #define CS52 2
1778
+ #define WGM52 3
1779
+ #define WGM53 4
1780
+ #define ICES5 6
1781
+ #define ICNC5 7
1782
+
1783
+ #define TCCR5C _SFR_MEM8(0x122)
1784
+ #define FOC5C 5
1785
+ #define FOC5B 6
1786
+ #define FOC5A 7
1787
+
1788
+ /* Reserved [0x123] */
1789
+
1790
+ /* Combine TCNT5L and TCNT5H */
1791
+ #define TCNT5 _SFR_MEM16(0x124)
1792
+
1793
+ #define TCNT5L _SFR_MEM8(0x124)
1794
+ #define TCNT5H _SFR_MEM8(0x125)
1795
+
1796
+ /* Combine ICR5L and ICR5H */
1797
+ #define ICR5 _SFR_MEM16(0x126)
1798
+
1799
+ #define ICR5L _SFR_MEM8(0x126)
1800
+ #define ICR5H _SFR_MEM8(0x127)
1801
+
1802
+ /* Combine OCR5AL and OCR5AH */
1803
+ #define OCR5A _SFR_MEM16(0x128)
1804
+
1805
+ #define OCR5AL _SFR_MEM8(0x128)
1806
+ #define OCR5AH _SFR_MEM8(0x129)
1807
+
1808
+ /* Combine OCR5BL and OCR5BH */
1809
+ #define OCR5B _SFR_MEM16(0x12A)
1810
+
1811
+ #define OCR5BL _SFR_MEM8(0x12A)
1812
+ #define OCR5BH _SFR_MEM8(0x12B)
1813
+
1814
+ /* Combine OCR5CL and OCR5CH */
1815
+ #define OCR5C _SFR_MEM16(0x12C)
1816
+
1817
+ #define OCR5CL _SFR_MEM8(0x12C)
1818
+ #define OCR5CH _SFR_MEM8(0x12D)
1819
+
1820
+ /* Reserved [0x12E] */
1821
+
1822
+ #define LLCR _SFR_MEM8(0x12F)
1823
+ #define LLENCAL 0
1824
+ #define LLSHORT 1
1825
+ #define LLTCO 2
1826
+ #define LLCAL 3
1827
+ #define LLCOMP 4
1828
+ #define LLDONE 5
1829
+
1830
+ #define LLDRL _SFR_MEM8(0x130)
1831
+ #define LLDRL0 0
1832
+ #define LLDRL1 1
1833
+ #define LLDRL2 2
1834
+ #define LLDRL3 3
1835
+
1836
+ #define LLDRH _SFR_MEM8(0x131)
1837
+ #define LLDRH0 0
1838
+ #define LLDRH1 1
1839
+ #define LLDRH2 2
1840
+ #define LLDRH3 3
1841
+ #define LLDRH4 4
1842
+
1843
+ #define DRTRAM3 _SFR_MEM8(0x132)
1844
+ #define ENDRT 4
1845
+ #define DRTSWOK 5
1846
+
1847
+ #define DRTRAM2 _SFR_MEM8(0x133)
1848
+
1849
+ #define DRTRAM1 _SFR_MEM8(0x134)
1850
+
1851
+ #define DRTRAM0 _SFR_MEM8(0x135)
1852
+
1853
+ #define DPDS0 _SFR_MEM8(0x136)
1854
+ #define PBDRV0 0
1855
+ #define PBDRV1 1
1856
+ #define PDDRV0 2
1857
+ #define PDDRV1 3
1858
+ #define PEDRV0 4
1859
+ #define PEDRV1 5
1860
+ #define PFDRV0 6
1861
+ #define PFDRV1 7
1862
+
1863
+ #define DPDS1 _SFR_MEM8(0x137)
1864
+ #define PGDRV0 0
1865
+ #define PGDRV1 1
1866
+
1867
+ #define PARCR _SFR_MEM8(0x138)
1868
+ #define PARUFI 0
1869
+ #define PARDFI 1
1870
+ #define PALTU0 2
1871
+ #define PALTU1 3
1872
+ #define PALTU2 4
1873
+ #define PALTD0 5
1874
+ #define PALTD1 6
1875
+ #define PALTD2 7
1876
+
1877
+ #define TRXPR _SFR_MEM8(0x139)
1878
+ #define TRXRST 0
1879
+ #define SLPTR 1
1880
+
1881
+ /* Reserved [0x13A..0x13B] */
1882
+
1883
+ #define AES_CTRL _SFR_MEM8(0x13C)
1884
+ #define AES_IM 2
1885
+ #define AES_DIR 3
1886
+ #define AES_MODE 5
1887
+ #define AES_REQUEST 7
1888
+
1889
+ #define AES_STATUS _SFR_MEM8(0x13D)
1890
+ #define AES_DONE 0
1891
+ #define AES_ER 7
1892
+
1893
+ #define AES_STATE _SFR_MEM8(0x13E)
1894
+ #define AES_STATE0 0
1895
+ #define AES_STATE1 1
1896
+ #define AES_STATE2 2
1897
+ #define AES_STATE3 3
1898
+ #define AES_STATE4 4
1899
+ #define AES_STATE5 5
1900
+ #define AES_STATE6 6
1901
+ #define AES_STATE7 7
1902
+
1903
+ #define AES_KEY _SFR_MEM8(0x13F)
1904
+ #define AES_KEY0 0
1905
+ #define AES_KEY1 1
1906
+ #define AES_KEY2 2
1907
+ #define AES_KEY3 3
1908
+ #define AES_KEY4 4
1909
+ #define AES_KEY5 5
1910
+ #define AES_KEY6 6
1911
+ #define AES_KEY7 7
1912
+
1913
+ /* Reserved [0x140] */
1914
+
1915
+ #define TRX_STATUS _SFR_MEM8(0x141)
1916
+ #define TRX_STATUS0 0
1917
+ #define TRX_STATUS1 1
1918
+ #define TRX_STATUS2 2
1919
+ #define TRX_STATUS3 3
1920
+ #define TRX_STATUS4 4
1921
+ #define TST_STATUS 5
1922
+ #define CCA_STATUS 6
1923
+ #define CCA_DONE 7
1924
+
1925
+ #define TRX_STATE _SFR_MEM8(0x142)
1926
+ #define TRX_CMD0 0
1927
+ #define TRX_CMD1 1
1928
+ #define TRX_CMD2 2
1929
+ #define TRX_CMD3 3
1930
+ #define TRX_CMD4 4
1931
+ #define TRAC_STATUS0 5
1932
+ #define TRAC_STATUS1 6
1933
+ #define TRAC_STATUS2 7
1934
+
1935
+ #define TRX_CTRL_0 _SFR_MEM8(0x143)
1936
+ #define PMU_IF_INV 4
1937
+ #define PMU_START 5
1938
+ #define PMU_EN 6
1939
+ #define Res7 7
1940
+
1941
+ #define TRX_CTRL_1 _SFR_MEM8(0x144)
1942
+ #define PLL_TX_FLT 4
1943
+ #define TX_AUTO_CRC_ON 5
1944
+ #define IRQ_2_EXT_EN 6
1945
+ #define PA_EXT_EN 7
1946
+
1947
+ #define PHY_TX_PWR _SFR_MEM8(0x145)
1948
+ #define TX_PWR0 0
1949
+ #define TX_PWR1 1
1950
+ #define TX_PWR2 2
1951
+ #define TX_PWR3 3
1952
+
1953
+ #define PHY_RSSI _SFR_MEM8(0x146)
1954
+ #define RSSI0 0
1955
+ #define RSSI1 1
1956
+ #define RSSI2 2
1957
+ #define RSSI3 3
1958
+ #define RSSI4 4
1959
+ #define RND_VALUE0 5
1960
+ #define RND_VALUE1 6
1961
+ #define RX_CRC_VALID 7
1962
+
1963
+ #define PHY_ED_LEVEL _SFR_MEM8(0x147)
1964
+ #define ED_LEVEL0 0
1965
+ #define ED_LEVEL1 1
1966
+ #define ED_LEVEL2 2
1967
+ #define ED_LEVEL3 3
1968
+ #define ED_LEVEL4 4
1969
+ #define ED_LEVEL5 5
1970
+ #define ED_LEVEL6 6
1971
+ #define ED_LEVEL7 7
1972
+
1973
+ #define PHY_CC_CCA _SFR_MEM8(0x148)
1974
+ #define CHANNEL0 0
1975
+ #define CHANNEL1 1
1976
+ #define CHANNEL2 2
1977
+ #define CHANNEL3 3
1978
+ #define CHANNEL4 4
1979
+ #define CCA_MODE0 5
1980
+ #define CCA_MODE1 6
1981
+ #define CCA_REQUEST 7
1982
+
1983
+ #define CCA_THRES _SFR_MEM8(0x149)
1984
+ #define CCA_ED_THRES0 0
1985
+ #define CCA_ED_THRES1 1
1986
+ #define CCA_ED_THRES2 2
1987
+ #define CCA_ED_THRES3 3
1988
+ #define CCA_CS_THRES0 4
1989
+ #define CCA_CS_THRES1 5
1990
+ #define CCA_CS_THRES2 6
1991
+ #define CCA_CS_THRES3 7
1992
+
1993
+ #define RX_CTRL _SFR_MEM8(0x14A)
1994
+ #define PDT_THRES0 0
1995
+ #define PDT_THRES1 1
1996
+ #define PDT_THRES2 2
1997
+ #define PDT_THRES3 3
1998
+
1999
+ #define SFD_VALUE _SFR_MEM8(0x14B)
2000
+ #define SFD_VALUE0 0
2001
+ #define SFD_VALUE1 1
2002
+ #define SFD_VALUE2 2
2003
+ #define SFD_VALUE3 3
2004
+ #define SFD_VALUE4 4
2005
+ #define SFD_VALUE5 5
2006
+ #define SFD_VALUE6 6
2007
+ #define SFD_VALUE7 7
2008
+
2009
+ #define TRX_CTRL_2 _SFR_MEM8(0x14C)
2010
+ #define OQPSK_DATA_RATE0 0
2011
+ #define OQPSK_DATA_RATE1 1
2012
+ #define RX_SAFE_MODE 7
2013
+
2014
+ #define ANT_DIV _SFR_MEM8(0x14D)
2015
+ #define ANT_CTRL0 0
2016
+ #define ANT_CTRL1 1
2017
+ #define ANT_EXT_SW_EN 2
2018
+ #define ANT_DIV_EN 3
2019
+ #define ANT_SEL 7
2020
+
2021
+ #define IRQ_MASK _SFR_MEM8(0x14E)
2022
+ #define PLL_LOCK_EN 0
2023
+ #define PLL_UNLOCK_EN 1
2024
+ #define RX_START_EN 2
2025
+ #define RX_END_EN 3
2026
+ #define CCA_ED_DONE_EN 4
2027
+ #define AMI_EN 5
2028
+ #define TX_END_EN 6
2029
+ #define AWAKE_EN 7
2030
+
2031
+ #define IRQ_STATUS _SFR_MEM8(0x14F)
2032
+ #define PLL_LOCK 0
2033
+ #define PLL_UNLOCK 1
2034
+ #define RX_START 2
2035
+ #define RX_END 3
2036
+ #define CCA_ED_DONE 4
2037
+ #define AMI 5
2038
+ #define TX_END 6
2039
+ #define AWAKE 7
2040
+
2041
+ #define VREG_CTRL _SFR_MEM8(0x150)
2042
+ #define DVDD_OK 2
2043
+ #define DVREG_EXT 3
2044
+ #define AVDD_OK 6
2045
+ #define AVREG_EXT 7
2046
+
2047
+ #define BATMON _SFR_MEM8(0x151)
2048
+ #define BATMON_VTH0 0
2049
+ #define BATMON_VTH1 1
2050
+ #define BATMON_VTH2 2
2051
+ #define BATMON_VTH3 3
2052
+ #define BATMON_HR 4
2053
+ #define BATMON_OK 5
2054
+ #define BAT_LOW_EN 6
2055
+ #define BAT_LOW 7
2056
+
2057
+ #define XOSC_CTRL _SFR_MEM8(0x152)
2058
+ #define XTAL_TRIM0 0
2059
+ #define XTAL_TRIM1 1
2060
+ #define XTAL_TRIM2 2
2061
+ #define XTAL_TRIM3 3
2062
+ #define XTAL_MODE0 4
2063
+ #define XTAL_MODE1 5
2064
+ #define XTAL_MODE2 6
2065
+ #define XTAL_MODE3 7
2066
+
2067
+ #define CC_CTRL_0 _SFR_MEM8(0x153)
2068
+ #define CC_NUMBER0 0
2069
+ #define CC_NUMBER1 1
2070
+ #define CC_NUMBER2 2
2071
+ #define CC_NUMBER3 3
2072
+ #define CC_NUMBER4 4
2073
+ #define CC_NUMBER5 5
2074
+ #define CC_NUMBER6 6
2075
+ #define CC_NUMBER7 7
2076
+
2077
+ #define CC_CTRL_1 _SFR_MEM8(0x154)
2078
+ #define CC_BAND0 0
2079
+ #define CC_BAND1 1
2080
+ #define CC_BAND2 2
2081
+ #define CC_BAND3 3
2082
+
2083
+ #define RX_SYN _SFR_MEM8(0x155)
2084
+ #define RX_PDT_LEVEL0 0
2085
+ #define RX_PDT_LEVEL1 1
2086
+ #define RX_PDT_LEVEL2 2
2087
+ #define RX_PDT_LEVEL3 3
2088
+ #define RX_OVERRIDE 6
2089
+ #define RX_PDT_DIS 7
2090
+
2091
+ #define TRX_RPC _SFR_MEM8(0x156)
2092
+ #define XAH_RPC_EN 0
2093
+ #define IPAN_RPC_EN 1
2094
+ #define PLL_RPC_EN 3
2095
+ #define PDT_RPC_EN 4
2096
+ #define RX_RPC_EN 5
2097
+ #define RX_RPC_CTRL0 6
2098
+ #define RX_RPC_CTRL1 7
2099
+
2100
+ #define XAH_CTRL_1 _SFR_MEM8(0x157)
2101
+ #define AACK_PROM_MODE 1
2102
+ #define AACK_ACK_TIME 2
2103
+ #define AACK_UPLD_RES_FT 4
2104
+ #define AACK_FLTR_RES_FT 5
2105
+
2106
+ #define FTN_CTRL _SFR_MEM8(0x158)
2107
+ #define FTN_START 7
2108
+
2109
+ /* Reserved [0x159] */
2110
+
2111
+ #define PLL_CF _SFR_MEM8(0x15A)
2112
+ #define PLL_CF_START 7
2113
+
2114
+ #define PLL_DCU _SFR_MEM8(0x15B)
2115
+ #define PLL_DCU_START 7
2116
+
2117
+ #define PART_NUM _SFR_MEM8(0x15C)
2118
+ #define PART_NUM0 0
2119
+ #define PART_NUM1 1
2120
+ #define PART_NUM2 2
2121
+ #define PART_NUM3 3
2122
+ #define PART_NUM4 4
2123
+ #define PART_NUM5 5
2124
+ #define PART_NUM6 6
2125
+ #define PART_NUM7 7
2126
+
2127
+ #define VERSION_NUM _SFR_MEM8(0x15D)
2128
+ #define VERSION_NUM0 0
2129
+ #define VERSION_NUM1 1
2130
+ #define VERSION_NUM2 2
2131
+ #define VERSION_NUM3 3
2132
+ #define VERSION_NUM4 4
2133
+ #define VERSION_NUM5 5
2134
+ #define VERSION_NUM6 6
2135
+ #define VERSION_NUM7 7
2136
+
2137
+ #define MAN_ID_0 _SFR_MEM8(0x15E)
2138
+ #define MAN_ID_00 0
2139
+ #define MAN_ID_01 1
2140
+ #define MAN_ID_02 2
2141
+ #define MAN_ID_03 3
2142
+ #define MAN_ID_04 4
2143
+ #define MAN_ID_05 5
2144
+ #define MAN_ID_06 6
2145
+ #define MAN_ID_07 7
2146
+
2147
+ #define MAN_ID_1 _SFR_MEM8(0x15F)
2148
+ #define MAN_ID_10 0
2149
+ #define MAN_ID_11 1
2150
+ #define MAN_ID_12 2
2151
+ #define MAN_ID_13 3
2152
+ #define MAN_ID_14 4
2153
+ #define MAN_ID_15 5
2154
+ #define MAN_ID_16 6
2155
+ #define MAN_ID_17 7
2156
+
2157
+ #define SHORT_ADDR_0 _SFR_MEM8(0x160)
2158
+ #define SHORT_ADDR_00 0
2159
+ #define SHORT_ADDR_01 1
2160
+ #define SHORT_ADDR_02 2
2161
+ #define SHORT_ADDR_03 3
2162
+ #define SHORT_ADDR_04 4
2163
+ #define SHORT_ADDR_05 5
2164
+ #define SHORT_ADDR_06 6
2165
+ #define SHORT_ADDR_07 7
2166
+
2167
+ #define SHORT_ADDR_1 _SFR_MEM8(0x161)
2168
+ #define SHORT_ADDR_10 0
2169
+ #define SHORT_ADDR_11 1
2170
+ #define SHORT_ADDR_12 2
2171
+ #define SHORT_ADDR_13 3
2172
+ #define SHORT_ADDR_14 4
2173
+ #define SHORT_ADDR_15 5
2174
+ #define SHORT_ADDR_16 6
2175
+ #define SHORT_ADDR_17 7
2176
+
2177
+ #define PAN_ID_0 _SFR_MEM8(0x162)
2178
+ #define PAN_ID_00 0
2179
+ #define PAN_ID_01 1
2180
+ #define PAN_ID_02 2
2181
+ #define PAN_ID_03 3
2182
+ #define PAN_ID_04 4
2183
+ #define PAN_ID_05 5
2184
+ #define PAN_ID_06 6
2185
+ #define PAN_ID_07 7
2186
+
2187
+ #define PAN_ID_1 _SFR_MEM8(0x163)
2188
+ #define PAN_ID_10 0
2189
+ #define PAN_ID_11 1
2190
+ #define PAN_ID_12 2
2191
+ #define PAN_ID_13 3
2192
+ #define PAN_ID_14 4
2193
+ #define PAN_ID_15 5
2194
+ #define PAN_ID_16 6
2195
+ #define PAN_ID_17 7
2196
+
2197
+ #define IEEE_ADDR_0 _SFR_MEM8(0x164)
2198
+ #define IEEE_ADDR_00 0
2199
+ #define IEEE_ADDR_01 1
2200
+ #define IEEE_ADDR_02 2
2201
+ #define IEEE_ADDR_03 3
2202
+ #define IEEE_ADDR_04 4
2203
+ #define IEEE_ADDR_05 5
2204
+ #define IEEE_ADDR_06 6
2205
+ #define IEEE_ADDR_07 7
2206
+
2207
+ #define IEEE_ADDR_1 _SFR_MEM8(0x165)
2208
+ #define IEEE_ADDR_10 0
2209
+ #define IEEE_ADDR_11 1
2210
+ #define IEEE_ADDR_12 2
2211
+ #define IEEE_ADDR_13 3
2212
+ #define IEEE_ADDR_14 4
2213
+ #define IEEE_ADDR_15 5
2214
+ #define IEEE_ADDR_16 6
2215
+ #define IEEE_ADDR_17 7
2216
+
2217
+ #define IEEE_ADDR_2 _SFR_MEM8(0x166)
2218
+ #define IEEE_ADDR_20 0
2219
+ #define IEEE_ADDR_21 1
2220
+ #define IEEE_ADDR_22 2
2221
+ #define IEEE_ADDR_23 3
2222
+ #define IEEE_ADDR_24 4
2223
+ #define IEEE_ADDR_25 5
2224
+ #define IEEE_ADDR_26 6
2225
+ #define IEEE_ADDR_27 7
2226
+
2227
+ #define IEEE_ADDR_3 _SFR_MEM8(0x167)
2228
+ #define IEEE_ADDR_30 0
2229
+ #define IEEE_ADDR_31 1
2230
+ #define IEEE_ADDR_32 2
2231
+ #define IEEE_ADDR_33 3
2232
+ #define IEEE_ADDR_34 4
2233
+ #define IEEE_ADDR_35 5
2234
+ #define IEEE_ADDR_36 6
2235
+ #define IEEE_ADDR_37 7
2236
+
2237
+ #define IEEE_ADDR_4 _SFR_MEM8(0x168)
2238
+ #define IEEE_ADDR_40 0
2239
+ #define IEEE_ADDR_41 1
2240
+ #define IEEE_ADDR_42 2
2241
+ #define IEEE_ADDR_43 3
2242
+ #define IEEE_ADDR_44 4
2243
+ #define IEEE_ADDR_45 5
2244
+ #define IEEE_ADDR_46 6
2245
+ #define IEEE_ADDR_47 7
2246
+
2247
+ #define IEEE_ADDR_5 _SFR_MEM8(0x169)
2248
+ #define IEEE_ADDR_50 0
2249
+ #define IEEE_ADDR_51 1
2250
+ #define IEEE_ADDR_52 2
2251
+ #define IEEE_ADDR_53 3
2252
+ #define IEEE_ADDR_54 4
2253
+ #define IEEE_ADDR_55 5
2254
+ #define IEEE_ADDR_56 6
2255
+ #define IEEE_ADDR_57 7
2256
+
2257
+ #define IEEE_ADDR_6 _SFR_MEM8(0x16A)
2258
+ #define IEEE_ADDR_60 0
2259
+ #define IEEE_ADDR_61 1
2260
+ #define IEEE_ADDR_62 2
2261
+ #define IEEE_ADDR_63 3
2262
+ #define IEEE_ADDR_64 4
2263
+ #define IEEE_ADDR_65 5
2264
+ #define IEEE_ADDR_66 6
2265
+ #define IEEE_ADDR_67 7
2266
+
2267
+ #define IEEE_ADDR_7 _SFR_MEM8(0x16B)
2268
+ #define IEEE_ADDR_70 0
2269
+ #define IEEE_ADDR_71 1
2270
+ #define IEEE_ADDR_72 2
2271
+ #define IEEE_ADDR_73 3
2272
+ #define IEEE_ADDR_74 4
2273
+ #define IEEE_ADDR_75 5
2274
+ #define IEEE_ADDR_76 6
2275
+ #define IEEE_ADDR_77 7
2276
+
2277
+ #define XAH_CTRL_0 _SFR_MEM8(0x16C)
2278
+ #define SLOTTED_OPERATION 0
2279
+ #define MAX_CSMA_RETRIES0 1
2280
+ #define MAX_CSMA_RETRIES1 2
2281
+ #define MAX_CSMA_RETRIES2 3
2282
+ #define MAX_FRAME_RETRIES0 4
2283
+ #define MAX_FRAME_RETRIES1 5
2284
+ #define MAX_FRAME_RETRIES2 6
2285
+ #define MAX_FRAME_RETRIES3 7
2286
+
2287
+ #define CSMA_SEED_0 _SFR_MEM8(0x16D)
2288
+ #define CSMA_SEED_00 0
2289
+ #define CSMA_SEED_01 1
2290
+ #define CSMA_SEED_02 2
2291
+ #define CSMA_SEED_03 3
2292
+ #define CSMA_SEED_04 4
2293
+ #define CSMA_SEED_05 5
2294
+ #define CSMA_SEED_06 6
2295
+ #define CSMA_SEED_07 7
2296
+
2297
+ #define CSMA_SEED_1 _SFR_MEM8(0x16E)
2298
+ #define CSMA_SEED_10 0
2299
+ #define CSMA_SEED_11 1
2300
+ #define CSMA_SEED_12 2
2301
+ #define AACK_I_AM_COORD 3
2302
+ #define AACK_DIS_ACK 4
2303
+ #define AACK_SET_PD 5
2304
+ #define AACK_FVN_MODE0 6
2305
+ #define AACK_FVN_MODE1 7
2306
+
2307
+ #define CSMA_BE _SFR_MEM8(0x16F)
2308
+ #define MIN_BE0 0
2309
+ #define MIN_BE1 1
2310
+ #define MIN_BE2 2
2311
+ #define MIN_BE3 3
2312
+ #define MAX_BE0 4
2313
+ #define MAX_BE1 5
2314
+ #define MAX_BE2 6
2315
+ #define MAX_BE3 7
2316
+
2317
+ /* Reserved [0x170..0x175] */
2318
+
2319
+ #define TST_CTRL_DIGI _SFR_MEM8(0x176)
2320
+ #define TST_CTRL_DIG0 0
2321
+ #define TST_CTRL_DIG1 1
2322
+ #define TST_CTRL_DIG2 2
2323
+ #define TST_CTRL_DIG3 3
2324
+
2325
+ /* Reserved [0x177..0x17A] */
2326
+
2327
+ #define TST_RX_LENGTH _SFR_MEM8(0x17B)
2328
+ #define RX_LENGTH0 0
2329
+ #define RX_LENGTH1 1
2330
+ #define RX_LENGTH2 2
2331
+ #define RX_LENGTH3 3
2332
+ #define RX_LENGTH4 4
2333
+ #define RX_LENGTH5 5
2334
+ #define RX_LENGTH6 6
2335
+ #define RX_LENGTH7 7
2336
+
2337
+ /* Reserved [0x17C..0x17F] */
2338
+
2339
+ #define TRXFBST _SFR_MEM8(0x180)
2340
+
2341
+ /* Reserved [0x181..0x1FE] */
2342
+
2343
+ #define TRXFBEND _SFR_MEM8(0x1FF)
2344
+
2345
+
2346
+
2347
+ /* Values and associated defines */
2348
+
2349
+
2350
+ #define SLEEP_MODE_IDLE (0x00<<1)
2351
+ #define SLEEP_MODE_ADC (0x01<<1)
2352
+ #define SLEEP_MODE_PWR_DOWN (0x02<<1)
2353
+ #define SLEEP_MODE_PWR_SAVE (0x03<<1)
2354
+ #define SLEEP_MODE_STANDBY (0x06<<1)
2355
+ #define SLEEP_MODE_EXT_STANDBY (0x07<<1)
2356
+
2357
+ /* Interrupt vectors */
2358
+ /* Vector 0 is the reset vector */
2359
+ /* External Interrupt Request 0 */
2360
+ #define INT0_vect _VECTOR(1)
2361
+ #define INT0_vect_num 1
2362
+
2363
+ /* External Interrupt Request 1 */
2364
+ #define INT1_vect _VECTOR(2)
2365
+ #define INT1_vect_num 2
2366
+
2367
+ /* External Interrupt Request 2 */
2368
+ #define INT2_vect _VECTOR(3)
2369
+ #define INT2_vect_num 3
2370
+
2371
+ /* External Interrupt Request 3 */
2372
+ #define INT3_vect _VECTOR(4)
2373
+ #define INT3_vect_num 4
2374
+
2375
+ /* External Interrupt Request 4 */
2376
+ #define INT4_vect _VECTOR(5)
2377
+ #define INT4_vect_num 5
2378
+
2379
+ /* External Interrupt Request 5 */
2380
+ #define INT5_vect _VECTOR(6)
2381
+ #define INT5_vect_num 6
2382
+
2383
+ /* External Interrupt Request 6 */
2384
+ #define INT6_vect _VECTOR(7)
2385
+ #define INT6_vect_num 7
2386
+
2387
+ /* External Interrupt Request 7 */
2388
+ #define INT7_vect _VECTOR(8)
2389
+ #define INT7_vect_num 8
2390
+
2391
+ /* Pin Change Interrupt Request 0 */
2392
+ #define PCINT0_vect _VECTOR(9)
2393
+ #define PCINT0_vect_num 9
2394
+
2395
+ /* Pin Change Interrupt Request 1 */
2396
+ #define PCINT1_vect _VECTOR(10)
2397
+ #define PCINT1_vect_num 10
2398
+
2399
+ /* Pin Change Interrupt Request 2 */
2400
+ #define PCINT2_vect _VECTOR(11)
2401
+ #define PCINT2_vect_num 11
2402
+
2403
+ /* Watchdog Time-out Interrupt */
2404
+ #define WDT_vect _VECTOR(12)
2405
+ #define WDT_vect_num 12
2406
+
2407
+ /* Timer/Counter2 Compare Match A */
2408
+ #define TIMER2_COMPA_vect _VECTOR(13)
2409
+ #define TIMER2_COMPA_vect_num 13
2410
+
2411
+ /* Timer/Counter2 Compare Match B */
2412
+ #define TIMER2_COMPB_vect _VECTOR(14)
2413
+ #define TIMER2_COMPB_vect_num 14
2414
+
2415
+ /* Timer/Counter2 Overflow */
2416
+ #define TIMER2_OVF_vect _VECTOR(15)
2417
+ #define TIMER2_OVF_vect_num 15
2418
+
2419
+ /* Timer/Counter1 Capture Event */
2420
+ #define TIMER1_CAPT_vect _VECTOR(16)
2421
+ #define TIMER1_CAPT_vect_num 16
2422
+
2423
+ /* Timer/Counter1 Compare Match A */
2424
+ #define TIMER1_COMPA_vect _VECTOR(17)
2425
+ #define TIMER1_COMPA_vect_num 17
2426
+
2427
+ /* Timer/Counter1 Compare Match B */
2428
+ #define TIMER1_COMPB_vect _VECTOR(18)
2429
+ #define TIMER1_COMPB_vect_num 18
2430
+
2431
+ /* Timer/Counter1 Compare Match C */
2432
+ #define TIMER1_COMPC_vect _VECTOR(19)
2433
+ #define TIMER1_COMPC_vect_num 19
2434
+
2435
+ /* Timer/Counter1 Overflow */
2436
+ #define TIMER1_OVF_vect _VECTOR(20)
2437
+ #define TIMER1_OVF_vect_num 20
2438
+
2439
+ /* Timer/Counter0 Compare Match A */
2440
+ #define TIMER0_COMPA_vect _VECTOR(21)
2441
+ #define TIMER0_COMPA_vect_num 21
2442
+
2443
+ /* Timer/Counter0 Compare Match B */
2444
+ #define TIMER0_COMPB_vect _VECTOR(22)
2445
+ #define TIMER0_COMPB_vect_num 22
2446
+
2447
+ /* Timer/Counter0 Overflow */
2448
+ #define TIMER0_OVF_vect _VECTOR(23)
2449
+ #define TIMER0_OVF_vect_num 23
2450
+
2451
+ /* SPI Serial Transfer Complete */
2452
+ #define SPI_STC_vect _VECTOR(24)
2453
+ #define SPI_STC_vect_num 24
2454
+
2455
+ /* USART0, Rx Complete */
2456
+ #define USART0_RX_vect _VECTOR(25)
2457
+ #define USART0_RX_vect_num 25
2458
+
2459
+ /* USART0 Data register Empty */
2460
+ #define USART0_UDRE_vect _VECTOR(26)
2461
+ #define USART0_UDRE_vect_num 26
2462
+
2463
+ /* USART0, Tx Complete */
2464
+ #define USART0_TX_vect _VECTOR(27)
2465
+ #define USART0_TX_vect_num 27
2466
+
2467
+ /* Analog Comparator */
2468
+ #define ANALOG_COMP_vect _VECTOR(28)
2469
+ #define ANALOG_COMP_vect_num 28
2470
+
2471
+ /* ADC Conversion Complete */
2472
+ #define ADC_vect _VECTOR(29)
2473
+ #define ADC_vect_num 29
2474
+
2475
+ /* EEPROM Ready */
2476
+ #define EE_READY_vect _VECTOR(30)
2477
+ #define EE_READY_vect_num 30
2478
+
2479
+ /* Timer/Counter3 Capture Event */
2480
+ #define TIMER3_CAPT_vect _VECTOR(31)
2481
+ #define TIMER3_CAPT_vect_num 31
2482
+
2483
+ /* Timer/Counter3 Compare Match A */
2484
+ #define TIMER3_COMPA_vect _VECTOR(32)
2485
+ #define TIMER3_COMPA_vect_num 32
2486
+
2487
+ /* Timer/Counter3 Compare Match B */
2488
+ #define TIMER3_COMPB_vect _VECTOR(33)
2489
+ #define TIMER3_COMPB_vect_num 33
2490
+
2491
+ /* Timer/Counter3 Compare Match C */
2492
+ #define TIMER3_COMPC_vect _VECTOR(34)
2493
+ #define TIMER3_COMPC_vect_num 34
2494
+
2495
+ /* Timer/Counter3 Overflow */
2496
+ #define TIMER3_OVF_vect _VECTOR(35)
2497
+ #define TIMER3_OVF_vect_num 35
2498
+
2499
+ /* USART1, Rx Complete */
2500
+ #define USART1_RX_vect _VECTOR(36)
2501
+ #define USART1_RX_vect_num 36
2502
+
2503
+ /* USART1 Data register Empty */
2504
+ #define USART1_UDRE_vect _VECTOR(37)
2505
+ #define USART1_UDRE_vect_num 37
2506
+
2507
+ /* USART1, Tx Complete */
2508
+ #define USART1_TX_vect _VECTOR(38)
2509
+ #define USART1_TX_vect_num 38
2510
+
2511
+ /* 2-wire Serial Interface */
2512
+ #define TWI_vect _VECTOR(39)
2513
+ #define TWI_vect_num 39
2514
+
2515
+ /* Store Program Memory Read */
2516
+ #define SPM_READY_vect _VECTOR(40)
2517
+ #define SPM_READY_vect_num 40
2518
+
2519
+ /* Timer/Counter4 Capture Event */
2520
+ #define TIMER4_CAPT_vect _VECTOR(41)
2521
+ #define TIMER4_CAPT_vect_num 41
2522
+
2523
+ /* Timer/Counter4 Compare Match A */
2524
+ #define TIMER4_COMPA_vect _VECTOR(42)
2525
+ #define TIMER4_COMPA_vect_num 42
2526
+
2527
+ /* Timer/Counter4 Compare Match B */
2528
+ #define TIMER4_COMPB_vect _VECTOR(43)
2529
+ #define TIMER4_COMPB_vect_num 43
2530
+
2531
+ /* Timer/Counter4 Compare Match C */
2532
+ #define TIMER4_COMPC_vect _VECTOR(44)
2533
+ #define TIMER4_COMPC_vect_num 44
2534
+
2535
+ /* Timer/Counter4 Overflow */
2536
+ #define TIMER4_OVF_vect _VECTOR(45)
2537
+ #define TIMER4_OVF_vect_num 45
2538
+
2539
+ /* Timer/Counter5 Capture Event */
2540
+ #define TIMER5_CAPT_vect _VECTOR(46)
2541
+ #define TIMER5_CAPT_vect_num 46
2542
+
2543
+ /* Timer/Counter5 Compare Match A */
2544
+ #define TIMER5_COMPA_vect _VECTOR(47)
2545
+ #define TIMER5_COMPA_vect_num 47
2546
+
2547
+ /* Timer/Counter5 Compare Match B */
2548
+ #define TIMER5_COMPB_vect _VECTOR(48)
2549
+ #define TIMER5_COMPB_vect_num 48
2550
+
2551
+ /* Timer/Counter5 Compare Match C */
2552
+ #define TIMER5_COMPC_vect _VECTOR(49)
2553
+ #define TIMER5_COMPC_vect_num 49
2554
+
2555
+ /* Timer/Counter5 Overflow */
2556
+ #define TIMER5_OVF_vect _VECTOR(50)
2557
+ #define TIMER5_OVF_vect_num 50
2558
+
2559
+ /* TRX24 - PLL lock interrupt */
2560
+ #define TRX24_PLL_LOCK_vect _VECTOR(57)
2561
+ #define TRX24_PLL_LOCK_vect_num 57
2562
+
2563
+ /* TRX24 - PLL unlock interrupt */
2564
+ #define TRX24_PLL_UNLOCK_vect _VECTOR(58)
2565
+ #define TRX24_PLL_UNLOCK_vect_num 58
2566
+
2567
+ /* TRX24 - Receive start interrupt */
2568
+ #define TRX24_RX_START_vect _VECTOR(59)
2569
+ #define TRX24_RX_START_vect_num 59
2570
+
2571
+ /* TRX24 - RX_END interrupt */
2572
+ #define TRX24_RX_END_vect _VECTOR(60)
2573
+ #define TRX24_RX_END_vect_num 60
2574
+
2575
+ /* TRX24 - CCA/ED done interrupt */
2576
+ #define TRX24_CCA_ED_DONE_vect _VECTOR(61)
2577
+ #define TRX24_CCA_ED_DONE_vect_num 61
2578
+
2579
+ /* TRX24 - XAH - AMI */
2580
+ #define TRX24_XAH_AMI_vect _VECTOR(62)
2581
+ #define TRX24_XAH_AMI_vect_num 62
2582
+
2583
+ /* TRX24 - TX_END interrupt */
2584
+ #define TRX24_TX_END_vect _VECTOR(63)
2585
+ #define TRX24_TX_END_vect_num 63
2586
+
2587
+ /* TRX24 AWAKE - tranceiver is reaching state TRX_OFF */
2588
+ #define TRX24_AWAKE_vect _VECTOR(64)
2589
+ #define TRX24_AWAKE_vect_num 64
2590
+
2591
+ /* Symbol counter - compare match 1 interrupt */
2592
+ #define SCNT_CMP1_vect _VECTOR(65)
2593
+ #define SCNT_CMP1_vect_num 65
2594
+
2595
+ /* Symbol counter - compare match 2 interrupt */
2596
+ #define SCNT_CMP2_vect _VECTOR(66)
2597
+ #define SCNT_CMP2_vect_num 66
2598
+
2599
+ /* Symbol counter - compare match 3 interrupt */
2600
+ #define SCNT_CMP3_vect _VECTOR(67)
2601
+ #define SCNT_CMP3_vect_num 67
2602
+
2603
+ /* Symbol counter - overflow interrupt */
2604
+ #define SCNT_OVFL_vect _VECTOR(68)
2605
+ #define SCNT_OVFL_vect_num 68
2606
+
2607
+ /* Symbol counter - backoff interrupt */
2608
+ #define SCNT_BACKOFF_vect _VECTOR(69)
2609
+ #define SCNT_BACKOFF_vect_num 69
2610
+
2611
+ /* AES engine ready interrupt */
2612
+ #define AES_READY_vect _VECTOR(70)
2613
+ #define AES_READY_vect_num 70
2614
+
2615
+ /* Battery monitor indicates supply voltage below threshold */
2616
+ #define BAT_LOW_vect _VECTOR(71)
2617
+ #define BAT_LOW_vect_num 71
2618
+
2619
+ /* TRX24 TX start interrupt */
2620
+ #define TRX24_TX_START_vect _VECTOR(72)
2621
+ #define TRX24_TX_START_vect_num 72
2622
+
2623
+ /* Address match interrupt of address filter 0 */
2624
+ #define TRX24_AMI0_vect _VECTOR(73)
2625
+ #define TRX24_AMI0_vect_num 73
2626
+
2627
+ /* Address match interrupt of address filter 1 */
2628
+ #define TRX24_AMI1_vect _VECTOR(74)
2629
+ #define TRX24_AMI1_vect_num 74
2630
+
2631
+ /* Address match interrupt of address filter 2 */
2632
+ #define TRX24_AMI2_vect _VECTOR(75)
2633
+ #define TRX24_AMI2_vect_num 75
2634
+
2635
+ /* Address match interrupt of address filter 3 */
2636
+ #define TRX24_AMI3_vect _VECTOR(76)
2637
+ #define TRX24_AMI3_vect_num 76
2638
+
2639
+ #define _VECTORS_SIZE 308
2640
+
2641
+
2642
+ /* Constants */
2643
+
2644
+ #define SPM_PAGESIZE 256
2645
+ #define FLASHSTART 0x0000
2646
+ #define FLASHEND 0x1FFFF
2647
+ #define RAMSTART 0x0200
2648
+ #define RAMSIZE 16384
2649
+ #define RAMEND 0x41FF
2650
+ #define E2START 0
2651
+ #define E2SIZE 4096
2652
+ #define E2PAGESIZE 8
2653
+ #define E2END 0x0FFF
2654
+ #define XRAMEND RAMEND
2655
+
2656
+
2657
+ /* Fuses */
2658
+
2659
+ #define FUSE_MEMORY_SIZE 3
2660
+
2661
+ /* Low Fuse Byte */
2662
+ #define FUSE_CKSEL_SUT0 (unsigned char)~_BV(0)
2663
+ #define FUSE_CKSEL_SUT1 (unsigned char)~_BV(1)
2664
+ #define FUSE_CKSEL_SUT2 (unsigned char)~_BV(2)
2665
+ #define FUSE_CKSEL_SUT3 (unsigned char)~_BV(3)
2666
+ #define FUSE_CKSEL_SUT4 (unsigned char)~_BV(4)
2667
+ #define FUSE_CKSEL_SUT5 (unsigned char)~_BV(5)
2668
+ #define FUSE_CKOUT (unsigned char)~_BV(6)
2669
+ #define FUSE_CKDIV8 (unsigned char)~_BV(7)
2670
+ #define LFUSE_DEFAULT (FUSE_CKSEL_SUT0 & FUSE_CKSEL_SUT2 & FUSE_CKSEL_SUT3 & FUSE_CKSEL_SUT4 & FUSE_CKDIV8)
2671
+
2672
+
2673
+ /* High Fuse Byte */
2674
+ #define FUSE_BOOTRST (unsigned char)~_BV(0)
2675
+ #define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
2676
+ #define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
2677
+ #define FUSE_EESAVE (unsigned char)~_BV(3)
2678
+ #define FUSE_WDTON (unsigned char)~_BV(4)
2679
+ #define FUSE_SPIEN (unsigned char)~_BV(5)
2680
+ #define FUSE_JTAGEN (unsigned char)~_BV(6)
2681
+ #define FUSE_OCDEN (unsigned char)~_BV(7)
2682
+ #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
2683
+
2684
+
2685
+ /* Extended Fuse Byte */
2686
+ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
2687
+ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
2688
+ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
2689
+ #define EFUSE_DEFAULT (FUSE_BODLEVEL0)
2690
+
2691
+
2692
+
2693
+ /* Lock Bits */
2694
+ #define __LOCK_BITS_EXIST
2695
+ #define __BOOT_LOCK_BITS_0_EXIST
2696
+ #define __BOOT_LOCK_BITS_1_EXIST
2697
+
2698
+
2699
+ /* Signature */
2700
+ #define SIGNATURE_0 0x1E
2701
+ #define SIGNATURE_1 0xA7
2702
+ #define SIGNATURE_2 0x02
2703
+
2704
+
2705
+ #endif /* #ifdef _AVR_ATMEGA128RFR2_H_INCLUDED */
2706
+