arduino_ci 0.1.3 → 0.1.4

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Files changed (295) hide show
  1. checksums.yaml +4 -4
  2. data/README.md +77 -1
  3. data/cpp/arduino/Arduino.cpp +17 -7
  4. data/cpp/arduino/Arduino.h +151 -5
  5. data/cpp/arduino/ArduinoDefines.h +90 -0
  6. data/cpp/arduino/AvrMath.h +18 -28
  7. data/cpp/arduino/Godmode.cpp +62 -0
  8. data/cpp/arduino/Godmode.h +74 -0
  9. data/cpp/arduino/HardwareSerial.h +81 -0
  10. data/cpp/arduino/Print.h +67 -0
  11. data/cpp/arduino/Stream.h +210 -0
  12. data/cpp/arduino/WCharacter.h +96 -0
  13. data/cpp/arduino/WString.h +164 -0
  14. data/cpp/arduino/binary.h +518 -0
  15. data/cpp/arduino/include/README.md +3 -0
  16. data/cpp/arduino/include/common.h +333 -0
  17. data/cpp/arduino/include/fuse.h +274 -0
  18. data/cpp/arduino/include/io.h +643 -0
  19. data/cpp/arduino/include/io1200.h +274 -0
  20. data/cpp/arduino/include/io2313.h +385 -0
  21. data/cpp/arduino/include/io2323.h +210 -0
  22. data/cpp/arduino/include/io2333.h +461 -0
  23. data/cpp/arduino/include/io2343.h +214 -0
  24. data/cpp/arduino/include/io43u32x.h +440 -0
  25. data/cpp/arduino/include/io43u35x.h +432 -0
  26. data/cpp/arduino/include/io4414.h +500 -0
  27. data/cpp/arduino/include/io4433.h +489 -0
  28. data/cpp/arduino/include/io4434.h +588 -0
  29. data/cpp/arduino/include/io76c711.h +499 -0
  30. data/cpp/arduino/include/io8515.h +501 -0
  31. data/cpp/arduino/include/io8534.h +217 -0
  32. data/cpp/arduino/include/io8535.h +589 -0
  33. data/cpp/arduino/include/io86r401.h +309 -0
  34. data/cpp/arduino/include/io90pwm1.h +1157 -0
  35. data/cpp/arduino/include/io90pwm161.h +918 -0
  36. data/cpp/arduino/include/io90pwm216.h +1225 -0
  37. data/cpp/arduino/include/io90pwm2b.h +1466 -0
  38. data/cpp/arduino/include/io90pwm316.h +1272 -0
  39. data/cpp/arduino/include/io90pwm3b.h +1466 -0
  40. data/cpp/arduino/include/io90pwm81.h +1036 -0
  41. data/cpp/arduino/include/io90pwmx.h +1415 -0
  42. data/cpp/arduino/include/io90scr100.h +1719 -0
  43. data/cpp/arduino/include/ioa5272.h +803 -0
  44. data/cpp/arduino/include/ioa5505.h +803 -0
  45. data/cpp/arduino/include/ioa5702m322.h +2591 -0
  46. data/cpp/arduino/include/ioa5782.h +1843 -0
  47. data/cpp/arduino/include/ioa5790.h +907 -0
  48. data/cpp/arduino/include/ioa5790n.h +922 -0
  49. data/cpp/arduino/include/ioa5791.h +923 -0
  50. data/cpp/arduino/include/ioa5795.h +756 -0
  51. data/cpp/arduino/include/ioa5831.h +1949 -0
  52. data/cpp/arduino/include/ioa6285.h +740 -0
  53. data/cpp/arduino/include/ioa6286.h +740 -0
  54. data/cpp/arduino/include/ioa6289.h +847 -0
  55. data/cpp/arduino/include/ioa6612c.h +795 -0
  56. data/cpp/arduino/include/ioa6613c.h +795 -0
  57. data/cpp/arduino/include/ioa6614q.h +798 -0
  58. data/cpp/arduino/include/ioa6616c.h +865 -0
  59. data/cpp/arduino/include/ioa6617c.h +865 -0
  60. data/cpp/arduino/include/ioa664251.h +857 -0
  61. data/cpp/arduino/include/ioa8210.h +1843 -0
  62. data/cpp/arduino/include/ioa8510.h +1949 -0
  63. data/cpp/arduino/include/ioat94k.h +565 -0
  64. data/cpp/arduino/include/iocan128.h +100 -0
  65. data/cpp/arduino/include/iocan32.h +100 -0
  66. data/cpp/arduino/include/iocan64.h +100 -0
  67. data/cpp/arduino/include/iocanxx.h +2020 -0
  68. data/cpp/arduino/include/iom103.h +735 -0
  69. data/cpp/arduino/include/iom128.h +1299 -0
  70. data/cpp/arduino/include/iom1280.h +101 -0
  71. data/cpp/arduino/include/iom1281.h +101 -0
  72. data/cpp/arduino/include/iom1284.h +1099 -0
  73. data/cpp/arduino/include/iom1284p.h +1219 -0
  74. data/cpp/arduino/include/iom1284rfr2.h +2690 -0
  75. data/cpp/arduino/include/iom128a.h +1070 -0
  76. data/cpp/arduino/include/iom128rfa1.h +5385 -0
  77. data/cpp/arduino/include/iom128rfr2.h +2706 -0
  78. data/cpp/arduino/include/iom16.h +676 -0
  79. data/cpp/arduino/include/iom161.h +726 -0
  80. data/cpp/arduino/include/iom162.h +1022 -0
  81. data/cpp/arduino/include/iom163.h +686 -0
  82. data/cpp/arduino/include/iom164.h +101 -0
  83. data/cpp/arduino/include/iom164a.h +34 -0
  84. data/cpp/arduino/include/iom164p.h +34 -0
  85. data/cpp/arduino/include/iom164pa.h +1016 -0
  86. data/cpp/arduino/include/iom165.h +887 -0
  87. data/cpp/arduino/include/iom165a.h +832 -0
  88. data/cpp/arduino/include/iom165p.h +889 -0
  89. data/cpp/arduino/include/iom165pa.h +948 -0
  90. data/cpp/arduino/include/iom168.h +97 -0
  91. data/cpp/arduino/include/iom168a.h +35 -0
  92. data/cpp/arduino/include/iom168p.h +942 -0
  93. data/cpp/arduino/include/iom168pa.h +843 -0
  94. data/cpp/arduino/include/iom168pb.h +899 -0
  95. data/cpp/arduino/include/iom169.h +1174 -0
  96. data/cpp/arduino/include/iom169a.h +44 -0
  97. data/cpp/arduino/include/iom169p.h +1097 -0
  98. data/cpp/arduino/include/iom169pa.h +1485 -0
  99. data/cpp/arduino/include/iom16a.h +923 -0
  100. data/cpp/arduino/include/iom16hva.h +80 -0
  101. data/cpp/arduino/include/iom16hva2.h +883 -0
  102. data/cpp/arduino/include/iom16hvb.h +1052 -0
  103. data/cpp/arduino/include/iom16hvbrevb.h +1052 -0
  104. data/cpp/arduino/include/iom16m1.h +1571 -0
  105. data/cpp/arduino/include/iom16u2.h +1000 -0
  106. data/cpp/arduino/include/iom16u4.h +1423 -0
  107. data/cpp/arduino/include/iom2560.h +101 -0
  108. data/cpp/arduino/include/iom2561.h +101 -0
  109. data/cpp/arduino/include/iom2564rfr2.h +2691 -0
  110. data/cpp/arduino/include/iom256rfr2.h +2707 -0
  111. data/cpp/arduino/include/iom3000.h +237 -0
  112. data/cpp/arduino/include/iom32.h +755 -0
  113. data/cpp/arduino/include/iom323.h +744 -0
  114. data/cpp/arduino/include/iom324a.h +1014 -0
  115. data/cpp/arduino/include/iom324p.h +1016 -0
  116. data/cpp/arduino/include/iom324pa.h +1372 -0
  117. data/cpp/arduino/include/iom325.h +886 -0
  118. data/cpp/arduino/include/iom3250.h +982 -0
  119. data/cpp/arduino/include/iom3250a.h +34 -0
  120. data/cpp/arduino/include/iom3250p.h +34 -0
  121. data/cpp/arduino/include/iom3250pa.h +1042 -0
  122. data/cpp/arduino/include/iom325a.h +34 -0
  123. data/cpp/arduino/include/iom325p.h +34 -0
  124. data/cpp/arduino/include/iom325pa.h +937 -0
  125. data/cpp/arduino/include/iom328.h +34 -0
  126. data/cpp/arduino/include/iom328p.h +948 -0
  127. data/cpp/arduino/include/iom329.h +1069 -0
  128. data/cpp/arduino/include/iom3290.h +1227 -0
  129. data/cpp/arduino/include/iom3290a.h +34 -0
  130. data/cpp/arduino/include/iom3290pa.h +1123 -0
  131. data/cpp/arduino/include/iom329a.h +34 -0
  132. data/cpp/arduino/include/iom329p.h +1164 -0
  133. data/cpp/arduino/include/iom329pa.h +34 -0
  134. data/cpp/arduino/include/iom32a.h +686 -0
  135. data/cpp/arduino/include/iom32c1.h +1320 -0
  136. data/cpp/arduino/include/iom32hvb.h +1052 -0
  137. data/cpp/arduino/include/iom32hvbrevb.h +953 -0
  138. data/cpp/arduino/include/iom32m1.h +1625 -0
  139. data/cpp/arduino/include/iom32u2.h +1000 -0
  140. data/cpp/arduino/include/iom32u4.h +1512 -0
  141. data/cpp/arduino/include/iom32u6.h +1431 -0
  142. data/cpp/arduino/include/iom406.h +783 -0
  143. data/cpp/arduino/include/iom48.h +93 -0
  144. data/cpp/arduino/include/iom48a.h +35 -0
  145. data/cpp/arduino/include/iom48p.h +936 -0
  146. data/cpp/arduino/include/iom48pa.h +839 -0
  147. data/cpp/arduino/include/iom48pb.h +890 -0
  148. data/cpp/arduino/include/iom64.h +1311 -0
  149. data/cpp/arduino/include/iom640.h +101 -0
  150. data/cpp/arduino/include/iom644.h +101 -0
  151. data/cpp/arduino/include/iom644a.h +34 -0
  152. data/cpp/arduino/include/iom644p.h +101 -0
  153. data/cpp/arduino/include/iom644pa.h +1387 -0
  154. data/cpp/arduino/include/iom644rfr2.h +2685 -0
  155. data/cpp/arduino/include/iom645.h +881 -0
  156. data/cpp/arduino/include/iom6450.h +978 -0
  157. data/cpp/arduino/include/iom6450a.h +34 -0
  158. data/cpp/arduino/include/iom6450p.h +34 -0
  159. data/cpp/arduino/include/iom645a.h +34 -0
  160. data/cpp/arduino/include/iom645p.h +34 -0
  161. data/cpp/arduino/include/iom649.h +1061 -0
  162. data/cpp/arduino/include/iom6490.h +1182 -0
  163. data/cpp/arduino/include/iom6490a.h +34 -0
  164. data/cpp/arduino/include/iom6490p.h +34 -0
  165. data/cpp/arduino/include/iom649a.h +34 -0
  166. data/cpp/arduino/include/iom649p.h +1490 -0
  167. data/cpp/arduino/include/iom64a.h +1084 -0
  168. data/cpp/arduino/include/iom64c1.h +1321 -0
  169. data/cpp/arduino/include/iom64hve.h +1034 -0
  170. data/cpp/arduino/include/iom64hve2.h +767 -0
  171. data/cpp/arduino/include/iom64m1.h +1572 -0
  172. data/cpp/arduino/include/iom64rfr2.h +2701 -0
  173. data/cpp/arduino/include/iom8.h +665 -0
  174. data/cpp/arduino/include/iom8515.h +687 -0
  175. data/cpp/arduino/include/iom8535.h +772 -0
  176. data/cpp/arduino/include/iom88.h +97 -0
  177. data/cpp/arduino/include/iom88a.h +35 -0
  178. data/cpp/arduino/include/iom88p.h +941 -0
  179. data/cpp/arduino/include/iom88pa.h +1185 -0
  180. data/cpp/arduino/include/iom88pb.h +899 -0
  181. data/cpp/arduino/include/iom8a.h +621 -0
  182. data/cpp/arduino/include/iom8hva.h +76 -0
  183. data/cpp/arduino/include/iom8u2.h +997 -0
  184. data/cpp/arduino/include/iomx8.h +808 -0
  185. data/cpp/arduino/include/iomxx0_1.h +1692 -0
  186. data/cpp/arduino/include/iomxx4.h +954 -0
  187. data/cpp/arduino/include/iomxxhva.h +550 -0
  188. data/cpp/arduino/include/iotn10.h +512 -0
  189. data/cpp/arduino/include/iotn11.h +255 -0
  190. data/cpp/arduino/include/iotn12.h +288 -0
  191. data/cpp/arduino/include/iotn13.h +395 -0
  192. data/cpp/arduino/include/iotn13a.h +394 -0
  193. data/cpp/arduino/include/iotn15.h +363 -0
  194. data/cpp/arduino/include/iotn1634.h +914 -0
  195. data/cpp/arduino/include/iotn167.h +883 -0
  196. data/cpp/arduino/include/iotn20.h +776 -0
  197. data/cpp/arduino/include/iotn22.h +221 -0
  198. data/cpp/arduino/include/iotn2313.h +702 -0
  199. data/cpp/arduino/include/iotn2313a.h +812 -0
  200. data/cpp/arduino/include/iotn24.h +94 -0
  201. data/cpp/arduino/include/iotn24a.h +846 -0
  202. data/cpp/arduino/include/iotn25.h +93 -0
  203. data/cpp/arduino/include/iotn26.h +422 -0
  204. data/cpp/arduino/include/iotn261.h +93 -0
  205. data/cpp/arduino/include/iotn261a.h +987 -0
  206. data/cpp/arduino/include/iotn28.h +297 -0
  207. data/cpp/arduino/include/iotn4.h +477 -0
  208. data/cpp/arduino/include/iotn40.h +767 -0
  209. data/cpp/arduino/include/iotn4313.h +813 -0
  210. data/cpp/arduino/include/iotn43u.h +604 -0
  211. data/cpp/arduino/include/iotn44.h +94 -0
  212. data/cpp/arduino/include/iotn441.h +903 -0
  213. data/cpp/arduino/include/iotn44a.h +844 -0
  214. data/cpp/arduino/include/iotn45.h +93 -0
  215. data/cpp/arduino/include/iotn461.h +94 -0
  216. data/cpp/arduino/include/iotn461a.h +987 -0
  217. data/cpp/arduino/include/iotn48.h +806 -0
  218. data/cpp/arduino/include/iotn5.h +512 -0
  219. data/cpp/arduino/include/iotn828.h +911 -0
  220. data/cpp/arduino/include/iotn84.h +94 -0
  221. data/cpp/arduino/include/iotn841.h +903 -0
  222. data/cpp/arduino/include/iotn84a.h +844 -0
  223. data/cpp/arduino/include/iotn85.h +93 -0
  224. data/cpp/arduino/include/iotn861.h +94 -0
  225. data/cpp/arduino/include/iotn861a.h +988 -0
  226. data/cpp/arduino/include/iotn87.h +859 -0
  227. data/cpp/arduino/include/iotn88.h +806 -0
  228. data/cpp/arduino/include/iotn9.h +477 -0
  229. data/cpp/arduino/include/iotnx4.h +482 -0
  230. data/cpp/arduino/include/iotnx5.h +442 -0
  231. data/cpp/arduino/include/iotnx61.h +541 -0
  232. data/cpp/arduino/include/iousb1286.h +101 -0
  233. data/cpp/arduino/include/iousb1287.h +101 -0
  234. data/cpp/arduino/include/iousb162.h +101 -0
  235. data/cpp/arduino/include/iousb646.h +102 -0
  236. data/cpp/arduino/include/iousb647.h +102 -0
  237. data/cpp/arduino/include/iousb82.h +95 -0
  238. data/cpp/arduino/include/iousbxx2.h +807 -0
  239. data/cpp/arduino/include/iousbxx6_7.h +1336 -0
  240. data/cpp/arduino/include/iox128a1.h +7236 -0
  241. data/cpp/arduino/include/iox128a1u.h +8305 -0
  242. data/cpp/arduino/include/iox128a3.h +6987 -0
  243. data/cpp/arduino/include/iox128a3u.h +7697 -0
  244. data/cpp/arduino/include/iox128a4u.h +7309 -0
  245. data/cpp/arduino/include/iox128b1.h +6872 -0
  246. data/cpp/arduino/include/iox128b3.h +6288 -0
  247. data/cpp/arduino/include/iox128c3.h +6264 -0
  248. data/cpp/arduino/include/iox128d3.h +5749 -0
  249. data/cpp/arduino/include/iox128d4.h +5562 -0
  250. data/cpp/arduino/include/iox16a4.h +6748 -0
  251. data/cpp/arduino/include/iox16a4u.h +7309 -0
  252. data/cpp/arduino/include/iox16c4.h +6078 -0
  253. data/cpp/arduino/include/iox16d4.h +5717 -0
  254. data/cpp/arduino/include/iox16e5.h +7699 -0
  255. data/cpp/arduino/include/iox192a3.h +6987 -0
  256. data/cpp/arduino/include/iox192a3u.h +7697 -0
  257. data/cpp/arduino/include/iox192c3.h +6264 -0
  258. data/cpp/arduino/include/iox192d3.h +5749 -0
  259. data/cpp/arduino/include/iox256a3.h +6987 -0
  260. data/cpp/arduino/include/iox256a3b.h +6983 -0
  261. data/cpp/arduino/include/iox256a3bu.h +7706 -0
  262. data/cpp/arduino/include/iox256a3u.h +7697 -0
  263. data/cpp/arduino/include/iox256c3.h +6264 -0
  264. data/cpp/arduino/include/iox256d3.h +5709 -0
  265. data/cpp/arduino/include/iox32a4.h +6747 -0
  266. data/cpp/arduino/include/iox32a4u.h +7309 -0
  267. data/cpp/arduino/include/iox32c3.h +6264 -0
  268. data/cpp/arduino/include/iox32c4.h +6078 -0
  269. data/cpp/arduino/include/iox32d3.h +5105 -0
  270. data/cpp/arduino/include/iox32d4.h +5685 -0
  271. data/cpp/arduino/include/iox32e5.h +7699 -0
  272. data/cpp/arduino/include/iox384c3.h +6849 -0
  273. data/cpp/arduino/include/iox384d3.h +5833 -0
  274. data/cpp/arduino/include/iox64a1.h +7236 -0
  275. data/cpp/arduino/include/iox64a1u.h +8305 -0
  276. data/cpp/arduino/include/iox64a3.h +6987 -0
  277. data/cpp/arduino/include/iox64a3u.h +7697 -0
  278. data/cpp/arduino/include/iox64a4u.h +7309 -0
  279. data/cpp/arduino/include/iox64b1.h +6454 -0
  280. data/cpp/arduino/include/iox64b3.h +6288 -0
  281. data/cpp/arduino/include/iox64c3.h +6264 -0
  282. data/cpp/arduino/include/iox64d3.h +5764 -0
  283. data/cpp/arduino/include/iox64d4.h +5555 -0
  284. data/cpp/arduino/include/iox8e5.h +7699 -0
  285. data/cpp/arduino/include/lock.h +239 -0
  286. data/cpp/arduino/include/portpins.h +549 -0
  287. data/cpp/arduino/include/version.h +90 -0
  288. data/cpp/arduino/include/xmega.h +71 -0
  289. data/cpp/unittest/Assertion.h +9 -4
  290. data/cpp/unittest/Compare.h +93 -0
  291. data/lib/arduino_ci/arduino_installation.rb +1 -1
  292. data/lib/arduino_ci/cpp_library.rb +4 -1
  293. data/lib/arduino_ci/version.rb +1 -1
  294. data/misc/default.yaml +7 -0
  295. metadata +285 -2
@@ -0,0 +1,101 @@
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+ /* Copyright (c) 2005 Anatoly Sokolov
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+ All rights reserved.
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+
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+ Redistribution and use in source and binary forms, with or without
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+ modification, are permitted provided that the following conditions are met:
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+
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+ * Redistributions of source code must retain the above copyright
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+ notice, this list of conditions and the following disclaimer.
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+
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+ * Redistributions in binary form must reproduce the above copyright
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+ notice, this list of conditions and the following disclaimer in
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+ the documentation and/or other materials provided with the
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+ distribution.
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+
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+ * Neither the name of the copyright holders nor the names of
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+ contributors may be used to endorse or promote products derived
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+ from this software without specific prior written permission.
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+
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+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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+ POSSIBILITY OF SUCH DAMAGE. */
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+
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+ /* $Id: iom640.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */
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+
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+ /* avr/iom640.h - definitions for ATmega640 */
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+
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+ #ifndef _AVR_IOM640_H_
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+ #define _AVR_IOM640_H_ 1
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+
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+ #include "iomxx0_1.h"
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+
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+ /* Constants */
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+ #define SPM_PAGESIZE 256
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+ #define RAMSTART 0x200
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+ #define RAMEND 0x21FF
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+ #define XRAMEND 0xFFFF
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+ #define E2END 0xFFF
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+ #define E2PAGESIZE 8
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+ #define FLASHEND 0xFFFF
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+
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+
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+ /* Fuses */
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+
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+ #define FUSE_MEMORY_SIZE 3
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+
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+ /* Low Fuse Byte */
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+ #define FUSE_CKSEL0 (unsigned char)~_BV(0)
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+ #define FUSE_CKSEL1 (unsigned char)~_BV(1)
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+ #define FUSE_CKSEL2 (unsigned char)~_BV(2)
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+ #define FUSE_CKSEL3 (unsigned char)~_BV(3)
59
+ #define FUSE_SUT0 (unsigned char)~_BV(4)
60
+ #define FUSE_SUT1 (unsigned char)~_BV(5)
61
+ #define FUSE_CKOUT (unsigned char)~_BV(6)
62
+ #define FUSE_CKDIV8 (unsigned char)~_BV(7)
63
+ #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
64
+
65
+ /* High Fuse Byte */
66
+ #define FUSE_BOOTRST (unsigned char)~_BV(0)
67
+ #define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
68
+ #define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
69
+ #define FUSE_EESAVE (unsigned char)~_BV(3)
70
+ #define FUSE_WDTON (unsigned char)~_BV(4)
71
+ #define FUSE_SPIEN (unsigned char)~_BV(5)
72
+ #define FUSE_JTAGEN (unsigned char)~_BV(6)
73
+ #define FUSE_OCDEN (unsigned char)~_BV(7)
74
+ #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
75
+
76
+ /* Extended Fuse Byte */
77
+ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
78
+ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
79
+ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
80
+ #define EFUSE_DEFAULT (0xFF)
81
+
82
+
83
+ /* Lock Bits */
84
+ #define __LOCK_BITS_EXIST
85
+ #define __BOOT_LOCK_BITS_0_EXIST
86
+ #define __BOOT_LOCK_BITS_1_EXIST
87
+
88
+
89
+ /* Signature */
90
+ #define SIGNATURE_0 0x1E
91
+ #define SIGNATURE_1 0x96
92
+ #define SIGNATURE_2 0x08
93
+
94
+ #define SLEEP_MODE_IDLE (0x00<<1)
95
+ #define SLEEP_MODE_ADC (0x01<<1)
96
+ #define SLEEP_MODE_PWR_DOWN (0x02<<1)
97
+ #define SLEEP_MODE_PWR_SAVE (0x03<<1)
98
+ #define SLEEP_MODE_STANDBY (0x06<<1)
99
+ #define SLEEP_MODE_EXT_STANDBY (0x07<<1)
100
+
101
+ #endif /* _AVR_IOM640_H_ */
@@ -0,0 +1,101 @@
1
+ /* Copyright (c) 2005 Anatoly Sokolov
2
+ All rights reserved.
3
+
4
+ Redistribution and use in source and binary forms, with or without
5
+ modification, are permitted provided that the following conditions are met:
6
+
7
+ * Redistributions of source code must retain the above copyright
8
+ notice, this list of conditions and the following disclaimer.
9
+
10
+ * Redistributions in binary form must reproduce the above copyright
11
+ notice, this list of conditions and the following disclaimer in
12
+ the documentation and/or other materials provided with the
13
+ distribution.
14
+
15
+ * Neither the name of the copyright holders nor the names of
16
+ contributors may be used to endorse or promote products derived
17
+ from this software without specific prior written permission.
18
+
19
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29
+ POSSIBILITY OF SUCH DAMAGE. */
30
+
31
+ /* avr/iom644.h - definitions for ATmega644 */
32
+
33
+ /* $Id: iom644.h 2115 2010-04-05 23:19:53Z arcanum $ */
34
+
35
+ #ifndef _AVR_IOM644_H_
36
+ #define _AVR_IOM644_H_ 1
37
+
38
+ #include "iomxx4.h"
39
+
40
+ /* Constants */
41
+ #define SPM_PAGESIZE 256
42
+ #define RAMSTART (0x100)
43
+ #define RAMEND 0x10FF
44
+ #define XRAMEND RAMEND
45
+ #define E2END 0x7FF
46
+ #define E2PAGESIZE 8
47
+ #define FLASHEND 0xFFFF
48
+
49
+
50
+ /* Fuses */
51
+
52
+ #define FUSE_MEMORY_SIZE 3
53
+
54
+ /* Low Fuse Byte */
55
+ #define FUSE_CKSEL0 (unsigned char)~_BV(0)
56
+ #define FUSE_CKSEL1 (unsigned char)~_BV(1)
57
+ #define FUSE_CKSEL2 (unsigned char)~_BV(2)
58
+ #define FUSE_CKSEL3 (unsigned char)~_BV(3)
59
+ #define FUSE_SUT0 (unsigned char)~_BV(4)
60
+ #define FUSE_SUT1 (unsigned char)~_BV(5)
61
+ #define FUSE_CKOUT (unsigned char)~_BV(6)
62
+ #define FUSE_CKDIV8 (unsigned char)~_BV(7)
63
+ #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8)
64
+
65
+ /* High Fuse Byte */
66
+ #define FUSE_BOOTRST (unsigned char)~_BV(0)
67
+ #define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
68
+ #define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
69
+ #define FUSE_EESAVE (unsigned char)~_BV(3)
70
+ #define FUSE_WDTON (unsigned char)~_BV(4)
71
+ #define FUSE_SPIEN (unsigned char)~_BV(5)
72
+ #define FUSE_JTAGEN (unsigned char)~_BV(6)
73
+ #define FUSE_OCDEN (unsigned char)~_BV(7)
74
+ #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
75
+
76
+ /* Extended Fuse Byte */
77
+ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
78
+ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
79
+ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
80
+ #define EFUSE_DEFAULT (0xFF)
81
+
82
+
83
+ /* Lock Bits */
84
+ #define __LOCK_BITS_EXIST
85
+ #define __BOOT_LOCK_BITS_0_EXIST
86
+ #define __BOOT_LOCK_BITS_1_EXIST
87
+
88
+
89
+ /* Signature */
90
+ #define SIGNATURE_0 0x1E
91
+ #define SIGNATURE_1 0x96
92
+ #define SIGNATURE_2 0x09
93
+
94
+ #define SLEEP_MODE_IDLE (0x00<<1)
95
+ #define SLEEP_MODE_ADC (0x01<<1)
96
+ #define SLEEP_MODE_PWR_DOWN (0x02<<1)
97
+ #define SLEEP_MODE_PWR_SAVE (0x03<<1)
98
+ #define SLEEP_MODE_STANDBY (0x06<<1)
99
+ #define SLEEP_MODE_EXT_STANDBY (0x07<<1)
100
+
101
+ #endif /* _AVR_IOM644_H_ */
@@ -0,0 +1,34 @@
1
+ /*****************************************************************************
2
+ *
3
+ * Copyright (C) 2011 Atmel Corporation
4
+ * All rights reserved.
5
+ *
6
+ * Redistribution and use in source and binary forms, with or without
7
+ * modification, are permitted provided that the following conditions are met:
8
+ *
9
+ * * Redistributions of source code must retain the above copyright
10
+ * notice, this list of conditions and the following disclaimer.
11
+ *
12
+ * * Redistributions in binary form must reproduce the above copyright
13
+ * notice, this list of conditions and the following disclaimer in
14
+ * the documentation and/or other materials provided with the
15
+ * distribution.
16
+ *
17
+ * * Neither the name of the copyright holders nor the names of
18
+ * contributors may be used to endorse or promote products derived
19
+ * from this software without specific prior written permission.
20
+ *
21
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31
+ * POSSIBILITY OF SUCH DAMAGE.
32
+ ****************************************************************************/
33
+
34
+ #include "iom644.h"
@@ -0,0 +1,101 @@
1
+ /* Copyright (c) 2005 Anatoly Sokolov
2
+ All rights reserved.
3
+
4
+ Redistribution and use in source and binary forms, with or without
5
+ modification, are permitted provided that the following conditions are met:
6
+
7
+ * Redistributions of source code must retain the above copyright
8
+ notice, this list of conditions and the following disclaimer.
9
+
10
+ * Redistributions in binary form must reproduce the above copyright
11
+ notice, this list of conditions and the following disclaimer in
12
+ the documentation and/or other materials provided with the
13
+ distribution.
14
+
15
+ * Neither the name of the copyright holders nor the names of
16
+ contributors may be used to endorse or promote products derived
17
+ from this software without specific prior written permission.
18
+
19
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29
+ POSSIBILITY OF SUCH DAMAGE. */
30
+
31
+ /* avr/iom644p.h - definitions for ATmega644P */
32
+
33
+ /* $Id: iom644p.h 2115 2010-04-05 23:19:53Z arcanum $ */
34
+
35
+ #ifndef _AVR_IOM644P_H_
36
+ #define _AVR_IOM644P_H_ 1
37
+
38
+ #include "iomxx4.h"
39
+
40
+ /* Constants */
41
+ #define SPM_PAGESIZE 256
42
+ #define RAMSTART (0x100)
43
+ #define RAMEND 0x10FF
44
+ #define XRAMEND RAMEND
45
+ #define E2END 0x7FF
46
+ #define E2PAGESIZE 8
47
+ #define FLASHEND 0xFFFF
48
+
49
+
50
+ /* Fuses */
51
+
52
+ #define FUSE_MEMORY_SIZE 3
53
+
54
+ /* Low Fuse Byte */
55
+ #define FUSE_CKSEL0 (unsigned char)~_BV(0)
56
+ #define FUSE_CKSEL1 (unsigned char)~_BV(1)
57
+ #define FUSE_CKSEL2 (unsigned char)~_BV(2)
58
+ #define FUSE_CKSEL3 (unsigned char)~_BV(3)
59
+ #define FUSE_SUT0 (unsigned char)~_BV(4)
60
+ #define FUSE_SUT1 (unsigned char)~_BV(5)
61
+ #define FUSE_CKOUT (unsigned char)~_BV(6)
62
+ #define FUSE_CKDIV8 (unsigned char)~_BV(7)
63
+ #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8)
64
+
65
+ /* High Fuse Byte */
66
+ #define FUSE_BOOTRST (unsigned char)~_BV(0)
67
+ #define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
68
+ #define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
69
+ #define FUSE_EESAVE (unsigned char)~_BV(3)
70
+ #define FUSE_WDTON (unsigned char)~_BV(4)
71
+ #define FUSE_SPIEN (unsigned char)~_BV(5)
72
+ #define FUSE_JTAGEN (unsigned char)~_BV(6)
73
+ #define FUSE_OCDEN (unsigned char)~_BV(7)
74
+ #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
75
+
76
+ /* Extended Fuse Byte */
77
+ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
78
+ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
79
+ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
80
+ #define EFUSE_DEFAULT (0xFF)
81
+
82
+
83
+ /* Lock Bits */
84
+ #define __LOCK_BITS_EXIST
85
+ #define __BOOT_LOCK_BITS_0_EXIST
86
+ #define __BOOT_LOCK_BITS_1_EXIST
87
+
88
+
89
+ /* Signature */
90
+ #define SIGNATURE_0 0x1E
91
+ #define SIGNATURE_1 0x96
92
+ #define SIGNATURE_2 0x0A
93
+
94
+ #define SLEEP_MODE_IDLE (0x00<<1)
95
+ #define SLEEP_MODE_ADC (0x01<<1)
96
+ #define SLEEP_MODE_PWR_DOWN (0x02<<1)
97
+ #define SLEEP_MODE_PWR_SAVE (0x03<<1)
98
+ #define SLEEP_MODE_STANDBY (0x06<<1)
99
+ #define SLEEP_MODE_EXT_STANDBY (0x07<<1)
100
+
101
+ #endif /* _AVR_IOM644P_H_ */
@@ -0,0 +1,1387 @@
1
+ /* Copyright (c) 2009 Atmel Corporation
2
+ All rights reserved.
3
+
4
+ Redistribution and use in source and binary forms, with or without
5
+ modification, are permitted provided that the following conditions are met:
6
+
7
+ * Redistributions of source code must retain the above copyright
8
+ notice, this list of conditions and the following disclaimer.
9
+
10
+ * Redistributions in binary form must reproduce the above copyright
11
+ notice, this list of conditions and the following disclaimer in
12
+ the documentation and/or other materials provided with the
13
+ distribution.
14
+
15
+ * Neither the name of the copyright holders nor the names of
16
+ contributors may be used to endorse or promote products derived
17
+ from this software without specific prior written permission.
18
+
19
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29
+ POSSIBILITY OF SUCH DAMAGE. */
30
+
31
+ /* $Id: iom644pa.h 2035 2009-11-02 02:44:17Z arcanum $ */
32
+
33
+ /* avr/iom644PA.h - definitions for ATmega644PA */
34
+
35
+ /* This file should only be included from <avr/io.h>, never directly. */
36
+
37
+ #ifndef _AVR_IO_H_
38
+ # error "Include <avr/io.h> instead of this file."
39
+ #endif
40
+
41
+ #ifndef _AVR_IOXXX_H_
42
+ # define _AVR_IOXXX_H_ "iom644PA.h"
43
+ #else
44
+ # error "Attempt to include more than one <avr/ioXXX.h> file."
45
+ #endif
46
+
47
+
48
+ #ifndef _AVR_ATmega644PA_H_
49
+ #define _AVR_ATmega644PA_H_ 1
50
+
51
+
52
+ /* Registers and associated bit numbers. */
53
+
54
+ #define PINA _SFR_IO8(0x00)
55
+ #define PINA0 0
56
+ #define PINA1 1
57
+ #define PINA2 2
58
+ #define PINA3 3
59
+ #define PINA4 4
60
+ #define PINA5 5
61
+ #define PINA6 6
62
+ #define PINA7 7
63
+
64
+ #define DDRA _SFR_IO8(0x01)
65
+ #define DDA0 0
66
+ #define DDA1 1
67
+ #define DDA2 2
68
+ #define DDA3 3
69
+ #define DDA4 4
70
+ #define DDA5 5
71
+ #define DDA6 6
72
+ #define DDA7 7
73
+
74
+ #define PORTA _SFR_IO8(0x02)
75
+ #define PORTA0 0
76
+ #define PORTA1 1
77
+ #define PORTA2 2
78
+ #define PORTA3 3
79
+ #define PORTA4 4
80
+ #define PORTA5 5
81
+ #define PORTA6 6
82
+ #define PORTA7 7
83
+
84
+ #define PINB _SFR_IO8(0x03)
85
+ #define PINB0 0
86
+ #define PINB1 1
87
+ #define PINB2 2
88
+ #define PINB3 3
89
+ #define PINB4 4
90
+ #define PINB5 5
91
+ #define PINB6 6
92
+ #define PINB7 7
93
+
94
+ #define DDRB _SFR_IO8(0x04)
95
+ #define DDB0 0
96
+ #define DDB1 1
97
+ #define DDB2 2
98
+ #define DDB3 3
99
+ #define DDB4 4
100
+ #define DDB5 5
101
+ #define DDB6 6
102
+ #define DDB7 7
103
+
104
+ #define PORTB _SFR_IO8(0x05)
105
+ #define PORTB0 0
106
+ #define PORTB1 1
107
+ #define PORTB2 2
108
+ #define PORTB3 3
109
+ #define PORTB4 4
110
+ #define PORTB5 5
111
+ #define PORTB6 6
112
+ #define PORTB7 7
113
+
114
+ #define PINC _SFR_IO8(0x06)
115
+ #define PINC0 0
116
+ #define PINC1 1
117
+ #define PINC2 2
118
+ #define PINC3 3
119
+ #define PINC4 4
120
+ #define PINC5 5
121
+ #define PINC6 6
122
+ #define PINC7 7
123
+
124
+ #define DDRC _SFR_IO8(0x07)
125
+ #define DDC0 0
126
+ #define DDC1 1
127
+ #define DDC2 2
128
+ #define DDC3 3
129
+ #define DDC4 4
130
+ #define DDC5 5
131
+ #define DDC6 6
132
+ #define DDC7 7
133
+
134
+ #define PORTC _SFR_IO8(0x08)
135
+ #define PORTC0 0
136
+ #define PORTC1 1
137
+ #define PORTC2 2
138
+ #define PORTC3 3
139
+ #define PORTC4 4
140
+ #define PORTC5 5
141
+ #define PORTC6 6
142
+ #define PORTC7 7
143
+
144
+ #define PIND _SFR_IO8(0x09)
145
+ #define PIND0 0
146
+ #define PIND1 1
147
+ #define PIND2 2
148
+ #define PIND3 3
149
+ #define PIND4 4
150
+ #define PIND5 5
151
+ #define PIND6 6
152
+ #define PIND7 7
153
+
154
+ #define DDRD _SFR_IO8(0x0A)
155
+ #define DDD0 0
156
+ #define DDD1 1
157
+ #define DDD2 2
158
+ #define DDD3 3
159
+ #define DDD4 4
160
+ #define DDD5 5
161
+ #define DDD6 6
162
+ #define DDD7 7
163
+
164
+ #define PORTD _SFR_IO8(0x0B)
165
+ #define PORTD0 0
166
+ #define PORTD1 1
167
+ #define PORTD2 2
168
+ #define PORTD3 3
169
+ #define PORTD4 4
170
+ #define PORTD5 5
171
+ #define PORTD6 6
172
+ #define PORTD7 7
173
+
174
+ #define TIFR0 _SFR_IO8(0x15)
175
+ #define TOV0 0
176
+ #define OCF0A 1
177
+ #define OCF0B 2
178
+
179
+ #define TIFR1 _SFR_IO8(0x16)
180
+ #define TOV1 0
181
+ #define OCF1A 1
182
+ #define OCF1B 2
183
+ #define ICF1 5
184
+
185
+ #define TIFR2 _SFR_IO8(0x17)
186
+ #define TOV2 0
187
+ #define OCF2A 1
188
+ #define OCF2B 2
189
+
190
+ #define PCIFR _SFR_IO8(0x1B)
191
+ #define PCIF0 0
192
+ #define PCIF1 1
193
+ #define PCIF2 2
194
+ #define PCIF3 3
195
+
196
+ #define EIFR _SFR_IO8(0x1C)
197
+ #define INTF0 0
198
+ #define INTF1 1
199
+ #define INTF2 2
200
+
201
+ #define EIMSK _SFR_IO8(0x1D)
202
+ #define INT0 0
203
+ #define INT1 1
204
+ #define INT2 2
205
+
206
+ #define GPIOR0 _SFR_IO8(0x1E)
207
+ #define GPIOR00 0
208
+ #define GPIOR01 1
209
+ #define GPIOR02 2
210
+ #define GPIOR03 3
211
+ #define GPIOR04 4
212
+ #define GPIOR05 5
213
+ #define GPIOR06 6
214
+ #define GPIOR07 7
215
+
216
+ #define EECR _SFR_IO8(0x1F)
217
+ #define EERE 0
218
+ #define EEPE 1
219
+ #define EEMPE 2
220
+ #define EERIE 3
221
+ #define EEPM0 4
222
+ #define EEPM1 5
223
+
224
+ #define EEDR _SFR_IO8(0x20)
225
+ #define EEDR0 0
226
+ #define EEDR1 1
227
+ #define EEDR2 2
228
+ #define EEDR3 3
229
+ #define EEDR4 4
230
+ #define EEDR5 5
231
+ #define EEDR6 6
232
+ #define EEDR7 7
233
+
234
+ #define EEAR _SFR_IO16(0x21)
235
+
236
+ #define EEARL _SFR_IO8(0x21)
237
+ #define EEAR0 0
238
+ #define EEAR1 1
239
+ #define EEAR2 2
240
+ #define EEAR3 3
241
+ #define EEAR4 4
242
+ #define EEAR5 5
243
+ #define EEAR6 6
244
+ #define EEAR7 7
245
+
246
+ #define EEARH _SFR_IO8(0x22)
247
+ #define EEAR8 0
248
+ #define EEAR9 1
249
+ #define EEAR10 2
250
+ #define EEAR11 3
251
+
252
+ #define GTCCR _SFR_IO8(0x23)
253
+ #define PSRSYNC 0
254
+ #define PSRASY 1
255
+ #define TSM 7
256
+
257
+ #define TCCR0A _SFR_IO8(0x24)
258
+ #define WGM00 0
259
+ #define WGM01 1
260
+ #define COM0B0 4
261
+ #define COM0B1 5
262
+ #define COM0A0 6
263
+ #define COM0A1 7
264
+
265
+ #define TCCR0B _SFR_IO8(0x25)
266
+ #define CS00 0
267
+ #define CS01 1
268
+ #define CS02 2
269
+ #define WGM02 3
270
+ #define FOC0B 6
271
+ #define FOC0A 7
272
+
273
+ #define TCNT0 _SFR_IO8(0x26)
274
+ #define TCNT0_0 0
275
+ #define TCNT0_1 1
276
+ #define TCNT0_2 2
277
+ #define TCNT0_3 3
278
+ #define TCNT0_4 4
279
+ #define TCNT0_5 5
280
+ #define TCNT0_6 6
281
+ #define TCNT0_7 7
282
+
283
+ #define OCR0A _SFR_IO8(0x27)
284
+ #define OCR0A_0 0
285
+ #define OCR0A_1 1
286
+ #define OCR0A_2 2
287
+ #define OCR0A_3 3
288
+ #define OCR0A_4 4
289
+ #define OCR0A_5 5
290
+ #define OCR0A_6 6
291
+ #define OCR0A_7 7
292
+
293
+ #define OCR0B _SFR_IO8(0x28)
294
+ #define OCR0B_0 0
295
+ #define OCR0B_1 1
296
+ #define OCR0B_2 2
297
+ #define OCR0B_3 3
298
+ #define OCR0B_4 4
299
+ #define OCR0B_5 5
300
+ #define OCR0B_6 6
301
+ #define OCR0B_7 7
302
+
303
+ #define GPIOR1 _SFR_IO8(0x2A)
304
+ #define GPIOR10 0
305
+ #define GPIOR11 1
306
+ #define GPIOR12 2
307
+ #define GPIOR13 3
308
+ #define GPIOR14 4
309
+ #define GPIOR15 5
310
+ #define GPIOR16 6
311
+ #define GPIOR17 7
312
+
313
+ #define GPIOR2 _SFR_IO8(0x2B)
314
+ #define GPIOR20 0
315
+ #define GPIOR21 1
316
+ #define GPIOR22 2
317
+ #define GPIOR23 3
318
+ #define GPIOR24 4
319
+ #define GPIOR25 5
320
+ #define GPIOR26 6
321
+ #define GPIOR27 7
322
+
323
+ #define SPCR _SFR_IO8(0x2C)
324
+ #define SPR0 0
325
+ #define SPR1 1
326
+ #define CPHA 2
327
+ #define CPOL 3
328
+ #define MSTR 4
329
+ #define DORD 5
330
+ #define SPE 6
331
+ #define SPIE 7
332
+
333
+ #define SPSR _SFR_IO8(0x2D)
334
+ #define SPI2X 0
335
+ #define WCOL 6
336
+ #define SPIF 7
337
+
338
+ #define SPDR _SFR_IO8(0x2E)
339
+ #define SPDR0 0
340
+ #define SPDR1 1
341
+ #define SPDR2 2
342
+ #define SPDR3 3
343
+ #define SPDR4 4
344
+ #define SPDR5 5
345
+ #define SPDR6 6
346
+ #define SPDR7 7
347
+
348
+ #define ACSR _SFR_IO8(0x30)
349
+ #define ACIS0 0
350
+ #define ACIS1 1
351
+ #define ACIC 2
352
+ #define ACIE 3
353
+ #define ACI 4
354
+ #define ACO 5
355
+ #define ACBG 6
356
+ #define ACD 7
357
+
358
+ #define OCDR _SFR_IO8(0x31)
359
+ #define OCDR0 0
360
+ #define OCDR1 1
361
+ #define OCDR2 2
362
+ #define OCDR3 3
363
+ #define OCDR4 4
364
+ #define OCDR5 5
365
+ #define OCDR6 6
366
+ #define OCDR7 7
367
+
368
+ #define SMCR _SFR_IO8(0x33)
369
+ #define SE 0
370
+ #define SM0 1
371
+ #define SM1 2
372
+ #define SM2 3
373
+
374
+ #define MCUSR _SFR_IO8(0x34)
375
+ #define PORF 0
376
+ #define EXTRF 1
377
+ #define BORF 2
378
+ #define WDRF 3
379
+ #define JTRF 4
380
+
381
+ #define MCUCR _SFR_IO8(0x35)
382
+ #define IVCE 0
383
+ #define IVSEL 1
384
+ #define PUD 4
385
+ #define BODSE 5
386
+ #define BODS 6
387
+ #define JTD 7
388
+
389
+ #define SPMCSR _SFR_IO8(0x37)
390
+ #define SPMEN 0
391
+ #define PGERS 1
392
+ #define PGWRT 2
393
+ #define BLBSET 3
394
+ #define RWWSRE 4
395
+ #define SIGRD 5
396
+ #define RWWSB 6
397
+ #define SPMIE 7
398
+
399
+ #define WDTCSR _SFR_MEM8(0x60)
400
+ #define WDP0 0
401
+ #define WDP1 1
402
+ #define WDP2 2
403
+ #define WDE 3
404
+ #define WDCE 4
405
+ #define WDP3 5
406
+ #define WDIE 6
407
+ #define WDIF 7
408
+
409
+ #define CLKPR _SFR_MEM8(0x61)
410
+ #define CLKPS0 0
411
+ #define CLKPS1 1
412
+ #define CLKPS2 2
413
+ #define CLKPS3 3
414
+ #define CLKPCE 7
415
+
416
+ #define PRR0 _SFR_MEM8(0x64)
417
+ #define PRADC 0
418
+ #define PRUSART0 1
419
+ #define PRSPI 2
420
+ #define PRTIM1 3
421
+ #define PRUSART1 4
422
+ #define PRTIM0 5
423
+ #define PRTIM2 6
424
+ #define PRTWI 7
425
+
426
+ #define __AVR_HAVE_PRR0 ((1<<PRADC)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRUSART0)|(1<<PRUSART1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
427
+ #define __AVR_HAVE_PRR0_PRADC
428
+ #define __AVR_HAVE_PRR0_PRSPI
429
+ #define __AVR_HAVE_PRR0_PRTIM1
430
+ #define __AVR_HAVE_PRR0_PRUSART0
431
+ #define __AVR_HAVE_PRR0_PRUSART1
432
+ #define __AVR_HAVE_PRR0_PRTIM0
433
+ #define __AVR_HAVE_PRR0_PRTIM2
434
+ #define __AVR_HAVE_PRR0_PRTWI
435
+
436
+ #define OSCCAL _SFR_MEM8(0x66)
437
+ #define CAL0 0
438
+ #define CAL1 1
439
+ #define CAL2 2
440
+ #define CAL3 3
441
+ #define CAL4 4
442
+ #define CAL5 5
443
+ #define CAL6 6
444
+ #define CAL7 7
445
+
446
+ #define PCICR _SFR_MEM8(0x68)
447
+ #define PCIE0 0
448
+ #define PCIE1 1
449
+ #define PCIE2 2
450
+ #define PCIE3 3
451
+
452
+ #define EICRA _SFR_MEM8(0x69)
453
+ #define ISC00 0
454
+ #define ISC01 1
455
+ #define ISC10 2
456
+ #define ISC11 3
457
+ #define ISC20 4
458
+ #define ISC21 5
459
+
460
+ #define PCMSK0 _SFR_MEM8(0x6B)
461
+ #define PCINT0 0
462
+ #define PCINT1 1
463
+ #define PCINT2 2
464
+ #define PCINT3 3
465
+ #define PCINT4 4
466
+ #define PCINT5 5
467
+ #define PCINT6 6
468
+ #define PCINT7 7
469
+
470
+ #define PCMSK1 _SFR_MEM8(0x6C)
471
+ #define PCINT8 0
472
+ #define PCINT9 1
473
+ #define PCINT10 2
474
+ #define PCINT11 3
475
+ #define PCINT12 4
476
+ #define PCINT13 5
477
+ #define PCINT14 6
478
+ #define PCINT15 7
479
+
480
+ #define PCMSK2 _SFR_MEM8(0x6D)
481
+ #define PCINT16 0
482
+ #define PCINT17 1
483
+ #define PCINT18 2
484
+ #define PCINT19 3
485
+ #define PCINT20 4
486
+ #define PCINT21 5
487
+ #define PCINT22 6
488
+ #define PCINT23 7
489
+
490
+ #define TIMSK0 _SFR_MEM8(0x6E)
491
+ #define TOIE0 0
492
+ #define OCIE0A 1
493
+ #define OCIE0B 2
494
+
495
+ #define TIMSK1 _SFR_MEM8(0x6F)
496
+ #define TOIE1 0
497
+ #define OCIE1A 1
498
+ #define OCIE1B 2
499
+ #define ICIE1 5
500
+
501
+ #define TIMSK2 _SFR_MEM8(0x70)
502
+ #define TOIE2 0
503
+ #define OCIE2A 1
504
+ #define OCIE2B 2
505
+
506
+ #define PCMSK3 _SFR_MEM8(0x73)
507
+ #define PCINT24 0
508
+ #define PCINT25 1
509
+ #define PCINT26 2
510
+ #define PCINT27 3
511
+ #define PCINT28 4
512
+ #define PCINT29 5
513
+ #define PCINT30 6
514
+ #define PCINT31 7
515
+
516
+ #ifndef __ASSEMBLER__
517
+ #define ADC _SFR_MEM16(0x78)
518
+ #endif
519
+ #define ADCW _SFR_MEM16(0x78)
520
+
521
+ #define ADCL _SFR_MEM8(0x78)
522
+ #define ADCL0 0
523
+ #define ADCL1 1
524
+ #define ADCL2 2
525
+ #define ADCL3 3
526
+ #define ADCL4 4
527
+ #define ADCL5 5
528
+ #define ADCL6 6
529
+ #define ADCL7 7
530
+
531
+ #define ADCH _SFR_MEM8(0x79)
532
+ #define ADCH0 0
533
+ #define ADCH1 1
534
+ #define ADCH2 2
535
+ #define ADCH3 3
536
+ #define ADCH4 4
537
+ #define ADCH5 5
538
+ #define ADCH6 6
539
+ #define ADCH7 7
540
+
541
+ #define ADCSRA _SFR_MEM8(0x7A)
542
+ #define ADPS0 0
543
+ #define ADPS1 1
544
+ #define ADPS2 2
545
+ #define ADIE 3
546
+ #define ADIF 4
547
+ #define ADATE 5
548
+ #define ADSC 6
549
+ #define ADEN 7
550
+
551
+ #define ADCSRB _SFR_MEM8(0x7B)
552
+ #define ADTS0 0
553
+ #define ADTS1 1
554
+ #define ADTS2 2
555
+ #define ACME 6
556
+
557
+ #define ADMUX _SFR_MEM8(0x7C)
558
+ #define MUX0 0
559
+ #define MUX1 1
560
+ #define MUX2 2
561
+ #define MUX3 3
562
+ #define MUX4 4
563
+ #define ADLAR 5
564
+ #define REFS0 6
565
+ #define REFS1 7
566
+
567
+ #define DIDR0 _SFR_MEM8(0x7E)
568
+ #define ADC0D 0
569
+ #define ADC1D 1
570
+ #define ADC2D 2
571
+ #define ADC3D 3
572
+ #define ADC4D 4
573
+ #define ADC5D 5
574
+ #define ADC6D 6
575
+ #define ADC7D 7
576
+
577
+ #define DIDR1 _SFR_MEM8(0x7F)
578
+ #define AIN0D 0
579
+ #define AIN1D 1
580
+
581
+ #define TCCR1A _SFR_MEM8(0x80)
582
+ #define WGM10 0
583
+ #define WGM11 1
584
+ #define COM1B0 4
585
+ #define COM1B1 5
586
+ #define COM1A0 6
587
+ #define COM1A1 7
588
+
589
+ #define TCCR1B _SFR_MEM8(0x81)
590
+ #define CS10 0
591
+ #define CS11 1
592
+ #define CS12 2
593
+ #define WGM12 3
594
+ #define WGM13 4
595
+ #define ICES1 6
596
+ #define ICNC1 7
597
+
598
+ #define TCCR1C _SFR_MEM8(0x82)
599
+ #define FOC1B 6
600
+ #define FOC1A 7
601
+
602
+ #define TCNT1 _SFR_MEM16(0x84)
603
+
604
+ #define TCNT1L _SFR_MEM8(0x84)
605
+ #define TCNT1L0 0
606
+ #define TCNT1L1 1
607
+ #define TCNT1L2 2
608
+ #define TCNT1L3 3
609
+ #define TCNT1L4 4
610
+ #define TCNT1L5 5
611
+ #define TCNT1L6 6
612
+ #define TCNT1L7 7
613
+
614
+ #define TCNT1H _SFR_MEM8(0x85)
615
+ #define TCNT1H0 0
616
+ #define TCNT1H1 1
617
+ #define TCNT1H2 2
618
+ #define TCNT1H3 3
619
+ #define TCNT1H4 4
620
+ #define TCNT1H5 5
621
+ #define TCNT1H6 6
622
+ #define TCNT1H7 7
623
+
624
+ #define ICR1 _SFR_MEM16(0x86)
625
+
626
+ #define ICR1L _SFR_MEM8(0x86)
627
+ #define ICR1L0 0
628
+ #define ICR1L1 1
629
+ #define ICR1L2 2
630
+ #define ICR1L3 3
631
+ #define ICR1L4 4
632
+ #define ICR1L5 5
633
+ #define ICR1L6 6
634
+ #define ICR1L7 7
635
+
636
+ #define ICR1H _SFR_MEM8(0x87)
637
+ #define ICR1H0 0
638
+ #define ICR1H1 1
639
+ #define ICR1H2 2
640
+ #define ICR1H3 3
641
+ #define ICR1H4 4
642
+ #define ICR1H5 5
643
+ #define ICR1H6 6
644
+ #define ICR1H7 7
645
+
646
+ #define OCR1A _SFR_MEM16(0x88)
647
+
648
+ #define OCR1AL _SFR_MEM8(0x88)
649
+ #define OCR1AL0 0
650
+ #define OCR1AL1 1
651
+ #define OCR1AL2 2
652
+ #define OCR1AL3 3
653
+ #define OCR1AL4 4
654
+ #define OCR1AL5 5
655
+ #define OCR1AL6 6
656
+ #define OCR1AL7 7
657
+
658
+ #define OCR1AH _SFR_MEM8(0x89)
659
+ #define OCR1AH0 0
660
+ #define OCR1AH1 1
661
+ #define OCR1AH2 2
662
+ #define OCR1AH3 3
663
+ #define OCR1AH4 4
664
+ #define OCR1AH5 5
665
+ #define OCR1AH6 6
666
+ #define OCR1AH7 7
667
+
668
+ #define OCR1B _SFR_MEM16(0x8A)
669
+
670
+ #define OCR1BL _SFR_MEM8(0x8A)
671
+ #define OCR1BL0 0
672
+ #define OCR1BL1 1
673
+ #define OCR1BL2 2
674
+ #define OCR1BL3 3
675
+ #define OCR1BL4 4
676
+ #define OCR1BL5 5
677
+ #define OCR1BL6 6
678
+ #define OCR1BL7 7
679
+
680
+ #define OCR1BH _SFR_MEM8(0x8B)
681
+ #define OCR1BH0 0
682
+ #define OCR1BH1 1
683
+ #define OCR1BH2 2
684
+ #define OCR1BH3 3
685
+ #define OCR1BH4 4
686
+ #define OCR1BH5 5
687
+ #define OCR1BH6 6
688
+ #define OCR1BH7 7
689
+
690
+ #define TCCR2A _SFR_MEM8(0xB0)
691
+ #define WGM20 0
692
+ #define WGM21 1
693
+ #define COM2B0 4
694
+ #define COM2B1 5
695
+ #define COM2A0 6
696
+ #define COM2A1 7
697
+
698
+ #define TCCR2B _SFR_MEM8(0xB1)
699
+ #define CS20 0
700
+ #define CS21 1
701
+ #define CS22 2
702
+ #define WGM22 3
703
+ #define FOC2B 6
704
+ #define FOC2A 7
705
+
706
+ #define TCNT2 _SFR_MEM8(0xB2)
707
+ #define TCNT2_0 0
708
+ #define TCNT2_1 1
709
+ #define TCNT2_2 2
710
+ #define TCNT2_3 3
711
+ #define TCNT2_4 4
712
+ #define TCNT2_5 5
713
+ #define TCNT2_6 6
714
+ #define TCNT2_7 7
715
+
716
+ #define OCR2A _SFR_MEM8(0xB3)
717
+ #define OCR2A_0 0
718
+ #define OCR2A_1 1
719
+ #define OCR2A_2 2
720
+ #define OCR2A_3 3
721
+ #define OCR2A_4 4
722
+ #define OCR2A_5 5
723
+ #define OCR2A_6 6
724
+ #define OCR2A_7 7
725
+
726
+ #define OCR2B _SFR_MEM8(0xB4)
727
+ #define OCR2B_0 0
728
+ #define OCR2B_1 1
729
+ #define OCR2B_2 2
730
+ #define OCR2B_3 3
731
+ #define OCR2B_4 4
732
+ #define OCR2B_5 5
733
+ #define OCR2B_6 6
734
+ #define OCR2B_7 7
735
+
736
+ #define ASSR _SFR_MEM8(0xB6)
737
+ #define TCR2BUB 0
738
+ #define TCR2AUB 1
739
+ #define OCR2BUB 2
740
+ #define OCR2AUB 3
741
+ #define TCN2UB 4
742
+ #define AS2 5
743
+ #define EXCLK 6
744
+
745
+ #define TWBR _SFR_MEM8(0xB8)
746
+ #define TWBR0 0
747
+ #define TWBR1 1
748
+ #define TWBR2 2
749
+ #define TWBR3 3
750
+ #define TWBR4 4
751
+ #define TWBR5 5
752
+ #define TWBR6 6
753
+ #define TWBR7 7
754
+
755
+ #define TWSR _SFR_MEM8(0xB9)
756
+ #define TWPS0 0
757
+ #define TWPS1 1
758
+ #define TWS3 3
759
+ #define TWS4 4
760
+ #define TWS5 5
761
+ #define TWS6 6
762
+ #define TWS7 7
763
+
764
+ #define TWAR _SFR_MEM8(0xBA)
765
+ #define TWGCE 0
766
+ #define TWA0 1
767
+ #define TWA1 2
768
+ #define TWA2 3
769
+ #define TWA3 4
770
+ #define TWA4 5
771
+ #define TWA5 6
772
+ #define TWA6 7
773
+
774
+ #define TWDR _SFR_MEM8(0xBB)
775
+ #define TWD0 0
776
+ #define TWD1 1
777
+ #define TWD2 2
778
+ #define TWD3 3
779
+ #define TWD4 4
780
+ #define TWD5 5
781
+ #define TWD6 6
782
+ #define TWD7 7
783
+
784
+ #define TWCR _SFR_MEM8(0xBC)
785
+ #define TWIE 0
786
+ #define TWEN 2
787
+ #define TWWC 3
788
+ #define TWSTO 4
789
+ #define TWSTA 5
790
+ #define TWEA 6
791
+ #define TWINT 7
792
+
793
+ #define TWAMR _SFR_MEM8(0xBD)
794
+ #define TWAM0 1
795
+ #define TWAM1 2
796
+ #define TWAM2 3
797
+ #define TWAM3 4
798
+ #define TWAM4 5
799
+ #define TWAM5 6
800
+ #define TWAM6 7
801
+
802
+ #define UCSR0A _SFR_MEM8(0xC0)
803
+ #define MPCM0 0
804
+ #define U2X0 1
805
+ #define UPE0 2
806
+ #define DOR0 3
807
+ #define FE0 4
808
+ #define UDRE0 5
809
+ #define TXC0 6
810
+ #define RXC0 7
811
+
812
+ #define UCSR0B _SFR_MEM8(0xC1)
813
+ #define TXB80 0
814
+ #define RXB80 1
815
+ #define UCSZ02 2
816
+ #define TXEN0 3
817
+ #define RXEN0 4
818
+ #define UDRIE0 5
819
+ #define TXCIE0 6
820
+ #define RXCIE0 7
821
+
822
+ #define UCSR0C _SFR_MEM8(0xC2)
823
+ #define UCPOL0 0
824
+ #define UCSZ00 1
825
+ #define UCSZ01 2
826
+ #define USBS0 3
827
+ #define UPM00 4
828
+ #define UPM01 5
829
+ #define UMSEL00 6
830
+ #define UMSEL01 7
831
+
832
+ #define UBRR0 _SFR_MEM16(0xC4)
833
+
834
+ #define UBRR0L _SFR_MEM8(0xC4)
835
+ #define _UBRR0 0
836
+ #define _UBRR1 1
837
+ #define UBRR2 2
838
+ #define UBRR3 3
839
+ #define UBRR4 4
840
+ #define UBRR5 5
841
+ #define UBRR6 6
842
+ #define UBRR7 7
843
+
844
+ #define UBRR0H _SFR_MEM8(0xC5)
845
+ #define UBRR8 0
846
+ #define UBRR9 1
847
+ #define UBRR10 2
848
+ #define UBRR11 3
849
+
850
+ #define UDR0 _SFR_MEM8(0xC6)
851
+ #define UDR0_0 0
852
+ #define UDR0_1 1
853
+ #define UDR0_2 2
854
+ #define UDR0_3 3
855
+ #define UDR0_4 4
856
+ #define UDR0_5 5
857
+ #define UDR0_6 6
858
+ #define UDR0_7 7
859
+
860
+ #define UCSR1A _SFR_MEM8(0xC8)
861
+ #define MPCM1 0
862
+ #define U2X1 1
863
+ #define UPE1 2
864
+ #define DOR1 3
865
+ #define FE1 4
866
+ #define UDRE1 5
867
+ #define TXC1 6
868
+ #define RXC1 7
869
+
870
+ #define UCSR1B _SFR_MEM8(0xC9)
871
+ #define TXB81 0
872
+ #define RXB81 1
873
+ #define UCSZ12 2
874
+ #define TXEN1 3
875
+ #define RXEN1 4
876
+ #define UDRIE1 5
877
+ #define TXCIE1 6
878
+ #define RXCIE1 7
879
+
880
+ #define UCSR1C _SFR_MEM8(0xCA)
881
+ #define UCPOL1 0
882
+ #define UCSZ10 1
883
+ #define UCSZ11 2
884
+ #define USBS1 3
885
+ #define UPM10 4
886
+ #define UPM11 5
887
+ #define UMSEL10 6
888
+ #define UMSEL11 7
889
+
890
+ #define UBRR1 _SFR_MEM16(0xCC)
891
+
892
+ #define UBRR1L _SFR_MEM8(0xCC)
893
+ #define UBRR_0 0
894
+ #define UBRR_1 1
895
+ #define UBRR_2 2
896
+ #define UBRR_3 3
897
+ #define UBRR_4 4
898
+ #define UBRR_5 5
899
+ #define UBRR_6 6
900
+ #define UBRR_7 7
901
+
902
+ #define UBRR1H _SFR_MEM8(0xCD)
903
+ #define UBRR_8 0
904
+ #define UBRR_9 1
905
+ #define UBRR_10 2
906
+ #define UBRR_11 3
907
+
908
+ #define UDR1 _SFR_MEM8(0xCE)
909
+ #define UDR1_0 0
910
+ #define UDR1_1 1
911
+ #define UDR1_2 2
912
+ #define UDR1_3 3
913
+ #define UDR1_4 4
914
+ #define UDR1_5 5
915
+ #define UDR1_6 6
916
+ #define UDR1_7 7
917
+
918
+
919
+ /* Interrupt vectors */
920
+ /* Vector 0 is the reset vector */
921
+ #define INT0_vect_num 1
922
+ #define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */
923
+ #define INT1_vect_num 2
924
+ #define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */
925
+ #define INT2_vect_num 3
926
+ #define INT2_vect _VECTOR(3) /* External Interrupt Request 2 */
927
+ #define PCINT0_vect_num 4
928
+ #define PCINT0_vect _VECTOR(4) /* Pin Change Interrupt Request 0 */
929
+ #define PCINT1_vect_num 5
930
+ #define PCINT1_vect _VECTOR(5) /* Pin Change Interrupt Request 1 */
931
+ #define PCINT2_vect_num 6
932
+ #define PCINT2_vect _VECTOR(6) /* Pin Change Interrupt Request 2 */
933
+ #define PCINT3_vect_num 7
934
+ #define PCINT3_vect _VECTOR(7) /* Pin Change Interrupt Request 3 */
935
+ #define WDT_vect_num 8
936
+ #define WDT_vect _VECTOR(8) /* Watchdog Time-out Interrupt */
937
+ #define TIMER2_COMPA_vect_num 9
938
+ #define TIMER2_COMPA_vect _VECTOR(9) /* Timer/Counter2 Compare Match A */
939
+ #define TIMER2_COMPB_vect_num 10
940
+ #define TIMER2_COMPB_vect _VECTOR(10) /* Timer/Counter2 Compare Match B */
941
+ #define TIMER2_OVF_vect_num 11
942
+ #define TIMER2_OVF_vect _VECTOR(11) /* Timer/Counter2 Overflow */
943
+ #define TIMER1_CAPT_vect_num 12
944
+ #define TIMER1_CAPT_vect _VECTOR(12) /* Timer/Counter1 Capture Event */
945
+ #define TIMER1_COMPA_vect_num 13
946
+ #define TIMER1_COMPA_vect _VECTOR(13) /* Timer/Counter1 Compare Match A */
947
+ #define TIMER1_COMPB_vect_num 14
948
+ #define TIMER1_COMPB_vect _VECTOR(14) /* Timer/Counter1 Compare Match B */
949
+ #define TIMER1_OVF_vect_num 15
950
+ #define TIMER1_OVF_vect _VECTOR(15) /* Timer/Counter1 Overflow */
951
+ #define TIMER0_COMPA_vect_num 16
952
+ #define TIMER0_COMPA_vect _VECTOR(16) /* Timer/Counter0 Compare Match A */
953
+ #define TIMER0_COMPB_vect_num 17
954
+ #define TIMER0_COMPB_vect _VECTOR(17) /* Timer/Counter0 Compare Match B */
955
+ #define TIMER0_OVF_vect_num 18
956
+ #define TIMER0_OVF_vect _VECTOR(18) /* Timer/Counter0 Overflow */
957
+ #define SPI_STC_vect_num 19
958
+ #define SPI_STC_vect _VECTOR(19) /* SPI Serial Transfer Complete */
959
+ #define USART0_RX_vect_num 20
960
+ #define USART0_RX_vect _VECTOR(20) /* USART0, Rx Complete */
961
+ #define USART0_UDRE_vect_num 21
962
+ #define USART0_UDRE_vect _VECTOR(21) /* USART0 Data register Empty */
963
+ #define USART0_TX_vect_num 22
964
+ #define USART0_TX_vect _VECTOR(22) /* USART0, Tx Complete */
965
+ #define ANALOG_COMP_vect_num 23
966
+ #define ANALOG_COMP_vect _VECTOR(23) /* Analog Comparator */
967
+ #define ADC_vect_num 24
968
+ #define ADC_vect _VECTOR(24) /* ADC Conversion Complete */
969
+ #define EE_READY_vect_num 25
970
+ #define EE_READY_vect _VECTOR(25) /* EEPROM Ready */
971
+ #define TWI_vect_num 26
972
+ #define TWI_vect _VECTOR(26) /* 2-wire Serial Interface */
973
+ #define SPM_READY_vect_num 27
974
+ #define SPM_READY_vect _VECTOR(27) /* Store Program Memory Read */
975
+ #define USART1_RX_vect_num 28
976
+ #define USART1_RX_vect _VECTOR(28) /* USART1 RX complete */
977
+ #define USART1_UDRE_vect_num 29
978
+ #define USART1_UDRE_vect _VECTOR(29) /* USART1 Data Register Empty */
979
+ #define USART1_TX_vect_num 30
980
+ #define USART1_TX_vect _VECTOR(30) /* USART1 TX complete */
981
+
982
+ #define _VECTOR_SIZE 4 /* Size of individual vector. */
983
+ #define _VECTORS_SIZE (31 * _VECTOR_SIZE)
984
+
985
+
986
+ /* Constants */
987
+ #define SPM_PAGESIZE (256)
988
+ #define RAMSTART (0x100)
989
+ #define RAMSIZE (4096)
990
+ #define RAMEND (RAMSTART + RAMSIZE - 1)
991
+ #define XRAMSTART (0x0)
992
+ #define XRAMSIZE (0)
993
+ #define XRAMEND (RAMEND)
994
+ #define E2END (0x7FF)
995
+ #define E2PAGESIZE (8)
996
+ #define FLASHEND (0xFFFF)
997
+
998
+
999
+ /* Fuses */
1000
+ #define FUSE_MEMORY_SIZE 3
1001
+
1002
+ /* Low Fuse Byte */
1003
+ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */
1004
+ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */
1005
+ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */
1006
+ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */
1007
+ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */
1008
+ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */
1009
+ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */
1010
+ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */
1011
+ #define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0)
1012
+
1013
+ /* High Fuse Byte */
1014
+ #define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */
1015
+ #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */
1016
+ #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */
1017
+ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */
1018
+ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */
1019
+ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */
1020
+ #define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */
1021
+ #define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */
1022
+ #define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
1023
+
1024
+ /* Extended Fuse Byte */
1025
+ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */
1026
+ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */
1027
+ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */
1028
+ #define EFUSE_DEFAULT (0xFF)
1029
+
1030
+
1031
+ /* Lock Bits */
1032
+ #define __LOCK_BITS_EXIST
1033
+ #define __BOOT_LOCK_BITS_0_EXIST
1034
+ #define __BOOT_LOCK_BITS_1_EXIST
1035
+
1036
+
1037
+ /* Signature */
1038
+ #define SIGNATURE_0 0x1E
1039
+ #define SIGNATURE_1 0x96
1040
+ #define SIGNATURE_2 0x0A
1041
+
1042
+
1043
+ /* Device Pin Definitions */
1044
+ #define MOSI_DDR DDRB
1045
+ #define MOSI_PORT PORTB
1046
+ #define MOSI_PIN PINB
1047
+ #define MOSI_BIT 5
1048
+
1049
+ #define PCINT13_DDR DDRB
1050
+ #define PCINT13_PORT PORTB
1051
+ #define PCINT13_PIN PINB
1052
+ #define PCINT13_BIT 5
1053
+
1054
+ #define MISO_DDR DDRB
1055
+ #define MISO_PORT PORTB
1056
+ #define MISO_PIN PINB
1057
+ #define MISO_BIT 6
1058
+
1059
+ #define PCINT14_DDR DDRB
1060
+ #define PCINT14_PORT PORTB
1061
+ #define PCINT14_PIN PINB
1062
+ #define PCINT14_BIT 6
1063
+
1064
+ #define SCK_DDR DDRB
1065
+ #define SCK_PORT PORTB
1066
+ #define SCK_PIN PINB
1067
+ #define SCK_BIT 7
1068
+
1069
+ #define PCINT15_DDR DDRB
1070
+ #define PCINT15_PORT PORTB
1071
+ #define PCINT15_PIN PINB
1072
+ #define PCINT15_BIT 7
1073
+
1074
+ #define RXD_DDR DDRD
1075
+ #define RXD_PORT PORTD
1076
+ #define RXD_PIN PIND
1077
+ #define RXD_BIT 0
1078
+
1079
+ #define PCINT24_DDR DDRD
1080
+ #define PCINT24_PORT PORTD
1081
+ #define PCINT24_PIN PIND
1082
+ #define PCINT24_BIT 0
1083
+
1084
+ #define TXD_DDR DDRD
1085
+ #define TXD_PORT PORTD
1086
+ #define TXD_PIN PIND
1087
+ #define TXD_BIT 1
1088
+
1089
+ #define PCINT25_DDR DDRD
1090
+ #define PCINT25_PORT PORTD
1091
+ #define PCINT25_PIN PIND
1092
+ #define PCINT25_BIT 1
1093
+
1094
+ #define INT0_DDR DDRD
1095
+ #define INT0_PORT PORTD
1096
+ #define INT0_PIN PIND
1097
+ #define INT0_BIT 2
1098
+
1099
+ #define RDX1_DDR DDRD
1100
+ #define RDX1_PORT PORTD
1101
+ #define RDX1_PIN PIND
1102
+ #define RDX1_BIT 2
1103
+
1104
+ #define PCINT26_DDR DDRD
1105
+ #define PCINT26_PORT PORTD
1106
+ #define PCINT26_PIN PIND
1107
+ #define PCINT26_BIT 2
1108
+
1109
+ #define INT1_DDR DDRD
1110
+ #define INT1_PORT PORTD
1111
+ #define INT1_PIN PIND
1112
+ #define INT1_BIT 3
1113
+
1114
+ #define TXD1_DDR DDRD
1115
+ #define TXD1_PORT PORTD
1116
+ #define TXD1_PIN PIND
1117
+ #define TXD1_BIT 3
1118
+
1119
+ #define PCINT27_DDR DDRD
1120
+ #define PCINT27_PORT PORTD
1121
+ #define PCINT27_PIN PIND
1122
+ #define PCINT27_BIT 3
1123
+
1124
+ #define OC1B_DDR DDRD
1125
+ #define OC1B_PORT PORTD
1126
+ #define OC1B_PIN PIND
1127
+ #define OC1B_BIT 4
1128
+
1129
+ #define XCK1_DDR DDRD
1130
+ #define XCK1_PORT PORTD
1131
+ #define XCK1_PIN PIND
1132
+ #define XCK1_BIT 4
1133
+
1134
+ #define PCINT28_DDR DDRD
1135
+ #define PCINT28_PORT PORTD
1136
+ #define PCINT28_PIN PIND
1137
+ #define PCINT28_BIT 4
1138
+
1139
+ #define OC1A_DDR DDRD
1140
+ #define OC1A_PORT PORTD
1141
+ #define OC1A_PIN PIND
1142
+ #define OC1A_BIT 5
1143
+
1144
+ #define PCINT29_DDR DDRD
1145
+ #define PCINT29_PORT PORTD
1146
+ #define PCINT29_PIN PIND
1147
+ #define PCINT29_BIT 5
1148
+
1149
+ #define ICP_DDR DDRD
1150
+ #define ICP_PORT PORTD
1151
+ #define ICP_PIN PIND
1152
+ #define ICP_BIT 6
1153
+
1154
+ #define OC2B_DDR DDRD
1155
+ #define OC2B_PORT PORTD
1156
+ #define OC2B_PIN PIND
1157
+ #define OC2B_BIT 6
1158
+
1159
+ #define PCINT30_DDR DDRD
1160
+ #define PCINT30_PORT PORTD
1161
+ #define PCINT30_PIN PIND
1162
+ #define PCINT30_BIT 6
1163
+
1164
+ #define OC2A_DDR DDRD
1165
+ #define OC2A_PORT PORTD
1166
+ #define OC2A_PIN PIND
1167
+ #define OC2A_BIT 7
1168
+
1169
+ #define PCINT31_DDR DDRD
1170
+ #define PCINT31_PORT PORTD
1171
+ #define PCINT31_PIN PIND
1172
+ #define PCINT31_BIT 7
1173
+
1174
+ #define SCL_DDR DDRC
1175
+ #define SCL_PORT PORTC
1176
+ #define SCL_PIN PINC
1177
+ #define SCL_BIT 0
1178
+
1179
+ #define PCINT16_DDR DDRC
1180
+ #define PCINT16_PORT PORTC
1181
+ #define PCINT16_PIN PINC
1182
+ #define PCINT16_BIT 0
1183
+
1184
+ #define SDA_DDR DDRC
1185
+ #define SDA_PORT PORTC
1186
+ #define SDA_PIN PINC
1187
+ #define SDA_BIT 1
1188
+
1189
+ #define PCINT17_DDR DDRC
1190
+ #define PCINT17_PORT PORTC
1191
+ #define PCINT17_PIN PINC
1192
+ #define PCINT17_BIT 1
1193
+
1194
+ #define PCINT18_DDR DDRC
1195
+ #define PCINT18_PORT PORTC
1196
+ #define PCINT18_PIN PINC
1197
+ #define PCINT18_BIT 2
1198
+
1199
+ #define PCINT19_DDR DDRC
1200
+ #define PCINT19_PORT PORTC
1201
+ #define PCINT19_PIN PINC
1202
+ #define PCINT19_BIT 3
1203
+
1204
+ #define PCINT20_DDR DDRC
1205
+ #define PCINT20_PORT PORTC
1206
+ #define PCINT20_PIN PINC
1207
+ #define PCINT20_BIT 4
1208
+
1209
+ #define PCINT21_DDR DDRC
1210
+ #define PCINT21_PORT PORTC
1211
+ #define PCINT21_PIN PINC
1212
+ #define PCINT21_BIT 5
1213
+
1214
+ #define PCINT22_DDR DDRC
1215
+ #define PCINT22_PORT PORTC
1216
+ #define PCINT22_PIN PINC
1217
+ #define PCINT22_BIT 6
1218
+
1219
+ #define PCINT23_DDR DDRC
1220
+ #define PCINT23_PORT PORTC
1221
+ #define PCINT23_PIN PINC
1222
+ #define PCINT23_BIT 7
1223
+
1224
+ #define ADC7_DDR DDRA
1225
+ #define ADC7_PORT PORTA
1226
+ #define ADC7_PIN PINA
1227
+ #define ADC7_BIT 7
1228
+
1229
+ #define PCINT7_DDR DDRA
1230
+ #define PCINT7_PORT PORTA
1231
+ #define PCINT7_PIN PINA
1232
+ #define PCINT7_BIT 7
1233
+
1234
+ #define ADC6_DDR DDRA
1235
+ #define ADC6_PORT PORTA
1236
+ #define ADC6_PIN PINA
1237
+ #define ADC6_BIT 6
1238
+
1239
+ #define PCINT6_DDR DDRA
1240
+ #define PCINT6_PORT PORTA
1241
+ #define PCINT6_PIN PINA
1242
+ #define PCINT6_BIT 6
1243
+
1244
+ #define ADC5_DDR DDRA
1245
+ #define ADC5_PORT PORTA
1246
+ #define ADC5_PIN PINA
1247
+ #define ADC5_BIT 5
1248
+
1249
+ #define PCINT5_DDR DDRA
1250
+ #define PCINT5_PORT PORTA
1251
+ #define PCINT5_PIN PINA
1252
+ #define PCINT5_BIT 5
1253
+
1254
+ #define ADC4_DDR DDRA
1255
+ #define ADC4_PORT PORTA
1256
+ #define ADC4_PIN PINA
1257
+ #define ADC4_BIT 4
1258
+
1259
+ #define PCINT4_DDR DDRA
1260
+ #define PCINT4_PORT PORTA
1261
+ #define PCINT4_PIN PINA
1262
+ #define PCINT4_BIT 4
1263
+
1264
+ #define ADC3_DDR DDRA
1265
+ #define ADC3_PORT PORTA
1266
+ #define ADC3_PIN PINA
1267
+ #define ADC3_BIT 3
1268
+
1269
+ #define PCINT3_DDR DDRA
1270
+ #define PCINT3_PORT PORTA
1271
+ #define PCINT3_PIN PINA
1272
+ #define PCINT3_BIT 3
1273
+
1274
+ #define ADC2_DDR DDRA
1275
+ #define ADC2_PORT PORTA
1276
+ #define ADC2_PIN PINA
1277
+ #define ADC2_BIT 2
1278
+
1279
+ #define PCINT2_DDR DDRA
1280
+ #define PCINT2_PORT PORTA
1281
+ #define PCINT2_PIN PINA
1282
+ #define PCINT2_BIT 2
1283
+
1284
+ #define ADC1_DDR DDRA
1285
+ #define ADC1_PORT PORTA
1286
+ #define ADC1_PIN PINA
1287
+ #define ADC1_BIT 1
1288
+
1289
+ #define PCINT1_DDR DDRA
1290
+ #define PCINT1_PORT PORTA
1291
+ #define PCINT1_PIN PINA
1292
+ #define PCINT1_BIT 1
1293
+
1294
+ #define ADC0_DDR DDRA
1295
+ #define ADC0_PORT PORTA
1296
+ #define ADC0_PIN PINA
1297
+ #define ADC0_BIT 0
1298
+
1299
+ #define PCINT0_DDR DDRA
1300
+ #define PCINT0_PORT PORTA
1301
+ #define PCINT0_PIN PINA
1302
+ #define PCINT0_BIT 0
1303
+
1304
+ #define XCK_DDR DDRB
1305
+ #define XCK_PORT PORTB
1306
+ #define XCK_PIN PINB
1307
+ #define XCK_BIT 0
1308
+
1309
+ #define T0_DDR DDRB
1310
+ #define T0_PORT PORTB
1311
+ #define T0_PIN PINB
1312
+ #define T0_BIT 0
1313
+
1314
+ #define PCINT8_DDR DDRB
1315
+ #define PCINT8_PORT PORTB
1316
+ #define PCINT8_PIN PINB
1317
+ #define PCINT8_BIT 0
1318
+
1319
+ #define T1_DDR DDRB
1320
+ #define T1_PORT PORTB
1321
+ #define T1_PIN PINB
1322
+ #define T1_BIT 1
1323
+
1324
+ #define CLKO_DDR DDRB
1325
+ #define CLKO_PORT PORTB
1326
+ #define CLKO_PIN PINB
1327
+ #define CLKO_BIT 1
1328
+
1329
+ #define PCINT9_DDR DDRB
1330
+ #define PCINT9_PORT PORTB
1331
+ #define PCINT9_PIN PINB
1332
+ #define PCINT9_BIT 1
1333
+
1334
+ #define AIN0_DDR DDRB
1335
+ #define AIN0_PORT PORTB
1336
+ #define AIN0_PIN PINB
1337
+ #define AIN0_BIT 2
1338
+
1339
+ #define INT2_DDR DDRB
1340
+ #define INT2_PORT PORTB
1341
+ #define INT2_PIN PINB
1342
+ #define INT2_BIT 2
1343
+
1344
+ #define PCINT10_DDR DDRB
1345
+ #define PCINT10_PORT PORTB
1346
+ #define PCINT10_PIN PINB
1347
+ #define PCINT10_BIT 2
1348
+
1349
+ #define AIN1_DDR DDRB
1350
+ #define AIN1_PORT PORTB
1351
+ #define AIN1_PIN PINB
1352
+ #define AIN1_BIT 3
1353
+
1354
+ #define OC0A_DDR DDRB
1355
+ #define OC0A_PORT PORTB
1356
+ #define OC0A_PIN PINB
1357
+ #define OC0A_BIT 3
1358
+
1359
+ #define PCINT11_DDR DDRB
1360
+ #define PCINT11_PORT PORTB
1361
+ #define PCINT11_PIN PINB
1362
+ #define PCINT11_BIT 3
1363
+
1364
+ #define SS_DDR DDRB
1365
+ #define SS_PORT PORTB
1366
+ #define SS_PIN PINB
1367
+ #define SS_BIT 4
1368
+
1369
+ #define OC0B_DDR DDRB
1370
+ #define OC0B_PORT PORTB
1371
+ #define OC0B_PIN PINB
1372
+ #define OC0B_BIT 4
1373
+
1374
+ #define PCINT12_DDR DDRB
1375
+ #define PCINT12_PORT PORTB
1376
+ #define PCINT12_PIN PINB
1377
+ #define PCINT12_BIT 4
1378
+
1379
+ #define SLEEP_MODE_IDLE (0x00<<1)
1380
+ #define SLEEP_MODE_ADC (0x01<<1)
1381
+ #define SLEEP_MODE_PWR_DOWN (0x02<<1)
1382
+ #define SLEEP_MODE_PWR_SAVE (0x03<<1)
1383
+ #define SLEEP_MODE_STANDBY (0x06<<1)
1384
+ #define SLEEP_MODE_EXT_STANDBY (0x07<<1)
1385
+
1386
+ #endif /* _AVR_ATmega644PA_H_ */
1387
+