arduino_ci 0.1.3 → 0.1.4

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Files changed (295) hide show
  1. checksums.yaml +4 -4
  2. data/README.md +77 -1
  3. data/cpp/arduino/Arduino.cpp +17 -7
  4. data/cpp/arduino/Arduino.h +151 -5
  5. data/cpp/arduino/ArduinoDefines.h +90 -0
  6. data/cpp/arduino/AvrMath.h +18 -28
  7. data/cpp/arduino/Godmode.cpp +62 -0
  8. data/cpp/arduino/Godmode.h +74 -0
  9. data/cpp/arduino/HardwareSerial.h +81 -0
  10. data/cpp/arduino/Print.h +67 -0
  11. data/cpp/arduino/Stream.h +210 -0
  12. data/cpp/arduino/WCharacter.h +96 -0
  13. data/cpp/arduino/WString.h +164 -0
  14. data/cpp/arduino/binary.h +518 -0
  15. data/cpp/arduino/include/README.md +3 -0
  16. data/cpp/arduino/include/common.h +333 -0
  17. data/cpp/arduino/include/fuse.h +274 -0
  18. data/cpp/arduino/include/io.h +643 -0
  19. data/cpp/arduino/include/io1200.h +274 -0
  20. data/cpp/arduino/include/io2313.h +385 -0
  21. data/cpp/arduino/include/io2323.h +210 -0
  22. data/cpp/arduino/include/io2333.h +461 -0
  23. data/cpp/arduino/include/io2343.h +214 -0
  24. data/cpp/arduino/include/io43u32x.h +440 -0
  25. data/cpp/arduino/include/io43u35x.h +432 -0
  26. data/cpp/arduino/include/io4414.h +500 -0
  27. data/cpp/arduino/include/io4433.h +489 -0
  28. data/cpp/arduino/include/io4434.h +588 -0
  29. data/cpp/arduino/include/io76c711.h +499 -0
  30. data/cpp/arduino/include/io8515.h +501 -0
  31. data/cpp/arduino/include/io8534.h +217 -0
  32. data/cpp/arduino/include/io8535.h +589 -0
  33. data/cpp/arduino/include/io86r401.h +309 -0
  34. data/cpp/arduino/include/io90pwm1.h +1157 -0
  35. data/cpp/arduino/include/io90pwm161.h +918 -0
  36. data/cpp/arduino/include/io90pwm216.h +1225 -0
  37. data/cpp/arduino/include/io90pwm2b.h +1466 -0
  38. data/cpp/arduino/include/io90pwm316.h +1272 -0
  39. data/cpp/arduino/include/io90pwm3b.h +1466 -0
  40. data/cpp/arduino/include/io90pwm81.h +1036 -0
  41. data/cpp/arduino/include/io90pwmx.h +1415 -0
  42. data/cpp/arduino/include/io90scr100.h +1719 -0
  43. data/cpp/arduino/include/ioa5272.h +803 -0
  44. data/cpp/arduino/include/ioa5505.h +803 -0
  45. data/cpp/arduino/include/ioa5702m322.h +2591 -0
  46. data/cpp/arduino/include/ioa5782.h +1843 -0
  47. data/cpp/arduino/include/ioa5790.h +907 -0
  48. data/cpp/arduino/include/ioa5790n.h +922 -0
  49. data/cpp/arduino/include/ioa5791.h +923 -0
  50. data/cpp/arduino/include/ioa5795.h +756 -0
  51. data/cpp/arduino/include/ioa5831.h +1949 -0
  52. data/cpp/arduino/include/ioa6285.h +740 -0
  53. data/cpp/arduino/include/ioa6286.h +740 -0
  54. data/cpp/arduino/include/ioa6289.h +847 -0
  55. data/cpp/arduino/include/ioa6612c.h +795 -0
  56. data/cpp/arduino/include/ioa6613c.h +795 -0
  57. data/cpp/arduino/include/ioa6614q.h +798 -0
  58. data/cpp/arduino/include/ioa6616c.h +865 -0
  59. data/cpp/arduino/include/ioa6617c.h +865 -0
  60. data/cpp/arduino/include/ioa664251.h +857 -0
  61. data/cpp/arduino/include/ioa8210.h +1843 -0
  62. data/cpp/arduino/include/ioa8510.h +1949 -0
  63. data/cpp/arduino/include/ioat94k.h +565 -0
  64. data/cpp/arduino/include/iocan128.h +100 -0
  65. data/cpp/arduino/include/iocan32.h +100 -0
  66. data/cpp/arduino/include/iocan64.h +100 -0
  67. data/cpp/arduino/include/iocanxx.h +2020 -0
  68. data/cpp/arduino/include/iom103.h +735 -0
  69. data/cpp/arduino/include/iom128.h +1299 -0
  70. data/cpp/arduino/include/iom1280.h +101 -0
  71. data/cpp/arduino/include/iom1281.h +101 -0
  72. data/cpp/arduino/include/iom1284.h +1099 -0
  73. data/cpp/arduino/include/iom1284p.h +1219 -0
  74. data/cpp/arduino/include/iom1284rfr2.h +2690 -0
  75. data/cpp/arduino/include/iom128a.h +1070 -0
  76. data/cpp/arduino/include/iom128rfa1.h +5385 -0
  77. data/cpp/arduino/include/iom128rfr2.h +2706 -0
  78. data/cpp/arduino/include/iom16.h +676 -0
  79. data/cpp/arduino/include/iom161.h +726 -0
  80. data/cpp/arduino/include/iom162.h +1022 -0
  81. data/cpp/arduino/include/iom163.h +686 -0
  82. data/cpp/arduino/include/iom164.h +101 -0
  83. data/cpp/arduino/include/iom164a.h +34 -0
  84. data/cpp/arduino/include/iom164p.h +34 -0
  85. data/cpp/arduino/include/iom164pa.h +1016 -0
  86. data/cpp/arduino/include/iom165.h +887 -0
  87. data/cpp/arduino/include/iom165a.h +832 -0
  88. data/cpp/arduino/include/iom165p.h +889 -0
  89. data/cpp/arduino/include/iom165pa.h +948 -0
  90. data/cpp/arduino/include/iom168.h +97 -0
  91. data/cpp/arduino/include/iom168a.h +35 -0
  92. data/cpp/arduino/include/iom168p.h +942 -0
  93. data/cpp/arduino/include/iom168pa.h +843 -0
  94. data/cpp/arduino/include/iom168pb.h +899 -0
  95. data/cpp/arduino/include/iom169.h +1174 -0
  96. data/cpp/arduino/include/iom169a.h +44 -0
  97. data/cpp/arduino/include/iom169p.h +1097 -0
  98. data/cpp/arduino/include/iom169pa.h +1485 -0
  99. data/cpp/arduino/include/iom16a.h +923 -0
  100. data/cpp/arduino/include/iom16hva.h +80 -0
  101. data/cpp/arduino/include/iom16hva2.h +883 -0
  102. data/cpp/arduino/include/iom16hvb.h +1052 -0
  103. data/cpp/arduino/include/iom16hvbrevb.h +1052 -0
  104. data/cpp/arduino/include/iom16m1.h +1571 -0
  105. data/cpp/arduino/include/iom16u2.h +1000 -0
  106. data/cpp/arduino/include/iom16u4.h +1423 -0
  107. data/cpp/arduino/include/iom2560.h +101 -0
  108. data/cpp/arduino/include/iom2561.h +101 -0
  109. data/cpp/arduino/include/iom2564rfr2.h +2691 -0
  110. data/cpp/arduino/include/iom256rfr2.h +2707 -0
  111. data/cpp/arduino/include/iom3000.h +237 -0
  112. data/cpp/arduino/include/iom32.h +755 -0
  113. data/cpp/arduino/include/iom323.h +744 -0
  114. data/cpp/arduino/include/iom324a.h +1014 -0
  115. data/cpp/arduino/include/iom324p.h +1016 -0
  116. data/cpp/arduino/include/iom324pa.h +1372 -0
  117. data/cpp/arduino/include/iom325.h +886 -0
  118. data/cpp/arduino/include/iom3250.h +982 -0
  119. data/cpp/arduino/include/iom3250a.h +34 -0
  120. data/cpp/arduino/include/iom3250p.h +34 -0
  121. data/cpp/arduino/include/iom3250pa.h +1042 -0
  122. data/cpp/arduino/include/iom325a.h +34 -0
  123. data/cpp/arduino/include/iom325p.h +34 -0
  124. data/cpp/arduino/include/iom325pa.h +937 -0
  125. data/cpp/arduino/include/iom328.h +34 -0
  126. data/cpp/arduino/include/iom328p.h +948 -0
  127. data/cpp/arduino/include/iom329.h +1069 -0
  128. data/cpp/arduino/include/iom3290.h +1227 -0
  129. data/cpp/arduino/include/iom3290a.h +34 -0
  130. data/cpp/arduino/include/iom3290pa.h +1123 -0
  131. data/cpp/arduino/include/iom329a.h +34 -0
  132. data/cpp/arduino/include/iom329p.h +1164 -0
  133. data/cpp/arduino/include/iom329pa.h +34 -0
  134. data/cpp/arduino/include/iom32a.h +686 -0
  135. data/cpp/arduino/include/iom32c1.h +1320 -0
  136. data/cpp/arduino/include/iom32hvb.h +1052 -0
  137. data/cpp/arduino/include/iom32hvbrevb.h +953 -0
  138. data/cpp/arduino/include/iom32m1.h +1625 -0
  139. data/cpp/arduino/include/iom32u2.h +1000 -0
  140. data/cpp/arduino/include/iom32u4.h +1512 -0
  141. data/cpp/arduino/include/iom32u6.h +1431 -0
  142. data/cpp/arduino/include/iom406.h +783 -0
  143. data/cpp/arduino/include/iom48.h +93 -0
  144. data/cpp/arduino/include/iom48a.h +35 -0
  145. data/cpp/arduino/include/iom48p.h +936 -0
  146. data/cpp/arduino/include/iom48pa.h +839 -0
  147. data/cpp/arduino/include/iom48pb.h +890 -0
  148. data/cpp/arduino/include/iom64.h +1311 -0
  149. data/cpp/arduino/include/iom640.h +101 -0
  150. data/cpp/arduino/include/iom644.h +101 -0
  151. data/cpp/arduino/include/iom644a.h +34 -0
  152. data/cpp/arduino/include/iom644p.h +101 -0
  153. data/cpp/arduino/include/iom644pa.h +1387 -0
  154. data/cpp/arduino/include/iom644rfr2.h +2685 -0
  155. data/cpp/arduino/include/iom645.h +881 -0
  156. data/cpp/arduino/include/iom6450.h +978 -0
  157. data/cpp/arduino/include/iom6450a.h +34 -0
  158. data/cpp/arduino/include/iom6450p.h +34 -0
  159. data/cpp/arduino/include/iom645a.h +34 -0
  160. data/cpp/arduino/include/iom645p.h +34 -0
  161. data/cpp/arduino/include/iom649.h +1061 -0
  162. data/cpp/arduino/include/iom6490.h +1182 -0
  163. data/cpp/arduino/include/iom6490a.h +34 -0
  164. data/cpp/arduino/include/iom6490p.h +34 -0
  165. data/cpp/arduino/include/iom649a.h +34 -0
  166. data/cpp/arduino/include/iom649p.h +1490 -0
  167. data/cpp/arduino/include/iom64a.h +1084 -0
  168. data/cpp/arduino/include/iom64c1.h +1321 -0
  169. data/cpp/arduino/include/iom64hve.h +1034 -0
  170. data/cpp/arduino/include/iom64hve2.h +767 -0
  171. data/cpp/arduino/include/iom64m1.h +1572 -0
  172. data/cpp/arduino/include/iom64rfr2.h +2701 -0
  173. data/cpp/arduino/include/iom8.h +665 -0
  174. data/cpp/arduino/include/iom8515.h +687 -0
  175. data/cpp/arduino/include/iom8535.h +772 -0
  176. data/cpp/arduino/include/iom88.h +97 -0
  177. data/cpp/arduino/include/iom88a.h +35 -0
  178. data/cpp/arduino/include/iom88p.h +941 -0
  179. data/cpp/arduino/include/iom88pa.h +1185 -0
  180. data/cpp/arduino/include/iom88pb.h +899 -0
  181. data/cpp/arduino/include/iom8a.h +621 -0
  182. data/cpp/arduino/include/iom8hva.h +76 -0
  183. data/cpp/arduino/include/iom8u2.h +997 -0
  184. data/cpp/arduino/include/iomx8.h +808 -0
  185. data/cpp/arduino/include/iomxx0_1.h +1692 -0
  186. data/cpp/arduino/include/iomxx4.h +954 -0
  187. data/cpp/arduino/include/iomxxhva.h +550 -0
  188. data/cpp/arduino/include/iotn10.h +512 -0
  189. data/cpp/arduino/include/iotn11.h +255 -0
  190. data/cpp/arduino/include/iotn12.h +288 -0
  191. data/cpp/arduino/include/iotn13.h +395 -0
  192. data/cpp/arduino/include/iotn13a.h +394 -0
  193. data/cpp/arduino/include/iotn15.h +363 -0
  194. data/cpp/arduino/include/iotn1634.h +914 -0
  195. data/cpp/arduino/include/iotn167.h +883 -0
  196. data/cpp/arduino/include/iotn20.h +776 -0
  197. data/cpp/arduino/include/iotn22.h +221 -0
  198. data/cpp/arduino/include/iotn2313.h +702 -0
  199. data/cpp/arduino/include/iotn2313a.h +812 -0
  200. data/cpp/arduino/include/iotn24.h +94 -0
  201. data/cpp/arduino/include/iotn24a.h +846 -0
  202. data/cpp/arduino/include/iotn25.h +93 -0
  203. data/cpp/arduino/include/iotn26.h +422 -0
  204. data/cpp/arduino/include/iotn261.h +93 -0
  205. data/cpp/arduino/include/iotn261a.h +987 -0
  206. data/cpp/arduino/include/iotn28.h +297 -0
  207. data/cpp/arduino/include/iotn4.h +477 -0
  208. data/cpp/arduino/include/iotn40.h +767 -0
  209. data/cpp/arduino/include/iotn4313.h +813 -0
  210. data/cpp/arduino/include/iotn43u.h +604 -0
  211. data/cpp/arduino/include/iotn44.h +94 -0
  212. data/cpp/arduino/include/iotn441.h +903 -0
  213. data/cpp/arduino/include/iotn44a.h +844 -0
  214. data/cpp/arduino/include/iotn45.h +93 -0
  215. data/cpp/arduino/include/iotn461.h +94 -0
  216. data/cpp/arduino/include/iotn461a.h +987 -0
  217. data/cpp/arduino/include/iotn48.h +806 -0
  218. data/cpp/arduino/include/iotn5.h +512 -0
  219. data/cpp/arduino/include/iotn828.h +911 -0
  220. data/cpp/arduino/include/iotn84.h +94 -0
  221. data/cpp/arduino/include/iotn841.h +903 -0
  222. data/cpp/arduino/include/iotn84a.h +844 -0
  223. data/cpp/arduino/include/iotn85.h +93 -0
  224. data/cpp/arduino/include/iotn861.h +94 -0
  225. data/cpp/arduino/include/iotn861a.h +988 -0
  226. data/cpp/arduino/include/iotn87.h +859 -0
  227. data/cpp/arduino/include/iotn88.h +806 -0
  228. data/cpp/arduino/include/iotn9.h +477 -0
  229. data/cpp/arduino/include/iotnx4.h +482 -0
  230. data/cpp/arduino/include/iotnx5.h +442 -0
  231. data/cpp/arduino/include/iotnx61.h +541 -0
  232. data/cpp/arduino/include/iousb1286.h +101 -0
  233. data/cpp/arduino/include/iousb1287.h +101 -0
  234. data/cpp/arduino/include/iousb162.h +101 -0
  235. data/cpp/arduino/include/iousb646.h +102 -0
  236. data/cpp/arduino/include/iousb647.h +102 -0
  237. data/cpp/arduino/include/iousb82.h +95 -0
  238. data/cpp/arduino/include/iousbxx2.h +807 -0
  239. data/cpp/arduino/include/iousbxx6_7.h +1336 -0
  240. data/cpp/arduino/include/iox128a1.h +7236 -0
  241. data/cpp/arduino/include/iox128a1u.h +8305 -0
  242. data/cpp/arduino/include/iox128a3.h +6987 -0
  243. data/cpp/arduino/include/iox128a3u.h +7697 -0
  244. data/cpp/arduino/include/iox128a4u.h +7309 -0
  245. data/cpp/arduino/include/iox128b1.h +6872 -0
  246. data/cpp/arduino/include/iox128b3.h +6288 -0
  247. data/cpp/arduino/include/iox128c3.h +6264 -0
  248. data/cpp/arduino/include/iox128d3.h +5749 -0
  249. data/cpp/arduino/include/iox128d4.h +5562 -0
  250. data/cpp/arduino/include/iox16a4.h +6748 -0
  251. data/cpp/arduino/include/iox16a4u.h +7309 -0
  252. data/cpp/arduino/include/iox16c4.h +6078 -0
  253. data/cpp/arduino/include/iox16d4.h +5717 -0
  254. data/cpp/arduino/include/iox16e5.h +7699 -0
  255. data/cpp/arduino/include/iox192a3.h +6987 -0
  256. data/cpp/arduino/include/iox192a3u.h +7697 -0
  257. data/cpp/arduino/include/iox192c3.h +6264 -0
  258. data/cpp/arduino/include/iox192d3.h +5749 -0
  259. data/cpp/arduino/include/iox256a3.h +6987 -0
  260. data/cpp/arduino/include/iox256a3b.h +6983 -0
  261. data/cpp/arduino/include/iox256a3bu.h +7706 -0
  262. data/cpp/arduino/include/iox256a3u.h +7697 -0
  263. data/cpp/arduino/include/iox256c3.h +6264 -0
  264. data/cpp/arduino/include/iox256d3.h +5709 -0
  265. data/cpp/arduino/include/iox32a4.h +6747 -0
  266. data/cpp/arduino/include/iox32a4u.h +7309 -0
  267. data/cpp/arduino/include/iox32c3.h +6264 -0
  268. data/cpp/arduino/include/iox32c4.h +6078 -0
  269. data/cpp/arduino/include/iox32d3.h +5105 -0
  270. data/cpp/arduino/include/iox32d4.h +5685 -0
  271. data/cpp/arduino/include/iox32e5.h +7699 -0
  272. data/cpp/arduino/include/iox384c3.h +6849 -0
  273. data/cpp/arduino/include/iox384d3.h +5833 -0
  274. data/cpp/arduino/include/iox64a1.h +7236 -0
  275. data/cpp/arduino/include/iox64a1u.h +8305 -0
  276. data/cpp/arduino/include/iox64a3.h +6987 -0
  277. data/cpp/arduino/include/iox64a3u.h +7697 -0
  278. data/cpp/arduino/include/iox64a4u.h +7309 -0
  279. data/cpp/arduino/include/iox64b1.h +6454 -0
  280. data/cpp/arduino/include/iox64b3.h +6288 -0
  281. data/cpp/arduino/include/iox64c3.h +6264 -0
  282. data/cpp/arduino/include/iox64d3.h +5764 -0
  283. data/cpp/arduino/include/iox64d4.h +5555 -0
  284. data/cpp/arduino/include/iox8e5.h +7699 -0
  285. data/cpp/arduino/include/lock.h +239 -0
  286. data/cpp/arduino/include/portpins.h +549 -0
  287. data/cpp/arduino/include/version.h +90 -0
  288. data/cpp/arduino/include/xmega.h +71 -0
  289. data/cpp/unittest/Assertion.h +9 -4
  290. data/cpp/unittest/Compare.h +93 -0
  291. data/lib/arduino_ci/arduino_installation.rb +1 -1
  292. data/lib/arduino_ci/cpp_library.rb +4 -1
  293. data/lib/arduino_ci/version.rb +1 -1
  294. data/misc/default.yaml +7 -0
  295. metadata +285 -2
@@ -0,0 +1,1949 @@
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+ /*****************************************************************************
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+ *
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+ * Copyright (C) 2016 Atmel Corporation
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+ * All rights reserved.
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+ *
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+ * Redistribution and use in source and binary forms, with or without
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+ * modification, are permitted provided that the following conditions are met:
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+ *
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+ * * Redistributions of source code must retain the above copyright
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+ * notice, this list of conditions and the following disclaimer.
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+ *
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+ * * Redistributions in binary form must reproduce the above copyright
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+ * notice, this list of conditions and the following disclaimer in
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+ * the documentation and/or other materials provided with the
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+ * distribution.
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+ *
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+ * * Neither the name of the copyright holders nor the names of
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+ * contributors may be used to endorse or promote products derived
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+ * from this software without specific prior written permission.
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+ *
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+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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+ * POSSIBILITY OF SUCH DAMAGE.
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+ ****************************************************************************/
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+
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+
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+ #ifndef _AVR_ATA5831_H_INCLUDED
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+ #define _AVR_ATA5831_H_INCLUDED
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+
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+
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+ #ifndef _AVR_IO_H_
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+ # error "Include <avr/io.h> instead of this file."
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+ #endif
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+
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+ #ifndef _AVR_IOXXX_H_
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+ # define _AVR_IOXXX_H_ "ioa5831.h"
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+ #else
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+ # error "Attempt to include more than one <avr/ioXXX.h> file."
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+ #endif
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+
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+ /* Registers and associated bit numbers */
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+
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+ #define PRR0 _SFR_IO8(0x01)
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+ #define PRSPI 0
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+ #define PRRXDC 1
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+ #define PRTXDC 2
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+ #define PRCRC 3
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+ #define PRVM 4
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+ #define PRCO 5
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+
59
+ #define __AVR_HAVE_PRR0 ((1<<PRSPI)|(1<<PRRXDC)|(1<<PRTXDC)|(1<<PRCRC)|(1<<PRVM)|(1<<PRCO))
60
+ #define __AVR_HAVE_PRR0_PRSPI
61
+ #define __AVR_HAVE_PRR0_PRRXDC
62
+ #define __AVR_HAVE_PRR0_PRTXDC
63
+ #define __AVR_HAVE_PRR0_PRCRC
64
+ #define __AVR_HAVE_PRR0_PRVM
65
+ #define __AVR_HAVE_PRR0_PRCO
66
+
67
+ #define PRR1 _SFR_IO8(0x02)
68
+ #define PRT1 0
69
+ #define PRT2 1
70
+ #define PRT3 2
71
+ #define PRT4 3
72
+ #define PRT5 4
73
+
74
+ #define __AVR_HAVE_PRR1 ((1<<PRT1)|(1<<PRT2)|(1<<PRT3)|(1<<PRT4)|(1<<PRT5))
75
+ #define __AVR_HAVE_PRR1_PRT1
76
+ #define __AVR_HAVE_PRR1_PRT2
77
+ #define __AVR_HAVE_PRR1_PRT3
78
+ #define __AVR_HAVE_PRR1_PRT4
79
+ #define __AVR_HAVE_PRR1_PRT5
80
+
81
+ #define PRR2 _SFR_IO8(0x03)
82
+ #define PRXB 0
83
+ #define PRXA 1
84
+ #define PRSF 2
85
+ #define PRDF 3
86
+ #define PRIDS 4
87
+ #define PRRS 5
88
+ #define PRTM 6
89
+ #define PRSSM 7
90
+
91
+ #define __AVR_HAVE_PRR2 ((1<<PRXB)|(1<<PRXA)|(1<<PRSF)|(1<<PRDF)|(1<<PRIDS)|(1<<PRRS)|(1<<PRTM)|(1<<PRSSM))
92
+ #define __AVR_HAVE_PRR2_PRXB
93
+ #define __AVR_HAVE_PRR2_PRXA
94
+ #define __AVR_HAVE_PRR2_PRSF
95
+ #define __AVR_HAVE_PRR2_PRDF
96
+ #define __AVR_HAVE_PRR2_PRIDS
97
+ #define __AVR_HAVE_PRR2_PRRS
98
+ #define __AVR_HAVE_PRR2_PRTM
99
+ #define __AVR_HAVE_PRR2_PRSSM
100
+
101
+ #define RDPR _SFR_IO8(0x04)
102
+ #define PRPTB 0
103
+ #define PRPTA 1
104
+ #define PRFLT 2
105
+ #define PRTMP 3
106
+ #define APRPTB 4
107
+ #define APRPTA 5
108
+ #define ARDPRF 6
109
+ #define RDPRF 7
110
+
111
+ #define PINB _SFR_IO8(0x05)
112
+ #define PINB7 7
113
+ #define PINB6 6
114
+ #define PINB5 5
115
+ #define PINB4 4
116
+ #define PINB3 3
117
+ #define PINB2 2
118
+ #define PINB1 1
119
+ #define PINB0 0
120
+
121
+ #define DDRB _SFR_IO8(0x06)
122
+ #define DDRB7 7
123
+ // Inserted "DDB7" from "DDRB7" due to compatibility
124
+ #define DDB7 7
125
+ #define DDRB6 6
126
+ // Inserted "DDB6" from "DDRB6" due to compatibility
127
+ #define DDB6 6
128
+ #define DDRB5 5
129
+ // Inserted "DDB5" from "DDRB5" due to compatibility
130
+ #define DDB5 5
131
+ #define DDRB4 4
132
+ // Inserted "DDB4" from "DDRB4" due to compatibility
133
+ #define DDB4 4
134
+ #define DDRB3 3
135
+ // Inserted "DDB3" from "DDRB3" due to compatibility
136
+ #define DDB3 3
137
+ #define DDRB2 2
138
+ // Inserted "DDB2" from "DDRB2" due to compatibility
139
+ #define DDB2 2
140
+ #define DDRB1 1
141
+ // Inserted "DDB1" from "DDRB1" due to compatibility
142
+ #define DDB1 1
143
+ #define DDRB0 0
144
+ // Inserted "DDB0" from "DDRB0" due to compatibility
145
+ #define DDB0 0
146
+
147
+ #define PORTB _SFR_IO8(0x07)
148
+ #define PORTB7 7
149
+ #define PORTB6 6
150
+ #define PORTB5 5
151
+ #define PORTB4 4
152
+ #define PORTB3 3
153
+ #define PORTB2 2
154
+ #define PORTB1 1
155
+ #define PORTB0 0
156
+
157
+ #define PINC _SFR_IO8(0x08)
158
+ #define PINC5 5
159
+ #define PINC4 4
160
+ #define PINC3 3
161
+ #define PINC2 2
162
+ #define PINC1 1
163
+ #define PINC0 0
164
+
165
+ #define DDRC _SFR_IO8(0x09)
166
+ #define DDRC5 5
167
+ // Inserted "DDC5" from "DDRC5" due to compatibility
168
+ #define DDC5 5
169
+ #define DDRC4 4
170
+ // Inserted "DDC4" from "DDRC4" due to compatibility
171
+ #define DDC4 4
172
+ #define DDRC3 3
173
+ // Inserted "DDC3" from "DDRC3" due to compatibility
174
+ #define DDC3 3
175
+ #define DDRC2 2
176
+ // Inserted "DDC2" from "DDRC2" due to compatibility
177
+ #define DDC2 2
178
+ #define DDRC1 1
179
+ // Inserted "DDC1" from "DDRC1" due to compatibility
180
+ #define DDC1 1
181
+ #define DDRC0 0
182
+ // Inserted "DDC0" from "DDRC0" due to compatibility
183
+ #define DDC0 0
184
+
185
+ #define PORTC _SFR_IO8(0x0A)
186
+ #define PORTC5 5
187
+ #define PORTC4 4
188
+ #define PORTC3 3
189
+ #define PORTC2 2
190
+ #define PORTC1 1
191
+ #define PORTC0 0
192
+
193
+ #define FSCR _SFR_IO8(0x0B)
194
+ #define TXMOD 0
195
+ #define SFM 1
196
+ #define TXMS0 2
197
+ #define TXMS1 3
198
+ #define PAOER 4
199
+ #define PAON 7
200
+
201
+ /* Reserved [0x0C] */
202
+
203
+ #define RDSIFR _SFR_IO8(0x0D)
204
+ #define NBITA 0
205
+ #define NBITB 1
206
+ #define EOTA 2
207
+ #define EOTB 3
208
+ #define SOTA 4
209
+ #define SOTB 5
210
+ #define WCOA 6
211
+ #define WCOB 7
212
+
213
+ #define MCUCR _SFR_IO8(0x0E)
214
+ #define IVCE 0
215
+ #define IVSEL 1
216
+ #define SPIIO 2
217
+ #define ENPS 3
218
+ #define PUD 4
219
+ #define PB4HS 5
220
+ #define PB7LS 6
221
+ #define PB7HS 7
222
+
223
+ #define PCIFR _SFR_IO8(0x0F)
224
+ #define PCIF0 0
225
+ #define PCIF1 1
226
+
227
+ #define T0CR _SFR_IO8(0x10)
228
+ #define T0PS0 0
229
+ #define T0PS1 1
230
+ #define T0PS2 2
231
+ #define T0IE 3
232
+ #define T0PR 4
233
+
234
+ #define T1CR _SFR_IO8(0x11)
235
+ #define T1OTM 0
236
+ #define T1CTM 1
237
+ #define T1CRM 2
238
+ #define T1TOP 4
239
+ #define T1RES 5
240
+ #define T1TOS 6
241
+ #define T1ENA 7
242
+
243
+ #define T2CR _SFR_IO8(0x12)
244
+ #define T2OTM 0
245
+ #define T2CTM 1
246
+ #define T2CRM 2
247
+ #define T2TOP 4
248
+ #define T2RES 5
249
+ #define T2TOS 6
250
+ #define T2ENA 7
251
+
252
+ #define T3CR _SFR_IO8(0x13)
253
+ #define T3OTM 0
254
+ #define T3CTM 1
255
+ #define T3CRM 2
256
+ #define T3CPRM 3
257
+ #define T3TOP 4
258
+ #define T3RES 5
259
+ #define T3TOS 6
260
+ #define T3ENA 7
261
+
262
+ #define T4CR _SFR_IO8(0x14)
263
+ #define T4OTM 0
264
+ #define T4CTM 1
265
+ #define T4CRM 2
266
+ #define T4CPRM 3
267
+ #define T4TOP 4
268
+ #define T4RES 5
269
+ #define T4TOS 6
270
+ #define T4ENA 7
271
+
272
+ #define T1IFR _SFR_IO8(0x15)
273
+ #define T1OFF 0
274
+ #define T1COF 1
275
+
276
+ #define T2IFR _SFR_IO8(0x16)
277
+ #define T2OFF 0
278
+ #define T2COF 1
279
+
280
+ #define T3IFR _SFR_IO8(0x17)
281
+ #define T3OFF 0
282
+ #define T3COF 1
283
+ #define T3ICF 2
284
+
285
+ #define T4IFR _SFR_IO8(0x18)
286
+ #define T4OFF 0
287
+ #define T4COF 1
288
+ #define T4ICF 2
289
+
290
+ #define T5IFR _SFR_IO8(0x19)
291
+ #define T5OFF 0
292
+ #define T5COF 1
293
+
294
+ #define GPIOR0 _SFR_IO8(0x1A)
295
+
296
+ #define GPIOR3 _SFR_IO8(0x1B)
297
+
298
+ #define GPIOR4 _SFR_IO8(0x1C)
299
+
300
+ #define GPIOR5 _SFR_IO8(0x1D)
301
+
302
+ #define GPIOR6 _SFR_IO8(0x1E)
303
+
304
+ #define EECR _SFR_IO8(0x1F)
305
+ #define EERE 0
306
+ #define EEWE 1
307
+ #define EEMWE 2
308
+ #define EERIE 3
309
+ #define EEPM0 4
310
+ #define EEPM1 5
311
+ #define EEPAGE 6
312
+ #define NVMBSY 7
313
+
314
+ #define EEDR _SFR_IO8(0x20)
315
+
316
+ /* Combine EEARL and EEARH */
317
+ #define EEAR _SFR_IO16(0x21)
318
+
319
+ #define EEARL _SFR_IO8(0x21)
320
+ #define EEARH _SFR_IO8(0x22)
321
+
322
+ #define EEPR _SFR_IO8(0x23)
323
+ #define EEAP0 0
324
+ #define EEAP1 1
325
+ #define EEAP2 2
326
+ #define EEAP3 3
327
+
328
+ #define GPIOR1 _SFR_IO8(0x24)
329
+
330
+ #define GPIOR2 _SFR_IO8(0x25)
331
+
332
+ #define PCICR _SFR_IO8(0x26)
333
+ #define PCIE0 0
334
+ #define PCIE1 1
335
+
336
+ #define EIMSK _SFR_IO8(0x27)
337
+ #define INT0 0
338
+ #define INT1 1
339
+
340
+ #define EIFR _SFR_IO8(0x28)
341
+ #define INTF0 0
342
+ #define INTF1 1
343
+
344
+ #define CRCDIR _SFR_IO8(0x29)
345
+
346
+ #define VMCSR _SFR_IO8(0x2A)
347
+ #define VMLS0 0
348
+ #define VMLS1 1
349
+ #define VMLS2 2
350
+ #define VMLS3 3
351
+ #define VMIM 4
352
+ #define VMF 5
353
+
354
+ #define MCUSR _SFR_IO8(0x2B)
355
+ #define PORF 0
356
+ #define EXTRF 1
357
+ #define WDRF 3
358
+
359
+ #define SPCR _SFR_IO8(0x2C)
360
+ #define SPR0 0
361
+ #define SPR1 1
362
+ #define CPHA 2
363
+ #define CPOL 3
364
+ #define MSTR 4
365
+ #define DORD 5
366
+ #define SPE 6
367
+ #define SPIE 7
368
+
369
+ #define SPSR _SFR_IO8(0x2D)
370
+ #define SPI2X 0
371
+ #define RXIF 4
372
+ #define TXIF 5
373
+ #define SPIF 7
374
+
375
+ #define SPDR _SFR_IO8(0x2E)
376
+
377
+ #define T0IFR _SFR_IO8(0x2F)
378
+ #define T0F 0
379
+
380
+ /* Reserved [0x30] */
381
+
382
+ #define DWDR _SFR_IO8(0x31)
383
+
384
+ /* Reserved [0x32] */
385
+
386
+ #define RDCR _SFR_IO8(0x33)
387
+ #define RDPU 0
388
+ #define ADIVEN 1
389
+ #define RDEN 2
390
+
391
+ #define EOTSA _SFR_IO8(0x34)
392
+ #define CARFA 0
393
+ #define AMPFA 1
394
+ #define SYTFA 2
395
+ #define MANFA 3
396
+ #define TMOFA 4
397
+ #define TELRA 5
398
+ #define RRFA 6
399
+ #define EOTBF 7
400
+
401
+ #define EOTCA _SFR_IO8(0x35)
402
+ #define CARFEA 0
403
+ #define AMPFEA 1
404
+ #define SYTFEA 2
405
+ #define MANFEA 3
406
+ #define TMOFEA 4
407
+ #define TELREA 5
408
+ #define RRFEA 6
409
+ #define EOTBFE 7
410
+
411
+ #define EOTSB _SFR_IO8(0x36)
412
+ #define CARFB 0
413
+ #define AMPFB 1
414
+ #define SYTFB 2
415
+ #define MANFB 3
416
+ #define TMOFB 4
417
+ #define TELRB 5
418
+ #define RRFB 6
419
+ #define EOTAF 7
420
+
421
+ #define EOTCB _SFR_IO8(0x37)
422
+ #define CARFEB 0
423
+ #define AMPFEB 1
424
+ #define SYTFEB 2
425
+ #define MANFEB 3
426
+ #define TMOFEB 4
427
+ #define TELREB 5
428
+ #define RRFEB 6
429
+ #define EOTAFE 7
430
+
431
+ #define SMCR _SFR_IO8(0x38)
432
+ #define SE 0
433
+ #define SM0 1
434
+ #define SM1 2
435
+ #define SM2 3
436
+
437
+ #define CMCR _SFR_IO8(0x39)
438
+ #define CMM0 0
439
+ #define CMM1 1
440
+ #define CMM2 2
441
+ #define CCS 3
442
+ #define SRCD 4
443
+ #define CMONEN 6
444
+ #define CMCCE 7
445
+
446
+ #define CMIMR _SFR_IO8(0x3A)
447
+ #define ECIE 0
448
+
449
+ #define CLPR _SFR_IO8(0x3B)
450
+ #define CLKPS0 0
451
+ #define CLKPS1 1
452
+ #define CLKPS2 2
453
+ #define CLTPS0 3
454
+ #define CLTPS1 4
455
+ #define CLTPS2 5
456
+ #define CLPCE 7
457
+
458
+ #define SPMCSR _SFR_IO8(0x3C)
459
+ #define SELFPRGEN 0
460
+ #define PGERS 1
461
+ #define PGWRT 2
462
+ #define BLBSET 3
463
+ #define SPMIE 7
464
+
465
+ /* SP [0x3D..0x3E] */
466
+
467
+ /* SREG [0x3F] */
468
+
469
+ #define FSEN _SFR_MEM8(0x60)
470
+ #define SDPU 0
471
+ #define SDEN 1
472
+ #define GAEN 2
473
+ #define PEEN 3
474
+ #define ASEN 4
475
+ #define ANTT 5
476
+
477
+ #define FSFCR _SFR_MEM8(0x61)
478
+ #define BTSEL0 0
479
+ #define BTSEL1 1
480
+ #define ASDIV0 4
481
+ #define ASDIV1 5
482
+ #define ASDIV2 6
483
+ #define ASDIV3 7
484
+
485
+ /* Combine GACDIVL and GACDIVH */
486
+ #define GACDIV _SFR_MEM16(0x62)
487
+
488
+ #define GACDIVL _SFR_MEM8(0x62)
489
+ #define GACDIVH _SFR_MEM8(0x63)
490
+
491
+ #define FFREQ1L _SFR_MEM8(0x64)
492
+
493
+ #define FFREQ1M _SFR_MEM8(0x65)
494
+
495
+ #define FFREQ1H _SFR_MEM8(0x66)
496
+
497
+ #define FFREQ2L _SFR_MEM8(0x67)
498
+
499
+ #define FFREQ2M _SFR_MEM8(0x68)
500
+
501
+ #define FFREQ2H _SFR_MEM8(0x69)
502
+
503
+ /* Reserved [0x6A] */
504
+
505
+ #define EICRA _SFR_MEM8(0x6B)
506
+ #define ISC00 0
507
+ #define ISC01 1
508
+ #define ISC10 2
509
+ #define ISC11 3
510
+
511
+ #define PCMSK0 _SFR_MEM8(0x6C)
512
+ #define PCINT0 0
513
+ #define PCINT1 1
514
+ #define PCINT2 2
515
+ #define PCINT3 3
516
+ #define PCINT4 4
517
+ #define PCINT5 5
518
+ #define PCINT6 6
519
+ #define PCINT7 7
520
+
521
+ #define PCMSK1 _SFR_MEM8(0x6D)
522
+ #define PCINT8 0
523
+ #define PCINT9 1
524
+ #define PCINT10 2
525
+ #define PCINT11 3
526
+ #define PCINT12 4
527
+ #define PCINT13 5
528
+
529
+ #define WDTCR _SFR_MEM8(0x6E)
530
+ #define WDPS0 0
531
+ #define WDPS1 1
532
+ #define WDPS2 2
533
+ #define WDE 3
534
+ #define WDCE 4
535
+
536
+ #define T1CNT _SFR_MEM8(0x6F)
537
+
538
+ #define T1COR _SFR_MEM8(0x70)
539
+
540
+ #define T1MR _SFR_MEM8(0x71)
541
+ #define T1CS0 0
542
+ #define T1CS1 1
543
+ #define T1PS0 2
544
+ #define T1PS1 3
545
+ #define T1PS2 4
546
+ #define T1PS3 5
547
+ #define T1DC0 6
548
+ #define T1DC1 7
549
+
550
+ #define T1IMR _SFR_MEM8(0x72)
551
+ #define T1OIM 0
552
+ #define T1CIM 1
553
+
554
+ #define T2CNT _SFR_MEM8(0x73)
555
+
556
+ #define T2COR _SFR_MEM8(0x74)
557
+
558
+ #define T2MR _SFR_MEM8(0x75)
559
+ #define T2CS0 0
560
+ #define T2CS1 1
561
+ #define T2PS0 2
562
+ #define T2PS1 3
563
+ #define T2PS2 4
564
+ #define T2PS3 5
565
+ #define T2DC0 6
566
+ #define T2DC1 7
567
+
568
+ #define T2IMR _SFR_MEM8(0x76)
569
+ #define T2OIM 0
570
+ #define T2CIM 1
571
+
572
+ /* Combine T3CNTL and T3CNTH */
573
+ #define T3CNT _SFR_MEM16(0x77)
574
+
575
+ #define T3CNTL _SFR_MEM8(0x77)
576
+ #define T3CNTH _SFR_MEM8(0x78)
577
+
578
+ /* Combine T3CORL and T3CORH */
579
+ #define T3COR _SFR_MEM16(0x79)
580
+
581
+ #define T3CORL _SFR_MEM8(0x79)
582
+ #define T3CORH _SFR_MEM8(0x7A)
583
+
584
+ /* Combine T3ICRL and T3ICRH */
585
+ #define T3ICR _SFR_MEM16(0x7B)
586
+
587
+ #define T3ICRL _SFR_MEM8(0x7B)
588
+ #define T3ICRH _SFR_MEM8(0x7C)
589
+
590
+ #define T3MRA _SFR_MEM8(0x7D)
591
+ #define T3CS0 0
592
+ #define T3CS1 1
593
+ #define T3PS0 2
594
+ #define T3PS1 3
595
+ #define T3PS2 4
596
+
597
+ #define T3MRB _SFR_MEM8(0x7E)
598
+ #define T3SCE 1
599
+ #define T3CNC 2
600
+ #define T3CE0 3
601
+ #define T3CE1 4
602
+ #define T3ICS0 5
603
+ #define T3ICS1 6
604
+ #define T3ICS2 7
605
+
606
+ #define T3IMR _SFR_MEM8(0x7F)
607
+ #define T3OIM 0
608
+ #define T3CIM 1
609
+ #define T3CPIM 2
610
+
611
+ /* Combine T4CNTL and T4CNTH */
612
+ #define T4CNT _SFR_MEM16(0x80)
613
+
614
+ #define T4CNTL _SFR_MEM8(0x80)
615
+ #define T4CNTH _SFR_MEM8(0x81)
616
+
617
+ /* Combine T4CORL and T4CORH */
618
+ #define T4COR _SFR_MEM16(0x82)
619
+
620
+ #define T4CORL _SFR_MEM8(0x82)
621
+ #define T4CORH _SFR_MEM8(0x83)
622
+
623
+ /* Combine T4ICRL and T4ICRH */
624
+ #define T4ICR _SFR_MEM16(0x84)
625
+
626
+ #define T4ICRL _SFR_MEM8(0x84)
627
+ #define T4ICRH _SFR_MEM8(0x85)
628
+
629
+ #define T4MRA _SFR_MEM8(0x86)
630
+ #define T4CS0 0
631
+ #define T4CS1 1
632
+ #define T4PS0 2
633
+ #define T4PS1 3
634
+ #define T4PS2 4
635
+
636
+ #define T4MRB _SFR_MEM8(0x87)
637
+ #define T4SCE 1
638
+ #define T4CNC 2
639
+ #define T4CE0 3
640
+ #define T4CE1 4
641
+ #define T4ICS0 5
642
+ #define T4ICS1 6
643
+ #define T4ICS2 7
644
+
645
+ #define T4IMR _SFR_MEM8(0x88)
646
+ #define T4OIM 0
647
+ #define T4CIM 1
648
+ #define T4CPIM 2
649
+
650
+ /* Reserved [0x89] */
651
+
652
+ /* Combine T5OCRL and T5OCRH */
653
+ #define T5OCR _SFR_MEM16(0x8A)
654
+
655
+ #define T5OCRL _SFR_MEM8(0x8A)
656
+ #define T5OCRH _SFR_MEM8(0x8B)
657
+
658
+ #define T5CCR _SFR_MEM8(0x8C)
659
+ #define T5CS0 0
660
+ #define T5CS1 1
661
+ #define T5CS2 2
662
+ #define T5CTC 3
663
+
664
+ /* Combine T5CNTL and T5CNTH */
665
+ #define T5CNT _SFR_MEM16(0x8D)
666
+
667
+ #define T5CNTL _SFR_MEM8(0x8D)
668
+ #define T5CNTH _SFR_MEM8(0x8E)
669
+
670
+ #define T5IMR _SFR_MEM8(0x8F)
671
+ #define T5OIM 0
672
+ #define T5CIM 1
673
+
674
+ #define GTCCR _SFR_MEM8(0x90)
675
+ #define PSR10 0
676
+ #define TSM 7
677
+
678
+ #define SOTSB _SFR_MEM8(0x91)
679
+ #define CAROB 0
680
+ #define AMPOB 1
681
+ #define SYTOB 2
682
+ #define MANOB 3
683
+ #define WUPOB 4
684
+ #define SFIDOB 5
685
+ #define RROB 6
686
+ #define WCOAO 7
687
+
688
+ #define SOTSA _SFR_MEM8(0x92)
689
+ #define CAROA 0
690
+ #define AMPOA 1
691
+ #define SYTOA 2
692
+ #define MANOA 3
693
+ #define WUPOA 4
694
+ #define SFIDOA 5
695
+ #define RROA 6
696
+ #define WCOBO 7
697
+
698
+ #define SOTCB _SFR_MEM8(0x93)
699
+ #define CAROEB 0
700
+ #define AMPOEB 1
701
+ #define SYTOEB 2
702
+ #define MANOEB 3
703
+ #define WUPEB 4
704
+ #define SFIDEB 5
705
+ #define RROEB 6
706
+ #define WCOAOE 7
707
+
708
+ #define SOTCA _SFR_MEM8(0x94)
709
+ #define CAROEA 0
710
+ #define AMPOEA 1
711
+ #define SYTOEA 2
712
+ #define MANOEA 3
713
+ #define WUPEA 4
714
+ #define SFIDEA 5
715
+ #define RROEA 6
716
+ #define WCOBOE 7
717
+
718
+ #define TESRB _SFR_MEM8(0x95)
719
+ #define CRCOB 0
720
+ #define EOTLB0 1
721
+ #define EOTLB1 2
722
+
723
+ #define TESRA _SFR_MEM8(0x96)
724
+ #define CRCOA 0
725
+ #define EOTLA0 1
726
+ #define EOTLA1 2
727
+
728
+ /* Reserved [0x97] */
729
+
730
+ #define RDSIMR _SFR_MEM8(0x98)
731
+ #define NBITAM 0
732
+ #define NBITBM 1
733
+ #define EOTAM 2
734
+ #define EOTBM 3
735
+ #define SOTAM 4
736
+ #define SOTBM 5
737
+ #define WCOAM 6
738
+ #define WCOBM 7
739
+
740
+ #define RDOCR _SFR_MEM8(0x99)
741
+ #define TMDS0 1
742
+ #define TMDS1 2
743
+ #define ETRPA 3
744
+ #define ETRPB 4
745
+ #define RDSIDA 5
746
+ #define RDSIDB 6
747
+
748
+ /* Reserved [0x9A] */
749
+
750
+ #define TEMPL _SFR_MEM8(0x9B)
751
+
752
+ #define TEMPH _SFR_MEM8(0x9C)
753
+
754
+ #define SYCB _SFR_MEM8(0x9D)
755
+ #define SYCSB0 0
756
+ #define SYCSB1 1
757
+ #define SYCSB2 2
758
+ #define SYCSB3 3
759
+ #define SYTLB0 4
760
+ #define SYTLB1 5
761
+ #define SYTLB2 6
762
+ #define SYTLB3 7
763
+
764
+ #define SYCA _SFR_MEM8(0x9E)
765
+ #define SYCSA0 0
766
+ #define SYCSA1 1
767
+ #define SYCSA2 2
768
+ #define SYCSA3 3
769
+ #define SYTLA0 4
770
+ #define SYTLA1 5
771
+ #define SYTLA2 6
772
+ #define SYTLA3 7
773
+
774
+ #define RXFOB _SFR_MEM8(0x9F)
775
+
776
+ #define RXFOA _SFR_MEM8(0xA0)
777
+
778
+ #define DMMB _SFR_MEM8(0xA1)
779
+ #define DMATB0 0
780
+ #define DMATB1 1
781
+ #define DMATB2 2
782
+ #define DMATB3 3
783
+ #define DMATB4 4
784
+ #define DMPB 5
785
+ #define DMHB 6
786
+ #define DMNEB 7
787
+
788
+ #define DMMA _SFR_MEM8(0xA2)
789
+ #define DMATA0 0
790
+ #define DMATA1 1
791
+ #define DMATA2 2
792
+ #define DMATA3 3
793
+ #define DMATA4 4
794
+ #define DMPA 5
795
+ #define DMHA 6
796
+ #define DMNEA 7
797
+
798
+ #define DMCDB _SFR_MEM8(0xA3)
799
+ #define DMCLB0 0
800
+ #define DMCLB1 1
801
+ #define DMCLB2 2
802
+ #define DMCLB3 3
803
+ #define DMCLB4 4
804
+ #define DMCTB0 5
805
+ #define DMCTB1 6
806
+ #define DMCTB2 7
807
+
808
+ #define DMCDA _SFR_MEM8(0xA4)
809
+ #define DMCLA0 0
810
+ #define DMCLA1 1
811
+ #define DMCLA2 2
812
+ #define DMCLA3 3
813
+ #define DMCLA4 4
814
+ #define DMCTA0 5
815
+ #define DMCTA1 6
816
+ #define DMCTA2 7
817
+
818
+ #define DMCRB _SFR_MEM8(0xA5)
819
+ #define DMPGB0 0
820
+ #define DMPGB1 1
821
+ #define DMPGB2 2
822
+ #define DMPGB3 3
823
+ #define DMPGB4 4
824
+ #define SASKB 5
825
+ #define SY1TB 6
826
+ #define DMARB 7
827
+
828
+ #define DMCRA _SFR_MEM8(0xA6)
829
+ #define DMPGA0 0
830
+ #define DMPGA1 1
831
+ #define DMPGA2 2
832
+ #define DMPGA3 3
833
+ #define DMPGA4 4
834
+ #define SASKA 5
835
+ #define SY1TA 6
836
+ #define DMARA 7
837
+
838
+ #define DMDRB _SFR_MEM8(0xA7)
839
+ #define DMAB0 0
840
+ #define DMAB1 1
841
+ #define DMAB2 2
842
+ #define DMAB3 3
843
+ #define DMDNB0 4
844
+ #define DMDNB1 5
845
+ #define DMDNB2 6
846
+ #define DMDNB3 7
847
+
848
+ #define DMDRA _SFR_MEM8(0xA8)
849
+ #define DMAA0 0
850
+ #define DMAA1 1
851
+ #define DMAA2 2
852
+ #define DMAA3 3
853
+ #define DMDNA0 4
854
+ #define DMDNA1 5
855
+ #define DMDNA2 6
856
+ #define DMDNA3 7
857
+
858
+ #define CHCR _SFR_MEM8(0xA9)
859
+ #define BWM0 0
860
+ #define BWM1 1
861
+ #define BWM2 2
862
+ #define BWM3 3
863
+
864
+ #define CHDN _SFR_MEM8(0xAA)
865
+ #define BBDN0 0
866
+ #define BBDN1 1
867
+ #define BBDN2 2
868
+ #define BBDN3 3
869
+ #define BBDN4 4
870
+ #define ADCDN 5
871
+
872
+ #define SFIDCB _SFR_MEM8(0xAB)
873
+ #define SFIDTB0 0
874
+ #define SFIDTB1 1
875
+ #define SFIDTB2 2
876
+ #define SFIDTB3 3
877
+ #define SFIDTB4 4
878
+ #define SEMEB 7
879
+
880
+ #define SFIDLB _SFR_MEM8(0xAC)
881
+ #define SFIDLB0 0
882
+ #define SFIDLB1 1
883
+ #define SFIDLB2 2
884
+ #define SFIDLB3 3
885
+ #define SFIDLB4 4
886
+ #define SFIDLB5 5
887
+
888
+ #define WUPTB _SFR_MEM8(0xAD)
889
+ #define WUPTB0 0
890
+ #define WUPTB1 1
891
+ #define WUPTB2 2
892
+ #define WUPTB3 3
893
+ #define WUPTB4 4
894
+
895
+ #define WUPLB _SFR_MEM8(0xAE)
896
+ #define WUPLB0 0
897
+ #define WUPLB1 1
898
+ #define WUPLB2 2
899
+ #define WUPLB3 3
900
+ #define WUPLB4 4
901
+ #define WUPLB5 5
902
+
903
+ #define SFID1B _SFR_MEM8(0xAF)
904
+
905
+ #define SFID2B _SFR_MEM8(0xB0)
906
+
907
+ #define SFID3B _SFR_MEM8(0xB1)
908
+
909
+ #define SFID4B _SFR_MEM8(0xB2)
910
+
911
+ #define WUP1B _SFR_MEM8(0xB3)
912
+
913
+ #define WUP2B _SFR_MEM8(0xB4)
914
+
915
+ #define WUP3B _SFR_MEM8(0xB5)
916
+
917
+ #define WUP4B _SFR_MEM8(0xB6)
918
+
919
+ #define SFIDCA _SFR_MEM8(0xB7)
920
+ #define SFIDTA0 0
921
+ #define SFIDTA1 1
922
+ #define SFIDTA2 2
923
+ #define SFIDTA3 3
924
+ #define SFIDTA4 4
925
+ #define SEMEA 7
926
+
927
+ #define SFIDLA _SFR_MEM8(0xB8)
928
+ #define SFIDLA0 0
929
+ #define SFIDLA1 1
930
+ #define SFIDLA2 2
931
+ #define SFIDLA3 3
932
+ #define SFIDLA4 4
933
+ #define SFIDLA5 5
934
+
935
+ #define WUPTA _SFR_MEM8(0xB9)
936
+ #define WUPTA0 0
937
+ #define WUPTA1 1
938
+ #define WUPTA2 2
939
+ #define WUPTA3 3
940
+ #define WUPTA4 4
941
+
942
+ #define WUPLA _SFR_MEM8(0xBA)
943
+ #define WUPLA0 0
944
+ #define WUPLA1 1
945
+ #define WUPLA2 2
946
+ #define WUPLA3 3
947
+ #define WUPLA4 4
948
+ #define WUPLA5 5
949
+
950
+ #define SFID1A _SFR_MEM8(0xBB)
951
+
952
+ #define SFID2A _SFR_MEM8(0xBC)
953
+
954
+ #define SFID3A _SFR_MEM8(0xBD)
955
+
956
+ #define SFID4A _SFR_MEM8(0xBE)
957
+
958
+ #define WUP1A _SFR_MEM8(0xBF)
959
+
960
+ #define WUP2A _SFR_MEM8(0xC0)
961
+
962
+ #define WUP3A _SFR_MEM8(0xC1)
963
+
964
+ #define WUP4A _SFR_MEM8(0xC2)
965
+
966
+ #define CLKOD _SFR_MEM8(0xC3)
967
+
968
+ #define CLKOCR _SFR_MEM8(0xC4)
969
+ #define CLKOS0 0
970
+ #define CLKOS1 1
971
+ #define CLKOEN 2
972
+
973
+ #define XFUSE _SFR_MEM8(0xC5)
974
+
975
+ #define SRCCAL _SFR_MEM8(0xC6)
976
+ #define SRCCAL0 0
977
+ #define SRCCAL1 1
978
+ #define SRCCAL2 2
979
+ #define SRCCAL3 3
980
+ #define SRCCAL4 4
981
+ #define SRCCAL5 5
982
+ #define SRCTC0 6
983
+ #define SRCTC1 7
984
+
985
+ #define FRCCAL _SFR_MEM8(0xC7)
986
+ #define FRCCAL0 0
987
+ #define FRCCAL1 1
988
+ #define FRCCAL2 2
989
+ #define FRCCAL3 3
990
+ #define FRCCAL4 4
991
+ #define FRCTC 5
992
+
993
+ #define CMSR _SFR_MEM8(0xC8)
994
+ #define ECF 0
995
+
996
+ #define CMOCR _SFR_MEM8(0xC9)
997
+ #define FRCAO 0
998
+ #define SRCAO 1
999
+ #define FRCACT 2
1000
+ #define SRCACT 3
1001
+
1002
+ #define SUPFR _SFR_MEM8(0xCA)
1003
+ #define AVCCRF 0
1004
+ #define AVCCLF 1
1005
+
1006
+ #define SUPCR _SFR_MEM8(0xCB)
1007
+ #define AVCCRM 0
1008
+ #define AVCCLM 1
1009
+ #define PVEN 2
1010
+ #define DVDIS 4
1011
+ #define AVEN 5
1012
+ #define AVDIC 6
1013
+
1014
+ #define SUPCA1 _SFR_MEM8(0xCC)
1015
+ #define PV22 2
1016
+ #define PVDIC 3
1017
+ #define PVCAL0 4
1018
+ #define PVCAL1 5
1019
+ #define PVCAL2 6
1020
+ #define PVCAL3 7
1021
+
1022
+ #define SUPCA2 _SFR_MEM8(0xCD)
1023
+ #define BGCAL0 0
1024
+ #define BGCAL1 1
1025
+ #define BGCAL2 2
1026
+ #define BGCAL3 3
1027
+
1028
+ #define SUPCA3 _SFR_MEM8(0xCE)
1029
+ #define ACAL4 0
1030
+ #define ACAL5 1
1031
+ #define ACAL6 2
1032
+ #define ACAL7 3
1033
+ #define DCAL4 4
1034
+ #define DCAL5 5
1035
+ #define DCAL6 6
1036
+
1037
+ #define SUPCA4 _SFR_MEM8(0xCF)
1038
+ #define ACAL0 0
1039
+ #define ACAL1 1
1040
+ #define ACAL2 2
1041
+ #define ACAL3 3
1042
+ #define DCAL0 4
1043
+ #define DCAL1 5
1044
+ #define DCAL2 6
1045
+ #define DCAL3 7
1046
+
1047
+ #define CALRDY _SFR_MEM8(0xD0)
1048
+
1049
+ #define VMCAL _SFR_MEM8(0xD1)
1050
+ #define VMCAL0 0
1051
+ #define VMCAL1 1
1052
+ #define VMCAL2 2
1053
+
1054
+ #define DFS _SFR_MEM8(0xD2)
1055
+ #define DFFLRF 0
1056
+ #define DFUFL 1
1057
+ #define DFOFL 2
1058
+
1059
+ /* Combine DFTLL and DFTLH */
1060
+ #define DFTL _SFR_MEM16(0xD3)
1061
+
1062
+ #define DFTLL _SFR_MEM8(0xD3)
1063
+ #define DFTLH _SFR_MEM8(0xD4)
1064
+
1065
+ #define DFL _SFR_MEM8(0xD5)
1066
+ #define DFFLS0 0
1067
+ #define DFFLS1 1
1068
+ #define DFFLS2 2
1069
+ #define DFFLS3 3
1070
+ #define DFFLS4 4
1071
+ #define DFFLS5 5
1072
+ #define DFCLR 7
1073
+
1074
+ #define DFWP _SFR_MEM8(0xD6)
1075
+ #define DFWP0 0
1076
+ #define DFWP1 1
1077
+ #define DFWP2 2
1078
+ #define DFWP3 3
1079
+ #define DFWP4 4
1080
+ #define DFWP5 5
1081
+
1082
+ #define DFRP _SFR_MEM8(0xD7)
1083
+ #define DFRP0 0
1084
+ #define DFRP1 1
1085
+ #define DFRP2 2
1086
+ #define DFRP3 3
1087
+ #define DFRP4 4
1088
+ #define DFRP5 5
1089
+
1090
+ #define DFD _SFR_MEM8(0xD8)
1091
+
1092
+ #define DFI _SFR_MEM8(0xD9)
1093
+ #define DFFLIM 0
1094
+ #define DFERIM 1
1095
+
1096
+ #define DFC _SFR_MEM8(0xDA)
1097
+ #define DFFLC0 0
1098
+ #define DFFLC1 1
1099
+ #define DFFLC2 2
1100
+ #define DFFLC3 3
1101
+ #define DFFLC4 4
1102
+ #define DFFLC5 5
1103
+ #define DFDRA 7
1104
+
1105
+ #define SFS _SFR_MEM8(0xDB)
1106
+ #define SFFLRF 0
1107
+ #define SFUFL 1
1108
+ #define SFOFL 2
1109
+
1110
+ #define SFL _SFR_MEM8(0xDC)
1111
+ #define SFFLS0 0
1112
+ #define SFFLS1 1
1113
+ #define SFFLS2 2
1114
+ #define SFFLS3 3
1115
+ #define SFFLS4 4
1116
+ #define SFCLR 7
1117
+
1118
+ #define SFWP _SFR_MEM8(0xDD)
1119
+ #define SFWP0 0
1120
+ #define SFWP1 1
1121
+ #define SFWP2 2
1122
+ #define SFWP3 3
1123
+ #define SFWP4 4
1124
+
1125
+ #define SFRP _SFR_MEM8(0xDE)
1126
+ #define SFRP0 0
1127
+ #define SFRP1 1
1128
+ #define SFRP2 2
1129
+ #define SFRP3 3
1130
+ #define SFRP4 4
1131
+
1132
+ #define SFD _SFR_MEM8(0xDF)
1133
+
1134
+ #define SFI _SFR_MEM8(0xE0)
1135
+ #define SFFLIM 0
1136
+ #define SFERIM 1
1137
+
1138
+ #define SFC _SFR_MEM8(0xE1)
1139
+ #define SFFLC0 0
1140
+ #define SFFLC1 1
1141
+ #define SFFLC2 2
1142
+ #define SFFLC3 3
1143
+ #define SFFLC4 4
1144
+ #define SFDRA 7
1145
+
1146
+ #define SSMCR _SFR_MEM8(0xE2)
1147
+ #define SSMTX 0
1148
+ #define SSMTM 1
1149
+ #define SSMTGE 2
1150
+ #define SSMTPE 3
1151
+ #define SSMPVE 4
1152
+ #define SSMTAE 5
1153
+ #define SETRPA 6
1154
+ #define SETRPB 7
1155
+
1156
+ #define SSMRCR _SFR_MEM8(0xE3)
1157
+ #define SSMPA 0
1158
+ #define SSMPB 1
1159
+ #define SSMADA 2
1160
+ #define SSMADB 3
1161
+ #define SSMPVS 4
1162
+ #define SSMIFA 5
1163
+ #define SSMIDSE 6
1164
+ #define SSMTMOE 7
1165
+
1166
+ #define SSMFBR _SFR_MEM8(0xE4)
1167
+ #define SSMFID0 0
1168
+ #define SSMFID1 1
1169
+ #define SSMFID2 2
1170
+ #define SSMDFDT 3
1171
+ #define SSMHADT 4
1172
+ #define SSMPLDT 5
1173
+
1174
+ #define SSMRR _SFR_MEM8(0xE5)
1175
+ #define SSMR 0
1176
+ #define SSMST 1
1177
+
1178
+ #define SSMSR _SFR_MEM8(0xE6)
1179
+ #define SSMESM0 0
1180
+ #define SSMESM1 1
1181
+ #define SSMESM2 2
1182
+ #define SSMESM3 3
1183
+ #define SSMERR 7
1184
+
1185
+ #define SSMIFR _SFR_MEM8(0xE7)
1186
+ #define SSMIF 0
1187
+
1188
+ #define SSMIMR _SFR_MEM8(0xE8)
1189
+ #define SSMIM 0
1190
+
1191
+ #define MSMSTR _SFR_MEM8(0xE9)
1192
+ #define SSMMST0 0
1193
+ #define SSMMST1 1
1194
+ #define SSMMST2 2
1195
+ #define SSMMST3 3
1196
+ #define SSMMST4 4
1197
+
1198
+ #define SSMSTR _SFR_MEM8(0xEA)
1199
+ #define SSMSTA0 0
1200
+ #define SSMSTA1 1
1201
+ #define SSMSTA2 2
1202
+ #define SSMSTA3 3
1203
+ #define SSMSTA4 4
1204
+ #define SSMSTA5 5
1205
+
1206
+ #define SSMXSR _SFR_MEM8(0xEB)
1207
+ #define SSMSTB0 0
1208
+ #define SSMSTB1 1
1209
+ #define SSMSTB2 2
1210
+ #define SSMSTB3 3
1211
+ #define SSMSTB4 4
1212
+ #define SSMSTB5 5
1213
+
1214
+ #define MSMCR1 _SFR_MEM8(0xEC)
1215
+ #define MSMSM00 0
1216
+ #define MSMSM01 1
1217
+ #define MSMSM02 2
1218
+ #define MSMSM03 3
1219
+ #define MSMSM10 4
1220
+ #define MSMSM11 5
1221
+ #define MSMSM12 6
1222
+ #define MSMSM13 7
1223
+
1224
+ #define MSMCR2 _SFR_MEM8(0xED)
1225
+ #define MSMSM20 0
1226
+ #define MSMSM21 1
1227
+ #define MSMSM22 2
1228
+ #define MSMSM23 3
1229
+ #define MSMSM30 4
1230
+ #define MSMSM31 5
1231
+ #define MSMSM32 6
1232
+ #define MSMSM33 7
1233
+
1234
+ #define MSMCR3 _SFR_MEM8(0xEE)
1235
+ #define MSMSM40 0
1236
+ #define MSMSM41 1
1237
+ #define MSMSM42 2
1238
+ #define MSMSM43 3
1239
+ #define MSMSM50 4
1240
+ #define MSMSM51 5
1241
+ #define MSMSM52 6
1242
+ #define MSMSM53 7
1243
+
1244
+ #define MSMCR4 _SFR_MEM8(0xEF)
1245
+ #define MSMSM60 0
1246
+ #define MSMSM61 1
1247
+ #define MSMSM62 2
1248
+ #define MSMSM63 3
1249
+ #define MSMSM70 4
1250
+ #define MSMSM71 5
1251
+ #define MSMSM72 6
1252
+ #define MSMSM73 7
1253
+
1254
+ #define GTCR _SFR_MEM8(0xF0)
1255
+ #define RXTEHA 0
1256
+ #define GAPMA 1
1257
+ #define DARA 2
1258
+ #define IWUPA 3
1259
+ #define RXTEHB 4
1260
+ #define GAPMB 5
1261
+ #define DARB 6
1262
+ #define IWUPB 7
1263
+
1264
+ #define SOTC1A _SFR_MEM8(0xF1)
1265
+ #define CAROEA1 0
1266
+ #define AMPOEA1 1
1267
+ #define SYTOEA1 2
1268
+ #define MANOEA1 3
1269
+ #define WUPEA1 4
1270
+ #define SFIDEA1 5
1271
+ #define RROEA1 6
1272
+ #define WCOBOE1 7
1273
+
1274
+ #define SOTC2A _SFR_MEM8(0xF2)
1275
+ #define CAROEA2 0
1276
+ #define AMPOEA2 1
1277
+ #define SYTOEA2 2
1278
+ #define MANOEA2 3
1279
+ #define WUPEA2 4
1280
+ #define SFIDEA2 5
1281
+ #define RROEA2 6
1282
+ #define WCOBOE2 7
1283
+
1284
+ #define SOTC1B _SFR_MEM8(0xF3)
1285
+ #define CAROEB1 0
1286
+ #define AMPOEB1 1
1287
+ #define SYTOEB1 2
1288
+ #define MANOEB1 3
1289
+ #define WUPEB1 4
1290
+ #define SFIDEB1 5
1291
+ #define RROEB1 6
1292
+ #define WCOAOE1 7
1293
+
1294
+ #define SOTC2B _SFR_MEM8(0xF4)
1295
+ #define CAROEB2 0
1296
+ #define AMPOEB2 1
1297
+ #define SYTOEB2 2
1298
+ #define MANOEB2 3
1299
+ #define WUPEB2 4
1300
+ #define SFIDEB2 5
1301
+ #define RROEB2 6
1302
+ #define WCOAOE2 7
1303
+
1304
+ #define EOTC1A _SFR_MEM8(0xF5)
1305
+ #define CARFEA1 0
1306
+ #define AMPFEA1 1
1307
+ #define SYTFEA1 2
1308
+ #define MANFEA1 3
1309
+ #define TMOFEA1 4
1310
+ #define TELREA1 5
1311
+ #define RRFEA1 6
1312
+ #define EOTBFE1 7
1313
+
1314
+ #define EOTC2A _SFR_MEM8(0xF6)
1315
+ #define CARFEA2 0
1316
+ #define AMPFEA2 1
1317
+ #define SYTFEA2 2
1318
+ #define MANFEA2 3
1319
+ #define TMOFEA2 4
1320
+ #define TELREA2 5
1321
+ #define RRFEA2 6
1322
+ #define EOTBFE2 7
1323
+
1324
+ #define EOTC3A _SFR_MEM8(0xF7)
1325
+ #define CARFEA3 0
1326
+ #define AMPFEA3 1
1327
+ #define SYTFEA3 2
1328
+ #define MANFEA3 3
1329
+ #define TMOFEA3 4
1330
+ #define TELREA3 5
1331
+ #define RRFEA3 6
1332
+ #define EOTBFE3 7
1333
+
1334
+ #define EOTC1B _SFR_MEM8(0xF8)
1335
+ #define CARFEB1 0
1336
+ #define AMPFEB1 1
1337
+ #define SYTFEB1 2
1338
+ #define MANFEB1 3
1339
+ #define TMOFEB1 4
1340
+ #define TELREB1 5
1341
+ #define RRFEB1 6
1342
+ #define EOTAFE1 7
1343
+
1344
+ #define EOTC2B _SFR_MEM8(0xF9)
1345
+ #define CARFEB2 0
1346
+ #define AMPFEB2 1
1347
+ #define SYTFEB2 2
1348
+ #define MANFEB2 3
1349
+ #define TMOFEB2 4
1350
+ #define TELREB2 5
1351
+ #define RRFEB2 6
1352
+ #define EOTAFE2 7
1353
+
1354
+ #define EOTC3B _SFR_MEM8(0xFA)
1355
+ #define CARFEB3 0
1356
+ #define AMPFEB3 1
1357
+ #define SYTFEB3 2
1358
+ #define MANFEB3 3
1359
+ #define TMOFEB3 4
1360
+ #define TELREB3 5
1361
+ #define RRFEB3 6
1362
+ #define EOTAFE3 7
1363
+
1364
+ #define WCOTOA _SFR_MEM8(0xFB)
1365
+
1366
+ #define WCOTOB _SFR_MEM8(0xFC)
1367
+
1368
+ #define SOTTOA _SFR_MEM8(0xFD)
1369
+
1370
+ #define SOTTOB _SFR_MEM8(0xFE)
1371
+
1372
+ #define SSMFCR _SFR_MEM8(0xFF)
1373
+ #define SSMIDSO 0
1374
+ #define SSMIDSF 1
1375
+
1376
+ #define FESR _SFR_MEM8(0x100)
1377
+ #define LBSAT 0
1378
+ #define HBSAT 1
1379
+ #define XRDY 2
1380
+ #define PLCK 3
1381
+ #define ANTS 4
1382
+
1383
+ #define FEEN1 _SFR_MEM8(0x101)
1384
+ #define PLEN 0
1385
+ #define PLCAL 1
1386
+ #define XTOEN 2
1387
+ #define LNAEN 3
1388
+ #define ADEN 4
1389
+ #define ADCLK 5
1390
+ #define PLSP1 6
1391
+ #define ATEN 7
1392
+
1393
+ #define FEEN2 _SFR_MEM8(0x102)
1394
+ #define SDRX 0
1395
+ #define SDTX 1
1396
+ #define PAEN 2
1397
+ #define TMPM 3
1398
+ #define PLPEN 4
1399
+ #define XTPEN 5
1400
+ #define CPBIA 6
1401
+
1402
+ #define FELNA _SFR_MEM8(0x103)
1403
+ #define LBH0 0
1404
+ #define LBH1 1
1405
+ #define LBH2 2
1406
+ #define LBH3 3
1407
+ #define LBL0 4
1408
+ #define LBL1 5
1409
+ #define LBL2 6
1410
+ #define LBL3 7
1411
+
1412
+ #define FEAT _SFR_MEM8(0x104)
1413
+ #define ANTN0 0
1414
+ #define ANTN1 1
1415
+ #define ANTN2 2
1416
+ #define ANTN3 3
1417
+
1418
+ #define FEPAC _SFR_MEM8(0x105)
1419
+
1420
+ #define FEVCT _SFR_MEM8(0x106)
1421
+ #define FEVCT0 0
1422
+ #define FEVCT1 1
1423
+ #define FEVCT2 2
1424
+ #define FEVCT3 3
1425
+
1426
+ #define FEBT _SFR_MEM8(0x107)
1427
+ #define CTN20 0
1428
+ #define CTN21 1
1429
+ #define RTN20 2
1430
+ #define RTN21 3
1431
+
1432
+ #define FEMS _SFR_MEM8(0x108)
1433
+ #define PLLS0 0
1434
+ #define PLLS1 1
1435
+ #define PLLS2 2
1436
+ #define PLLS3 3
1437
+ #define PLLM0 4
1438
+ #define PLLM1 5
1439
+ #define PLLM2 6
1440
+ #define PLLM3 7
1441
+
1442
+ #define FETN4 _SFR_MEM8(0x109)
1443
+ #define CTN40 0
1444
+ #define CTN41 1
1445
+ #define CTN42 2
1446
+ #define CTN43 3
1447
+ #define RTN40 4
1448
+ #define RTN41 5
1449
+ #define RTN42 6
1450
+ #define RTN43 7
1451
+
1452
+ #define FECR _SFR_MEM8(0x10A)
1453
+ #define LBNHB 0
1454
+ #define S4N3 1
1455
+ #define ANDP 2
1456
+ #define ADHS 3
1457
+ #define PLCKG 4
1458
+ #define ANPS 5
1459
+
1460
+ #define FEVCO _SFR_MEM8(0x10B)
1461
+ #define CPCC0 0
1462
+ #define CPCC1 1
1463
+ #define CPCC2 2
1464
+ #define CPCC3 3
1465
+ #define VCOB0 4
1466
+ #define VCOB1 5
1467
+ #define VCOB2 6
1468
+ #define VCOB3 7
1469
+
1470
+ #define FEALR _SFR_MEM8(0x10C)
1471
+ #define RNGE0 0
1472
+ #define RNGE1 1
1473
+
1474
+ #define FEANT _SFR_MEM8(0x10D)
1475
+ #define LVLC0 0
1476
+ #define LVLC1 1
1477
+ #define LVLC2 2
1478
+ #define LVLC3 3
1479
+
1480
+ #define FEBIA _SFR_MEM8(0x10E)
1481
+ #define IFAEN 7
1482
+
1483
+ /* Reserved [0x10F..0x11F] */
1484
+
1485
+ #define TMFSM _SFR_MEM8(0x120)
1486
+ #define TMSSM0 0
1487
+ #define TMSSM1 1
1488
+ #define TMSSM2 2
1489
+ #define TMSSM3 3
1490
+ #define TMMSM0 4
1491
+ #define TMMSM1 5
1492
+ #define TMMSM2 6
1493
+
1494
+ /* Combine TMCRL and TMCRH */
1495
+ #define TMCR _SFR_MEM16(0x121)
1496
+
1497
+ #define TMCRL _SFR_MEM8(0x121)
1498
+ #define TMCRH _SFR_MEM8(0x122)
1499
+
1500
+ #define TMCSB _SFR_MEM8(0x123)
1501
+
1502
+ /* Combine TMCIL and TMCIH */
1503
+ #define TMCI _SFR_MEM16(0x124)
1504
+
1505
+ #define TMCIL _SFR_MEM8(0x124)
1506
+ #define TMCIH _SFR_MEM8(0x125)
1507
+
1508
+ /* Combine TMCPL and TMCPH */
1509
+ #define TMCP _SFR_MEM16(0x126)
1510
+
1511
+ #define TMCPL _SFR_MEM8(0x126)
1512
+ #define TMCPH _SFR_MEM8(0x127)
1513
+
1514
+ #define TMSHR _SFR_MEM8(0x128)
1515
+
1516
+ /* Combine TMTLL and TMTLH */
1517
+ #define TMTL _SFR_MEM16(0x129)
1518
+
1519
+ #define TMTLL _SFR_MEM8(0x129)
1520
+ #define TMTLH _SFR_MEM8(0x12A)
1521
+
1522
+ #define TMSSC _SFR_MEM8(0x12B)
1523
+ #define TMSSP0 0
1524
+ #define TMSSP1 1
1525
+ #define TMSSP2 2
1526
+ #define TMSSP3 3
1527
+ #define TMSSL0 4
1528
+ #define TMSSL1 5
1529
+ #define TMSSL2 6
1530
+ #define TMSSH 7
1531
+
1532
+ #define TMSR _SFR_MEM8(0x12C)
1533
+ #define TMTCF 0
1534
+
1535
+ #define TMCR2 _SFR_MEM8(0x12D)
1536
+ #define TMCRCE 0
1537
+ #define TMCRCL0 1
1538
+ #define TMCRCL1 2
1539
+ #define TMNRZE 3
1540
+ #define TMPOL 4
1541
+ #define TMSSE 5
1542
+ #define TMMSB 6
1543
+
1544
+ #define TMCR1 _SFR_MEM8(0x12E)
1545
+ #define TMPIS0 0
1546
+ #define TMPIS1 1
1547
+ #define TMPIS2 2
1548
+ #define TMSCS 3
1549
+ #define TMCIM 4
1550
+
1551
+ #define RXBC1 _SFR_MEM8(0x12F)
1552
+ #define RXCEA 0
1553
+ #define RXCBLA0 1
1554
+ #define RXCBLA1 2
1555
+ #define RXMSBA 3
1556
+ #define RXCEB 4
1557
+ #define RXCBLB0 5
1558
+ #define RXCBLB1 6
1559
+ #define RXMSBB 7
1560
+
1561
+ #define RXBC2 _SFR_MEM8(0x130)
1562
+ #define RXBPB 0
1563
+ #define RXBF 1
1564
+ #define RXBCLR 2
1565
+
1566
+ #define RXTLLB _SFR_MEM8(0x131)
1567
+
1568
+ #define RXTLHB _SFR_MEM8(0x132)
1569
+ #define RXTLHB0 0
1570
+ #define RXTLHB1 1
1571
+ #define RXTLHB2 2
1572
+ #define RXTLHB3 3
1573
+
1574
+ #define RXCRLB _SFR_MEM8(0x133)
1575
+
1576
+ #define RXCRHB _SFR_MEM8(0x134)
1577
+
1578
+ #define RXCSBB _SFR_MEM8(0x135)
1579
+
1580
+ #define RXCILB _SFR_MEM8(0x136)
1581
+
1582
+ #define RXCIHB _SFR_MEM8(0x137)
1583
+
1584
+ #define RXCPLB _SFR_MEM8(0x138)
1585
+
1586
+ #define RXCPHB _SFR_MEM8(0x139)
1587
+
1588
+ #define RXDSB _SFR_MEM8(0x13A)
1589
+
1590
+ #define RXTLLA _SFR_MEM8(0x13B)
1591
+
1592
+ #define RXTLHA _SFR_MEM8(0x13C)
1593
+ #define RXTLHA0 0
1594
+ #define RXTLHA1 1
1595
+ #define RXTLHA2 2
1596
+ #define RXTLHA3 3
1597
+
1598
+ #define RXCRLA _SFR_MEM8(0x13D)
1599
+
1600
+ #define RXCRHA _SFR_MEM8(0x13E)
1601
+
1602
+ #define RXCSBA _SFR_MEM8(0x13F)
1603
+
1604
+ #define RXCILA _SFR_MEM8(0x140)
1605
+
1606
+ #define RXCIHA _SFR_MEM8(0x141)
1607
+
1608
+ #define RXCPLA _SFR_MEM8(0x142)
1609
+
1610
+ #define RXCPHA _SFR_MEM8(0x143)
1611
+
1612
+ #define RXDSA _SFR_MEM8(0x144)
1613
+
1614
+ #define CRCCR _SFR_MEM8(0x145)
1615
+ #define CRCRS 0
1616
+ #define REFLI 1
1617
+ #define REFLO 2
1618
+
1619
+ #define CRCDOR _SFR_MEM8(0x146)
1620
+
1621
+ #define IDB0 _SFR_MEM8(0x147)
1622
+
1623
+ #define IDB1 _SFR_MEM8(0x148)
1624
+
1625
+ #define IDB2 _SFR_MEM8(0x149)
1626
+
1627
+ #define IDB3 _SFR_MEM8(0x14A)
1628
+
1629
+ #define IDC _SFR_MEM8(0x14B)
1630
+ #define IDL0 0
1631
+ #define IDL1 1
1632
+ #define IDBO0 2
1633
+ #define IDBO1 3
1634
+ #define IDFIM 5
1635
+ #define IDCLR 6
1636
+ #define IDCE 7
1637
+
1638
+ #define IDS _SFR_MEM8(0x14C)
1639
+ #define IDOK 0
1640
+ #define IDFULL 1
1641
+
1642
+ #define RSSAV _SFR_MEM8(0x14D)
1643
+
1644
+ #define RSSPK _SFR_MEM8(0x14E)
1645
+
1646
+ #define RSSL _SFR_MEM8(0x14F)
1647
+
1648
+ #define RSSH _SFR_MEM8(0x150)
1649
+
1650
+ #define RSSC _SFR_MEM8(0x151)
1651
+ #define RSUP0 0
1652
+ #define RSUP1 1
1653
+ #define RSUP2 2
1654
+ #define RSUP3 3
1655
+ #define RSWLH 4
1656
+ #define RSHRX 5
1657
+ #define RSPKF 6
1658
+
1659
+ #define DBCR _SFR_MEM8(0x152)
1660
+ #define DBMD 0
1661
+ #define DBCS 1
1662
+ #define DBTMS 2
1663
+ #define DBHA 3
1664
+
1665
+ #define DBTC _SFR_MEM8(0x153)
1666
+
1667
+ #define DBENB _SFR_MEM8(0x154)
1668
+
1669
+ #define DBENC _SFR_MEM8(0x155)
1670
+
1671
+ #define DBGSW _SFR_MEM8(0x156)
1672
+ #define DBGGS0 0
1673
+ #define DBGGS1 1
1674
+ #define DBGGS2 2
1675
+ #define DBGGS3 3
1676
+ #define CPBFOS0 4
1677
+ #define CPBFOS1 5
1678
+ #define CPBF 6
1679
+ #define DBGSE 7
1680
+
1681
+ #define SFFR _SFR_MEM8(0x157)
1682
+ #define RFL0 0
1683
+ #define RFL1 1
1684
+ #define RFL2 2
1685
+ #define RFC 3
1686
+ #define TFL0 4
1687
+ #define TFL1 5
1688
+ #define TFL2 6
1689
+ #define TFC 7
1690
+
1691
+ #define SFIR _SFR_MEM8(0x158)
1692
+ #define RIL0 0
1693
+ #define RIL1 1
1694
+ #define RIL2 2
1695
+ #define SRIE 3
1696
+ #define TIL0 4
1697
+ #define TIL1 5
1698
+ #define TIL2 6
1699
+ #define STIE 7
1700
+
1701
+ #define EECR2 _SFR_MEM8(0x159)
1702
+ #define EEBRE 0
1703
+
1704
+ #define PGMST _SFR_MEM8(0x15A)
1705
+ #define PGMSYN0 0
1706
+ #define PGMSYN1 1
1707
+ #define PGMSYN2 2
1708
+ #define PGMSYN3 3
1709
+ #define PGMSYN4 4
1710
+
1711
+ #define EEST _SFR_MEM8(0x15B)
1712
+ #define EESYN0 0
1713
+ #define EESYN1 1
1714
+ #define EESYN2 2
1715
+ #define EESYN3 3
1716
+
1717
+ #define RSIFG _SFR_MEM8(0x15C)
1718
+
1719
+ #define RSLDV _SFR_MEM8(0x15D)
1720
+
1721
+ #define RSHDV _SFR_MEM8(0x15E)
1722
+
1723
+ #define RSCOM _SFR_MEM8(0x15F)
1724
+ #define RSDC 0
1725
+ #define RSIFC 1
1726
+
1727
+
1728
+
1729
+ /* Values and associated defines */
1730
+
1731
+
1732
+ #define SLEEP_MODE_IDLE (0x00<<1)
1733
+ #define SLEEP_MODE_EXT_PWR_SAVE (0x01<<1)
1734
+ #define SLEEP_MODE_PWR_DOWN (0x02<<1)
1735
+ #define SLEEP_MODE_PWR_SAVE (0x03<<1)
1736
+
1737
+ /* Interrupt vectors */
1738
+ /* Vector 0 is the reset vector */
1739
+ /* External Interrupt Request 0 */
1740
+ #define INT0_vect _VECTOR(1)
1741
+ #define INT0_vect_num 1
1742
+
1743
+ /* External Interrupt Request 1 */
1744
+ #define INT1_vect _VECTOR(2)
1745
+ #define INT1_vect_num 2
1746
+
1747
+ /* Pin Change Interrupt Request 0 */
1748
+ #define PCI0_vect _VECTOR(3)
1749
+ #define PCI0_vect_num 3
1750
+
1751
+ /* Pin Change Interrupt Request 1 */
1752
+ #define PCI1_vect _VECTOR(4)
1753
+ #define PCI1_vect_num 4
1754
+
1755
+ /* Voltage Monitoring Interrupt */
1756
+ #define VMON_vect _VECTOR(5)
1757
+ #define VMON_vect_num 5
1758
+
1759
+ /* AVCC Reset Interrupt */
1760
+ #define AVCCR_vect _VECTOR(6)
1761
+ #define AVCCR_vect_num 6
1762
+
1763
+ /* AVCC Low Interrupt */
1764
+ #define AVCCL_vect _VECTOR(7)
1765
+ #define AVCCL_vect_num 7
1766
+
1767
+ /* Timer 0 Interval Interrupt */
1768
+ #define T0INT_vect _VECTOR(8)
1769
+ #define T0INT_vect_num 8
1770
+
1771
+ /* Timer/Counter1 Compare Match Interrupt */
1772
+ #define T1COMP_vect _VECTOR(9)
1773
+ #define T1COMP_vect_num 9
1774
+
1775
+ /* Timer/Counter1 Overflow Interrupt */
1776
+ #define T1OVF_vect _VECTOR(10)
1777
+ #define T1OVF_vect_num 10
1778
+
1779
+ /* Timer/Counter2 Compare Match Interrupt */
1780
+ #define T2COMP_vect _VECTOR(11)
1781
+ #define T2COMP_vect_num 11
1782
+
1783
+ /* Timer/Counter2 Overflow Interrupt */
1784
+ #define T2OVF_vect _VECTOR(12)
1785
+ #define T2OVF_vect_num 12
1786
+
1787
+ /* Timer/Counter3 Capture Event Interrupt */
1788
+ #define T3CAP_vect _VECTOR(13)
1789
+ #define T3CAP_vect_num 13
1790
+
1791
+ /* Timer/Counter3 Compare Match Interrupt */
1792
+ #define T3COMP_vect _VECTOR(14)
1793
+ #define T3COMP_vect_num 14
1794
+
1795
+ /* Timer/Counter3 Overflow Interrupt */
1796
+ #define T3OVF_vect _VECTOR(15)
1797
+ #define T3OVF_vect_num 15
1798
+
1799
+ /* Timer/Counter4 Capture Event Interrupt */
1800
+ #define T4CAP_vect _VECTOR(16)
1801
+ #define T4CAP_vect_num 16
1802
+
1803
+ /* Timer/Counter4 Compare Match Interrupt */
1804
+ #define T4COMP_vect _VECTOR(17)
1805
+ #define T4COMP_vect_num 17
1806
+
1807
+ /* Timer/Counter4 Overflow Interrupt */
1808
+ #define T4OVF_vect _VECTOR(18)
1809
+ #define T4OVF_vect_num 18
1810
+
1811
+ /* Timer/Counter5 Compare Match Interrupt */
1812
+ #define T5COMP_vect _VECTOR(19)
1813
+ #define T5COMP_vect_num 19
1814
+
1815
+ /* Timer/Counter5 Overflow Interrupt */
1816
+ #define T5OVF_vect _VECTOR(20)
1817
+ #define T5OVF_vect_num 20
1818
+
1819
+ /* SPI Serial Transfer Complete Interrupt */
1820
+ #define SPI_vect _VECTOR(21)
1821
+ #define SPI_vect_num 21
1822
+
1823
+ /* SPI Rx Buffer Interrupt */
1824
+ #define SRX_FIFO_vect _VECTOR(22)
1825
+ #define SRX_FIFO_vect_num 22
1826
+
1827
+ /* SPI Tx Buffer Interrupt */
1828
+ #define STX_FIFO_vect _VECTOR(23)
1829
+ #define STX_FIFO_vect_num 23
1830
+
1831
+ /* Sequencer State Machine Interrupt */
1832
+ #define SSM_vect _VECTOR(24)
1833
+ #define SSM_vect_num 24
1834
+
1835
+ /* Data FIFO fill level reached Interrupt */
1836
+ #define DFFLR_vect _VECTOR(25)
1837
+ #define DFFLR_vect_num 25
1838
+
1839
+ /* Data FIFO overflow or underflow error Interrupt */
1840
+ #define DFOUE_vect _VECTOR(26)
1841
+ #define DFOUE_vect_num 26
1842
+
1843
+ /* RSSI/Preamble FIFO fill level reached Interrupt */
1844
+ #define SFFLR_vect _VECTOR(27)
1845
+ #define SFFLR_vect_num 27
1846
+
1847
+ /* RSSI/Preamble FIFO overflow or underflow error Interrupt */
1848
+ #define SFOUE_vect _VECTOR(28)
1849
+ #define SFOUE_vect_num 28
1850
+
1851
+ /* Tx Modulator Telegram Finish Interrupt */
1852
+ #define TMTCF_vect _VECTOR(29)
1853
+ #define TMTCF_vect_num 29
1854
+
1855
+ /* UHF receiver wake up ok on Rx path B */
1856
+ #define UHF_WCOB_vect _VECTOR(30)
1857
+ #define UHF_WCOB_vect_num 30
1858
+
1859
+ /* UHF receiver wake up ok on Rx path A */
1860
+ #define UHF_WCOA_vect _VECTOR(31)
1861
+ #define UHF_WCOA_vect_num 31
1862
+
1863
+ /* UHF receiver start of telegram ok on Rx path B */
1864
+ #define UHF_SOTB_vect _VECTOR(32)
1865
+ #define UHF_SOTB_vect_num 32
1866
+
1867
+ /* UHF receiver start of telegram ok on Rx path A */
1868
+ #define UHF_SOTA_vect _VECTOR(33)
1869
+ #define UHF_SOTA_vect_num 33
1870
+
1871
+ /* UHF receiver end of telegram on Rx path B */
1872
+ #define UHF_EOTB_vect _VECTOR(34)
1873
+ #define UHF_EOTB_vect_num 34
1874
+
1875
+ /* UHF receiver end of telegram on Rx path A */
1876
+ #define UHF_EOTA_vect _VECTOR(35)
1877
+ #define UHF_EOTA_vect_num 35
1878
+
1879
+ /* UHF receiver new bit on Rx path B */
1880
+ #define UHF_NBITB_vect _VECTOR(36)
1881
+ #define UHF_NBITB_vect_num 36
1882
+
1883
+ /* UHF receiver new bit on Rx path A */
1884
+ #define UHF_NBITA_vect _VECTOR(37)
1885
+ #define UHF_NBITA_vect_num 37
1886
+
1887
+ /* External input Clock monitoring Interrupt */
1888
+ #define EXCM_vect _VECTOR(38)
1889
+ #define EXCM_vect_num 38
1890
+
1891
+ /* EEPROM Ready Interrupt */
1892
+ #define ERDY_vect _VECTOR(39)
1893
+ #define ERDY_vect_num 39
1894
+
1895
+ /* Store Program Memory Ready */
1896
+ #define SPMR_vect _VECTOR(40)
1897
+ #define SPMR_vect_num 40
1898
+
1899
+ /* IDSCAN Full Interrupt */
1900
+ #define IDFULL_vect _VECTOR(41)
1901
+ #define IDFULL_vect_num 41
1902
+
1903
+ #define _VECTORS_SIZE 168
1904
+
1905
+
1906
+ /* Constants */
1907
+
1908
+ #define SPM_PAGESIZE 64
1909
+ #define FLASHSTART 0x8000
1910
+ #define FLASHEND 0xCFFF
1911
+ #define RAMSTART 0x0200
1912
+ #define RAMSIZE 1024
1913
+ #define RAMEND 0x05FF
1914
+ #define E2START 0
1915
+ #define E2SIZE 1024
1916
+ #define E2PAGESIZE 16
1917
+ #define E2END 0x03FF
1918
+ #define XRAMEND RAMEND
1919
+
1920
+
1921
+ /* Fuses */
1922
+
1923
+ #define FUSE_MEMORY_SIZE 1
1924
+
1925
+ /* Fuse Byte */
1926
+ #define FUSE_EXTCLKEN (unsigned char)~_BV(0)
1927
+ #define FUSE_RSTDISBL (unsigned char)~_BV(1)
1928
+ #define FUSE_BOOTRST (unsigned char)~_BV(2)
1929
+ #define FUSE_EESAVE (unsigned char)~_BV(3)
1930
+ #define FUSE_WDTON (unsigned char)~_BV(4)
1931
+ #define FUSE_SPIEN (unsigned char)~_BV(5)
1932
+ #define FUSE_DWEN (unsigned char)~_BV(6)
1933
+ #define FUSE_CKDIV8 (unsigned char)~_BV(7)
1934
+ #define LFUSE_DEFAULT (FUSE_SPIEN)
1935
+
1936
+
1937
+
1938
+ /* Lock Bits */
1939
+ #define __LOCK_BITS_EXIST
1940
+
1941
+
1942
+ /* Signature */
1943
+ #define SIGNATURE_0 0x1E
1944
+ #define SIGNATURE_1 0x95
1945
+ #define SIGNATURE_2 0x61
1946
+
1947
+
1948
+ #endif /* #ifdef _AVR_ATA5831_H_INCLUDED */
1949
+