arduino_ci 0.1.3 → 0.1.4

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Files changed (295) hide show
  1. checksums.yaml +4 -4
  2. data/README.md +77 -1
  3. data/cpp/arduino/Arduino.cpp +17 -7
  4. data/cpp/arduino/Arduino.h +151 -5
  5. data/cpp/arduino/ArduinoDefines.h +90 -0
  6. data/cpp/arduino/AvrMath.h +18 -28
  7. data/cpp/arduino/Godmode.cpp +62 -0
  8. data/cpp/arduino/Godmode.h +74 -0
  9. data/cpp/arduino/HardwareSerial.h +81 -0
  10. data/cpp/arduino/Print.h +67 -0
  11. data/cpp/arduino/Stream.h +210 -0
  12. data/cpp/arduino/WCharacter.h +96 -0
  13. data/cpp/arduino/WString.h +164 -0
  14. data/cpp/arduino/binary.h +518 -0
  15. data/cpp/arduino/include/README.md +3 -0
  16. data/cpp/arduino/include/common.h +333 -0
  17. data/cpp/arduino/include/fuse.h +274 -0
  18. data/cpp/arduino/include/io.h +643 -0
  19. data/cpp/arduino/include/io1200.h +274 -0
  20. data/cpp/arduino/include/io2313.h +385 -0
  21. data/cpp/arduino/include/io2323.h +210 -0
  22. data/cpp/arduino/include/io2333.h +461 -0
  23. data/cpp/arduino/include/io2343.h +214 -0
  24. data/cpp/arduino/include/io43u32x.h +440 -0
  25. data/cpp/arduino/include/io43u35x.h +432 -0
  26. data/cpp/arduino/include/io4414.h +500 -0
  27. data/cpp/arduino/include/io4433.h +489 -0
  28. data/cpp/arduino/include/io4434.h +588 -0
  29. data/cpp/arduino/include/io76c711.h +499 -0
  30. data/cpp/arduino/include/io8515.h +501 -0
  31. data/cpp/arduino/include/io8534.h +217 -0
  32. data/cpp/arduino/include/io8535.h +589 -0
  33. data/cpp/arduino/include/io86r401.h +309 -0
  34. data/cpp/arduino/include/io90pwm1.h +1157 -0
  35. data/cpp/arduino/include/io90pwm161.h +918 -0
  36. data/cpp/arduino/include/io90pwm216.h +1225 -0
  37. data/cpp/arduino/include/io90pwm2b.h +1466 -0
  38. data/cpp/arduino/include/io90pwm316.h +1272 -0
  39. data/cpp/arduino/include/io90pwm3b.h +1466 -0
  40. data/cpp/arduino/include/io90pwm81.h +1036 -0
  41. data/cpp/arduino/include/io90pwmx.h +1415 -0
  42. data/cpp/arduino/include/io90scr100.h +1719 -0
  43. data/cpp/arduino/include/ioa5272.h +803 -0
  44. data/cpp/arduino/include/ioa5505.h +803 -0
  45. data/cpp/arduino/include/ioa5702m322.h +2591 -0
  46. data/cpp/arduino/include/ioa5782.h +1843 -0
  47. data/cpp/arduino/include/ioa5790.h +907 -0
  48. data/cpp/arduino/include/ioa5790n.h +922 -0
  49. data/cpp/arduino/include/ioa5791.h +923 -0
  50. data/cpp/arduino/include/ioa5795.h +756 -0
  51. data/cpp/arduino/include/ioa5831.h +1949 -0
  52. data/cpp/arduino/include/ioa6285.h +740 -0
  53. data/cpp/arduino/include/ioa6286.h +740 -0
  54. data/cpp/arduino/include/ioa6289.h +847 -0
  55. data/cpp/arduino/include/ioa6612c.h +795 -0
  56. data/cpp/arduino/include/ioa6613c.h +795 -0
  57. data/cpp/arduino/include/ioa6614q.h +798 -0
  58. data/cpp/arduino/include/ioa6616c.h +865 -0
  59. data/cpp/arduino/include/ioa6617c.h +865 -0
  60. data/cpp/arduino/include/ioa664251.h +857 -0
  61. data/cpp/arduino/include/ioa8210.h +1843 -0
  62. data/cpp/arduino/include/ioa8510.h +1949 -0
  63. data/cpp/arduino/include/ioat94k.h +565 -0
  64. data/cpp/arduino/include/iocan128.h +100 -0
  65. data/cpp/arduino/include/iocan32.h +100 -0
  66. data/cpp/arduino/include/iocan64.h +100 -0
  67. data/cpp/arduino/include/iocanxx.h +2020 -0
  68. data/cpp/arduino/include/iom103.h +735 -0
  69. data/cpp/arduino/include/iom128.h +1299 -0
  70. data/cpp/arduino/include/iom1280.h +101 -0
  71. data/cpp/arduino/include/iom1281.h +101 -0
  72. data/cpp/arduino/include/iom1284.h +1099 -0
  73. data/cpp/arduino/include/iom1284p.h +1219 -0
  74. data/cpp/arduino/include/iom1284rfr2.h +2690 -0
  75. data/cpp/arduino/include/iom128a.h +1070 -0
  76. data/cpp/arduino/include/iom128rfa1.h +5385 -0
  77. data/cpp/arduino/include/iom128rfr2.h +2706 -0
  78. data/cpp/arduino/include/iom16.h +676 -0
  79. data/cpp/arduino/include/iom161.h +726 -0
  80. data/cpp/arduino/include/iom162.h +1022 -0
  81. data/cpp/arduino/include/iom163.h +686 -0
  82. data/cpp/arduino/include/iom164.h +101 -0
  83. data/cpp/arduino/include/iom164a.h +34 -0
  84. data/cpp/arduino/include/iom164p.h +34 -0
  85. data/cpp/arduino/include/iom164pa.h +1016 -0
  86. data/cpp/arduino/include/iom165.h +887 -0
  87. data/cpp/arduino/include/iom165a.h +832 -0
  88. data/cpp/arduino/include/iom165p.h +889 -0
  89. data/cpp/arduino/include/iom165pa.h +948 -0
  90. data/cpp/arduino/include/iom168.h +97 -0
  91. data/cpp/arduino/include/iom168a.h +35 -0
  92. data/cpp/arduino/include/iom168p.h +942 -0
  93. data/cpp/arduino/include/iom168pa.h +843 -0
  94. data/cpp/arduino/include/iom168pb.h +899 -0
  95. data/cpp/arduino/include/iom169.h +1174 -0
  96. data/cpp/arduino/include/iom169a.h +44 -0
  97. data/cpp/arduino/include/iom169p.h +1097 -0
  98. data/cpp/arduino/include/iom169pa.h +1485 -0
  99. data/cpp/arduino/include/iom16a.h +923 -0
  100. data/cpp/arduino/include/iom16hva.h +80 -0
  101. data/cpp/arduino/include/iom16hva2.h +883 -0
  102. data/cpp/arduino/include/iom16hvb.h +1052 -0
  103. data/cpp/arduino/include/iom16hvbrevb.h +1052 -0
  104. data/cpp/arduino/include/iom16m1.h +1571 -0
  105. data/cpp/arduino/include/iom16u2.h +1000 -0
  106. data/cpp/arduino/include/iom16u4.h +1423 -0
  107. data/cpp/arduino/include/iom2560.h +101 -0
  108. data/cpp/arduino/include/iom2561.h +101 -0
  109. data/cpp/arduino/include/iom2564rfr2.h +2691 -0
  110. data/cpp/arduino/include/iom256rfr2.h +2707 -0
  111. data/cpp/arduino/include/iom3000.h +237 -0
  112. data/cpp/arduino/include/iom32.h +755 -0
  113. data/cpp/arduino/include/iom323.h +744 -0
  114. data/cpp/arduino/include/iom324a.h +1014 -0
  115. data/cpp/arduino/include/iom324p.h +1016 -0
  116. data/cpp/arduino/include/iom324pa.h +1372 -0
  117. data/cpp/arduino/include/iom325.h +886 -0
  118. data/cpp/arduino/include/iom3250.h +982 -0
  119. data/cpp/arduino/include/iom3250a.h +34 -0
  120. data/cpp/arduino/include/iom3250p.h +34 -0
  121. data/cpp/arduino/include/iom3250pa.h +1042 -0
  122. data/cpp/arduino/include/iom325a.h +34 -0
  123. data/cpp/arduino/include/iom325p.h +34 -0
  124. data/cpp/arduino/include/iom325pa.h +937 -0
  125. data/cpp/arduino/include/iom328.h +34 -0
  126. data/cpp/arduino/include/iom328p.h +948 -0
  127. data/cpp/arduino/include/iom329.h +1069 -0
  128. data/cpp/arduino/include/iom3290.h +1227 -0
  129. data/cpp/arduino/include/iom3290a.h +34 -0
  130. data/cpp/arduino/include/iom3290pa.h +1123 -0
  131. data/cpp/arduino/include/iom329a.h +34 -0
  132. data/cpp/arduino/include/iom329p.h +1164 -0
  133. data/cpp/arduino/include/iom329pa.h +34 -0
  134. data/cpp/arduino/include/iom32a.h +686 -0
  135. data/cpp/arduino/include/iom32c1.h +1320 -0
  136. data/cpp/arduino/include/iom32hvb.h +1052 -0
  137. data/cpp/arduino/include/iom32hvbrevb.h +953 -0
  138. data/cpp/arduino/include/iom32m1.h +1625 -0
  139. data/cpp/arduino/include/iom32u2.h +1000 -0
  140. data/cpp/arduino/include/iom32u4.h +1512 -0
  141. data/cpp/arduino/include/iom32u6.h +1431 -0
  142. data/cpp/arduino/include/iom406.h +783 -0
  143. data/cpp/arduino/include/iom48.h +93 -0
  144. data/cpp/arduino/include/iom48a.h +35 -0
  145. data/cpp/arduino/include/iom48p.h +936 -0
  146. data/cpp/arduino/include/iom48pa.h +839 -0
  147. data/cpp/arduino/include/iom48pb.h +890 -0
  148. data/cpp/arduino/include/iom64.h +1311 -0
  149. data/cpp/arduino/include/iom640.h +101 -0
  150. data/cpp/arduino/include/iom644.h +101 -0
  151. data/cpp/arduino/include/iom644a.h +34 -0
  152. data/cpp/arduino/include/iom644p.h +101 -0
  153. data/cpp/arduino/include/iom644pa.h +1387 -0
  154. data/cpp/arduino/include/iom644rfr2.h +2685 -0
  155. data/cpp/arduino/include/iom645.h +881 -0
  156. data/cpp/arduino/include/iom6450.h +978 -0
  157. data/cpp/arduino/include/iom6450a.h +34 -0
  158. data/cpp/arduino/include/iom6450p.h +34 -0
  159. data/cpp/arduino/include/iom645a.h +34 -0
  160. data/cpp/arduino/include/iom645p.h +34 -0
  161. data/cpp/arduino/include/iom649.h +1061 -0
  162. data/cpp/arduino/include/iom6490.h +1182 -0
  163. data/cpp/arduino/include/iom6490a.h +34 -0
  164. data/cpp/arduino/include/iom6490p.h +34 -0
  165. data/cpp/arduino/include/iom649a.h +34 -0
  166. data/cpp/arduino/include/iom649p.h +1490 -0
  167. data/cpp/arduino/include/iom64a.h +1084 -0
  168. data/cpp/arduino/include/iom64c1.h +1321 -0
  169. data/cpp/arduino/include/iom64hve.h +1034 -0
  170. data/cpp/arduino/include/iom64hve2.h +767 -0
  171. data/cpp/arduino/include/iom64m1.h +1572 -0
  172. data/cpp/arduino/include/iom64rfr2.h +2701 -0
  173. data/cpp/arduino/include/iom8.h +665 -0
  174. data/cpp/arduino/include/iom8515.h +687 -0
  175. data/cpp/arduino/include/iom8535.h +772 -0
  176. data/cpp/arduino/include/iom88.h +97 -0
  177. data/cpp/arduino/include/iom88a.h +35 -0
  178. data/cpp/arduino/include/iom88p.h +941 -0
  179. data/cpp/arduino/include/iom88pa.h +1185 -0
  180. data/cpp/arduino/include/iom88pb.h +899 -0
  181. data/cpp/arduino/include/iom8a.h +621 -0
  182. data/cpp/arduino/include/iom8hva.h +76 -0
  183. data/cpp/arduino/include/iom8u2.h +997 -0
  184. data/cpp/arduino/include/iomx8.h +808 -0
  185. data/cpp/arduino/include/iomxx0_1.h +1692 -0
  186. data/cpp/arduino/include/iomxx4.h +954 -0
  187. data/cpp/arduino/include/iomxxhva.h +550 -0
  188. data/cpp/arduino/include/iotn10.h +512 -0
  189. data/cpp/arduino/include/iotn11.h +255 -0
  190. data/cpp/arduino/include/iotn12.h +288 -0
  191. data/cpp/arduino/include/iotn13.h +395 -0
  192. data/cpp/arduino/include/iotn13a.h +394 -0
  193. data/cpp/arduino/include/iotn15.h +363 -0
  194. data/cpp/arduino/include/iotn1634.h +914 -0
  195. data/cpp/arduino/include/iotn167.h +883 -0
  196. data/cpp/arduino/include/iotn20.h +776 -0
  197. data/cpp/arduino/include/iotn22.h +221 -0
  198. data/cpp/arduino/include/iotn2313.h +702 -0
  199. data/cpp/arduino/include/iotn2313a.h +812 -0
  200. data/cpp/arduino/include/iotn24.h +94 -0
  201. data/cpp/arduino/include/iotn24a.h +846 -0
  202. data/cpp/arduino/include/iotn25.h +93 -0
  203. data/cpp/arduino/include/iotn26.h +422 -0
  204. data/cpp/arduino/include/iotn261.h +93 -0
  205. data/cpp/arduino/include/iotn261a.h +987 -0
  206. data/cpp/arduino/include/iotn28.h +297 -0
  207. data/cpp/arduino/include/iotn4.h +477 -0
  208. data/cpp/arduino/include/iotn40.h +767 -0
  209. data/cpp/arduino/include/iotn4313.h +813 -0
  210. data/cpp/arduino/include/iotn43u.h +604 -0
  211. data/cpp/arduino/include/iotn44.h +94 -0
  212. data/cpp/arduino/include/iotn441.h +903 -0
  213. data/cpp/arduino/include/iotn44a.h +844 -0
  214. data/cpp/arduino/include/iotn45.h +93 -0
  215. data/cpp/arduino/include/iotn461.h +94 -0
  216. data/cpp/arduino/include/iotn461a.h +987 -0
  217. data/cpp/arduino/include/iotn48.h +806 -0
  218. data/cpp/arduino/include/iotn5.h +512 -0
  219. data/cpp/arduino/include/iotn828.h +911 -0
  220. data/cpp/arduino/include/iotn84.h +94 -0
  221. data/cpp/arduino/include/iotn841.h +903 -0
  222. data/cpp/arduino/include/iotn84a.h +844 -0
  223. data/cpp/arduino/include/iotn85.h +93 -0
  224. data/cpp/arduino/include/iotn861.h +94 -0
  225. data/cpp/arduino/include/iotn861a.h +988 -0
  226. data/cpp/arduino/include/iotn87.h +859 -0
  227. data/cpp/arduino/include/iotn88.h +806 -0
  228. data/cpp/arduino/include/iotn9.h +477 -0
  229. data/cpp/arduino/include/iotnx4.h +482 -0
  230. data/cpp/arduino/include/iotnx5.h +442 -0
  231. data/cpp/arduino/include/iotnx61.h +541 -0
  232. data/cpp/arduino/include/iousb1286.h +101 -0
  233. data/cpp/arduino/include/iousb1287.h +101 -0
  234. data/cpp/arduino/include/iousb162.h +101 -0
  235. data/cpp/arduino/include/iousb646.h +102 -0
  236. data/cpp/arduino/include/iousb647.h +102 -0
  237. data/cpp/arduino/include/iousb82.h +95 -0
  238. data/cpp/arduino/include/iousbxx2.h +807 -0
  239. data/cpp/arduino/include/iousbxx6_7.h +1336 -0
  240. data/cpp/arduino/include/iox128a1.h +7236 -0
  241. data/cpp/arduino/include/iox128a1u.h +8305 -0
  242. data/cpp/arduino/include/iox128a3.h +6987 -0
  243. data/cpp/arduino/include/iox128a3u.h +7697 -0
  244. data/cpp/arduino/include/iox128a4u.h +7309 -0
  245. data/cpp/arduino/include/iox128b1.h +6872 -0
  246. data/cpp/arduino/include/iox128b3.h +6288 -0
  247. data/cpp/arduino/include/iox128c3.h +6264 -0
  248. data/cpp/arduino/include/iox128d3.h +5749 -0
  249. data/cpp/arduino/include/iox128d4.h +5562 -0
  250. data/cpp/arduino/include/iox16a4.h +6748 -0
  251. data/cpp/arduino/include/iox16a4u.h +7309 -0
  252. data/cpp/arduino/include/iox16c4.h +6078 -0
  253. data/cpp/arduino/include/iox16d4.h +5717 -0
  254. data/cpp/arduino/include/iox16e5.h +7699 -0
  255. data/cpp/arduino/include/iox192a3.h +6987 -0
  256. data/cpp/arduino/include/iox192a3u.h +7697 -0
  257. data/cpp/arduino/include/iox192c3.h +6264 -0
  258. data/cpp/arduino/include/iox192d3.h +5749 -0
  259. data/cpp/arduino/include/iox256a3.h +6987 -0
  260. data/cpp/arduino/include/iox256a3b.h +6983 -0
  261. data/cpp/arduino/include/iox256a3bu.h +7706 -0
  262. data/cpp/arduino/include/iox256a3u.h +7697 -0
  263. data/cpp/arduino/include/iox256c3.h +6264 -0
  264. data/cpp/arduino/include/iox256d3.h +5709 -0
  265. data/cpp/arduino/include/iox32a4.h +6747 -0
  266. data/cpp/arduino/include/iox32a4u.h +7309 -0
  267. data/cpp/arduino/include/iox32c3.h +6264 -0
  268. data/cpp/arduino/include/iox32c4.h +6078 -0
  269. data/cpp/arduino/include/iox32d3.h +5105 -0
  270. data/cpp/arduino/include/iox32d4.h +5685 -0
  271. data/cpp/arduino/include/iox32e5.h +7699 -0
  272. data/cpp/arduino/include/iox384c3.h +6849 -0
  273. data/cpp/arduino/include/iox384d3.h +5833 -0
  274. data/cpp/arduino/include/iox64a1.h +7236 -0
  275. data/cpp/arduino/include/iox64a1u.h +8305 -0
  276. data/cpp/arduino/include/iox64a3.h +6987 -0
  277. data/cpp/arduino/include/iox64a3u.h +7697 -0
  278. data/cpp/arduino/include/iox64a4u.h +7309 -0
  279. data/cpp/arduino/include/iox64b1.h +6454 -0
  280. data/cpp/arduino/include/iox64b3.h +6288 -0
  281. data/cpp/arduino/include/iox64c3.h +6264 -0
  282. data/cpp/arduino/include/iox64d3.h +5764 -0
  283. data/cpp/arduino/include/iox64d4.h +5555 -0
  284. data/cpp/arduino/include/iox8e5.h +7699 -0
  285. data/cpp/arduino/include/lock.h +239 -0
  286. data/cpp/arduino/include/portpins.h +549 -0
  287. data/cpp/arduino/include/version.h +90 -0
  288. data/cpp/arduino/include/xmega.h +71 -0
  289. data/cpp/unittest/Assertion.h +9 -4
  290. data/cpp/unittest/Compare.h +93 -0
  291. data/lib/arduino_ci/arduino_installation.rb +1 -1
  292. data/lib/arduino_ci/cpp_library.rb +4 -1
  293. data/lib/arduino_ci/version.rb +1 -1
  294. data/misc/default.yaml +7 -0
  295. metadata +285 -2
@@ -0,0 +1,1225 @@
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+ /* Copyright (c) 2007, Atmel Corporation
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+ All rights reserved.
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+
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+ Redistribution and use in source and binary forms, with or without
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+ modification, are permitted provided that the following conditions are met:
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+
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+ * Redistributions of source code must retain the above copyright
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+ notice, this list of conditions and the following disclaimer.
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+
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+ * Redistributions in binary form must reproduce the above copyright
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+ notice, this list of conditions and the following disclaimer in
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+ the documentation and/or other materials provided with the
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+ distribution.
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+
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+ * Neither the name of the copyright holders nor the names of
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+ contributors may be used to endorse or promote products derived
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+ from this software without specific prior written permission.
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+
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+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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+ POSSIBILITY OF SUCH DAMAGE. */
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+
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+ /* $Id: io90pwm216.h 2225 2011-03-02 16:27:26Z arcanum $ */
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+
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+ /* avr/io90pwm216.h - definitions for AT90PWM216 */
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+
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+ #ifndef _AVR_IO90PWM216_H_
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+ #define _AVR_IO90PWM216_H_ 1
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+
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+ /* This file should only be included from <avr/io.h>, never directly. */
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+
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+ #ifndef _AVR_IO_H_
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+ # error "Include <avr/io.h> instead of this file."
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+ #endif
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+
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+ #ifndef _AVR_IOXXX_H_
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+ # define _AVR_IOXXX_H_ "io90pwm216.h"
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+ #else
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+ # error "Attempt to include more than one <avr/ioXXX.h> file."
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+ #endif
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+
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+ /* I/O registers */
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+
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+ /* Port B Input Pins Address */
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+ #define PINB _SFR_IO8(0x03)
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+ #define PINB0 0
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+ #define PINB1 1
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+ #define PINB2 2
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+ #define PINB3 3
58
+ #define PINB4 4
59
+ #define PINB5 5
60
+ #define PINB6 6
61
+ #define PINB7 7
62
+
63
+ /* Port B Data Direction Register */
64
+ #define DDRB _SFR_IO8(0x04)
65
+ #define DDB0 0
66
+ #define DDB1 1
67
+ #define DDB2 2
68
+ #define DDB3 3
69
+ #define DDB4 4
70
+ #define DDB5 5
71
+ #define DDB6 6
72
+ #define DDB7 7
73
+
74
+ /* Port B Data Register */
75
+ #define PORTB _SFR_IO8(0x05)
76
+ #define PB0 0
77
+ #define PB1 1
78
+ #define PB2 2
79
+ #define PB3 3
80
+ #define PB4 4
81
+ #define PB5 5
82
+ #define PB6 6
83
+ #define PB7 7
84
+
85
+ /* Port C Input Pins Address */
86
+ #define PINC _SFR_IO8(0x06)
87
+ #define PINC0 0
88
+ #define PINC1 1
89
+ #define PINC2 2
90
+ #define PINC3 3
91
+ #define PINC4 4
92
+ #define PINC5 5
93
+ #define PINC6 6
94
+ #define PINC7 7
95
+
96
+ /* Port C Data Direction Register */
97
+ #define DDRC _SFR_IO8(0x07)
98
+ #define DDC0 0
99
+ #define DDC1 1
100
+ #define DDC2 2
101
+ #define DDC3 3
102
+ #define DDC4 4
103
+ #define DDC5 5
104
+ #define DDC6 6
105
+ #define DDC7 7
106
+
107
+ /* Port C Data Register */
108
+ #define PORTC _SFR_IO8(0x08)
109
+ #define PC0 0
110
+ #define PC1 1
111
+ #define PC2 2
112
+ #define PC3 3
113
+ #define PC4 4
114
+ #define PC5 5
115
+ #define PC6 6
116
+ #define PC7 7
117
+
118
+ /* Port D Input Pins Address */
119
+ #define PIND _SFR_IO8(0x09)
120
+ #define PIND0 0
121
+ #define PIND1 1
122
+ #define PIND2 2
123
+ #define PIND3 3
124
+ #define PIND4 4
125
+ #define PIND5 5
126
+ #define PIND6 6
127
+ #define PIND7 7
128
+
129
+ /* Port D Data Direction Register */
130
+ #define DDRD _SFR_IO8(0x0A)
131
+ #define DDD0 0
132
+ #define DDD1 1
133
+ #define DDD2 2
134
+ #define DDD3 3
135
+ #define DDD4 4
136
+ #define DDD5 5
137
+ #define DDD6 6
138
+ #define DDD7 7
139
+
140
+ /* Port D Data Register */
141
+ #define PORTD _SFR_IO8(0x0B)
142
+ #define PD0 0
143
+ #define PD1 1
144
+ #define PD2 2
145
+ #define PD3 3
146
+ #define PD4 4
147
+ #define PD5 5
148
+ #define PD6 6
149
+ #define PD7 7
150
+
151
+ /* Port E Input Pins Address */
152
+ #define PINE _SFR_IO8(0x0C)
153
+ #define PINE0 0
154
+ #define PINE1 1
155
+ #define PINE2 2
156
+
157
+ /* Port E Data Direction Register */
158
+ #define DDRE _SFR_IO8(0x0D)
159
+ #define DDE0 0
160
+ #define DDE1 1
161
+ #define DDE2 2
162
+
163
+ /* Port E Data Register */
164
+ #define PORTE _SFR_IO8(0x0E)
165
+ #define PE0 0
166
+ #define PE1 1
167
+ #define PE2 2
168
+
169
+ /* Timer/Counter 0 Interrupt Flag Register */
170
+ #define TIFR0 _SFR_IO8(0x15)
171
+ #define TOV0 0 /* Overflow Flag */
172
+ #define OCF0A 1 /* Output Compare Flag 0A */
173
+ #define OCF0B 2 /* Output Compare Flag 0B */
174
+
175
+ /* Timer/Counter1 Interrupt Flag Register */
176
+ #define TIFR1 _SFR_IO8(0x16)
177
+ #define TOV1 0 /* Overflow Flag */
178
+ #define OCF1A 1 /* Output Compare Flag 1A*/
179
+ #define OCF1B 2 /* Output Compare Flag 1B*/
180
+ #define ICF1 5 /* Input Capture Flag 1 */
181
+
182
+ /* General Purpose I/O Register 1 */
183
+ #define GPIOR1 _SFR_IO8(0x19)
184
+ #define GPIOR10 0
185
+ #define GPIOR11 1
186
+ #define GPIOR12 2
187
+ #define GPIOR13 3
188
+ #define GPIOR14 4
189
+ #define GPIOR15 5
190
+ #define GPIOR16 6
191
+ #define GPIOR17 7
192
+
193
+ /* General Purpose I/O Register 2 */
194
+ #define GPIOR2 _SFR_IO8(0x1A)
195
+ #define GPIOR20 0
196
+ #define GPIOR21 1
197
+ #define GPIOR22 2
198
+ #define GPIOR23 3
199
+ #define GPIOR24 4
200
+ #define GPIOR25 5
201
+ #define GPIOR26 6
202
+ #define GPIOR27 7
203
+
204
+ /* General Purpose I/O Register 3 */
205
+ #define GPIOR3 _SFR_IO8(0x1B)
206
+ #define GPIOR30 0
207
+ #define GPIOR31 1
208
+ #define GPIOR32 2
209
+ #define GPIOR33 3
210
+ #define GPIOR34 4
211
+ #define GPIOR35 5
212
+ #define GPIOR36 6
213
+ #define GPIOR37 7
214
+
215
+ /* External Interrupt Flag Register */
216
+ #define EIFR _SFR_IO8(0x1C)
217
+ #define INTF0 0
218
+ #define INTF1 1
219
+ #define INTF2 2
220
+ #define INTF3 3
221
+
222
+ /* External Interrupt Mask Register */
223
+ #define EIMSK _SFR_IO8(0x1D)
224
+ #define INT0 0 /* External Interrupt Request 0 Enable */
225
+ #define INT1 1 /* External Interrupt Request 1 Enable */
226
+ #define INT2 2 /* External Interrupt Request 2 Enable */
227
+ #define INT3 3 /* External Interrupt Request 3 Enable */
228
+
229
+ /* General Purpose I/O Register 0 */
230
+ #define GPIOR0 _SFR_IO8(0x1E)
231
+ #define GPIOR00 0
232
+ #define GPIOR01 1
233
+ #define GPIOR02 2
234
+ #define GPIOR03 3
235
+ #define GPIOR04 4
236
+ #define GPIOR05 5
237
+ #define GPIOR06 6
238
+ #define GPIOR07 7
239
+
240
+ /* EEPROM Control Register */
241
+ #define EECR _SFR_IO8(0x1F)
242
+ #define EERE 0 /* EEPROM Read Enable */
243
+ #define EEWE 1 /* EEPROM Write Enable */
244
+ #define EEMWE 2 /* EEPROM Master Write Enable */
245
+ #define EERIE 3 /* EEPROM Ready Interrupt Enable */
246
+
247
+ /* EEPROM Data Register */
248
+ #define EEDR _SFR_IO8(0x20)
249
+ #define EEDR0 0
250
+ #define EEDR1 1
251
+ #define EEDR2 2
252
+ #define EEDR3 3
253
+ #define EEDR4 4
254
+ #define EEDR5 5
255
+ #define EEDR6 6
256
+ #define EEDR7 7
257
+
258
+ /* The EEPROM Address Registers */
259
+ #define EEAR _SFR_IO16(0x21)
260
+ #define EEARL _SFR_IO8(0x21)
261
+ #define EEAR0 0
262
+ #define EEAR1 1
263
+ #define EEAR2 2
264
+ #define EEAR3 3
265
+ #define EEAR4 4
266
+ #define EEAR5 5
267
+ #define EEAR6 6
268
+ #define EEAR7 7
269
+ #define EEARH _SFR_IO8(0x22)
270
+ #define EEAR8 0
271
+ #define EEAR9 1
272
+ #define EEAR10 2
273
+ #define EEAR11 3
274
+
275
+ /* 6-char sequence denoting where to find the EEPROM registers in memory space.
276
+ Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
277
+ subroutines.
278
+ First two letters: EECR address.
279
+ Second two letters: EEDR address.
280
+ Last two letters: EEAR address. */
281
+ #define __EEPROM_REG_LOCATIONS__ 1F2021
282
+
283
+ /* General Timer/Counter Control Register */
284
+ #define GTCCR _SFR_IO8(0x23)
285
+ #define PSR10 0 /* Prescaler Reset Timer/Counter1 and Timer/Counter0 */
286
+ #define ICPSEL1 6 /* Timer1 Input Capture Selection Bit */
287
+ #define TSM 7 /* Timer/Counter Synchronization Mode */
288
+
289
+ /* Timer/Counter Control Register A */
290
+ #define TCCR0A _SFR_IO8(0x24)
291
+ #define WGM00 0 /* Waveform Generation Mode */
292
+ #define WGM01 1 /* Waveform Generation Mode */
293
+ #define COM0B0 4 /* Compare Output Mode, Fast PWm */
294
+ #define COM0B1 5 /* Compare Output Mode, Fast PWm */
295
+ #define COM0A0 6 /* Compare Output Mode, Phase Correct PWM Mode */
296
+ #define COM0A1 7 /* Compare Output Mode, Phase Correct PWM Mode */
297
+
298
+ /* Timer/Counter Control Register B */
299
+ #define TCCR0B _SFR_IO8(0x25)
300
+ #define CS00 0 /* Clock Select */
301
+ #define CS01 1 /* Clock Select */
302
+ #define CS02 2 /* Clock Select */
303
+ #define WGM02 3 /* Waveform Generation Mode */
304
+ #define FOC0B 6 /* Force Output Compare B */
305
+ #define FOC0A 7 /* Force Output Compare A */
306
+
307
+ /* Timer/Counter0 Register */
308
+ #define TCNT0 _SFR_IO8(0x26)
309
+ #define TCNT00 0
310
+ #define TCNT01 1
311
+ #define TCNT02 2
312
+ #define TCNT03 3
313
+ #define TCNT04 4
314
+ #define TCNT05 5
315
+ #define TCNT06 6
316
+ #define TCNT07 7
317
+
318
+ /* Timer/Counter0 Output Compare Register A */
319
+ #define OCR0A _SFR_IO8(0x27)
320
+ #define OCR0A0 0
321
+ #define OCR0A1 1
322
+ #define OCR0A2 2
323
+ #define OCR0A3 3
324
+ #define OCR0A4 4
325
+ #define OCR0A5 5
326
+ #define OCR0A6 6
327
+ #define OCR0A7 7
328
+
329
+ /* Timer/Counter0 Output Compare Register B */
330
+ #define OCR0B _SFR_IO8(0x28)
331
+ #define OCR0B0 0
332
+ #define OCR0B1 1
333
+ #define OCR0B2 2
334
+ #define OCR0B3 3
335
+ #define OCR0B4 4
336
+ #define OCR0B5 5
337
+ #define OCR0B6 6
338
+ #define OCR0B7 7
339
+
340
+ /* PLL Control and Status Register */
341
+ #define PLLCSR _SFR_IO8(0x29)
342
+ #define PLOCK 0 /* PLL Lock Detector */
343
+ #define PLLE 1 /* PLL Enable */
344
+ #define PLLF 2 /* PLL Factor */
345
+
346
+ /* SPI Control Register */
347
+ #define SPCR _SFR_IO8(0x2C)
348
+ #define SPR0 0 /* SPI Clock Rate Select 0 */
349
+ #define SPR1 1 /* SPI Clock Rate Select 1 */
350
+ #define CPHA 2 /* Clock Phase */
351
+ #define CPOL 3 /* Clock polarity */
352
+ #define MSTR 4 /* Master/Slave Select */
353
+ #define DORD 5 /* Data Order */
354
+ #define SPE 6 /* SPI Enable */
355
+ #define SPIE 7 /* SPI Interrupt Enable */
356
+
357
+ /* SPI Status Register */
358
+ #define SPSR _SFR_IO8(0x2D)
359
+ #define SPI2X 0 /* Double SPI Speed Bit */
360
+ #define WCOL 6 /* Write Collision Flag */
361
+ #define SPIF 7 /* SPI Interrupt Flag */
362
+
363
+ /* SPI Data Register */
364
+ #define SPDR _SFR_IO8(0x2E)
365
+ #define SPD0 0
366
+ #define SPD1 1
367
+ #define SPD2 2
368
+ #define SPD3 3
369
+ #define SPD4 4
370
+ #define SPD5 5
371
+ #define SPD6 6
372
+ #define SPD7 7
373
+
374
+ /* Analog Comparator Status Register */
375
+ #define ACSR _SFR_IO8(0x30)
376
+ #define AC0O 0 /* Analog Comparator 0 Output Bit */
377
+ #define AC1O 1 /* Analog Comparator 1 Output Bit */
378
+ #define AC2O 2 /* Analog Comparator 2 Output Bit */
379
+ #define AC0IF 4 /* Analog Comparator 0 Interrupt Flag Bit */
380
+ #define AC1IF 5 /* Analog Comparator 1 Interrupt Flag Bit */
381
+ #define AC2IF 6 /* Analog Comparator 2 Interrupt Flag Bit */
382
+ #define ACCKDIV 7 /* Analog Comparator Clock Divider */
383
+
384
+ /* Sleep Mode Control Register */
385
+ #define SMCR _SFR_IO8(0x33)
386
+ #define SE 0 /* Sleep Enable */
387
+ #define SM0 1 /* Sleep Mode Select bit0 */
388
+ #define SM1 2 /* Sleep Mode Select bit1 */
389
+ #define SM2 3 /* Sleep Mode Select bit2 */
390
+
391
+ /* MCU Status Register */
392
+ #define MCUSR _SFR_IO8(0x34)
393
+ #define PORF 0 /* Power-on reset flag */
394
+ #define EXTRF 1 /* External Reset Flag */
395
+ #define BORF 2 /* Brown-out Reset Flag */
396
+ #define WDRF 3 /* Watchdog Reset Flag */
397
+
398
+ /* MCU Control Register */
399
+ #define MCUCR _SFR_IO8(0x35)
400
+ #define IVCE 0 /* Interrupt Vector Change Enable */
401
+ #define IVSEL 1 /* Interrupt Vector Select */
402
+ #define PUD 4 /* Pull-up disable */
403
+ #define SPIPS 7 /* SPI Pin Select */
404
+
405
+ /* Store Program Memory Control Register */
406
+ #define SPMCSR _SFR_IO8(0x37)
407
+ #define SPMEN 0 /* Store Program Memory Enable */
408
+ #define PGERS 1 /* Page Erase */
409
+ #define PGWRT 2 /* Page Write */
410
+ #define BLBSET 3 /* Boot Lock Bit Set */
411
+ #define RWWSRE 4 /* Read While Write section read enable */
412
+ #define RWWSB 6 /* Read While Write Section Busy */
413
+ #define SPMIE 7 /* SPM Interrupt Enable */
414
+
415
+ /* Watchdog Timer Control Register */
416
+ #define WDTCSR _SFR_MEM8(0x60)
417
+ #define WDP0 0 /* Watchdog Timer Prescaler bit0 */
418
+ #define WDP1 1 /* Watchdog Timer Prescaler bit1 */
419
+ #define WDP2 2 /* Watchdog Timer Prescaler bit2 */
420
+ #define WDE 3 /* Watchdog Enable */
421
+ #define WDCE 4 /* Watchdog Change Enable */
422
+ #define WDP3 5 /* Watchdog Timer Prescaler bit3 */
423
+ #define WDIE 6 /* Watchdog Timeout Interrupt Enable */
424
+ #define WDIF 7 /* Watchdog Timeout Interrupt Flag */
425
+
426
+ /* Clock Prescaler Register */
427
+ #define CLKPR _SFR_MEM8(0x61)
428
+ #define CLKPS0 0 /* Clock Prescaler Select bit0 */
429
+ #define CLKPS1 1 /* Clock Prescaler Select bit1 */
430
+ #define CLKPS2 2 /* Clock Prescaler Select bit2 */
431
+ #define CLKPS3 3 /* Clock Prescaler Select bit3 */
432
+ #define CLKPCE 7 /* Clock Prescaler Change Enable */
433
+
434
+ /* Power Reduction Register */
435
+ #define PRR _SFR_MEM8(0x64)
436
+ #define PRADC 0 /* Power Reduction ADC */
437
+ #define PRUSART0 1 /* Power Reduction USART0 */
438
+ #define PRUSART PRUSART0 /* Define to maintain backward-compatibility */
439
+ #define PRSPI 2 /* Power Reduction Serial Peripheral Interface */
440
+ #define PRTIM0 3 /* Power Reduction Timer/Counter0 */
441
+ #define PRTIM1 4 /* Power Reduction Timer/Counter1 */
442
+ #define PRPSC0 5 /* Power Reduction PSC0 */
443
+ #define PRPSC1 6 /* Power Reduction PSC1 */
444
+ #define PRPSC2 7 /* Power Reduction PSC2 */
445
+
446
+ #define __AVR_HAVE_PRR ((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRPSC0)|(1<<PRPSC1)|(1<<PRPSC2))
447
+ #define __AVR_HAVE_PRR_PRADC
448
+ #define __AVR_HAVE_PRR_PRUSART0
449
+ #define __AVR_HAVE_PRR_PRSPI
450
+ #define __AVR_HAVE_PRR_PRTIM0
451
+ #define __AVR_HAVE_PRR_PRTIM1
452
+ #define __AVR_HAVE_PRR_PRPSC0
453
+ #define __AVR_HAVE_PRR_PRPSC1
454
+ #define __AVR_HAVE_PRR_PRPSC2
455
+
456
+ /* Oscillator Calibration Value */
457
+ #define OSCCAL _SFR_MEM8(0x66)
458
+ #define CAL0 0
459
+ #define CAL1 1
460
+ #define CAL2 2
461
+ #define CAL3 3
462
+ #define CAL4 4
463
+ #define CAL5 5
464
+ #define CAL6 6
465
+
466
+ /* External Interrupt Control Register A */
467
+ #define EICRA _SFR_MEM8(0x69)
468
+ #define ISC00 0
469
+ #define ISC01 1
470
+ #define ISC10 2
471
+ #define ISC11 3
472
+ #define ISC20 4
473
+ #define ISC21 5
474
+ #define ISC30 6
475
+ #define ISC31 7
476
+
477
+ /* Timer/Counter0 Interrupt Mask Register */
478
+ #define TIMSK0 _SFR_MEM8(0x6E)
479
+ #define TOIE0 0 /* Overflow Interrupt Enable */
480
+ #define OCIE0A 1 /* Output Compare Match A Interrupt Enable */
481
+ #define OCIE0B 2 /* Output Compare Match B Interrupt Enable */
482
+
483
+ /* Timer/Counter1 Interrupt Mask Register */
484
+ #define TIMSK1 _SFR_MEM8(0x6F)
485
+ #define TOIE1 0 /* Overflow Interrupt Enable */
486
+ #define OCIE1A 1 /* Output Compare Match A Interrupt Enable */
487
+ #define OCIE1B 2 /* Output Compare Match B Interrupt Enable */
488
+ #define ICIE1 5 /* Input Capture Interrupt Enable */
489
+
490
+ /* Amplifier 0 Control and Status register */
491
+ #define AMP0CSR _SFR_MEM8(0x76)
492
+ #define AMP0TS0 0
493
+ #define AMP0TS1 1
494
+ #define AMP0G0 4
495
+ #define AMP0G1 5
496
+ #define AMP0IS 6
497
+ #define AMP0EN 7
498
+
499
+ /* Amplifier 1 Control and Status register */
500
+ #define AMP1CSR _SFR_MEM8(0x77)
501
+ #define AMP1TS0 0
502
+ #define AMP1TS1 1
503
+ #define AMP1G0 4
504
+ #define AMP1G1 5
505
+ #define AMP1IS 6
506
+ #define AMP1EN 7
507
+
508
+ /* ADC Result Data Register */
509
+ #ifndef __ASSEMBLER__
510
+ #define ADC _SFR_MEM16(0x78)
511
+ #endif
512
+ #define ADCW _SFR_MEM16(0x78)
513
+ #define ADCL _SFR_MEM8(0x78)
514
+ #define ADCH _SFR_MEM8(0x79)
515
+
516
+ /* ADC Control and Status Register A */
517
+ #define ADCSRA _SFR_MEM8(0x7A)
518
+ #define ADPS0 0 /* ADC Prescaler Select bit0 */
519
+ #define ADPS1 1 /* ADC Prescaler Select bit1 */
520
+ #define ADPS2 2 /* ADC Prescaler Select bit2 */
521
+ #define ADIE 3 /* ADC Interrupt Enable */
522
+ #define ADIF 4 /* ADC Interrupt Flag */
523
+ #define ADATE 5 /* ADC Auto Trigger Enable */
524
+ #define ADSC 6 /* ADC Start Conversion */
525
+ #define ADEN 7 /* ADC Enable */
526
+
527
+ /* ADC Control and Status Register B */
528
+ #define ADCSRB _SFR_MEM8(0x7B)
529
+ #define ADTS0 0 /* ADC Auto Trigger Source 0 */
530
+ #define ADTS1 1 /* ADC Auto Trigger Source 1 */
531
+ #define ADTS2 2 /* ADC Auto Trigger Source 2 */
532
+ #define ADTS3 3 /* ADC Auto Trigger Source 3 */
533
+ #define ADHSM 7 /* ADC High Speed Mode */
534
+
535
+ /* ADC multiplexer Selection Register */
536
+ #define ADMUX _SFR_MEM8(0x7C)
537
+ #define MUX0 0 /* Analog Channel and Gain Selection bit0 */
538
+ #define MUX1 1 /* Analog Channel and Gain Selection bit1 */
539
+ #define MUX2 2 /* Analog Channel and Gain Selection bit2 */
540
+ #define MUX3 3 /* Analog Channel and Gain Selection bit3 */
541
+ #define ADLAR 5 /* Left Adjust Result */
542
+ #define REFS0 6 /* Reference Selection bit0 */
543
+ #define REFS1 7 /* Reference Selection bit1 */
544
+
545
+ /* Digital Input Disable Register 0 */
546
+ #define DIDR0 _SFR_MEM8(0x7E)
547
+ #define ADC0D 0 /* ADC0 Digital input Disable */
548
+ #define ADC1D 1 /* ADC1 Digital input Disable */
549
+ #define ADC2D 2 /* ADC2 Digital input Disable */
550
+ #define ADC3D 3 /* ADC3 Digital input Disable */
551
+ #define ADC4D 4 /* ADC4 Digital input Disable */
552
+ #define ADC5D 5 /* ADC5 Digital input Disable */
553
+ #define ADC6D 6 /* ADC6 Digital input Disable */
554
+ #define ADC7D 7 /* ADC7 Digital input Disable */
555
+
556
+ /* Digital Input Disable Register 1 */
557
+ #define DIDR1 _SFR_MEM8(0x7F)
558
+ #define ADC8D 0 /* ADC8 Digital input Disable */
559
+ #define ADC9D 1 /* ADC9 Digital input Disable */
560
+ #define ADC10D 2 /* ADC10 Digital input Disable */
561
+ #define AMP0ND 3
562
+ #define AMP0PD 4
563
+ #define ACMP0D 5
564
+
565
+ /* Timer/Counter1 Control Register A */
566
+ #define TCCR1A _SFR_MEM8(0x80)
567
+ #define WGM10 0 /* Waveform Generation Mode */
568
+ #define WGM11 1 /* Waveform Generation Mode */
569
+ #define COM1B0 4 /* Compare Output Mode 1B, bit 0 */
570
+ #define COM1B1 5 /* Compare Output Mode 1B, bit 1 */
571
+ #define COM1A0 6 /* Comparet Ouput Mode 1A, bit 0 */
572
+ #define COM1A1 7 /* Comparet Ouput Mode 1A, bit 1 */
573
+
574
+ /* Timer/Counter1 Control Register B */
575
+ #define TCCR1B _SFR_MEM8(0x81)
576
+ #define CS10 0 /* Prescaler source of Timer/Counter 1 */
577
+ #define CS11 1 /* Prescaler source of Timer/Counter 1 */
578
+ #define CS12 2 /* Prescaler source of Timer/Counter 1 */
579
+ #define WGM12 3 /* Waveform Generation Mode */
580
+ #define WGM13 4 /* Waveform Generation Mode */
581
+ #define ICES1 6 /* Input Capture 1 Edge Select */
582
+ #define ICNC1 7 /* Input Capture 1 Noise Canceler */
583
+
584
+ /* Timer/Counter1 Control Register C */
585
+ #define TCCR1C _SFR_MEM8(0x82)
586
+ #define FOC1B 6 /* Force Output Compare for Channel B */
587
+ #define FOC1A 7 /* Force Output Compare for Channel A */
588
+
589
+ /* Timer/Counter1 */
590
+ #define TCNT1 _SFR_MEM16(0x84)
591
+ #define TCNT1L _SFR_MEM8(0x84)
592
+ #define TCNT10 0
593
+ #define TCNT11 1
594
+ #define TCNT12 2
595
+ #define TCNT13 3
596
+ #define TCNT14 4
597
+ #define TCNT15 5
598
+ #define TCNT16 6
599
+ #define TCNT17 7
600
+ #define TCNT1H _SFR_MEM8(0x85)
601
+ #define TCNT18 0
602
+ #define TCNT19 1
603
+ #define TCNT110 2
604
+ #define TCNT111 3
605
+ #define TCNT112 4
606
+ #define TCNT113 5
607
+ #define TCNT114 6
608
+ #define TCNT115 7
609
+
610
+ /* Input Capture Register 1 */
611
+ #define ICR1 _SFR_MEM16(0x86)
612
+ #define ICR1L _SFR_MEM8(0x86)
613
+ #define ICR17 7
614
+ #define ICR16 6
615
+ #define ICR15 5
616
+ #define ICR14 4
617
+ #define ICR13 3
618
+ #define ICR12 2
619
+ #define ICR11 1
620
+ #define ICR10 0
621
+ #define ICR1H _SFR_MEM8(0x87)
622
+ #define ICR115 7
623
+ #define ICR114 6
624
+ #define ICR113 5
625
+ #define ICR112 4
626
+ #define ICR111 3
627
+ #define ICR110 2
628
+ #define ICR19 1
629
+ #define ICR18 0
630
+
631
+ /* Output Compare Register 1 A */
632
+ #define OCR1A _SFR_MEM16(0x88)
633
+ #define OCR1AL _SFR_MEM8(0x88)
634
+ #define OCR1A0 0
635
+ #define OCR1A1 1
636
+ #define OCR1A2 2
637
+ #define OCR1A3 3
638
+ #define OCR1A4 4
639
+ #define OCR1A5 5
640
+ #define OCR1A6 6
641
+ #define OCR1A7 7
642
+ #define OCR1AH _SFR_MEM8(0x89)
643
+ #define OCR1A8 0
644
+ #define OCR1A9 1
645
+ #define OCR1A10 2
646
+ #define OCR1A11 3
647
+ #define OCR1A12 4
648
+ #define OCR1A13 5
649
+ #define OCR1A14 6
650
+ #define OCR1A15 7
651
+
652
+ /* Output Compare Register 1 B */
653
+ #define OCR1B _SFR_MEM16(0x8A)
654
+ #define OCR1BL _SFR_MEM8(0x8A)
655
+ #define OCR1B0 0
656
+ #define OCR1B1 1
657
+ #define OCR1B2 2
658
+ #define OCR1B3 3
659
+ #define OCR1B4 4
660
+ #define OCR1B5 5
661
+ #define OCR1B6 6
662
+ #define OCR1B7 7
663
+ #define OCR1BH _SFR_MEM8(0x8B)
664
+ #define OCR1B8 0
665
+ #define OCR1B9 1
666
+ #define OCR1B10 2
667
+ #define OCR1B11 3
668
+ #define OCR1B12 4
669
+ #define OCR1B13 5
670
+ #define OCR1B14 6
671
+ #define OCR1B15 7
672
+
673
+ /* PSC0 Interrupt Flag Register */
674
+ #define PIFR0 _SFR_MEM8(0xA0)
675
+ #define PEOP0 0 /* End Of PSC0 Interrupt */
676
+ #define PRN00 1 /* PSC0 Ramp Number bit0 */
677
+ #define PRN01 2 /* PSC0 Ramp Number bit1 */
678
+ #define PEV0A 3 /* PSC0 External Event A Interrupt */
679
+ #define PEV0B 4 /* PSC0 External Event B Interrupt */
680
+ #define PSEI0 5 /* PSC0 Synchro Error Interrupt */
681
+ #define POAC0A 6 /* PSC0 Output A Activity */
682
+ #define POAC0B 7 /* PSC0 Output B Activity */
683
+
684
+ /* PSC0 Interrupt Mask Register */
685
+ #define PIM0 _SFR_MEM8(0xA1)
686
+ #define PEOPE0 0 /* PSC0 End Of Cycle Interrupt Enable */
687
+ #define PEVE0A 3 /* PSC0 External Event A Interrupt Enable */
688
+ #define PEVE0B 4 /* PSC0 External Event B Interrupt Enable */
689
+ #define PSEIE0 5 /* PSC0 Synchro Error Interrupt Enable */
690
+
691
+ /* PSC1 Interrupt Flag Register */
692
+ #define PIFR1 _SFR_MEM8(0xA2)
693
+
694
+ /* PSC1 Interrupt Mask Register */
695
+ #define PIM1 _SFR_MEM8(0xA3)
696
+
697
+ /* PSC2 Interrupt Flag Register */
698
+ #define PIFR2 _SFR_MEM8(0xA4)
699
+ #define PEOP2 0 /* End Of PSC2 Interrupt */
700
+ #define PRN20 1 /* PSC2 Ramp Number bit0 */
701
+ #define PRN21 2 /* PSC2 Ramp Number bit1 */
702
+ #define PEV2A 3 /* PSC2 External Event A Interrupt */
703
+ #define PEV2B 4 /* PSC2 External Event B Interrupt */
704
+ #define PSEI2 5 /* PSC2 Synchro Error Interrupt */
705
+ #define POAC2A 6 /* PSC2 Output A Activity */
706
+ #define POAC2B 7 /* PSC2 Output B Activity */
707
+
708
+ /* PSC2 Interrupt Mask Register */
709
+ #define PIM2 _SFR_MEM8(0xA5)
710
+ #define PEOPE2 0 /* PSC2 End Of Cycle Interrupt Enable */
711
+ #define PEVE2A 3 /* PSC2 External Event A Interrupt Enable */
712
+ #define PEVE2B 4 /* PSC2 External Event B Interrupt Enable */
713
+ #define PSEIE2 5 /* PSC2 Synchro Error Interrupt Enable */
714
+
715
+ /* Digital to Analog Conversion Control Register */
716
+ #define DACON _SFR_MEM8(0xAA)
717
+ #define DAEN 0 /* Digital to Analog Enable bit */
718
+ #define DAOE 1 /* Digital to Analog Output Enable bit */
719
+ #define DALA 2 /* Digital to Analog Left Adjust */
720
+ #define DATS0 4 /* DAC Trigger Selection bit0 */
721
+ #define DATS1 5 /* DAC Trigger Selection bit1 */
722
+ #define DATS2 6 /* DAC Trigger Selection bit2 */
723
+ #define DAATE 7 /* DAC Auto Trigger Enable bit */
724
+
725
+ /* Digital to Analog Converter input Register */
726
+ #define DAC _SFR_MEM16(0xAB)
727
+ #define DACL _SFR_MEM8(0xAB)
728
+ #define DACH _SFR_MEM8(0xAC)
729
+
730
+ /* Analog Comparator 0 Control Register */
731
+ #define AC0CON _SFR_MEM8(0xAD)
732
+ #define AC0M0 0 /* Analog Comparator 0 Multiplexer register bit0 */
733
+ #define AC0M1 1 /* Analog Comparator 0 Multiplexer register bit1 */
734
+ #define AC0M2 2 /* Analog Comparator 0 Multiplexer register bit2 */
735
+ #define AC0IS0 4 /* Analog Comparator 0 Interrupt Select bit0 */
736
+ #define AC0IS1 5 /* Analog Comparator 0 Interrupt Select bit1 */
737
+ #define AC0IE 6 /* Analog Comparator 0 Interrupt Enable bit */
738
+ #define AC0EN 7 /* Analog Comparator 0 Enable Bit */
739
+
740
+ /* Analog Comparator 1 Control Register */
741
+ #define AC1CON _SFR_MEM8(0xAE)
742
+ #define AC1M0 0 /* Analog Comparator 1 Multiplexer register bit0 */
743
+ #define AC1M1 1 /* Analog Comparator 1 Multiplexer register bit1 */
744
+ #define AC1M2 2 /* Analog Comparator 1 Multiplexer register bit2 */
745
+ #define AC1ICE 3 /* Analog Comparator 1 Interrupt Capture Enable bit */
746
+ #define AC1IS0 4 /* Analog Comparator 1 Interrupt Select bit0 */
747
+ #define AC1IS1 5 /* Analog Comparator 1 Interrupt Select bit1 */
748
+ #define AC1IE 6 /* Analog Comparator 1 Interrupt Enable bit */
749
+ #define AC1EN 7 /* Analog Comparator 1 Enable Bit */
750
+
751
+ /* Analog Comparator 2 Control Register */
752
+ #define AC2CON _SFR_MEM8(0xAF)
753
+ #define AC2M0 0 /* Analog Comparator 2 Multiplexer register bit0 */
754
+ #define AC2M1 1 /* Analog Comparator 2 Multiplexer register bit1 */
755
+ #define AC2M2 2 /* Analog Comparator 2 Multiplexer register bit2 */
756
+ #define AC2IS0 4 /* Analog Comparator 2 Interrupt Select bit0 */
757
+ #define AC2IS1 5 /* Analog Comparator 2 Interrupt Select bit1 */
758
+ #define AC2IE 6 /* Analog Comparator 2 Interrupt Enable bit */
759
+ #define AC2EN 7 /* Analog Comparator 2 Enable Bit */
760
+
761
+ /* USART Control and Status Register A */
762
+ #define UCSRA _SFR_MEM8(0xC0)
763
+ #define MPCM 0 /* Multi-processor Communication Mode */
764
+ #define U2X 1 /* Double the USART Transmission Speed */
765
+ #define UPE 2 /* USART Parity Error */
766
+ #define DOR 3 /* Data OverRun */
767
+ #define FE 4 /* Frame Error */
768
+ #define UDRE 5 /* USART Data Register Empty */
769
+ #define TXC 6 /* USART Transmit Complete */
770
+ #define RXC 7 /* USART Receive Complete */
771
+
772
+ /* USART Control and Status Register B */
773
+ #define UCSRB _SFR_MEM8(0xC1)
774
+ #define TXB8 0 /* Transmit Data Bit 8 */
775
+ #define RXB8 1 /* Receive Data Bit 8 */
776
+ #define UCSZ2 2 /* Character Size */
777
+ #define TXEN 3 /* Transmitter Enable */
778
+ #define RXEN 4 /* Receiver Enable */
779
+ #define UDRIE 5 /* USART Data Register Empty Interrupt Enable */
780
+ #define TXCIE 6 /* TX Complete Interrupt Enable */
781
+ #define RXCIE 7 /* RX Complete Interrupt Enable */
782
+
783
+ /* USART Control and Status Register C */
784
+ #define UCSRC _SFR_MEM8(0xC2)
785
+ #define UCPOL 0 /* Clock Polarity */
786
+ #define UCSZ0 1 /* Character Size bit0 */
787
+ #define UCSZ1 2 /* Character Size bit1 */
788
+ #define USBS 3 /* Stop Bit Select */
789
+ #define UPM0 4 /* Parity Mode bit0 */
790
+ #define UPM1 5 /* Parity Mode bit1 */
791
+ #define UMSEL 6 /* USART Mode Select */
792
+
793
+ /* USART Baud Rate Register */
794
+ #define UBRR _SFR_MEM16(0xC4)
795
+ #define UBRRL _SFR_MEM8(0xC4)
796
+ #define UBRRH _SFR_MEM8(0xC5)
797
+
798
+ /* USART I/O Data Register */
799
+ #define UDR _SFR_MEM8(0xC6)
800
+
801
+ /* EUSART Control and Status Register A */
802
+ #define EUCSRA _SFR_MEM8(0xC8)
803
+ #define URxS0 0 /* EUSART Receive Character Size bit0 */
804
+ #define URxS1 1 /* EUSART Receive Character Size bit1 */
805
+ #define URxS2 2 /* EUSART Receive Character Size bit2 */
806
+ #define URxS3 3 /* EUSART Receive Character Size bit3 */
807
+ #define UTxS0 4 /* EUSART Transmit Character Size bit0 */
808
+ #define UTxS1 5 /* EUSART Transmit Character Size bit1 */
809
+ #define UTxS2 6 /* EUSART Transmit Character Size bit2 */
810
+ #define UTxS3 7 /* EUSART Transmit Character Size bit3 */
811
+
812
+ /* EUSART Control and Status Register B */
813
+ #define EUCSRB _SFR_MEM8(0xC9)
814
+ #define BODR 0 /* Bit Order */
815
+ #define EMCH 1 /* Manchester mode */
816
+ #define EUSBS 3 /* EUSBS Enable Bit */
817
+ #define EUSART 4 /* EUSART Enable Bit */
818
+
819
+ /* EUSART Control and Status Register C */
820
+ #define EUCSRC _SFR_MEM8(0xCA)
821
+ #define STP0 0 /* Stop bits values bit0 */
822
+ #define STP1 1 /* Stop bits values bit1 */
823
+ #define F1617 2
824
+ #define FEM 3 /* Frame Error Manchester */
825
+
826
+ /* Manchester receiver Baud Rate Registers */
827
+ #define MUBRR _SFR_MEM16(0xCC)
828
+ #define MUBRRL _SFR_MEM8(0xCC)
829
+ #define MUBRRH _SFR_MEM8(0xCD)
830
+
831
+ /* EUSART I/O Data Register */
832
+ #define EUDR _SFR_MEM8(0xCE)
833
+
834
+ /* PSC 0 Synchro and Output Configuration */
835
+ #define PSOC0 _SFR_MEM8(0xD0)
836
+ #define POEN0A 0 /* PSC 0 OUT Part A Output Enable */
837
+ #define POEN0B 2 /* PSC 0 OUT Part B Output Enable */
838
+ #define PSYNC00 4 /* Synchronization Out for ADC Selection bit0 */
839
+ #define PSYNC01 5 /* Synchronization Out for ADC Selection bit1 */
840
+
841
+ /* Output Compare SA Registers */
842
+ #define OCR0SA _SFR_MEM16(0xD2)
843
+ #define OCR0SAL _SFR_MEM8(0xD2)
844
+ #define OCR0SAH _SFR_MEM8(0xD3)
845
+
846
+ /* Output Compare RA Registers */
847
+ #define OCR0RA _SFR_MEM16(0xD4)
848
+ #define OCR0RAL _SFR_MEM8(0xD4)
849
+ #define OCR0RAH _SFR_MEM8(0xD5)
850
+
851
+ /* Output Compare SB Registers */
852
+ #define OCR0SB _SFR_MEM16(0xD6)
853
+ #define OCR0SBL _SFR_MEM8(0xD6)
854
+ #define OCR0SBH _SFR_MEM8(0xD7)
855
+
856
+ /* Output Compare RB Registers */
857
+ #define OCR0RB _SFR_MEM16(0xD8)
858
+ #define OCR0RBL _SFR_MEM8(0xD8)
859
+ #define OCR0RBH _SFR_MEM8(0xD9)
860
+
861
+ /* PSC 0 Configuration Register */
862
+ #define PCNF0 _SFR_MEM8(0xDA)
863
+ #define PCLKSEL0 1 /* PSC 0 Input Clock Select */
864
+ #define POP0 2 /* PSC 0 Output Polarity */
865
+ #define PMODE00 3 /* PSC 0 Mode bit0 */
866
+ #define PMODE01 4 /* PSC 0 Mode bit1 */
867
+ #define PLOCK0 5 /* PSC 0 Lock */
868
+ #define PALOCK0 6 /* PSC 0 Autolock */
869
+ #define PFIFTY0 7 /* PSC 0 Fifty */
870
+
871
+ /* PSC 0 Control Register */
872
+ #define PCTL0 _SFR_MEM8(0xDB)
873
+ #define PRUN0 0 /* PSC 0 Run */
874
+ #define PCCYC0 1 /* PSC 0 Complete Cycle */
875
+ #define PARUN0 2 /* PSC 0 Autorun */
876
+ #define PAOC0A 3 /* PSC 0 Asynchronous Output Control A */
877
+ #define PAOC0B 4 /* PSC 0 Asynchronous Output Control B */
878
+ #define PBFM0 5 /* Balance Flank Width Modulation */
879
+ #define PPRE00 6 /* PSC 0 Prescaler Select bit0 */
880
+ #define PPRE01 7 /* PSC 0 Prescaler Select bit1 */
881
+
882
+ /* PSC 0 Input A Control Register */
883
+ #define PFRC0A _SFR_MEM8(0xDC)
884
+ #define PRFM0A0 0 /* PSC 0 Fault Mode bit0 */
885
+ #define PRFM0A1 1 /* PSC 0 Fault Mode bit1 */
886
+ #define PRFM0A2 2 /* PSC 0 Fault Mode bit2 */
887
+ #define PRFM0A3 3 /* PSC 0 Fault Mode bit3 */
888
+ #define PFLTE0A 4 /* PSC 0 Filter Enable on Input Part A */
889
+ #define PELEV0A 5 /* PSC 0 Edge Level Selector of Input Part A */
890
+ #define PISEL0A 6 /* PSC 0 Input Select for Part A */
891
+ #define PCAE0A 7 /* PSC 0 Capture Enable Input Part A */
892
+
893
+ /* PSC 0 Input B Control Register */
894
+ #define PFRC0B _SFR_MEM8(0xDD)
895
+ #define PRFM0B0 0 /* PSC 0 Fault Mode bit0 */
896
+ #define PRFM0B1 1 /* PSC 0 Fault Mode bit1 */
897
+ #define PRFM0B2 2 /* PSC 0 Fault Mode bit2 */
898
+ #define PRFM0B3 3 /* PSC 0 Fault Mode bit3 */
899
+ #define PFLTE0B 4 /* PSC 0 Filter Enable on Input Part B */
900
+ #define PELEV0B 5 /* PSC 0 Edge Level Selector of Input Part B */
901
+ #define PISEL0B 6 /* PSC 0 Input Select for Part B */
902
+ #define PCAE0B 7 /* PSC 0 Capture Enable Input Part B */
903
+
904
+ /* PSC 0 Input Capture Registers */
905
+ #define PICR0 _SFR_MEM16(0xDE)
906
+ #define PICR0L _SFR_MEM8(0xDE)
907
+ #define PICR0H _SFR_MEM8(0xDF)
908
+ #define PCST0 7 /* PSC Capture Software Trig bit */
909
+
910
+ /* PSC 1 Synchro and Output Configuration */
911
+ #define PSOC1 _SFR_MEM8(0xE0)
912
+
913
+ /* Output Compare SA Registers */
914
+ #define OCR1SA _SFR_MEM16(0xE2)
915
+ #define OCR1SAL _SFR_MEM8(0xE2)
916
+ #define OCR1SAH _SFR_MEM8(0xE3)
917
+
918
+ /* Output Compare RA Registers */
919
+ #define OCR1RA _SFR_MEM16(0xE4)
920
+ #define OCR1RAL _SFR_MEM8(0xE4)
921
+ #define OCR1RAH _SFR_MEM8(0xE5)
922
+
923
+ /* Output Compare SB Registers */
924
+ #define OCR1SB _SFR_MEM16(0xE6)
925
+ #define OCR1SBL _SFR_MEM8(0xE6)
926
+ #define OCR1SBH _SFR_MEM8(0xE7)
927
+
928
+ /* Output Compare RB Registers */
929
+ #define OCR1RB _SFR_MEM16(0xE8)
930
+ #define OCR1RBL _SFR_MEM8(0xE8)
931
+ #define OCR1RBH _SFR_MEM8(0xE9)
932
+
933
+ /* PSC 1 Configuration Register */
934
+ #define PCNF1 _SFR_MEM8(0xEA)
935
+
936
+ /* PSC 1 Control Register */
937
+ #define PCTL1 _SFR_MEM8(0xEB)
938
+
939
+ /* PSC 1 Input A Control Register */
940
+ #define PFRC1A _SFR_MEM8(0xEC)
941
+
942
+ /* PSC 1 Input B Control Register */
943
+ #define PFRC1B _SFR_MEM8(0xED)
944
+
945
+ /* PSC 1 Input Capture Registers */
946
+ #define PICR1 _SFR_MEM16(0xEE)
947
+ #define PICR1L _SFR_MEM8(0xEE)
948
+ #define PICR1H _SFR_MEM8(0xEF)
949
+
950
+ /* PSC 2 Synchro and Output Configuration */
951
+ #define PSOC2 _SFR_MEM8(0xF0)
952
+ #define POEN2A 0 /* PSC 2 OUT Part A Output Enable */
953
+ #define POEN2C 1 /* PSCOUT22 Output Enable */
954
+ #define POEN2B 2 /* PSC 2 OUT Part B Output Enable */
955
+ #define POEN2D 3 /* PSCOUT23 Output Enable */
956
+ #define PSYNC20 4 /* Synchronization Out for ADC Selection bit0 */
957
+ #define PSYNC21 5 /* Synchronization Out for ADC Selection bit1 */
958
+ #define POS22 6 /* PSCOUT22 Selection */
959
+ #define POS23 7 /* PSCOUT23 Selection */
960
+
961
+ /* PSC 2 Output Matrix */
962
+ #define POM2 _SFR_MEM8(0xF1)
963
+ #define POMV2A0 0 /* Output Matrix Output A Ramp 0 */
964
+ #define POMV2A1 1 /* Output Matrix Output A Ramp 1 */
965
+ #define POMV2A2 2 /* Output Matrix Output A Ramp 2 */
966
+ #define POMV2A3 3 /* Output Matrix Output A Ramp 3 */
967
+ #define POMV2B0 4 /* Output Matrix Output B Ramp 0 */
968
+ #define POMV2B1 5 /* Output Matrix Output B Ramp 1 */
969
+ #define POMV2B2 6 /* Output Matrix Output B Ramp 2 */
970
+ #define POMV2B3 7 /* Output Matrix Output B Ramp 3 */
971
+
972
+ /* Output Compare SA Registers */
973
+ #define OCR2SA _SFR_MEM16(0xF2)
974
+ #define OCR2SAL _SFR_MEM8(0xF2)
975
+ #define OCR2SAH _SFR_MEM8(0xF3)
976
+
977
+ /* Output Compare RA Registers */
978
+ #define OCR2RA _SFR_MEM16(0xF4)
979
+ #define OCR2RAL _SFR_MEM8(0xF4)
980
+ #define OCR2RAH _SFR_MEM8(0xF5)
981
+
982
+ /* Output Compare SB Registers */
983
+ #define OCR2SB _SFR_MEM16(0xF6)
984
+ #define OCR2SBL _SFR_MEM8(0xF6)
985
+ #define OCR2SBH _SFR_MEM8(0xF7)
986
+
987
+ /* Output Compare RB Registers */
988
+ #define OCR2RB _SFR_MEM16(0xF8)
989
+ #define OCR2RBL _SFR_MEM8(0xF8)
990
+ #define OCR2RBH _SFR_MEM8(0xF9)
991
+
992
+ /* PSC 2 Configuration Register */
993
+ #define PCNF2 _SFR_MEM8(0xFA)
994
+ #define POME2 0 /* PSC 2 Output Matrix Enable */
995
+ #define PCLKSEL2 1 /* PSC 2 Input Clock Select */
996
+ #define POP2 2 /* PSC 2 Output Polarity */
997
+ #define PMODE20 3 /* PSC 2 Mode bit0 */
998
+ #define PMODE21 4 /* PSC 2 Mode bit1 */
999
+ #define PLOCK2 5 /* PSC 2 Lock */
1000
+ #define PALOCK2 6 /* PSC 2 Autolock */
1001
+ #define PFIFTY2 7 /* PSC 2 Fifty */
1002
+
1003
+ /* PSC 2 Control Register */
1004
+ #define PCTL2 _SFR_MEM8(0xFB)
1005
+ #define PRUN2 0 /* PSC 2 Run */
1006
+ #define PCCYC2 1 /* PSC 2 Complete Cycle */
1007
+ #define PARUN2 2 /* PSC 2 Autorun */
1008
+ #define PAOC2A 3 /* PSC 2 Asynchronous Output Control A */
1009
+ #define PAOC2B 4 /* PSC 2 Asynchronous Output Control B */
1010
+ #define PBFM2 5 /* Balance Flank Width Modulation */
1011
+ #define PPRE20 6 /* PSC 2 Prescaler Select bit0 */
1012
+ #define PPRE21 7 /* PSC 2 Prescaler Select bit1 */
1013
+
1014
+ /* PSC 2 Input A Control Register */
1015
+ #define PFRC2A _SFR_MEM8(0xFC)
1016
+ #define PRFM2A0 0 /* PSC 2 Fault Mode bit0 */
1017
+ #define PRFM2A1 1 /* PSC 2 Fault Mode bit1 */
1018
+ #define PRFM2A2 2 /* PSC 2 Fault Mode bit2 */
1019
+ #define PRFM2A3 3 /* PSC 2 Fault Mode bit3 */
1020
+ #define PFLTE2A 4 /* PSC 2 Filter Enable on Input Part A */
1021
+ #define PELEV2A 5 /* PSC 2 Edge Level Selector of Input Part A */
1022
+ #define PISEL2A 6 /* PSC 2 Input Select for Part A */
1023
+ #define PCAE2A 7 /* PSC 2 Capture Enable Input Part A */
1024
+
1025
+ /* PSC 2 Input B Control Register */
1026
+ #define PFRC2B _SFR_MEM8(0xFD)
1027
+ #define PRFM2B0 0 /* PSC 2 Fault Mode bit0 */
1028
+ #define PRFM2B1 1 /* PSC 2 Fault Mode bit1 */
1029
+ #define PRFM2B2 2 /* PSC 2 Fault Mode bit2 */
1030
+ #define PRFM2B3 3 /* PSC 2 Fault Mode bit3 */
1031
+ #define PFLTE2B 4 /* PSC 2 Filter Enable on Input Part B */
1032
+ #define PELEV2B 5 /* PSC 2 Edge Level Selector of Input Part B */
1033
+ #define PISEL2B 6 /* PSC 2 Input Select for Part B */
1034
+ #define PCAE2B 7 /* PSC 2 Capture Enable Input Part B */
1035
+
1036
+ /* PSC 2 Input Capture Registers */
1037
+ #define PICR2 _SFR_MEM16(0xFE)
1038
+ #define PICR2L _SFR_MEM8(0xFE)
1039
+ #define PICR2H _SFR_MEM8(0xFF)
1040
+ #define PCST2 7 /* PSC Capture Software Trig bit */
1041
+
1042
+
1043
+ /* Interrupt Vectors */
1044
+ /* Interrupt 0 is the reset vector. */
1045
+
1046
+ /* PSC2 Capture Event */
1047
+ #define PSC2_CAPT_vect_num 1
1048
+ #define PSC2_CAPT_vect _VECTOR(1)
1049
+
1050
+ /* PSC2 End Cycle */
1051
+ #define PSC2_EC_vect_num 2
1052
+ #define PSC2_EC_vect _VECTOR(2)
1053
+
1054
+ /* PSC1 Capture Event */
1055
+ #define PSC1_CAPT_vect_num 3
1056
+ #define PSC1_CAPT_vect _VECTOR(3)
1057
+
1058
+ /* PSC1 End Cycle */
1059
+ #define PSC1_EC_vect_num 4
1060
+ #define PSC1_EC_vect _VECTOR(4)
1061
+
1062
+ /* PSC0 Capture Event */
1063
+ #define PSC0_CAPT_vect_num 5
1064
+ #define PSC0_CAPT_vect _VECTOR(5)
1065
+
1066
+ /* PSC0 End Cycle */
1067
+ #define PSC0_EC_vect_num 6
1068
+ #define PSC0_EC_vect _VECTOR(6)
1069
+
1070
+ /* Analog Comparator 0 */
1071
+ #define ANALOG_COMP_0_vect_num 7
1072
+ #define ANALOG_COMP_0_vect _VECTOR(7)
1073
+
1074
+ /* Analog Comparator 1 */
1075
+ #define ANALOG_COMP_1_vect_num 8
1076
+ #define ANALOG_COMP_1_vect _VECTOR(8)
1077
+
1078
+ /* Analog Comparator 2 */
1079
+ #define ANALOG_COMP_2_vect_num 9
1080
+ #define ANALOG_COMP_2_vect _VECTOR(9)
1081
+
1082
+ /* External Interrupt Request 0 */
1083
+ #define INT0_vect_num 10
1084
+ #define INT0_vect _VECTOR(10)
1085
+
1086
+ /* Timer/Counter1 Capture Event */
1087
+ #define TIMER1_CAPT_vect_num 11
1088
+ #define TIMER1_CAPT_vect _VECTOR(11)
1089
+
1090
+ /* Timer/Counter1 Compare Match A */
1091
+ #define TIMER1_COMPA_vect_num 12
1092
+ #define TIMER1_COMPA_vect _VECTOR(12)
1093
+
1094
+ /* Timer/Counter Compare Match B */
1095
+ #define TIMER1_COMPB_vect_num 13
1096
+ #define TIMER1_COMPB_vect _VECTOR(13)
1097
+
1098
+ /* Timer/Counter1 Overflow */
1099
+ #define TIMER1_OVF_vect_num 15
1100
+ #define TIMER1_OVF_vect _VECTOR(15)
1101
+
1102
+ /* Timer/Counter0 Compare Match A */
1103
+ #define TIMER0_COMP_A_vect_num 16
1104
+ #define TIMER0_COMP_A_vect _VECTOR(16)
1105
+
1106
+ /* Timer/Counter0 Overflow */
1107
+ #define TIMER0_OVF_vect_num 17
1108
+ #define TIMER0_OVF_vect _VECTOR(17)
1109
+
1110
+ /* ADC Conversion Complete */
1111
+ #define ADC_vect_num 18
1112
+ #define ADC_vect _VECTOR(18)
1113
+
1114
+ /* External Interrupt Request 1 */
1115
+ #define INT1_vect_num 19
1116
+ #define INT1_vect _VECTOR(19)
1117
+
1118
+ /* SPI Serial Transfer Complete */
1119
+ #define SPI_STC_vect_num 20
1120
+ #define SPI_STC_vect _VECTOR(20)
1121
+
1122
+ /* USART, Rx Complete */
1123
+ #define USART_RX_vect_num 21
1124
+ #define USART_RX_vect _VECTOR(21)
1125
+
1126
+ /* USART Data Register Empty */
1127
+ #define USART_UDRE_vect_num 22
1128
+ #define USART_UDRE_vect _VECTOR(22)
1129
+
1130
+ /* USART, Tx Complete */
1131
+ #define USART_TX_vect_num 23
1132
+ #define USART_TX_vect _VECTOR(23)
1133
+
1134
+ /* External Interrupt Request 2 */
1135
+ #define INT2_vect_num 24
1136
+ #define INT2_vect _VECTOR(24)
1137
+
1138
+ /* Watchdog Timeout Interrupt */
1139
+ #define WDT_vect_num 25
1140
+ #define WDT_vect _VECTOR(25)
1141
+
1142
+ /* EEPROM Ready */
1143
+ #define EE_READY_vect_num 26
1144
+ #define EE_READY_vect _VECTOR(26)
1145
+
1146
+ /* Timer Counter 0 Compare Match B */
1147
+ #define TIMER0_COMPB_vect_num 27
1148
+ #define TIMER0_COMPB_vect _VECTOR(27)
1149
+
1150
+ /* External Interrupt Request 3 */
1151
+ #define INT3_vect_num 28
1152
+ #define INT3_vect _VECTOR(28)
1153
+
1154
+ /* Store Program Memory Read */
1155
+ #define SPM_READY_vect_num 31
1156
+ #define SPM_READY_vect _VECTOR(31)
1157
+
1158
+ #define _VECTORS_SIZE (4 * 32)
1159
+
1160
+ /* Constants */
1161
+
1162
+ #define RAMSTART 0x100
1163
+ #define RAMEND 0x4FF
1164
+ #define XRAMSIZE 0
1165
+ #define XRAMEND RAMEND
1166
+ #define E2END 0x1FF
1167
+ #define E2PAGESIZE 4
1168
+ #define FLASHEND 0x3FFF
1169
+ #define SPM_PAGESIZE 128
1170
+
1171
+
1172
+ /* Fuse Information */
1173
+
1174
+ #define FUSE_MEMORY_SIZE 3
1175
+
1176
+ /* Low Fuse Byte */
1177
+ #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */
1178
+ #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */
1179
+ #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */
1180
+ #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */
1181
+ #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */
1182
+ #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */
1183
+ #define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator output option */
1184
+ #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */
1185
+ #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
1186
+
1187
+ /* High Fuse Byte */
1188
+ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
1189
+ #define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
1190
+ #define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
1191
+ #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */
1192
+ #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */
1193
+ #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */
1194
+ #define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */
1195
+ #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Diasble */
1196
+ #define HFUSE_DEFAULT (FUSE_SPIEN)
1197
+
1198
+ /* Extended Fuse Byte */
1199
+ #define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */
1200
+ #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */
1201
+ #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */
1202
+ #define FUSE_PSCRV (unsigned char)~_BV(4)
1203
+ #define FUSE_PSC0RB (unsigned char)~_BV(5)
1204
+ #define FUSE_PSC1RB (unsigned char)~_BV(6)
1205
+ #define FUSE_PSC2RB (unsigned char)~_BV(7)
1206
+ #define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
1207
+
1208
+
1209
+ /* Lock Bits */
1210
+ #define __LOCK_BITS_EXIST
1211
+ #define __BOOT_LOCK_BITS_0_EXIST
1212
+ #define __BOOT_LOCK_BITS_1_EXIST
1213
+
1214
+
1215
+ /* Signature */
1216
+ #define SIGNATURE_0 0x1E
1217
+ #define SIGNATURE_1 0x94
1218
+ #define SIGNATURE_2 0x83
1219
+
1220
+ #define SLEEP_MODE_IDLE (0x00<<1)
1221
+ #define SLEEP_MODE_ADC (0x01<<1)
1222
+ #define SLEEP_MODE_PWR_DOWN (0x02<<1)
1223
+ #define SLEEP_MODE_STANDBY (0x06<<1)
1224
+
1225
+ #endif /* _AVR_IO90PWM216_H_ */