aarch64 1.0.1 → 2.0.0

data/lib/aarch64/instructions/ldxr.rb

@@ -4,24 +4,24 @@ module AArch64
     # Load Exclusive Register
     # LDXR  <Wt>, [<Xn|SP>{,#0}]
     # LDXR  <Xt>, [<Xn|SP>{,#0}]
-    class LDXR
+    class LDXR < Instruction
       def initialize rt, rn, size
-        @rt   = rt
-        @rn   = rn
-        @size = size
+        @rt   = check_mask(rt, 0x1f)
+        @rn   = check_mask(rn, 0x1f)
+        @size = check_mask(size, 0x03)
       end
 
       def encode
-        LDXR(@size, @rn.to_i, @rt.to_i)
+        LDXR(@size, @rn, @rt)
       end
 
       private
 
       def LDXR size, rn, rt
         insn = 0b00_001000_0_1_0_11111_0_11111_00000_00000
-        insn |= ((size & 0x3) << 30)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((size) << 30)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/lslv.rb

@@ -4,26 +4,26 @@ module AArch64
     # Logical Shift Left Variable
     # LSLV  <Wd>, <Wn>, <Wm>
     # LSLV  <Xd>, <Xn>, <Xm>
-    class LSLV
+    class LSLV < Instruction
       def initialize rd, rn, rm, sf
-        @rd = rd
-        @rn = rn
-        @rm = rm
-        @sf = sf
+        @rd = check_mask(rd, 0x1f)
+        @rn = check_mask(rn, 0x1f)
+        @rm = check_mask(rm, 0x1f)
+        @sf = check_mask(sf, 0x01)
       end
 
       def encode
-        LSLV(@sf, @rm.to_i, @rn.to_i, @rd.to_i)
+        LSLV(@sf, @rm, @rn, @rd)
       end
 
       private
 
       def LSLV sf, rm, rn, rd
         insn = 0b0_0_0_11010110_00000_0010_00_00000_00000
-        insn |= ((sf & 0x1) << 31)
-        insn |= ((rm & 0x1f) << 16)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((sf) << 31)
+        insn |= ((rm) << 16)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/lsrv.rb

@@ -4,26 +4,26 @@ module AArch64
     # Logical Shift Right Variable
     # LSRV  <Wd>, <Wn>, <Wm>
     # LSRV  <Xd>, <Xn>, <Xm>
-    class LSRV
+    class LSRV < Instruction
       def initialize rd, rn, rm, sf
-        @rd = rd
-        @rn = rn
-        @rm = rm
-        @sf = sf
+        @rd = check_mask(rd, 0x1f)
+        @rn = check_mask(rn, 0x1f)
+        @rm = check_mask(rm, 0x1f)
+        @sf = check_mask(sf, 0x01)
       end
 
       def encode
-        LSRV(@sf, @rm.to_i, @rn.to_i, @rd.to_i)
+        LSRV(@sf, @rm, @rn, @rd)
       end
 
       private
 
       def LSRV sf, rm, rn, rd
         insn = 0b0_0_0_11010110_00000_0010_01_00000_00000
-        insn |= ((sf & 0x1) << 31)
-        insn |= ((rm & 0x1f) << 16)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((sf) << 31)
+        insn |= ((rm) << 16)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/madd.rb

@@ -4,28 +4,28 @@ module AArch64
     # Multiply-Add
     # MADD  <Wd>, <Wn>, <Wm>, <Wa>
     # MADD  <Xd>, <Xn>, <Xm>, <Xa>
-    class MADD
+    class MADD < Instruction
       def initialize rd, rn, rm, ra, sf
-        @rd = rd
-        @rn = rn
-        @rm = rm
-        @ra = ra
-        @sf = sf
+        @rd = check_mask(rd, 0x1f)
+        @rn = check_mask(rn, 0x1f)
+        @rm = check_mask(rm, 0x1f)
+        @ra = check_mask(ra, 0x1f)
+        @sf = check_mask(sf, 0x01)
       end
 
       def encode
-        MADD(@sf, @rm.to_i, @ra.to_i, @rn.to_i, @rd.to_i)
+        MADD(@sf, @rm, @ra, @rn, @rd)
       end
 
       private
 
       def MADD sf, rm, ra, rn, rd
         insn = 0b0_00_11011_000_00000_0_00000_00000_00000
-        insn |= ((sf & 0x1) << 31)
-        insn |= ((rm & 0x1f) << 16)
-        insn |= ((ra & 0x1f) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((sf) << 31)
+        insn |= ((rm) << 16)
+        insn |= ((ra) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/movk.rb

@@ -4,26 +4,26 @@ module AArch64
     # Move wide with keep
     # MOVK  <Wd>, #<imm>{, LSL #<shift>}
     # MOVK  <Xd>, #<imm>{, LSL #<shift>}
-    class MOVK
+    class MOVK < Instruction
       def initialize reg, imm, shift, sf
-        @reg   = reg
-        @imm   = imm
-        @shift = shift
-        @sf    = sf
+        @reg   = check_mask(reg, 0x1f)
+        @imm   = check_mask(imm, 0xffff)
+        @shift = check_mask(shift, 0x03)
+        @sf    = check_mask(sf, 0x01)
       end
 
       def encode
-        MOVK(@sf, @shift, @imm, @reg.to_i)
+        MOVK(@sf, @shift, @imm, @reg)
       end
 
       private
 
       def MOVK sf, hw, imm16, rd
         insn = 0b0_11_100101_00_0000000000000000_00000
-        insn |= ((sf & 0x1) << 31)
-        insn |= ((hw & 0x3) << 21)
-        insn |= ((imm16 & 0xffff) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((sf) << 31)
+        insn |= ((hw) << 21)
+        insn |= ((imm16) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/movn.rb

@@ -4,26 +4,26 @@ module AArch64
     # Move wide with NOT
     # MOVN  <Wd>, #<imm>{, LSL #<shift>}
     # MOVN  <Xd>, #<imm>{, LSL #<shift>}
-    class MOVN
+    class MOVN < Instruction
       def initialize rd, imm16, hw, sf
-        @rd    = rd
-        @imm16 = imm16
-        @hw    = hw
-        @sf    = sf
+        @rd    = check_mask(rd, 0x1f)
+        @imm16 = check_mask(imm16, 0xffff)
+        @hw    = check_mask(hw, 0x03)
+        @sf    = check_mask(sf, 0x01)
       end
 
       def encode
-        MOVN(@sf, @hw, @imm16, @rd.to_i)
+        MOVN(@sf, @hw, @imm16, @rd)
       end
 
       private
 
       def MOVN sf, hw, imm16, rd
         insn = 0b0_00_100101_00_0000000000000000_00000
-        insn |= ((sf & 0x1) << 31)
-        insn |= ((hw & 0x3) << 21)
-        insn |= ((imm16 & 0xffff) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((sf) << 31)
+        insn |= ((hw) << 21)
+        insn |= ((imm16) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/movz.rb

@@ -4,26 +4,26 @@ module AArch64
     # Move wide with zero
     # MOVZ  <Wd>, #<imm>{, LSL #<shift>}
     # MOVZ  <Xd>, #<imm>{, LSL #<shift>}
-    class MOVZ
+    class MOVZ < Instruction
       def initialize reg, imm, shift, sf
-        @reg   = reg
-        @imm   = imm
-        @shift = shift
-        @sf    = sf
+        @reg   = check_mask(reg, 0x1f)
+        @imm   = check_mask(imm, 0xffff)
+        @shift = check_mask(shift, 0x03)
+        @sf    = check_mask(sf, 0x01)
       end
 
       def encode
-        MOVZ(@sf, @shift, @imm, @reg.to_i)
+        MOVZ(@sf, @shift, @imm, @reg)
       end
 
       private
 
       def MOVZ sf, hw, imm16, rd
         insn = 0b0_10_100101_00_0000000000000000_00000
-        insn |= ((sf & 0x1) << 31)
-        insn |= ((hw & 0x3) << 21)
-        insn |= ((imm16 & 0xffff) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((sf) << 31)
+        insn |= ((hw) << 21)
+        insn |= ((imm16) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/mrs.rb

@@ -3,30 +3,30 @@ module AArch64
     # MRS -- A64
     # Move System Register
     # MRS  <Xt>, (<systemreg>|S<op0>_<op1>_<Cn>_<Cm>_<op2>)
-    class MRS
+    class MRS < Instruction
       def initialize o0, op1, crn, crm, op2, rt
-        @o0  = o0
-        @op1 = op1
-        @crn = crn
-        @crm = crm
-        @op2 = op2
-        @rt  = rt
+        @o0  = check_mask(o0, 0x01)
+        @op1 = check_mask(op1, 0x07)
+        @crn = check_mask(crn, 0x0f)
+        @crm = check_mask(crm, 0x0f)
+        @op2 = check_mask(op2, 0x07)
+        @rt  = check_mask(rt, 0x1f)
       end
 
       def encode
-        MRS(@o0, @op1, @crn, @crm, @op2, @rt.to_i)
+        MRS(@o0, @op1, @crn, @crm, @op2, @rt)
       end
 
       private
 
       def MRS o0, op1, crn, crm, op2, rt
         insn = 0b1101010100_1_1_0_000_0000_0000_000_00000
-        insn |= ((o0 & 0x1) << 19)
-        insn |= ((op1 & 0x7) << 16)
-        insn |= ((crn & 0xf) << 12)
-        insn |= ((crm & 0xf) << 8)
-        insn |= ((op2 & 0x7) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((o0) << 19)
+        insn |= ((op1) << 16)
+        insn |= ((crn) << 12)
+        insn |= ((crm) << 8)
+        insn |= ((op2) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/msr_imm.rb

@@ -3,11 +3,11 @@ module AArch64
     # MSR (immediate) -- A64
     # Move immediate value to Special Register
     # MSR  <pstatefield>, #<imm>
-    class MSR_imm
+    class MSR_imm < Instruction
       def initialize op1, crm, op2
-        @op1 = op1
-        @crm = crm
-        @op2 = op2
+        @op1 = check_mask(op1, 0x07)
+        @crm = check_mask(crm, 0x0f)
+        @op2 = check_mask(op2, 0x07)
       end
 
       def encode
@@ -18,9 +18,9 @@ module AArch64
 
       def MSR_imm op1, crm, op2
         insn = 0b1101010100_0_00_000_0100_0000_000_11111
-        insn |= ((op1 & 0x7) << 16)
-        insn |= ((crm & 0xf) << 8)
-        insn |= ((op2 & 0x7) << 5)
+        insn |= ((op1) << 16)
+        insn |= ((crm) << 8)
+        insn |= ((op2) << 5)
         insn
       end
     end

data/lib/aarch64/instructions/msr_reg.rb

@@ -3,30 +3,30 @@ module AArch64
     # MSR (register) -- A64
     # Move general-purpose register to System Register
     # MSR  (<systemreg>|S<op0>_<op1>_<Cn>_<Cm>_<op2>), <Xt>
-    class MSR_reg
+    class MSR_reg < Instruction
       def initialize o0, op1, crn, crm, op2, rt
-        @o0  = o0
-        @op1 = op1
-        @crn = crn
-        @crm = crm
-        @op2 = op2
-        @rt  = rt
+        @o0  = check_mask(o0, 0x01)
+        @op1 = check_mask(op1, 0x07)
+        @crn = check_mask(crn, 0x0f)
+        @crm = check_mask(crm, 0x0f)
+        @op2 = check_mask(op2, 0x07)
+        @rt  = check_mask(rt, 0x1f)
       end
 
       def encode
-        MSR_reg(@o0, @op1, @crn, @crm, @op2, @rt.to_i)
+        MSR_reg(@o0, @op1, @crn, @crm, @op2, @rt)
       end
 
       private
 
       def MSR_reg o0, op1, crn, crm, op2, rt
         insn = 0b1101010100_0_1_0_000_0000_0000_000_00000
-        insn |= ((o0 & 0x1) << 19)
-        insn |= ((op1 & 0x7) << 16)
-        insn |= ((crn & 0xf) << 12)
-        insn |= ((crm & 0xf) << 8)
-        insn |= ((op2 & 0x7) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((o0) << 19)
+        insn |= ((op1) << 16)
+        insn |= ((crn) << 12)
+        insn |= ((crm) << 8)
+        insn |= ((op2) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/msub.rb

@@ -4,28 +4,28 @@ module AArch64
     # Multiply-Subtract
     # MSUB  <Wd>, <Wn>, <Wm>, <Wa>
     # MSUB  <Xd>, <Xn>, <Xm>, <Xa>
-    class MSUB
+    class MSUB < Instruction
       def initialize rd, rn, rm, ra, sf
-        @rd = rd
-        @rn = rn
-        @rm = rm
-        @ra = ra
-        @sf = sf
+        @rd = check_mask(rd, 0x1f)
+        @rn = check_mask(rn, 0x1f)
+        @rm = check_mask(rm, 0x1f)
+        @ra = check_mask(ra, 0x1f)
+        @sf = check_mask(sf, 0x01)
       end
 
       def encode
-        MSUB(@sf, @rm.to_i, @ra.to_i, @rn.to_i, @rd.to_i)
+        MSUB(@sf, @rm, @ra, @rn, @rd)
       end
 
       private
 
       def MSUB sf, rm, ra, rn, rd
         insn = 0b0_00_11011_000_00000_1_00000_00000_00000
-        insn |= ((sf & 0x1) << 31)
-        insn |= ((rm & 0x1f) << 16)
-        insn |= ((ra & 0x1f) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((sf) << 31)
+        insn |= ((rm) << 16)
+        insn |= ((ra) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/nop.rb

@@ -3,7 +3,7 @@ module AArch64
     # NOP -- A64
     # No Operation
     # NOP
-    class NOP
+    class NOP < Instruction
       def encode
         0b1101010100_0_00_011_0010_0000_000_11111
       end

data/lib/aarch64/instructions/orn_log_shift.rb

@@ -4,30 +4,30 @@ module AArch64
     # Bitwise OR NOT (shifted register)
     # ORN  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
     # ORN  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
-    class ORN_log_shift
+    class ORN_log_shift < Instruction
       def initialize rd, rn, rm, shift, imm6, sf
-        @rd    = rd
-        @rn    = rn
-        @rm    = rm
-        @shift = shift
-        @imm6  = imm6
-        @sf    = sf
+        @rd    = check_mask(rd, 0x1f)
+        @rn    = check_mask(rn, 0x1f)
+        @rm    = check_mask(rm, 0x1f)
+        @shift = check_mask(shift, 0x03)
+        @imm6  = check_mask(imm6, 0x3f)
+        @sf    = check_mask(sf, 0x01)
       end
 
       def encode
-        ORN_log_shift(@sf, @shift, @rm.to_i, @imm6, @rn.to_i, @rd.to_i)
+        ORN_log_shift(@sf, @shift, @rm, @imm6, @rn, @rd)
       end
 
       private
 
       def ORN_log_shift sf, shift, rm, imm6, rn, rd
         insn = 0b0_01_01010_00_1_00000_000000_00000_00000
-        insn |= ((sf & 0x1) << 31)
-        insn |= ((shift & 0x3) << 22)
-        insn |= ((rm & 0x1f) << 16)
-        insn |= ((imm6 & 0x3f) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((sf) << 31)
+        insn |= ((shift) << 22)
+        insn |= ((rm) << 16)
+        insn |= ((imm6) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/orr_log_imm.rb

@@ -4,30 +4,30 @@ module AArch64
     # Bitwise OR (immediate)
     # ORR  <Wd|WSP>, <Wn>, #<imm>
     # ORR  <Xd|SP>, <Xn>, #<imm>
-    class ORR_log_imm
+    class ORR_log_imm < Instruction
       def initialize rd, rn, n, immr, imms, sf
-        @rd   = rd
-        @rn   = rn
-        @n    = n
-        @immr = immr
-        @imms = imms
-        @sf   = sf
+        @rd   = check_mask(rd, 0x1f)
+        @rn   = check_mask(rn, 0x1f)
+        @n    = check_mask(n, 0x01)
+        @immr = check_mask(immr, 0x3f)
+        @imms = check_mask(imms, 0x3f)
+        @sf   = check_mask(sf, 0x01)
       end
 
       def encode
-        ORR_log_imm(@sf, @n, @immr, @imms, @rn.to_i, @rd.to_i)
+        ORR_log_imm(@sf, @n, @immr, @imms, @rn, @rd)
       end
 
       private
 
       def ORR_log_imm sf, n, immr, imms, rn, rd
         insn = 0b0_01_100100_0_000000_000000_00000_00000
-        insn |= ((sf & 0x1) << 31)
-        insn |= ((n & 0x1) << 22)
-        insn |= ((immr & 0x3f) << 16)
-        insn |= ((imms & 0x3f) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((sf) << 31)
+        insn |= ((n) << 22)
+        insn |= ((immr) << 16)
+        insn |= ((imms) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/orr_log_shift.rb

@@ -4,30 +4,30 @@ module AArch64
     # Bitwise OR (shifted register)
     # ORR  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
     # ORR  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
-    class ORR_log_shift
+    class ORR_log_shift < Instruction
       def initialize rd, rn, rm, shift, imm6, sf
-        @rd    = rd
-        @rn    = rn
-        @rm    = rm
-        @shift = shift
-        @imm6  = imm6
-        @sf    = sf
+        @rd    = check_mask(rd, 0x1f)
+        @rn    = check_mask(rn, 0x1f)
+        @rm    = check_mask(rm, 0x1f)
+        @shift = check_mask(shift, 0x03)
+        @imm6  = check_mask(imm6, 0x3f)
+        @sf    = check_mask(sf, 0x01)
       end
 
       def encode
-        ORR_log_shift(@sf, @shift, @rm.to_i, @imm6, @rn.to_i, @rd.to_i)
+        ORR_log_shift(@sf, @shift, @rm, @imm6, @rn, @rd)
       end
 
       private
 
       def ORR_log_shift sf, shift, rm, imm6, rn, rd
         insn = 0b0_01_01010_00_0_00000_000000_00000_00000
-        insn |= ((sf & 0x1) << 31)
-        insn |= ((shift & 0x3) << 22)
-        insn |= ((rm & 0x1f) << 16)
-        insn |= ((imm6 & 0x3f) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((sf) << 31)
+        insn |= ((shift) << 22)
+        insn |= ((rm) << 16)
+        insn |= ((imm6) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/pacda.rb

@@ -4,24 +4,24 @@ module AArch64
     # Pointer Authentication Code for Data address, using key A
     # PACDA  <Xd>, <Xn|SP>
     # PACDZA  <Xd>
-    class PACDA
+    class PACDA < Instruction
       def initialize rd, rn, z
-        @rd = rd
-        @rn = rn
-        @z  = z
+        @rd = check_mask(rd, 0x1f)
+        @rn = check_mask(rn, 0x1f)
+        @z  = check_mask(z, 0x01)
       end
 
       def encode
-        PACDA(@z, @rn.to_i, @rd.to_i)
+        PACDA(@z, @rn, @rd)
       end
 
       private
 
       def PACDA z, rn, rd
         insn = 0b1_1_0_11010110_00001_0_0_0_010_00000_00000
-        insn |= ((z & 0x1) << 13)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((z) << 13)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/pacdb.rb

@@ -4,24 +4,24 @@ module AArch64
     # Pointer Authentication Code for Data address, using key B
     # PACDB  <Xd>, <Xn|SP>
     # PACDZB  <Xd>
-    class PACDB
+    class PACDB < Instruction
       def initialize rd, rn, z
-        @rd = rd
-        @rn = rn
-        @z  = z
+        @rd = check_mask(rd, 0x1f)
+        @rn = check_mask(rn, 0x1f)
+        @z  = check_mask(z, 0x01)
       end
 
       def encode
-        PACDB(@z, @rn.to_i, @rd.to_i)
+        PACDB(@z, @rn, @rd)
       end
 
       private
 
       def PACDB z, rn, rd
         insn = 0b1_1_0_11010110_00001_0_0_0_011_00000_00000
-        insn |= ((z & 0x1) << 13)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((z) << 13)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end